1/* $NetBSD: jz4775-dma.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * This header provides macros for JZ4775 DMA bindings. 6 * 7 * Copyright (c) 2020 ��������� (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__ 11#define __DT_BINDINGS_DMA_JZ4775_DMA_H__ 12 13/* 14 * Request type numbers for the JZ4775 DMA controller (written to the DRTn 15 * register for the channel). 16 */ 17#define JZ4775_DMA_I2S0_TX 0x6 18#define JZ4775_DMA_I2S0_RX 0x7 19#define JZ4775_DMA_AUTO 0x8 20#define JZ4775_DMA_SADC_RX 0x9 21#define JZ4775_DMA_UART3_TX 0x0e 22#define JZ4775_DMA_UART3_RX 0x0f 23#define JZ4775_DMA_UART2_TX 0x10 24#define JZ4775_DMA_UART2_RX 0x11 25#define JZ4775_DMA_UART1_TX 0x12 26#define JZ4775_DMA_UART1_RX 0x13 27#define JZ4775_DMA_UART0_TX 0x14 28#define JZ4775_DMA_UART0_RX 0x15 29#define JZ4775_DMA_SSI0_TX 0x16 30#define JZ4775_DMA_SSI0_RX 0x17 31#define JZ4775_DMA_MSC0_TX 0x1a 32#define JZ4775_DMA_MSC0_RX 0x1b 33#define JZ4775_DMA_MSC1_TX 0x1c 34#define JZ4775_DMA_MSC1_RX 0x1d 35#define JZ4775_DMA_MSC2_TX 0x1e 36#define JZ4775_DMA_MSC2_RX 0x1f 37#define JZ4775_DMA_PCM0_TX 0x20 38#define JZ4775_DMA_PCM0_RX 0x21 39#define JZ4775_DMA_SMB0_TX 0x24 40#define JZ4775_DMA_SMB0_RX 0x25 41#define JZ4775_DMA_SMB1_TX 0x26 42#define JZ4775_DMA_SMB1_RX 0x27 43#define JZ4775_DMA_SMB2_TX 0x28 44#define JZ4775_DMA_SMB2_RX 0x29 45 46#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */ 47