1/* $NetBSD: s5pv210.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 6 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 7 * 8 * Device Tree binding constants for Samsung S5PV210 clock controller. 9 */ 10 11#ifndef _DT_BINDINGS_CLOCK_S5PV210_H 12#define _DT_BINDINGS_CLOCK_S5PV210_H 13 14/* Core clocks. */ 15#define FIN_PLL 1 16#define FOUT_APLL 2 17#define FOUT_MPLL 3 18#define FOUT_EPLL 4 19#define FOUT_VPLL 5 20 21/* Muxes. */ 22#define MOUT_FLASH 6 23#define MOUT_PSYS 7 24#define MOUT_DSYS 8 25#define MOUT_MSYS 9 26#define MOUT_VPLL 10 27#define MOUT_EPLL 11 28#define MOUT_MPLL 12 29#define MOUT_APLL 13 30#define MOUT_VPLLSRC 14 31#define MOUT_CSIS 15 32#define MOUT_FIMD 16 33#define MOUT_CAM1 17 34#define MOUT_CAM0 18 35#define MOUT_DAC 19 36#define MOUT_MIXER 20 37#define MOUT_HDMI 21 38#define MOUT_G2D 22 39#define MOUT_MFC 23 40#define MOUT_G3D 24 41#define MOUT_FIMC2 25 42#define MOUT_FIMC1 26 43#define MOUT_FIMC0 27 44#define MOUT_UART3 28 45#define MOUT_UART2 29 46#define MOUT_UART1 30 47#define MOUT_UART0 31 48#define MOUT_MMC3 32 49#define MOUT_MMC2 33 50#define MOUT_MMC1 34 51#define MOUT_MMC0 35 52#define MOUT_PWM 36 53#define MOUT_SPI0 37 54#define MOUT_SPI1 38 55#define MOUT_DMC0 39 56#define MOUT_PWI 40 57#define MOUT_HPM 41 58#define MOUT_SPDIF 42 59#define MOUT_AUDIO2 43 60#define MOUT_AUDIO1 44 61#define MOUT_AUDIO0 45 62 63/* Dividers. */ 64#define DOUT_PCLKP 46 65#define DOUT_HCLKP 47 66#define DOUT_PCLKD 48 67#define DOUT_HCLKD 49 68#define DOUT_PCLKM 50 69#define DOUT_HCLKM 51 70#define DOUT_A2M 52 71#define DOUT_APLL 53 72#define DOUT_CSIS 54 73#define DOUT_FIMD 55 74#define DOUT_CAM1 56 75#define DOUT_CAM0 57 76#define DOUT_TBLK 58 77#define DOUT_G2D 59 78#define DOUT_MFC 60 79#define DOUT_G3D 61 80#define DOUT_FIMC2 62 81#define DOUT_FIMC1 63 82#define DOUT_FIMC0 64 83#define DOUT_UART3 65 84#define DOUT_UART2 66 85#define DOUT_UART1 67 86#define DOUT_UART0 68 87#define DOUT_MMC3 69 88#define DOUT_MMC2 70 89#define DOUT_MMC1 71 90#define DOUT_MMC0 72 91#define DOUT_PWM 73 92#define DOUT_SPI1 74 93#define DOUT_SPI0 75 94#define DOUT_DMC0 76 95#define DOUT_PWI 77 96#define DOUT_HPM 78 97#define DOUT_COPY 79 98#define DOUT_FLASH 80 99#define DOUT_AUDIO2 81 100#define DOUT_AUDIO1 82 101#define DOUT_AUDIO0 83 102#define DOUT_DPM 84 103#define DOUT_DVSEM 85 104 105/* Gates */ 106#define SCLK_FIMC 86 107#define CLK_CSIS 87 108#define CLK_ROTATOR 88 109#define CLK_FIMC2 89 110#define CLK_FIMC1 90 111#define CLK_FIMC0 91 112#define CLK_MFC 92 113#define CLK_G2D 93 114#define CLK_G3D 94 115#define CLK_IMEM 95 116#define CLK_PDMA1 96 117#define CLK_PDMA0 97 118#define CLK_MDMA 98 119#define CLK_DMC1 99 120#define CLK_DMC0 100 121#define CLK_NFCON 101 122#define CLK_SROMC 102 123#define CLK_CFCON 103 124#define CLK_NANDXL 104 125#define CLK_USB_HOST 105 126#define CLK_USB_OTG 106 127#define CLK_HDMI 107 128#define CLK_TVENC 108 129#define CLK_MIXER 109 130#define CLK_VP 110 131#define CLK_DSIM 111 132#define CLK_FIMD 112 133#define CLK_TZIC3 113 134#define CLK_TZIC2 114 135#define CLK_TZIC1 115 136#define CLK_TZIC0 116 137#define CLK_VIC3 117 138#define CLK_VIC2 118 139#define CLK_VIC1 119 140#define CLK_VIC0 120 141#define CLK_TSI 121 142#define CLK_HSMMC3 122 143#define CLK_HSMMC2 123 144#define CLK_HSMMC1 124 145#define CLK_HSMMC0 125 146#define CLK_JTAG 126 147#define CLK_MODEMIF 127 148#define CLK_CORESIGHT 128 149#define CLK_SDM 129 150#define CLK_SECSS 130 151#define CLK_PCM2 131 152#define CLK_PCM1 132 153#define CLK_PCM0 133 154#define CLK_SYSCON 134 155#define CLK_GPIO 135 156#define CLK_TSADC 136 157#define CLK_PWM 137 158#define CLK_WDT 138 159#define CLK_KEYIF 139 160#define CLK_UART3 140 161#define CLK_UART2 141 162#define CLK_UART1 142 163#define CLK_UART0 143 164#define CLK_SYSTIMER 144 165#define CLK_RTC 145 166#define CLK_SPI1 146 167#define CLK_SPI0 147 168#define CLK_I2C_HDMI_PHY 148 169#define CLK_I2C1 149 170#define CLK_I2C2 150 171#define CLK_I2C0 151 172#define CLK_I2S1 152 173#define CLK_I2S2 153 174#define CLK_I2S0 154 175#define CLK_AC97 155 176#define CLK_SPDIF 156 177#define CLK_TZPC3 157 178#define CLK_TZPC2 158 179#define CLK_TZPC1 159 180#define CLK_TZPC0 160 181#define CLK_SECKEY 161 182#define CLK_IEM_APC 162 183#define CLK_IEM_IEC 163 184#define CLK_CHIPID 164 185#define CLK_JPEG 163 186 187/* Special clocks*/ 188#define SCLK_PWI 164 189#define SCLK_SPDIF 165 190#define SCLK_AUDIO2 166 191#define SCLK_AUDIO1 167 192#define SCLK_AUDIO0 168 193#define SCLK_PWM 169 194#define SCLK_SPI1 170 195#define SCLK_SPI0 171 196#define SCLK_UART3 172 197#define SCLK_UART2 173 198#define SCLK_UART1 174 199#define SCLK_UART0 175 200#define SCLK_MMC3 176 201#define SCLK_MMC2 177 202#define SCLK_MMC1 178 203#define SCLK_MMC0 179 204#define SCLK_FINVPLL 180 205#define SCLK_CSIS 181 206#define SCLK_FIMD 182 207#define SCLK_CAM1 183 208#define SCLK_CAM0 184 209#define SCLK_DAC 185 210#define SCLK_MIXER 186 211#define SCLK_HDMI 187 212#define SCLK_FIMC2 188 213#define SCLK_FIMC1 189 214#define SCLK_FIMC0 190 215#define SCLK_HDMI27M 191 216#define SCLK_HDMIPHY 192 217#define SCLK_USBPHY0 193 218#define SCLK_USBPHY1 194 219 220/* S5P6442-specific clocks */ 221#define MOUT_D0SYNC 195 222#define MOUT_D1SYNC 196 223#define DOUT_MIXER 197 224#define CLK_ETB 198 225#define CLK_ETM 199 226 227/* CLKOUT */ 228#define FOUT_APLL_CLKOUT 200 229#define FOUT_MPLL_CLKOUT 201 230#define DOUT_APLL_CLKOUT 202 231#define MOUT_CLKSEL 203 232#define DOUT_CLKOUT 204 233#define MOUT_CLKOUT 205 234 235/* Total number of clocks. */ 236#define NR_CLKS 206 237 238#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ 239