1/* $NetBSD: rv1108-cru.h,v 1.1.1.3 2020/01/03 14:33:05 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-or-later */ 4/* 5 * Copyright (c) 2016 Rockchip Electronics Co. Ltd. 6 * Author: Shawn Lin <shawn.lin@rock-chips.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H 11 12/* pll id */ 13#define PLL_APLL 0 14#define PLL_DPLL 1 15#define PLL_GPLL 2 16#define ARMCLK 3 17 18/* sclk gates (special clocks) */ 19#define SCLK_SPI0 65 20#define SCLK_NANDC 67 21#define SCLK_SDMMC 68 22#define SCLK_SDIO 69 23#define SCLK_EMMC 71 24#define SCLK_UART0 72 25#define SCLK_UART1 73 26#define SCLK_UART2 74 27#define SCLK_I2S0 75 28#define SCLK_I2S1 76 29#define SCLK_I2S2 77 30#define SCLK_TIMER0 78 31#define SCLK_TIMER1 79 32#define SCLK_SFC 80 33#define SCLK_SDMMC_DRV 81 34#define SCLK_SDIO_DRV 82 35#define SCLK_EMMC_DRV 83 36#define SCLK_SDMMC_SAMPLE 84 37#define SCLK_SDIO_SAMPLE 85 38#define SCLK_EMMC_SAMPLE 86 39#define SCLK_VENC_CORE 87 40#define SCLK_HEVC_CORE 88 41#define SCLK_HEVC_CABAC 89 42#define SCLK_PWM0_PMU 90 43#define SCLK_I2C0_PMU 91 44#define SCLK_WIFI 92 45#define SCLK_CIFOUT 93 46#define SCLK_MIPI_CSI_OUT 94 47#define SCLK_CIF0 95 48#define SCLK_CIF1 96 49#define SCLK_CIF2 97 50#define SCLK_CIF3 98 51#define SCLK_DSP 99 52#define SCLK_DSP_IOP 100 53#define SCLK_DSP_EPP 101 54#define SCLK_DSP_EDP 102 55#define SCLK_DSP_EDAP 103 56#define SCLK_CVBS_HOST 104 57#define SCLK_HDMI_SFR 105 58#define SCLK_HDMI_CEC 106 59#define SCLK_CRYPTO 107 60#define SCLK_SPI 108 61#define SCLK_SARADC 109 62#define SCLK_TSADC 110 63#define SCLK_MAC_PRE 111 64#define SCLK_MAC 112 65#define SCLK_MAC_RX 113 66#define SCLK_MAC_REF 114 67#define SCLK_MAC_REFOUT 115 68#define SCLK_DSP_PFM 116 69#define SCLK_RGA 117 70#define SCLK_I2C1 118 71#define SCLK_I2C2 119 72#define SCLK_I2C3 120 73#define SCLK_PWM 121 74#define SCLK_ISP 122 75#define SCLK_USBPHY 123 76#define SCLK_I2S0_SRC 124 77#define SCLK_I2S1_SRC 125 78#define SCLK_I2S2_SRC 126 79#define SCLK_UART0_SRC 127 80#define SCLK_UART1_SRC 128 81#define SCLK_UART2_SRC 129 82 83#define DCLK_VOP_SRC 185 84#define DCLK_HDMIPHY 186 85#define DCLK_VOP 187 86 87/* aclk gates */ 88#define ACLK_DMAC 192 89#define ACLK_PRE 193 90#define ACLK_CORE 194 91#define ACLK_ENMCORE 195 92#define ACLK_RKVENC 196 93#define ACLK_RKVDEC 197 94#define ACLK_VPU 198 95#define ACLK_CIF0 199 96#define ACLK_VIO0 200 97#define ACLK_VIO1 201 98#define ACLK_VOP 202 99#define ACLK_IEP 203 100#define ACLK_RGA 204 101#define ACLK_ISP 205 102#define ACLK_CIF1 206 103#define ACLK_CIF2 207 104#define ACLK_CIF3 208 105#define ACLK_PERI 209 106#define ACLK_GMAC 210 107 108/* pclk gates */ 109#define PCLK_GPIO1 256 110#define PCLK_GPIO2 257 111#define PCLK_GPIO3 258 112#define PCLK_GRF 259 113#define PCLK_I2C1 260 114#define PCLK_I2C2 261 115#define PCLK_I2C3 262 116#define PCLK_SPI 263 117#define PCLK_SFC 264 118#define PCLK_UART0 265 119#define PCLK_UART1 266 120#define PCLK_UART2 267 121#define PCLK_TSADC 268 122#define PCLK_PWM 269 123#define PCLK_TIMER 270 124#define PCLK_PERI 271 125#define PCLK_GPIO0_PMU 272 126#define PCLK_I2C0_PMU 273 127#define PCLK_PWM0_PMU 274 128#define PCLK_ISP 275 129#define PCLK_VIO 276 130#define PCLK_MIPI_DSI 277 131#define PCLK_HDMI_CTRL 278 132#define PCLK_SARADC 279 133#define PCLK_DSP_CFG 280 134#define PCLK_BUS 281 135#define PCLK_EFUSE0 282 136#define PCLK_EFUSE1 283 137#define PCLK_WDT 284 138#define PCLK_GMAC 285 139 140/* hclk gates */ 141#define HCLK_I2S0_8CH 320 142#define HCLK_I2S1_2CH 321 143#define HCLK_I2S2_2CH 322 144#define HCLK_NANDC 323 145#define HCLK_SDMMC 324 146#define HCLK_SDIO 325 147#define HCLK_EMMC 326 148#define HCLK_PERI 327 149#define HCLK_SFC 328 150#define HCLK_RKVENC 329 151#define HCLK_RKVDEC 330 152#define HCLK_CIF0 331 153#define HCLK_VIO 332 154#define HCLK_VOP 333 155#define HCLK_IEP 334 156#define HCLK_RGA 335 157#define HCLK_ISP 336 158#define HCLK_CRYPTO_MST 337 159#define HCLK_CRYPTO_SLV 338 160#define HCLK_HOST0 339 161#define HCLK_OTG 340 162#define HCLK_CIF1 341 163#define HCLK_CIF2 342 164#define HCLK_CIF3 343 165#define HCLK_BUS 344 166#define HCLK_VPU 345 167 168#define CLK_NR_CLKS (HCLK_VPU + 1) 169 170/* reset id */ 171#define SRST_CORE_PO_AD 0 172#define SRST_CORE_AD 1 173#define SRST_L2_AD 2 174#define SRST_CPU_NIU_AD 3 175#define SRST_CORE_PO 4 176#define SRST_CORE 5 177#define SRST_L2 6 178#define SRST_CORE_DBG 8 179#define PRST_DBG 9 180#define RST_DAP 10 181#define PRST_DBG_NIU 11 182#define ARST_STRC_SYS_AD 15 183 184#define SRST_DDRPHY_CLKDIV 16 185#define SRST_DDRPHY 17 186#define PRST_DDRPHY 18 187#define PRST_HDMIPHY 19 188#define PRST_VDACPHY 20 189#define PRST_VADCPHY 21 190#define PRST_MIPI_CSI_PHY 22 191#define PRST_MIPI_DSI_PHY 23 192#define PRST_ACODEC 24 193#define ARST_BUS_NIU 25 194#define PRST_TOP_NIU 26 195#define ARST_INTMEM 27 196#define HRST_ROM 28 197#define ARST_DMAC 29 198#define SRST_MSCH_NIU 30 199#define PRST_MSCH_NIU 31 200 201#define PRST_DDRUPCTL 32 202#define NRST_DDRUPCTL 33 203#define PRST_DDRMON 34 204#define HRST_I2S0_8CH 35 205#define MRST_I2S0_8CH 36 206#define HRST_I2S1_2CH 37 207#define MRST_IS21_2CH 38 208#define HRST_I2S2_2CH 39 209#define MRST_I2S2_2CH 40 210#define HRST_CRYPTO 41 211#define SRST_CRYPTO 42 212#define PRST_SPI 43 213#define SRST_SPI 44 214#define PRST_UART0 45 215#define PRST_UART1 46 216#define PRST_UART2 47 217 218#define SRST_UART0 48 219#define SRST_UART1 49 220#define SRST_UART2 50 221#define PRST_I2C1 51 222#define PRST_I2C2 52 223#define PRST_I2C3 53 224#define SRST_I2C1 54 225#define SRST_I2C2 55 226#define SRST_I2C3 56 227#define PRST_PWM1 58 228#define SRST_PWM1 60 229#define PRST_WDT 61 230#define PRST_GPIO1 62 231#define PRST_GPIO2 63 232 233#define PRST_GPIO3 64 234#define PRST_GRF 65 235#define PRST_EFUSE 66 236#define PRST_EFUSE512 67 237#define PRST_TIMER0 68 238#define SRST_TIMER0 69 239#define SRST_TIMER1 70 240#define PRST_TSADC 71 241#define SRST_TSADC 72 242#define PRST_SARADC 73 243#define SRST_SARADC 74 244#define HRST_SYSBUS 75 245#define PRST_USBGRF 76 246 247#define ARST_PERIPH_NIU 80 248#define HRST_PERIPH_NIU 81 249#define PRST_PERIPH_NIU 82 250#define HRST_PERIPH 83 251#define HRST_SDMMC 84 252#define HRST_SDIO 85 253#define HRST_EMMC 86 254#define HRST_NANDC 87 255#define NRST_NANDC 88 256#define HRST_SFC 89 257#define SRST_SFC 90 258#define ARST_GMAC 91 259#define HRST_OTG 92 260#define SRST_OTG 93 261#define SRST_OTG_ADP 94 262#define HRST_HOST0 95 263 264#define HRST_HOST0_AUX 96 265#define HRST_HOST0_ARB 97 266#define SRST_HOST0_EHCIPHY 98 267#define SRST_HOST0_UTMI 99 268#define SRST_USBPOR 100 269#define SRST_UTMI0 101 270#define SRST_UTMI1 102 271 272#define ARST_VIO0_NIU 102 273#define ARST_VIO1_NIU 103 274#define HRST_VIO_NIU 104 275#define PRST_VIO_NIU 105 276#define ARST_VOP 106 277#define HRST_VOP 107 278#define DRST_VOP 108 279#define ARST_IEP 109 280#define HRST_IEP 110 281#define ARST_RGA 111 282#define HRST_RGA 112 283#define SRST_RGA 113 284#define PRST_CVBS 114 285#define PRST_HDMI 115 286#define SRST_HDMI 116 287#define PRST_MIPI_DSI 117 288 289#define ARST_ISP_NIU 118 290#define HRST_ISP_NIU 119 291#define HRST_ISP 120 292#define SRST_ISP 121 293#define ARST_VIP0 122 294#define HRST_VIP0 123 295#define PRST_VIP0 124 296#define ARST_VIP1 125 297#define HRST_VIP1 126 298#define PRST_VIP1 127 299#define ARST_VIP2 128 300#define HRST_VIP2 129 301#define PRST_VIP2 120 302#define ARST_VIP3 121 303#define HRST_VIP3 122 304#define PRST_VIP4 123 305 306#define PRST_CIF1TO4 124 307#define SRST_CVBS_CLK 125 308#define HRST_CVBS 126 309 310#define ARST_VPU_NIU 140 311#define HRST_VPU_NIU 141 312#define ARST_VPU 142 313#define HRST_VPU 143 314#define ARST_RKVDEC_NIU 144 315#define HRST_RKVDEC_NIU 145 316#define ARST_RKVDEC 146 317#define HRST_RKVDEC 147 318#define SRST_RKVDEC_CABAC 148 319#define SRST_RKVDEC_CORE 149 320#define ARST_RKVENC_NIU 150 321#define HRST_RKVENC_NIU 151 322#define ARST_RKVENC 152 323#define HRST_RKVENC 153 324#define SRST_RKVENC_CORE 154 325 326#define SRST_DSP_CORE 156 327#define SRST_DSP_SYS 157 328#define SRST_DSP_GLOBAL 158 329#define SRST_DSP_OECM 159 330#define PRST_DSP_IOP_NIU 160 331#define ARST_DSP_EPP_NIU 161 332#define ARST_DSP_EDP_NIU 162 333#define PRST_DSP_DBG_NIU 163 334#define PRST_DSP_CFG_NIU 164 335#define PRST_DSP_GRF 165 336#define PRST_DSP_MAILBOX 166 337#define PRST_DSP_INTC 167 338#define PRST_DSP_PFM_MON 169 339#define SRST_DSP_PFM_MON 170 340#define ARST_DSP_EDAP_NIU 171 341 342#define SRST_PMU 172 343#define SRST_PMU_I2C0 173 344#define PRST_PMU_I2C0 174 345#define PRST_PMU_GPIO0 175 346#define PRST_PMU_INTMEM 176 347#define PRST_PMU_PWM0 177 348#define SRST_PMU_PWM0 178 349#define PRST_PMU_GRF 179 350#define SRST_PMU_NIU 180 351#define SRST_PMU_PVTM 181 352#define ARST_DSP_EDP_PERF 184 353#define ARST_DSP_EPP_PERF 185 354 355#endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */ 356