1/* $NetBSD: rk3568-cru.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 * Author: Elaine Zhang <zhangqing@rock-chips.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RK3568_H 11 12/* pmucru-clocks indices */ 13 14/* pmucru plls */ 15#define PLL_PPLL 1 16#define PLL_HPLL 2 17 18/* pmucru clocks */ 19#define XIN_OSC0_DIV 4 20#define CLK_RTC_32K 5 21#define CLK_PMU 6 22#define CLK_I2C0 7 23#define CLK_RTC32K_FRAC 8 24#define CLK_UART0_DIV 9 25#define CLK_UART0_FRAC 10 26#define SCLK_UART0 11 27#define DBCLK_GPIO0 12 28#define CLK_PWM0 13 29#define CLK_CAPTURE_PWM0_NDFT 14 30#define CLK_PMUPVTM 15 31#define CLK_CORE_PMUPVTM 16 32#define CLK_REF24M 17 33#define XIN_OSC0_USBPHY0_G 18 34#define CLK_USBPHY0_REF 19 35#define XIN_OSC0_USBPHY1_G 20 36#define CLK_USBPHY1_REF 21 37#define XIN_OSC0_MIPIDSIPHY0_G 22 38#define CLK_MIPIDSIPHY0_REF 23 39#define XIN_OSC0_MIPIDSIPHY1_G 24 40#define CLK_MIPIDSIPHY1_REF 25 41#define CLK_WIFI_DIV 26 42#define CLK_WIFI_OSC0 27 43#define CLK_WIFI 28 44#define CLK_PCIEPHY0_DIV 29 45#define CLK_PCIEPHY0_OSC0 30 46#define CLK_PCIEPHY0_REF 31 47#define CLK_PCIEPHY1_DIV 32 48#define CLK_PCIEPHY1_OSC0 33 49#define CLK_PCIEPHY1_REF 34 50#define CLK_PCIEPHY2_DIV 35 51#define CLK_PCIEPHY2_OSC0 36 52#define CLK_PCIEPHY2_REF 37 53#define CLK_PCIE30PHY_REF_M 38 54#define CLK_PCIE30PHY_REF_N 39 55#define CLK_HDMI_REF 40 56#define XIN_OSC0_EDPPHY_G 41 57#define PCLK_PDPMU 42 58#define PCLK_PMU 43 59#define PCLK_UART0 44 60#define PCLK_I2C0 45 61#define PCLK_GPIO0 46 62#define PCLK_PMUPVTM 47 63#define PCLK_PWM0 48 64#define CLK_PDPMU 49 65#define SCLK_32K_IOE 50 66 67#define CLKPMU_NR_CLKS (SCLK_32K_IOE + 1) 68 69/* cru-clocks indices */ 70 71/* cru plls */ 72#define PLL_APLL 1 73#define PLL_DPLL 2 74#define PLL_CPLL 3 75#define PLL_GPLL 4 76#define PLL_VPLL 5 77#define PLL_NPLL 6 78 79/* cru clocks */ 80#define CPLL_333M 9 81#define ARMCLK 10 82#define USB480M 11 83#define ACLK_CORE_NIU2BUS 18 84#define CLK_CORE_PVTM 19 85#define CLK_CORE_PVTM_CORE 20 86#define CLK_CORE_PVTPLL 21 87#define CLK_GPU_SRC 22 88#define CLK_GPU_PRE_NDFT 23 89#define CLK_GPU_PRE_MUX 24 90#define ACLK_GPU_PRE 25 91#define PCLK_GPU_PRE 26 92#define CLK_GPU 27 93#define CLK_GPU_NP5 28 94#define PCLK_GPU_PVTM 29 95#define CLK_GPU_PVTM 30 96#define CLK_GPU_PVTM_CORE 31 97#define CLK_GPU_PVTPLL 32 98#define CLK_NPU_SRC 33 99#define CLK_NPU_PRE_NDFT 34 100#define CLK_NPU 35 101#define CLK_NPU_NP5 36 102#define HCLK_NPU_PRE 37 103#define PCLK_NPU_PRE 38 104#define ACLK_NPU_PRE 39 105#define ACLK_NPU 40 106#define HCLK_NPU 41 107#define PCLK_NPU_PVTM 42 108#define CLK_NPU_PVTM 43 109#define CLK_NPU_PVTM_CORE 44 110#define CLK_NPU_PVTPLL 45 111#define CLK_DDRPHY1X_SRC 46 112#define CLK_DDRPHY1X_HWFFC_SRC 47 113#define CLK_DDR1X 48 114#define CLK_MSCH 49 115#define CLK24_DDRMON 50 116#define ACLK_GIC_AUDIO 51 117#define HCLK_GIC_AUDIO 52 118#define HCLK_SDMMC_BUFFER 53 119#define DCLK_SDMMC_BUFFER 54 120#define ACLK_GIC600 55 121#define ACLK_SPINLOCK 56 122#define HCLK_I2S0_8CH 57 123#define HCLK_I2S1_8CH 58 124#define HCLK_I2S2_2CH 59 125#define HCLK_I2S3_2CH 60 126#define CLK_I2S0_8CH_TX_SRC 61 127#define CLK_I2S0_8CH_TX_FRAC 62 128#define MCLK_I2S0_8CH_TX 63 129#define I2S0_MCLKOUT_TX 64 130#define CLK_I2S0_8CH_RX_SRC 65 131#define CLK_I2S0_8CH_RX_FRAC 66 132#define MCLK_I2S0_8CH_RX 67 133#define I2S0_MCLKOUT_RX 68 134#define CLK_I2S1_8CH_TX_SRC 69 135#define CLK_I2S1_8CH_TX_FRAC 70 136#define MCLK_I2S1_8CH_TX 71 137#define I2S1_MCLKOUT_TX 72 138#define CLK_I2S1_8CH_RX_SRC 73 139#define CLK_I2S1_8CH_RX_FRAC 74 140#define MCLK_I2S1_8CH_RX 75 141#define I2S1_MCLKOUT_RX 76 142#define CLK_I2S2_2CH_SRC 77 143#define CLK_I2S2_2CH_FRAC 78 144#define MCLK_I2S2_2CH 79 145#define I2S2_MCLKOUT 80 146#define CLK_I2S3_2CH_TX_SRC 81 147#define CLK_I2S3_2CH_TX_FRAC 82 148#define MCLK_I2S3_2CH_TX 83 149#define I2S3_MCLKOUT_TX 84 150#define CLK_I2S3_2CH_RX_SRC 85 151#define CLK_I2S3_2CH_RX_FRAC 86 152#define MCLK_I2S3_2CH_RX 87 153#define I2S3_MCLKOUT_RX 88 154#define HCLK_PDM 89 155#define MCLK_PDM 90 156#define HCLK_VAD 91 157#define HCLK_SPDIF_8CH 92 158#define MCLK_SPDIF_8CH_SRC 93 159#define MCLK_SPDIF_8CH_FRAC 94 160#define MCLK_SPDIF_8CH 95 161#define HCLK_AUDPWM 96 162#define SCLK_AUDPWM_SRC 97 163#define SCLK_AUDPWM_FRAC 98 164#define SCLK_AUDPWM 99 165#define HCLK_ACDCDIG 100 166#define CLK_ACDCDIG_I2C 101 167#define CLK_ACDCDIG_DAC 102 168#define CLK_ACDCDIG_ADC 103 169#define ACLK_SECURE_FLASH 104 170#define HCLK_SECURE_FLASH 105 171#define ACLK_CRYPTO_NS 106 172#define HCLK_CRYPTO_NS 107 173#define CLK_CRYPTO_NS_CORE 108 174#define CLK_CRYPTO_NS_PKA 109 175#define CLK_CRYPTO_NS_RNG 110 176#define HCLK_TRNG_NS 111 177#define CLK_TRNG_NS 112 178#define PCLK_OTPC_NS 113 179#define CLK_OTPC_NS_SBPI 114 180#define CLK_OTPC_NS_USR 115 181#define HCLK_NANDC 116 182#define NCLK_NANDC 117 183#define HCLK_SFC 118 184#define HCLK_SFC_XIP 119 185#define SCLK_SFC 120 186#define ACLK_EMMC 121 187#define HCLK_EMMC 122 188#define BCLK_EMMC 123 189#define CCLK_EMMC 124 190#define TCLK_EMMC 125 191#define ACLK_PIPE 126 192#define PCLK_PIPE 127 193#define PCLK_PIPE_GRF 128 194#define ACLK_PCIE20_MST 129 195#define ACLK_PCIE20_SLV 130 196#define ACLK_PCIE20_DBI 131 197#define PCLK_PCIE20 132 198#define CLK_PCIE20_AUX_NDFT 133 199#define CLK_PCIE20_AUX_DFT 134 200#define CLK_PCIE20_PIPE_DFT 135 201#define ACLK_PCIE30X1_MST 136 202#define ACLK_PCIE30X1_SLV 137 203#define ACLK_PCIE30X1_DBI 138 204#define PCLK_PCIE30X1 139 205#define CLK_PCIE30X1_AUX_NDFT 140 206#define CLK_PCIE30X1_AUX_DFT 141 207#define CLK_PCIE30X1_PIPE_DFT 142 208#define ACLK_PCIE30X2_MST 143 209#define ACLK_PCIE30X2_SLV 144 210#define ACLK_PCIE30X2_DBI 145 211#define PCLK_PCIE30X2 146 212#define CLK_PCIE30X2_AUX_NDFT 147 213#define CLK_PCIE30X2_AUX_DFT 148 214#define CLK_PCIE30X2_PIPE_DFT 149 215#define ACLK_SATA0 150 216#define CLK_SATA0_PMALIVE 151 217#define CLK_SATA0_RXOOB 152 218#define CLK_SATA0_PIPE_NDFT 153 219#define CLK_SATA0_PIPE_DFT 154 220#define ACLK_SATA1 155 221#define CLK_SATA1_PMALIVE 156 222#define CLK_SATA1_RXOOB 157 223#define CLK_SATA1_PIPE_NDFT 158 224#define CLK_SATA1_PIPE_DFT 159 225#define ACLK_SATA2 160 226#define CLK_SATA2_PMALIVE 161 227#define CLK_SATA2_RXOOB 162 228#define CLK_SATA2_PIPE_NDFT 163 229#define CLK_SATA2_PIPE_DFT 164 230#define ACLK_USB3OTG0 165 231#define CLK_USB3OTG0_REF 166 232#define CLK_USB3OTG0_SUSPEND 167 233#define ACLK_USB3OTG1 168 234#define CLK_USB3OTG1_REF 169 235#define CLK_USB3OTG1_SUSPEND 170 236#define CLK_XPCS_EEE 171 237#define PCLK_XPCS 172 238#define ACLK_PHP 173 239#define HCLK_PHP 174 240#define PCLK_PHP 175 241#define HCLK_SDMMC0 176 242#define CLK_SDMMC0 177 243#define HCLK_SDMMC1 178 244#define CLK_SDMMC1 179 245#define ACLK_GMAC0 180 246#define PCLK_GMAC0 181 247#define CLK_MAC0_2TOP 182 248#define CLK_MAC0_OUT 183 249#define CLK_MAC0_REFOUT 184 250#define CLK_GMAC0_PTP_REF 185 251#define ACLK_USB 186 252#define HCLK_USB 187 253#define PCLK_USB 188 254#define HCLK_USB2HOST0 189 255#define HCLK_USB2HOST0_ARB 190 256#define HCLK_USB2HOST1 191 257#define HCLK_USB2HOST1_ARB 192 258#define HCLK_SDMMC2 193 259#define CLK_SDMMC2 194 260#define ACLK_GMAC1 195 261#define PCLK_GMAC1 196 262#define CLK_MAC1_2TOP 197 263#define CLK_MAC1_OUT 198 264#define CLK_MAC1_REFOUT 199 265#define CLK_GMAC1_PTP_REF 200 266#define ACLK_PERIMID 201 267#define HCLK_PERIMID 202 268#define ACLK_VI 203 269#define HCLK_VI 204 270#define PCLK_VI 205 271#define ACLK_VICAP 206 272#define HCLK_VICAP 207 273#define DCLK_VICAP 208 274#define ICLK_VICAP_G 209 275#define ACLK_ISP 210 276#define HCLK_ISP 211 277#define CLK_ISP 212 278#define PCLK_CSI2HOST1 213 279#define CLK_CIF_OUT 214 280#define CLK_CAM0_OUT 215 281#define CLK_CAM1_OUT 216 282#define ACLK_VO 217 283#define HCLK_VO 218 284#define PCLK_VO 219 285#define ACLK_VOP_PRE 220 286#define ACLK_VOP 221 287#define HCLK_VOP 222 288#define DCLK_VOP0 223 289#define DCLK_VOP1 224 290#define DCLK_VOP2 225 291#define CLK_VOP_PWM 226 292#define ACLK_HDCP 227 293#define HCLK_HDCP 228 294#define PCLK_HDCP 229 295#define PCLK_HDMI_HOST 230 296#define CLK_HDMI_SFR 231 297#define PCLK_DSITX_0 232 298#define PCLK_DSITX_1 233 299#define PCLK_EDP_CTRL 234 300#define CLK_EDP_200M 235 301#define ACLK_VPU_PRE 236 302#define HCLK_VPU_PRE 237 303#define ACLK_VPU 238 304#define HCLK_VPU 239 305#define ACLK_RGA_PRE 240 306#define HCLK_RGA_PRE 241 307#define PCLK_RGA_PRE 242 308#define ACLK_RGA 243 309#define HCLK_RGA 244 310#define CLK_RGA_CORE 245 311#define ACLK_IEP 246 312#define HCLK_IEP 247 313#define CLK_IEP_CORE 248 314#define HCLK_EBC 249 315#define DCLK_EBC 250 316#define ACLK_JDEC 251 317#define HCLK_JDEC 252 318#define ACLK_JENC 253 319#define HCLK_JENC 254 320#define PCLK_EINK 255 321#define HCLK_EINK 256 322#define ACLK_RKVENC_PRE 257 323#define HCLK_RKVENC_PRE 258 324#define ACLK_RKVENC 259 325#define HCLK_RKVENC 260 326#define CLK_RKVENC_CORE 261 327#define ACLK_RKVDEC_PRE 262 328#define HCLK_RKVDEC_PRE 263 329#define ACLK_RKVDEC 264 330#define HCLK_RKVDEC 265 331#define CLK_RKVDEC_CA 266 332#define CLK_RKVDEC_CORE 267 333#define CLK_RKVDEC_HEVC_CA 268 334#define ACLK_BUS 269 335#define PCLK_BUS 270 336#define PCLK_TSADC 271 337#define CLK_TSADC_TSEN 272 338#define CLK_TSADC 273 339#define PCLK_SARADC 274 340#define CLK_SARADC 275 341#define PCLK_SCR 276 342#define PCLK_WDT_NS 277 343#define TCLK_WDT_NS 278 344#define ACLK_DMAC0 279 345#define ACLK_DMAC1 280 346#define ACLK_MCU 281 347#define PCLK_INTMUX 282 348#define PCLK_MAILBOX 283 349#define PCLK_UART1 284 350#define CLK_UART1_SRC 285 351#define CLK_UART1_FRAC 286 352#define SCLK_UART1 287 353#define PCLK_UART2 288 354#define CLK_UART2_SRC 289 355#define CLK_UART2_FRAC 290 356#define SCLK_UART2 291 357#define PCLK_UART3 292 358#define CLK_UART3_SRC 293 359#define CLK_UART3_FRAC 294 360#define SCLK_UART3 295 361#define PCLK_UART4 296 362#define CLK_UART4_SRC 297 363#define CLK_UART4_FRAC 298 364#define SCLK_UART4 299 365#define PCLK_UART5 300 366#define CLK_UART5_SRC 301 367#define CLK_UART5_FRAC 302 368#define SCLK_UART5 303 369#define PCLK_UART6 304 370#define CLK_UART6_SRC 305 371#define CLK_UART6_FRAC 306 372#define SCLK_UART6 307 373#define PCLK_UART7 308 374#define CLK_UART7_SRC 309 375#define CLK_UART7_FRAC 310 376#define SCLK_UART7 311 377#define PCLK_UART8 312 378#define CLK_UART8_SRC 313 379#define CLK_UART8_FRAC 314 380#define SCLK_UART8 315 381#define PCLK_UART9 316 382#define CLK_UART9_SRC 317 383#define CLK_UART9_FRAC 318 384#define SCLK_UART9 319 385#define PCLK_CAN0 320 386#define CLK_CAN0 321 387#define PCLK_CAN1 322 388#define CLK_CAN1 323 389#define PCLK_CAN2 324 390#define CLK_CAN2 325 391#define CLK_I2C 326 392#define PCLK_I2C1 327 393#define CLK_I2C1 328 394#define PCLK_I2C2 329 395#define CLK_I2C2 330 396#define PCLK_I2C3 331 397#define CLK_I2C3 332 398#define PCLK_I2C4 333 399#define CLK_I2C4 334 400#define PCLK_I2C5 335 401#define CLK_I2C5 336 402#define PCLK_SPI0 337 403#define CLK_SPI0 338 404#define PCLK_SPI1 339 405#define CLK_SPI1 340 406#define PCLK_SPI2 341 407#define CLK_SPI2 342 408#define PCLK_SPI3 343 409#define CLK_SPI3 344 410#define PCLK_PWM1 345 411#define CLK_PWM1 346 412#define CLK_PWM1_CAPTURE 347 413#define PCLK_PWM2 348 414#define CLK_PWM2 349 415#define CLK_PWM2_CAPTURE 350 416#define PCLK_PWM3 351 417#define CLK_PWM3 352 418#define CLK_PWM3_CAPTURE 353 419#define DBCLK_GPIO 354 420#define PCLK_GPIO1 355 421#define DBCLK_GPIO1 356 422#define PCLK_GPIO2 357 423#define DBCLK_GPIO2 358 424#define PCLK_GPIO3 359 425#define DBCLK_GPIO3 360 426#define PCLK_GPIO4 361 427#define DBCLK_GPIO4 362 428#define OCC_SCAN_CLK_GPIO 363 429#define PCLK_TIMER 364 430#define CLK_TIMER0 365 431#define CLK_TIMER1 366 432#define CLK_TIMER2 367 433#define CLK_TIMER3 368 434#define CLK_TIMER4 369 435#define CLK_TIMER5 370 436#define ACLK_TOP_HIGH 371 437#define ACLK_TOP_LOW 372 438#define HCLK_TOP 373 439#define PCLK_TOP 374 440#define PCLK_PCIE30PHY 375 441#define CLK_OPTC_ARB 376 442#define PCLK_MIPICSIPHY 377 443#define PCLK_MIPIDSIPHY0 378 444#define PCLK_MIPIDSIPHY1 379 445#define PCLK_PIPEPHY0 380 446#define PCLK_PIPEPHY1 381 447#define PCLK_PIPEPHY2 382 448#define PCLK_CPU_BOOST 383 449#define CLK_CPU_BOOST 384 450#define PCLK_OTPPHY 385 451#define SCLK_GMAC0 386 452#define SCLK_GMAC0_RGMII_SPEED 387 453#define SCLK_GMAC0_RMII_SPEED 388 454#define SCLK_GMAC0_RX_TX 389 455#define SCLK_GMAC1 390 456#define SCLK_GMAC1_RGMII_SPEED 391 457#define SCLK_GMAC1_RMII_SPEED 392 458#define SCLK_GMAC1_RX_TX 393 459#define SCLK_SDMMC0_DRV 394 460#define SCLK_SDMMC0_SAMPLE 395 461#define SCLK_SDMMC1_DRV 396 462#define SCLK_SDMMC1_SAMPLE 397 463#define SCLK_SDMMC2_DRV 398 464#define SCLK_SDMMC2_SAMPLE 399 465#define SCLK_EMMC_DRV 400 466#define SCLK_EMMC_SAMPLE 401 467#define PCLK_EDPPHY_GRF 402 468#define CLK_HDMI_CEC 403 469#define CLK_I2S0_8CH_TX 404 470#define CLK_I2S0_8CH_RX 405 471#define CLK_I2S1_8CH_TX 406 472#define CLK_I2S1_8CH_RX 407 473#define CLK_I2S2_2CH 408 474#define CLK_I2S3_2CH_TX 409 475#define CLK_I2S3_2CH_RX 410 476#define CPLL_500M 411 477#define CPLL_250M 412 478#define CPLL_125M 413 479#define CPLL_62P5M 414 480#define CPLL_50M 415 481#define CPLL_25M 416 482#define CPLL_100M 417 483#define SCLK_DDRCLK 418 484 485#define PCLK_CORE_PVTM 450 486 487#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1) 488 489/* pmu soft-reset indices */ 490/* pmucru_softrst_con0 */ 491#define SRST_P_PDPMU_NIU 0 492#define SRST_P_PMUCRU 1 493#define SRST_P_PMUGRF 2 494#define SRST_P_I2C0 3 495#define SRST_I2C0 4 496#define SRST_P_UART0 5 497#define SRST_S_UART0 6 498#define SRST_P_PWM0 7 499#define SRST_PWM0 8 500#define SRST_P_GPIO0 9 501#define SRST_GPIO0 10 502#define SRST_P_PMUPVTM 11 503#define SRST_PMUPVTM 12 504 505/* soft-reset indices */ 506 507/* cru_softrst_con0 */ 508#define SRST_NCORERESET0 0 509#define SRST_NCORERESET1 1 510#define SRST_NCORERESET2 2 511#define SRST_NCORERESET3 3 512#define SRST_NCPUPORESET0 4 513#define SRST_NCPUPORESET1 5 514#define SRST_NCPUPORESET2 6 515#define SRST_NCPUPORESET3 7 516#define SRST_NSRESET 8 517#define SRST_NSPORESET 9 518#define SRST_NATRESET 10 519#define SRST_NGICRESET 11 520#define SRST_NPRESET 12 521#define SRST_NPERIPHRESET 13 522 523/* cru_softrst_con1 */ 524#define SRST_A_CORE_NIU2DDR 16 525#define SRST_A_CORE_NIU2BUS 17 526#define SRST_P_DBG_NIU 18 527#define SRST_P_DBG 19 528#define SRST_P_DBG_DAPLITE 20 529#define SRST_DAP 21 530#define SRST_A_ADB400_CORE2GIC 22 531#define SRST_A_ADB400_GIC2CORE 23 532#define SRST_P_CORE_GRF 24 533#define SRST_P_CORE_PVTM 25 534#define SRST_CORE_PVTM 26 535#define SRST_CORE_PVTPLL 27 536 537/* cru_softrst_con2 */ 538#define SRST_GPU 32 539#define SRST_A_GPU_NIU 33 540#define SRST_P_GPU_NIU 34 541#define SRST_P_GPU_PVTM 35 542#define SRST_GPU_PVTM 36 543#define SRST_GPU_PVTPLL 37 544#define SRST_A_NPU_NIU 40 545#define SRST_H_NPU_NIU 41 546#define SRST_P_NPU_NIU 42 547#define SRST_A_NPU 43 548#define SRST_H_NPU 44 549#define SRST_P_NPU_PVTM 45 550#define SRST_NPU_PVTM 46 551#define SRST_NPU_PVTPLL 47 552 553/* cru_softrst_con3 */ 554#define SRST_A_MSCH 51 555#define SRST_HWFFC_CTRL 52 556#define SRST_DDR_ALWAYSON 53 557#define SRST_A_DDRSPLIT 54 558#define SRST_DDRDFI_CTL 55 559#define SRST_A_DMA2DDR 57 560 561/* cru_softrst_con4 */ 562#define SRST_A_PERIMID_NIU 64 563#define SRST_H_PERIMID_NIU 65 564#define SRST_A_GIC_AUDIO_NIU 66 565#define SRST_H_GIC_AUDIO_NIU 67 566#define SRST_A_GIC600 68 567#define SRST_A_GIC600_DEBUG 69 568#define SRST_A_GICADB_CORE2GIC 70 569#define SRST_A_GICADB_GIC2CORE 71 570#define SRST_A_SPINLOCK 72 571#define SRST_H_SDMMC_BUFFER 73 572#define SRST_D_SDMMC_BUFFER 74 573#define SRST_H_I2S0_8CH 75 574#define SRST_H_I2S1_8CH 76 575#define SRST_H_I2S2_2CH 77 576#define SRST_H_I2S3_2CH 78 577 578/* cru_softrst_con5 */ 579#define SRST_M_I2S0_8CH_TX 80 580#define SRST_M_I2S0_8CH_RX 81 581#define SRST_M_I2S1_8CH_TX 82 582#define SRST_M_I2S1_8CH_RX 83 583#define SRST_M_I2S2_2CH 84 584#define SRST_M_I2S3_2CH_TX 85 585#define SRST_M_I2S3_2CH_RX 86 586#define SRST_H_PDM 87 587#define SRST_M_PDM 88 588#define SRST_H_VAD 89 589#define SRST_H_SPDIF_8CH 90 590#define SRST_M_SPDIF_8CH 91 591#define SRST_H_AUDPWM 92 592#define SRST_S_AUDPWM 93 593#define SRST_H_ACDCDIG 94 594#define SRST_ACDCDIG 95 595 596/* cru_softrst_con6 */ 597#define SRST_A_SECURE_FLASH_NIU 96 598#define SRST_H_SECURE_FLASH_NIU 97 599#define SRST_A_CRYPTO_NS 103 600#define SRST_H_CRYPTO_NS 104 601#define SRST_CRYPTO_NS_CORE 105 602#define SRST_CRYPTO_NS_PKA 106 603#define SRST_CRYPTO_NS_RNG 107 604#define SRST_H_TRNG_NS 108 605#define SRST_TRNG_NS 109 606 607/* cru_softrst_con7 */ 608#define SRST_H_NANDC 112 609#define SRST_N_NANDC 113 610#define SRST_H_SFC 114 611#define SRST_H_SFC_XIP 115 612#define SRST_S_SFC 116 613#define SRST_A_EMMC 117 614#define SRST_H_EMMC 118 615#define SRST_B_EMMC 119 616#define SRST_C_EMMC 120 617#define SRST_T_EMMC 121 618 619/* cru_softrst_con8 */ 620#define SRST_A_PIPE_NIU 128 621#define SRST_P_PIPE_NIU 130 622#define SRST_P_PIPE_GRF 133 623#define SRST_A_SATA0 134 624#define SRST_SATA0_PIPE 135 625#define SRST_SATA0_PMALIVE 136 626#define SRST_SATA0_RXOOB 137 627#define SRST_A_SATA1 138 628#define SRST_SATA1_PIPE 139 629#define SRST_SATA1_PMALIVE 140 630#define SRST_SATA1_RXOOB 141 631 632/* cru_softrst_con9 */ 633#define SRST_A_SATA2 144 634#define SRST_SATA2_PIPE 145 635#define SRST_SATA2_PMALIVE 146 636#define SRST_SATA2_RXOOB 147 637#define SRST_USB3OTG0 148 638#define SRST_USB3OTG1 149 639#define SRST_XPCS 150 640#define SRST_XPCS_TX_DIV10 151 641#define SRST_XPCS_RX_DIV10 152 642#define SRST_XPCS_XGXS_RX 153 643 644/* cru_softrst_con10 */ 645#define SRST_P_PCIE20 160 646#define SRST_PCIE20_POWERUP 161 647#define SRST_MSTR_ARESET_PCIE20 162 648#define SRST_SLV_ARESET_PCIE20 163 649#define SRST_DBI_ARESET_PCIE20 164 650#define SRST_BRESET_PCIE20 165 651#define SRST_PERST_PCIE20 166 652#define SRST_CORE_RST_PCIE20 167 653#define SRST_NSTICKY_RST_PCIE20 168 654#define SRST_STICKY_RST_PCIE20 169 655#define SRST_PWR_RST_PCIE20 170 656 657/* cru_softrst_con11 */ 658#define SRST_P_PCIE30X1 176 659#define SRST_PCIE30X1_POWERUP 177 660#define SRST_M_ARESET_PCIE30X1 178 661#define SRST_S_ARESET_PCIE30X1 179 662#define SRST_D_ARESET_PCIE30X1 180 663#define SRST_BRESET_PCIE30X1 181 664#define SRST_PERST_PCIE30X1 182 665#define SRST_CORE_RST_PCIE30X1 183 666#define SRST_NSTC_RST_PCIE30X1 184 667#define SRST_STC_RST_PCIE30X1 185 668#define SRST_PWR_RST_PCIE30X1 186 669 670/* cru_softrst_con12 */ 671#define SRST_P_PCIE30X2 192 672#define SRST_PCIE30X2_POWERUP 193 673#define SRST_M_ARESET_PCIE30X2 194 674#define SRST_S_ARESET_PCIE30X2 195 675#define SRST_D_ARESET_PCIE30X2 196 676#define SRST_BRESET_PCIE30X2 197 677#define SRST_PERST_PCIE30X2 198 678#define SRST_CORE_RST_PCIE30X2 199 679#define SRST_NSTC_RST_PCIE30X2 200 680#define SRST_STC_RST_PCIE30X2 201 681#define SRST_PWR_RST_PCIE30X2 202 682 683/* cru_softrst_con13 */ 684#define SRST_A_PHP_NIU 208 685#define SRST_H_PHP_NIU 209 686#define SRST_P_PHP_NIU 210 687#define SRST_H_SDMMC0 211 688#define SRST_SDMMC0 212 689#define SRST_H_SDMMC1 213 690#define SRST_SDMMC1 214 691#define SRST_A_GMAC0 215 692#define SRST_GMAC0_TIMESTAMP 216 693 694/* cru_softrst_con14 */ 695#define SRST_A_USB_NIU 224 696#define SRST_H_USB_NIU 225 697#define SRST_P_USB_NIU 226 698#define SRST_P_USB_GRF 227 699#define SRST_H_USB2HOST0 228 700#define SRST_H_USB2HOST0_ARB 229 701#define SRST_USB2HOST0_UTMI 230 702#define SRST_H_USB2HOST1 231 703#define SRST_H_USB2HOST1_ARB 232 704#define SRST_USB2HOST1_UTMI 233 705#define SRST_H_SDMMC2 234 706#define SRST_SDMMC2 235 707#define SRST_A_GMAC1 236 708#define SRST_GMAC1_TIMESTAMP 237 709 710/* cru_softrst_con15 */ 711#define SRST_A_VI_NIU 240 712#define SRST_H_VI_NIU 241 713#define SRST_P_VI_NIU 242 714#define SRST_A_VICAP 247 715#define SRST_H_VICAP 248 716#define SRST_D_VICAP 249 717#define SRST_I_VICAP 250 718#define SRST_P_VICAP 251 719#define SRST_H_ISP 252 720#define SRST_ISP 253 721#define SRST_P_CSI2HOST1 255 722 723/* cru_softrst_con16 */ 724#define SRST_A_VO_NIU 256 725#define SRST_H_VO_NIU 257 726#define SRST_P_VO_NIU 258 727#define SRST_A_VOP_NIU 259 728#define SRST_A_VOP 260 729#define SRST_H_VOP 261 730#define SRST_VOP0 262 731#define SRST_VOP1 263 732#define SRST_VOP2 264 733#define SRST_VOP_PWM 265 734#define SRST_A_HDCP 266 735#define SRST_H_HDCP 267 736#define SRST_P_HDCP 268 737#define SRST_P_HDMI_HOST 270 738#define SRST_HDMI_HOST 271 739 740/* cru_softrst_con17 */ 741#define SRST_P_DSITX_0 272 742#define SRST_P_DSITX_1 273 743#define SRST_P_EDP_CTRL 274 744#define SRST_EDP_24M 275 745#define SRST_A_VPU_NIU 280 746#define SRST_H_VPU_NIU 281 747#define SRST_A_VPU 282 748#define SRST_H_VPU 283 749#define SRST_H_EINK 286 750#define SRST_P_EINK 287 751 752/* cru_softrst_con18 */ 753#define SRST_A_RGA_NIU 288 754#define SRST_H_RGA_NIU 289 755#define SRST_P_RGA_NIU 290 756#define SRST_A_RGA 292 757#define SRST_H_RGA 293 758#define SRST_RGA_CORE 294 759#define SRST_A_IEP 295 760#define SRST_H_IEP 296 761#define SRST_IEP_CORE 297 762#define SRST_H_EBC 298 763#define SRST_D_EBC 299 764#define SRST_A_JDEC 300 765#define SRST_H_JDEC 301 766#define SRST_A_JENC 302 767#define SRST_H_JENC 303 768 769/* cru_softrst_con19 */ 770#define SRST_A_VENC_NIU 304 771#define SRST_H_VENC_NIU 305 772#define SRST_A_RKVENC 307 773#define SRST_H_RKVENC 308 774#define SRST_RKVENC_CORE 309 775 776/* cru_softrst_con20 */ 777#define SRST_A_RKVDEC_NIU 320 778#define SRST_H_RKVDEC_NIU 321 779#define SRST_A_RKVDEC 322 780#define SRST_H_RKVDEC 323 781#define SRST_RKVDEC_CA 324 782#define SRST_RKVDEC_CORE 325 783#define SRST_RKVDEC_HEVC_CA 326 784 785/* cru_softrst_con21 */ 786#define SRST_A_BUS_NIU 336 787#define SRST_P_BUS_NIU 338 788#define SRST_P_CAN0 340 789#define SRST_CAN0 341 790#define SRST_P_CAN1 342 791#define SRST_CAN1 343 792#define SRST_P_CAN2 344 793#define SRST_CAN2 345 794#define SRST_P_GPIO1 346 795#define SRST_GPIO1 347 796#define SRST_P_GPIO2 348 797#define SRST_GPIO2 349 798#define SRST_P_GPIO3 350 799#define SRST_GPIO3 351 800 801/* cru_softrst_con22 */ 802#define SRST_P_GPIO4 352 803#define SRST_GPIO4 353 804#define SRST_P_I2C1 354 805#define SRST_I2C1 355 806#define SRST_P_I2C2 356 807#define SRST_I2C2 357 808#define SRST_P_I2C3 358 809#define SRST_I2C3 359 810#define SRST_P_I2C4 360 811#define SRST_I2C4 361 812#define SRST_P_I2C5 362 813#define SRST_I2C5 363 814#define SRST_P_OTPC_NS 364 815#define SRST_OTPC_NS_SBPI 365 816#define SRST_OTPC_NS_USR 366 817 818/* cru_softrst_con23 */ 819#define SRST_P_PWM1 368 820#define SRST_PWM1 369 821#define SRST_P_PWM2 370 822#define SRST_PWM2 371 823#define SRST_P_PWM3 372 824#define SRST_PWM3 373 825#define SRST_P_SPI0 374 826#define SRST_SPI0 375 827#define SRST_P_SPI1 376 828#define SRST_SPI1 377 829#define SRST_P_SPI2 378 830#define SRST_SPI2 379 831#define SRST_P_SPI3 380 832#define SRST_SPI3 381 833 834/* cru_softrst_con24 */ 835#define SRST_P_SARADC 384 836#define SRST_P_TSADC 385 837#define SRST_TSADC 386 838#define SRST_P_TIMER 387 839#define SRST_TIMER0 388 840#define SRST_TIMER1 389 841#define SRST_TIMER2 390 842#define SRST_TIMER3 391 843#define SRST_TIMER4 392 844#define SRST_TIMER5 393 845#define SRST_P_UART1 394 846#define SRST_S_UART1 395 847 848/* cru_softrst_con25 */ 849#define SRST_P_UART2 400 850#define SRST_S_UART2 401 851#define SRST_P_UART3 402 852#define SRST_S_UART3 403 853#define SRST_P_UART4 404 854#define SRST_S_UART4 405 855#define SRST_P_UART5 406 856#define SRST_S_UART5 407 857#define SRST_P_UART6 408 858#define SRST_S_UART6 409 859#define SRST_P_UART7 410 860#define SRST_S_UART7 411 861#define SRST_P_UART8 412 862#define SRST_S_UART8 413 863#define SRST_P_UART9 414 864#define SRST_S_UART9 415 865 866/* cru_softrst_con26 */ 867#define SRST_P_GRF 416 868#define SRST_P_GRF_VCCIO12 417 869#define SRST_P_GRF_VCCIO34 418 870#define SRST_P_GRF_VCCIO567 419 871#define SRST_P_SCR 420 872#define SRST_P_WDT_NS 421 873#define SRST_T_WDT_NS 422 874#define SRST_P_DFT2APB 423 875#define SRST_A_MCU 426 876#define SRST_P_INTMUX 427 877#define SRST_P_MAILBOX 428 878 879/* cru_softrst_con27 */ 880#define SRST_A_TOP_HIGH_NIU 432 881#define SRST_A_TOP_LOW_NIU 433 882#define SRST_H_TOP_NIU 434 883#define SRST_P_TOP_NIU 435 884#define SRST_P_TOP_CRU 438 885#define SRST_P_DDRPHY 439 886#define SRST_DDRPHY 440 887#define SRST_P_MIPICSIPHY 442 888#define SRST_P_MIPIDSIPHY0 443 889#define SRST_P_MIPIDSIPHY1 444 890#define SRST_P_PCIE30PHY 445 891#define SRST_PCIE30PHY 446 892#define SRST_P_PCIE30PHY_GRF 447 893 894/* cru_softrst_con28 */ 895#define SRST_P_APB2ASB_LEFT 448 896#define SRST_P_APB2ASB_BOTTOM 449 897#define SRST_P_ASB2APB_LEFT 450 898#define SRST_P_ASB2APB_BOTTOM 451 899#define SRST_P_PIPEPHY0 452 900#define SRST_PIPEPHY0 453 901#define SRST_P_PIPEPHY1 454 902#define SRST_PIPEPHY1 455 903#define SRST_P_PIPEPHY2 456 904#define SRST_PIPEPHY2 457 905#define SRST_P_USB2PHY0_GRF 458 906#define SRST_P_USB2PHY1_GRF 459 907#define SRST_P_CPU_BOOST 460 908#define SRST_CPU_BOOST 461 909#define SRST_P_OTPPHY 462 910#define SRST_OTPPHY 463 911 912/* cru_softrst_con29 */ 913#define SRST_USB2PHY0_POR 464 914#define SRST_USB2PHY0_USB3OTG0 465 915#define SRST_USB2PHY0_USB3OTG1 466 916#define SRST_USB2PHY1_POR 467 917#define SRST_USB2PHY1_USB2HOST0 468 918#define SRST_USB2PHY1_USB2HOST1 469 919#define SRST_P_EDPPHY_GRF 470 920#define SRST_TSADCPHY 471 921#define SRST_GMAC0_DELAYLINE 472 922#define SRST_GMAC1_DELAYLINE 473 923#define SRST_OTPC_ARB 474 924#define SRST_P_PIPEPHY0_GRF 475 925#define SRST_P_PIPEPHY1_GRF 476 926#define SRST_P_PIPEPHY2_GRF 477 927 928#endif 929