1/* $NetBSD: rk3288-cru.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-or-later */ 4/* 5 * Copyright (c) 2014 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko@sntech.de> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 10#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H 11 12/* core clocks */ 13#define PLL_APLL 1 14#define PLL_DPLL 2 15#define PLL_CPLL 3 16#define PLL_GPLL 4 17#define PLL_NPLL 5 18#define ARMCLK 6 19 20/* sclk gates (special clocks) */ 21#define SCLK_GPU 64 22#define SCLK_SPI0 65 23#define SCLK_SPI1 66 24#define SCLK_SPI2 67 25#define SCLK_SDMMC 68 26#define SCLK_SDIO0 69 27#define SCLK_SDIO1 70 28#define SCLK_EMMC 71 29#define SCLK_TSADC 72 30#define SCLK_SARADC 73 31#define SCLK_PS2C 74 32#define SCLK_NANDC0 75 33#define SCLK_NANDC1 76 34#define SCLK_UART0 77 35#define SCLK_UART1 78 36#define SCLK_UART2 79 37#define SCLK_UART3 80 38#define SCLK_UART4 81 39#define SCLK_I2S0 82 40#define SCLK_SPDIF 83 41#define SCLK_SPDIF8CH 84 42#define SCLK_TIMER0 85 43#define SCLK_TIMER1 86 44#define SCLK_TIMER2 87 45#define SCLK_TIMER3 88 46#define SCLK_TIMER4 89 47#define SCLK_TIMER5 90 48#define SCLK_TIMER6 91 49#define SCLK_HSADC 92 50#define SCLK_OTGPHY0 93 51#define SCLK_OTGPHY1 94 52#define SCLK_OTGPHY2 95 53#define SCLK_OTG_ADP 96 54#define SCLK_HSICPHY480M 97 55#define SCLK_HSICPHY12M 98 56#define SCLK_MACREF 99 57#define SCLK_LCDC_PWM0 100 58#define SCLK_LCDC_PWM1 101 59#define SCLK_MAC_RX 102 60#define SCLK_MAC_TX 103 61#define SCLK_EDP_24M 104 62#define SCLK_EDP 105 63#define SCLK_RGA 106 64#define SCLK_ISP 107 65#define SCLK_ISP_JPE 108 66#define SCLK_HDMI_HDCP 109 67#define SCLK_HDMI_CEC 110 68#define SCLK_HEVC_CABAC 111 69#define SCLK_HEVC_CORE 112 70#define SCLK_I2S0_OUT 113 71#define SCLK_SDMMC_DRV 114 72#define SCLK_SDIO0_DRV 115 73#define SCLK_SDIO1_DRV 116 74#define SCLK_EMMC_DRV 117 75#define SCLK_SDMMC_SAMPLE 118 76#define SCLK_SDIO0_SAMPLE 119 77#define SCLK_SDIO1_SAMPLE 120 78#define SCLK_EMMC_SAMPLE 121 79#define SCLK_USBPHY480M_SRC 122 80#define SCLK_PVTM_CORE 123 81#define SCLK_PVTM_GPU 124 82#define SCLK_CRYPTO 125 83#define SCLK_MIPIDSI_24M 126 84#define SCLK_VIP_OUT 127 85 86#define SCLK_MAC 151 87#define SCLK_MACREF_OUT 152 88 89#define DCLK_VOP0 190 90#define DCLK_VOP1 191 91 92/* aclk gates */ 93#define ACLK_GPU 192 94#define ACLK_DMAC1 193 95#define ACLK_DMAC2 194 96#define ACLK_MMU 195 97#define ACLK_GMAC 196 98#define ACLK_VOP0 197 99#define ACLK_VOP1 198 100#define ACLK_CRYPTO 199 101#define ACLK_RGA 200 102#define ACLK_RGA_NIU 201 103#define ACLK_IEP 202 104#define ACLK_VIO0_NIU 203 105#define ACLK_VIP 204 106#define ACLK_ISP 205 107#define ACLK_VIO1_NIU 206 108#define ACLK_HEVC 207 109#define ACLK_VCODEC 208 110#define ACLK_CPU 209 111#define ACLK_PERI 210 112 113/* pclk gates */ 114#define PCLK_GPIO0 320 115#define PCLK_GPIO1 321 116#define PCLK_GPIO2 322 117#define PCLK_GPIO3 323 118#define PCLK_GPIO4 324 119#define PCLK_GPIO5 325 120#define PCLK_GPIO6 326 121#define PCLK_GPIO7 327 122#define PCLK_GPIO8 328 123#define PCLK_GRF 329 124#define PCLK_SGRF 330 125#define PCLK_PMU 331 126#define PCLK_I2C0 332 127#define PCLK_I2C1 333 128#define PCLK_I2C2 334 129#define PCLK_I2C3 335 130#define PCLK_I2C4 336 131#define PCLK_I2C5 337 132#define PCLK_SPI0 338 133#define PCLK_SPI1 339 134#define PCLK_SPI2 340 135#define PCLK_UART0 341 136#define PCLK_UART1 342 137#define PCLK_UART2 343 138#define PCLK_UART3 344 139#define PCLK_UART4 345 140#define PCLK_TSADC 346 141#define PCLK_SARADC 347 142#define PCLK_SIM 348 143#define PCLK_GMAC 349 144#define PCLK_PWM 350 145#define PCLK_RKPWM 351 146#define PCLK_PS2C 352 147#define PCLK_TIMER 353 148#define PCLK_TZPC 354 149#define PCLK_EDP_CTRL 355 150#define PCLK_MIPI_DSI0 356 151#define PCLK_MIPI_DSI1 357 152#define PCLK_MIPI_CSI 358 153#define PCLK_LVDS_PHY 359 154#define PCLK_HDMI_CTRL 360 155#define PCLK_VIO2_H2P 361 156#define PCLK_CPU 362 157#define PCLK_PERI 363 158#define PCLK_DDRUPCTL0 364 159#define PCLK_PUBL0 365 160#define PCLK_DDRUPCTL1 366 161#define PCLK_PUBL1 367 162#define PCLK_WDT 368 163#define PCLK_EFUSE256 369 164#define PCLK_EFUSE1024 370 165#define PCLK_ISP_IN 371 166 167/* hclk gates */ 168#define HCLK_GPS 448 169#define HCLK_OTG0 449 170#define HCLK_USBHOST0 450 171#define HCLK_USBHOST1 451 172#define HCLK_HSIC 452 173#define HCLK_NANDC0 453 174#define HCLK_NANDC1 454 175#define HCLK_TSP 455 176#define HCLK_SDMMC 456 177#define HCLK_SDIO0 457 178#define HCLK_SDIO1 458 179#define HCLK_EMMC 459 180#define HCLK_HSADC 460 181#define HCLK_CRYPTO 461 182#define HCLK_I2S0 462 183#define HCLK_SPDIF 463 184#define HCLK_SPDIF8CH 464 185#define HCLK_VOP0 465 186#define HCLK_VOP1 466 187#define HCLK_ROM 467 188#define HCLK_IEP 468 189#define HCLK_ISP 469 190#define HCLK_RGA 470 191#define HCLK_VIO_AHB_ARBI 471 192#define HCLK_VIO_NIU 472 193#define HCLK_VIP 473 194#define HCLK_VIO2_H2P 474 195#define HCLK_HEVC 475 196#define HCLK_VCODEC 476 197#define HCLK_CPU 477 198#define HCLK_PERI 478 199 200#define CLK_NR_CLKS (HCLK_PERI + 1) 201 202/* soft-reset indices */ 203#define SRST_CORE0 0 204#define SRST_CORE1 1 205#define SRST_CORE2 2 206#define SRST_CORE3 3 207#define SRST_CORE0_PO 4 208#define SRST_CORE1_PO 5 209#define SRST_CORE2_PO 6 210#define SRST_CORE3_PO 7 211#define SRST_PDCORE_STRSYS 8 212#define SRST_PDBUS_STRSYS 9 213#define SRST_L2C 10 214#define SRST_TOPDBG 11 215#define SRST_CORE0_DBG 12 216#define SRST_CORE1_DBG 13 217#define SRST_CORE2_DBG 14 218#define SRST_CORE3_DBG 15 219 220#define SRST_PDBUG_AHB_ARBITOR 16 221#define SRST_EFUSE256 17 222#define SRST_DMAC1 18 223#define SRST_INTMEM 19 224#define SRST_ROM 20 225#define SRST_SPDIF8CH 21 226#define SRST_TIMER 22 227#define SRST_I2S0 23 228#define SRST_SPDIF 24 229#define SRST_TIMER0 25 230#define SRST_TIMER1 26 231#define SRST_TIMER2 27 232#define SRST_TIMER3 28 233#define SRST_TIMER4 29 234#define SRST_TIMER5 30 235#define SRST_EFUSE 31 236 237#define SRST_GPIO0 32 238#define SRST_GPIO1 33 239#define SRST_GPIO2 34 240#define SRST_GPIO3 35 241#define SRST_GPIO4 36 242#define SRST_GPIO5 37 243#define SRST_GPIO6 38 244#define SRST_GPIO7 39 245#define SRST_GPIO8 40 246#define SRST_I2C0 42 247#define SRST_I2C1 43 248#define SRST_I2C2 44 249#define SRST_I2C3 45 250#define SRST_I2C4 46 251#define SRST_I2C5 47 252 253#define SRST_DWPWM 48 254#define SRST_MMC_PERI 49 255#define SRST_PERIPH_MMU 50 256#define SRST_DAP 51 257#define SRST_DAP_SYS 52 258#define SRST_TPIU 53 259#define SRST_PMU_APB 54 260#define SRST_GRF 55 261#define SRST_PMU 56 262#define SRST_PERIPH_AXI 57 263#define SRST_PERIPH_AHB 58 264#define SRST_PERIPH_APB 59 265#define SRST_PERIPH_NIU 60 266#define SRST_PDPERI_AHB_ARBI 61 267#define SRST_EMEM 62 268#define SRST_USB_PERI 63 269 270#define SRST_DMAC2 64 271#define SRST_MAC 66 272#define SRST_GPS 67 273#define SRST_RKPWM 69 274#define SRST_CCP 71 275#define SRST_USBHOST0 72 276#define SRST_HSIC 73 277#define SRST_HSIC_AUX 74 278#define SRST_HSIC_PHY 75 279#define SRST_HSADC 76 280#define SRST_NANDC0 77 281#define SRST_NANDC1 78 282 283#define SRST_TZPC 80 284#define SRST_SPI0 83 285#define SRST_SPI1 84 286#define SRST_SPI2 85 287#define SRST_SARADC 87 288#define SRST_PDALIVE_NIU 88 289#define SRST_PDPMU_INTMEM 89 290#define SRST_PDPMU_NIU 90 291#define SRST_SGRF 91 292 293#define SRST_VIO_ARBI 96 294#define SRST_RGA_NIU 97 295#define SRST_VIO0_NIU_AXI 98 296#define SRST_VIO_NIU_AHB 99 297#define SRST_LCDC0_AXI 100 298#define SRST_LCDC0_AHB 101 299#define SRST_LCDC0_DCLK 102 300#define SRST_VIO1_NIU_AXI 103 301#define SRST_VIP 104 302#define SRST_RGA_CORE 105 303#define SRST_IEP_AXI 106 304#define SRST_IEP_AHB 107 305#define SRST_RGA_AXI 108 306#define SRST_RGA_AHB 109 307#define SRST_ISP 110 308#define SRST_EDP 111 309 310#define SRST_VCODEC_AXI 112 311#define SRST_VCODEC_AHB 113 312#define SRST_VIO_H2P 114 313#define SRST_MIPIDSI0 115 314#define SRST_MIPIDSI1 116 315#define SRST_MIPICSI 117 316#define SRST_LVDS_PHY 118 317#define SRST_LVDS_CON 119 318#define SRST_GPU 120 319#define SRST_HDMI 121 320#define SRST_CORE_PVTM 124 321#define SRST_GPU_PVTM 125 322 323#define SRST_MMC0 128 324#define SRST_SDIO0 129 325#define SRST_SDIO1 130 326#define SRST_EMMC 131 327#define SRST_USBOTG_AHB 132 328#define SRST_USBOTG_PHY 133 329#define SRST_USBOTG_CON 134 330#define SRST_USBHOST0_AHB 135 331#define SRST_USBHOST0_PHY 136 332#define SRST_USBHOST0_CON 137 333#define SRST_USBHOST1_AHB 138 334#define SRST_USBHOST1_PHY 139 335#define SRST_USBHOST1_CON 140 336#define SRST_USB_ADP 141 337#define SRST_ACC_EFUSE 142 338 339#define SRST_CORESIGHT 144 340#define SRST_PD_CORE_AHB_NOC 145 341#define SRST_PD_CORE_APB_NOC 146 342#define SRST_PD_CORE_MP_AXI 147 343#define SRST_GIC 148 344#define SRST_LCDC_PWM0 149 345#define SRST_LCDC_PWM1 150 346#define SRST_VIO0_H2P_BRG 151 347#define SRST_VIO1_H2P_BRG 152 348#define SRST_RGA_H2P_BRG 153 349#define SRST_HEVC 154 350#define SRST_TSADC 159 351 352#define SRST_DDRPHY0 160 353#define SRST_DDRPHY0_APB 161 354#define SRST_DDRCTRL0 162 355#define SRST_DDRCTRL0_APB 163 356#define SRST_DDRPHY0_CTRL 164 357#define SRST_DDRPHY1 165 358#define SRST_DDRPHY1_APB 166 359#define SRST_DDRCTRL1 167 360#define SRST_DDRCTRL1_APB 168 361#define SRST_DDRPHY1_CTRL 169 362#define SRST_DDRMSCH0 170 363#define SRST_DDRMSCH1 171 364#define SRST_CRYPTO 174 365#define SRST_C2C_HOST 175 366 367#define SRST_LCDC1_AXI 176 368#define SRST_LCDC1_AHB 177 369#define SRST_LCDC1_DCLK 178 370#define SRST_UART0 179 371#define SRST_UART1 180 372#define SRST_UART2 181 373#define SRST_UART3 182 374#define SRST_UART4 183 375#define SRST_SIMC 186 376#define SRST_PS2C 187 377#define SRST_TSP 188 378#define SRST_TSP_CLKIN0 189 379#define SRST_TSP_CLKIN1 190 380#define SRST_TSP_27M 191 381 382#endif 383