rk3188-cru-common.h revision 1.1.1.1
1/* $NetBSD: rk3188-cru-common.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3/* 4 * Copyright (c) 2014 MundoReader S.L. 5 * Author: Heiko Stuebner <heiko@sntech.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 19#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 20 21/* core clocks from */ 22#define PLL_APLL 1 23#define PLL_DPLL 2 24#define PLL_CPLL 3 25#define PLL_GPLL 4 26#define CORE_PERI 5 27#define CORE_L2C 6 28#define ARMCLK 7 29 30/* sclk gates (special clocks) */ 31#define SCLK_UART0 64 32#define SCLK_UART1 65 33#define SCLK_UART2 66 34#define SCLK_UART3 67 35#define SCLK_MAC 68 36#define SCLK_SPI0 69 37#define SCLK_SPI1 70 38#define SCLK_SARADC 71 39#define SCLK_SDMMC 72 40#define SCLK_SDIO 73 41#define SCLK_EMMC 74 42#define SCLK_I2S0 75 43#define SCLK_I2S1 76 44#define SCLK_I2S2 77 45#define SCLK_SPDIF 78 46#define SCLK_CIF0 79 47#define SCLK_CIF1 80 48#define SCLK_OTGPHY0 81 49#define SCLK_OTGPHY1 82 50#define SCLK_HSADC 83 51#define SCLK_TIMER0 84 52#define SCLK_TIMER1 85 53#define SCLK_TIMER2 86 54#define SCLK_TIMER3 87 55#define SCLK_TIMER4 88 56#define SCLK_TIMER5 89 57#define SCLK_TIMER6 90 58#define SCLK_JTAG 91 59#define SCLK_SMC 92 60#define SCLK_TSADC 93 61 62#define DCLK_LCDC0 190 63#define DCLK_LCDC1 191 64 65/* aclk gates */ 66#define ACLK_DMA1 192 67#define ACLK_DMA2 193 68#define ACLK_GPS 194 69#define ACLK_LCDC0 195 70#define ACLK_LCDC1 196 71#define ACLK_GPU 197 72#define ACLK_SMC 198 73#define ACLK_CIF 199 74#define ACLK_IPP 200 75#define ACLK_RGA 201 76#define ACLK_CIF0 202 77#define ACLK_CPU 203 78#define ACLK_PERI 204 79 80/* pclk gates */ 81#define PCLK_GRF 320 82#define PCLK_PMU 321 83#define PCLK_TIMER0 322 84#define PCLK_TIMER1 323 85#define PCLK_TIMER2 324 86#define PCLK_TIMER3 325 87#define PCLK_PWM01 326 88#define PCLK_PWM23 327 89#define PCLK_SPI0 328 90#define PCLK_SPI1 329 91#define PCLK_SARADC 330 92#define PCLK_WDT 331 93#define PCLK_UART0 332 94#define PCLK_UART1 333 95#define PCLK_UART2 334 96#define PCLK_UART3 335 97#define PCLK_I2C0 336 98#define PCLK_I2C1 337 99#define PCLK_I2C2 338 100#define PCLK_I2C3 339 101#define PCLK_I2C4 340 102#define PCLK_GPIO0 341 103#define PCLK_GPIO1 342 104#define PCLK_GPIO2 343 105#define PCLK_GPIO3 344 106#define PCLK_GPIO4 345 107#define PCLK_GPIO6 346 108#define PCLK_EFUSE 347 109#define PCLK_TZPC 348 110#define PCLK_TSADC 349 111#define PCLK_CPU 350 112#define PCLK_PERI 351 113#define PCLK_DDRUPCTL 352 114#define PCLK_PUBL 353 115 116/* hclk gates */ 117#define HCLK_SDMMC 448 118#define HCLK_SDIO 449 119#define HCLK_EMMC 450 120#define HCLK_OTG0 451 121#define HCLK_EMAC 452 122#define HCLK_SPDIF 453 123#define HCLK_I2S0 454 124#define HCLK_I2S1 455 125#define HCLK_I2S2 456 126#define HCLK_OTG1 457 127#define HCLK_HSIC 458 128#define HCLK_HSADC 459 129#define HCLK_PIDF 460 130#define HCLK_LCDC0 461 131#define HCLK_LCDC1 462 132#define HCLK_ROM 463 133#define HCLK_CIF0 464 134#define HCLK_IPP 465 135#define HCLK_RGA 466 136#define HCLK_NANDC0 467 137#define HCLK_CPU 468 138#define HCLK_PERI 469 139 140#define CLK_NR_CLKS (HCLK_PERI + 1) 141 142/* soft-reset indices */ 143#define SRST_MCORE 2 144#define SRST_CORE0 3 145#define SRST_CORE1 4 146#define SRST_MCORE_DBG 7 147#define SRST_CORE0_DBG 8 148#define SRST_CORE1_DBG 9 149#define SRST_CORE0_WDT 12 150#define SRST_CORE1_WDT 13 151#define SRST_STRC_SYS 14 152#define SRST_L2C 15 153 154#define SRST_CPU_AHB 17 155#define SRST_AHB2APB 19 156#define SRST_DMA1 20 157#define SRST_INTMEM 21 158#define SRST_ROM 22 159#define SRST_SPDIF 26 160#define SRST_TIMER0 27 161#define SRST_TIMER1 28 162#define SRST_EFUSE 30 163 164#define SRST_GPIO0 32 165#define SRST_GPIO1 33 166#define SRST_GPIO2 34 167#define SRST_GPIO3 35 168 169#define SRST_UART0 39 170#define SRST_UART1 40 171#define SRST_UART2 41 172#define SRST_UART3 42 173#define SRST_I2C0 43 174#define SRST_I2C1 44 175#define SRST_I2C2 45 176#define SRST_I2C3 46 177#define SRST_I2C4 47 178 179#define SRST_PWM0 48 180#define SRST_PWM1 49 181#define SRST_DAP_PO 50 182#define SRST_DAP 51 183#define SRST_DAP_SYS 52 184#define SRST_TPIU_ATB 53 185#define SRST_PMU_APB 54 186#define SRST_GRF 55 187#define SRST_PMU 56 188#define SRST_PERI_AXI 57 189#define SRST_PERI_AHB 58 190#define SRST_PERI_APB 59 191#define SRST_PERI_NIU 60 192#define SRST_CPU_PERI 61 193#define SRST_EMEM_PERI 62 194#define SRST_USB_PERI 63 195 196#define SRST_DMA2 64 197#define SRST_SMC 65 198#define SRST_MAC 66 199#define SRST_NANC0 68 200#define SRST_USBOTG0 69 201#define SRST_USBPHY0 70 202#define SRST_OTGC0 71 203#define SRST_USBOTG1 72 204#define SRST_USBPHY1 73 205#define SRST_OTGC1 74 206#define SRST_HSADC 76 207#define SRST_PIDFILTER 77 208#define SRST_DDR_MSCH 79 209 210#define SRST_TZPC 80 211#define SRST_SDMMC 81 212#define SRST_SDIO 82 213#define SRST_EMMC 83 214#define SRST_SPI0 84 215#define SRST_SPI1 85 216#define SRST_WDT 86 217#define SRST_SARADC 87 218#define SRST_DDRPHY 88 219#define SRST_DDRPHY_APB 89 220#define SRST_DDRCTL 90 221#define SRST_DDRCTL_APB 91 222#define SRST_DDRPUB 93 223 224#define SRST_VIO0_AXI 98 225#define SRST_VIO0_AHB 99 226#define SRST_LCDC0_AXI 100 227#define SRST_LCDC0_AHB 101 228#define SRST_LCDC0_DCLK 102 229#define SRST_LCDC1_AXI 103 230#define SRST_LCDC1_AHB 104 231#define SRST_LCDC1_DCLK 105 232#define SRST_IPP_AXI 106 233#define SRST_IPP_AHB 107 234#define SRST_RGA_AXI 108 235#define SRST_RGA_AHB 109 236#define SRST_CIF0 110 237 238#define SRST_VCODEC_AXI 112 239#define SRST_VCODEC_AHB 113 240#define SRST_VIO1_AXI 114 241#define SRST_VCODEC_CPU 115 242#define SRST_VCODEC_NIU 116 243#define SRST_GPU 120 244#define SRST_GPU_NIU 122 245#define SRST_TFUN_ATB 125 246#define SRST_TFUN_APB 126 247#define SRST_CTI4_APB 127 248 249#define SRST_TPIU_APB 128 250#define SRST_TRACE 129 251#define SRST_CORE_DBG 130 252#define SRST_DBG_APB 131 253#define SRST_CTI0 132 254#define SRST_CTI0_APB 133 255#define SRST_CTI1 134 256#define SRST_CTI1_APB 135 257#define SRST_PTM_CORE0 136 258#define SRST_PTM_CORE1 137 259#define SRST_PTM0 138 260#define SRST_PTM0_ATB 139 261#define SRST_PTM1 140 262#define SRST_PTM1_ATB 141 263#define SRST_CTM 142 264#define SRST_TS 143 265 266#endif 267