r8a7792-cpg-mssr.h revision 1.1.1.2
1/* $NetBSD: r8a7792-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:01 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8#ifndef __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 9#define __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ 10 11#include <dt-bindings/clock/renesas-cpg-mssr.h> 12 13/* r8a7792 CPG Core Clocks */ 14#define R8A7792_CLK_Z 0 15#define R8A7792_CLK_ZG 1 16#define R8A7792_CLK_ZTR 2 17#define R8A7792_CLK_ZTRD2 3 18#define R8A7792_CLK_ZT 4 19#define R8A7792_CLK_ZX 5 20#define R8A7792_CLK_ZS 6 21#define R8A7792_CLK_HP 7 22#define R8A7792_CLK_I 8 23#define R8A7792_CLK_B 9 24#define R8A7792_CLK_LB 10 25#define R8A7792_CLK_P 11 26#define R8A7792_CLK_CL 12 27#define R8A7792_CLK_M2 13 28#define R8A7792_CLK_IMP 14 29#define R8A7792_CLK_ZB3 15 30#define R8A7792_CLK_ZB3D2 16 31#define R8A7792_CLK_DDR 17 32#define R8A7792_CLK_SD 18 33#define R8A7792_CLK_MP 19 34#define R8A7792_CLK_QSPI 20 35#define R8A7792_CLK_CP 21 36#define R8A7792_CLK_CPEX 22 37#define R8A7792_CLK_RCAN 23 38#define R8A7792_CLK_R 24 39#define R8A7792_CLK_OSC 25 40 41#endif /* __DT_BINDINGS_CLOCK_R8A7792_CPG_MSSR_H__ */ 42