1/* $NetBSD: qcom,mmcc-sdm660.h,v 1.1.1.1 2021/11/07 16:49:58 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_MSM_MMCC_660_H 9#define _DT_BINDINGS_CLK_MSM_MMCC_660_H 10 11#define AHB_CLK_SRC 0 12#define BYTE0_CLK_SRC 1 13#define BYTE1_CLK_SRC 2 14#define CAMSS_GP0_CLK_SRC 3 15#define CAMSS_GP1_CLK_SRC 4 16#define CCI_CLK_SRC 5 17#define CPP_CLK_SRC 6 18#define CSI0_CLK_SRC 7 19#define CSI0PHYTIMER_CLK_SRC 8 20#define CSI1_CLK_SRC 9 21#define CSI1PHYTIMER_CLK_SRC 10 22#define CSI2_CLK_SRC 11 23#define CSI2PHYTIMER_CLK_SRC 12 24#define CSI3_CLK_SRC 13 25#define CSIPHY_CLK_SRC 14 26#define DP_AUX_CLK_SRC 15 27#define DP_CRYPTO_CLK_SRC 16 28#define DP_GTC_CLK_SRC 17 29#define DP_LINK_CLK_SRC 18 30#define DP_PIXEL_CLK_SRC 19 31#define ESC0_CLK_SRC 20 32#define ESC1_CLK_SRC 21 33#define JPEG0_CLK_SRC 22 34#define MCLK0_CLK_SRC 23 35#define MCLK1_CLK_SRC 24 36#define MCLK2_CLK_SRC 25 37#define MCLK3_CLK_SRC 26 38#define MDP_CLK_SRC 27 39#define MMPLL0_PLL 28 40#define MMPLL10_PLL 29 41#define MMPLL1_PLL 30 42#define MMPLL3_PLL 31 43#define MMPLL4_PLL 32 44#define MMPLL5_PLL 33 45#define MMPLL6_PLL 34 46#define MMPLL7_PLL 35 47#define MMPLL8_PLL 36 48#define BIMC_SMMU_AHB_CLK 37 49#define BIMC_SMMU_AXI_CLK 38 50#define CAMSS_AHB_CLK 39 51#define CAMSS_CCI_AHB_CLK 40 52#define CAMSS_CCI_CLK 41 53#define CAMSS_CPHY_CSID0_CLK 42 54#define CAMSS_CPHY_CSID1_CLK 43 55#define CAMSS_CPHY_CSID2_CLK 44 56#define CAMSS_CPHY_CSID3_CLK 45 57#define CAMSS_CPP_AHB_CLK 46 58#define CAMSS_CPP_AXI_CLK 47 59#define CAMSS_CPP_CLK 48 60#define CAMSS_CPP_VBIF_AHB_CLK 49 61#define CAMSS_CSI0_AHB_CLK 50 62#define CAMSS_CSI0_CLK 51 63#define CAMSS_CSI0PHYTIMER_CLK 52 64#define CAMSS_CSI0PIX_CLK 53 65#define CAMSS_CSI0RDI_CLK 54 66#define CAMSS_CSI1_AHB_CLK 55 67#define CAMSS_CSI1_CLK 56 68#define CAMSS_CSI1PHYTIMER_CLK 57 69#define CAMSS_CSI1PIX_CLK 58 70#define CAMSS_CSI1RDI_CLK 59 71#define CAMSS_CSI2_AHB_CLK 60 72#define CAMSS_CSI2_CLK 61 73#define CAMSS_CSI2PHYTIMER_CLK 62 74#define CAMSS_CSI2PIX_CLK 63 75#define CAMSS_CSI2RDI_CLK 64 76#define CAMSS_CSI3_AHB_CLK 65 77#define CAMSS_CSI3_CLK 66 78#define CAMSS_CSI3PIX_CLK 67 79#define CAMSS_CSI3RDI_CLK 68 80#define CAMSS_CSI_VFE0_CLK 69 81#define CAMSS_CSI_VFE1_CLK 70 82#define CAMSS_CSIPHY0_CLK 71 83#define CAMSS_CSIPHY1_CLK 72 84#define CAMSS_CSIPHY2_CLK 73 85#define CAMSS_GP0_CLK 74 86#define CAMSS_GP1_CLK 75 87#define CAMSS_ISPIF_AHB_CLK 76 88#define CAMSS_JPEG0_CLK 77 89#define CAMSS_JPEG_AHB_CLK 78 90#define CAMSS_JPEG_AXI_CLK 79 91#define CAMSS_MCLK0_CLK 80 92#define CAMSS_MCLK1_CLK 81 93#define CAMSS_MCLK2_CLK 82 94#define CAMSS_MCLK3_CLK 83 95#define CAMSS_MICRO_AHB_CLK 84 96#define CAMSS_TOP_AHB_CLK 85 97#define CAMSS_VFE0_AHB_CLK 86 98#define CAMSS_VFE0_CLK 87 99#define CAMSS_VFE0_STREAM_CLK 88 100#define CAMSS_VFE1_AHB_CLK 89 101#define CAMSS_VFE1_CLK 90 102#define CAMSS_VFE1_STREAM_CLK 91 103#define CAMSS_VFE_VBIF_AHB_CLK 92 104#define CAMSS_VFE_VBIF_AXI_CLK 93 105#define CSIPHY_AHB2CRIF_CLK 94 106#define CXO_CLK 95 107#define MDSS_AHB_CLK 96 108#define MDSS_AXI_CLK 97 109#define MDSS_BYTE0_CLK 98 110#define MDSS_BYTE0_INTF_CLK 99 111#define MDSS_BYTE0_INTF_DIV_CLK 100 112#define MDSS_BYTE1_CLK 101 113#define MDSS_BYTE1_INTF_CLK 102 114#define MDSS_DP_AUX_CLK 103 115#define MDSS_DP_CRYPTO_CLK 104 116#define MDSS_DP_GTC_CLK 105 117#define MDSS_DP_LINK_CLK 106 118#define MDSS_DP_LINK_INTF_CLK 107 119#define MDSS_DP_PIXEL_CLK 108 120#define MDSS_ESC0_CLK 109 121#define MDSS_ESC1_CLK 110 122#define MDSS_HDMI_DP_AHB_CLK 111 123#define MDSS_MDP_CLK 112 124#define MDSS_PCLK0_CLK 113 125#define MDSS_PCLK1_CLK 114 126#define MDSS_ROT_CLK 115 127#define MDSS_VSYNC_CLK 116 128#define MISC_AHB_CLK 117 129#define MISC_CXO_CLK 118 130#define MNOC_AHB_CLK 119 131#define SNOC_DVM_AXI_CLK 120 132#define THROTTLE_CAMSS_AHB_CLK 121 133#define THROTTLE_CAMSS_AXI_CLK 122 134#define THROTTLE_MDSS_AHB_CLK 123 135#define THROTTLE_MDSS_AXI_CLK 124 136#define THROTTLE_VIDEO_AHB_CLK 125 137#define THROTTLE_VIDEO_AXI_CLK 126 138#define VIDEO_AHB_CLK 127 139#define VIDEO_AXI_CLK 128 140#define VIDEO_CORE_CLK 129 141#define VIDEO_SUBCORE0_CLK 130 142#define PCLK0_CLK_SRC 131 143#define PCLK1_CLK_SRC 132 144#define ROT_CLK_SRC 133 145#define VFE0_CLK_SRC 134 146#define VFE1_CLK_SRC 135 147#define VIDEO_CORE_CLK_SRC 136 148#define VSYNC_CLK_SRC 137 149#define MDSS_BYTE1_INTF_DIV_CLK 138 150#define AXI_CLK_SRC 139 151 152#define VENUS_GDSC 0 153#define VENUS_CORE0_GDSC 1 154#define MDSS_GDSC 2 155#define CAMSS_TOP_GDSC 3 156#define CAMSS_VFE0_GDSC 4 157#define CAMSS_VFE1_GDSC 5 158#define CAMSS_CPP_GDSC 6 159#define BIMC_SMMU_GDSC 7 160 161#define CAMSS_MICRO_BCR 0 162 163#endif 164 165