1/* $NetBSD: px30-cru.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4 5#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 6#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 7 8/* core clocks */ 9#define PLL_APLL 1 10#define PLL_DPLL 2 11#define PLL_CPLL 3 12#define PLL_NPLL 4 13#define APLL_BOOST_H 5 14#define APLL_BOOST_L 6 15#define ARMCLK 7 16 17/* sclk gates (special clocks) */ 18#define USB480M 14 19#define SCLK_PDM 15 20#define SCLK_I2S0_TX 16 21#define SCLK_I2S0_TX_OUT 17 22#define SCLK_I2S0_RX 18 23#define SCLK_I2S0_RX_OUT 19 24#define SCLK_I2S1 20 25#define SCLK_I2S1_OUT 21 26#define SCLK_I2S2 22 27#define SCLK_I2S2_OUT 23 28#define SCLK_UART1 24 29#define SCLK_UART2 25 30#define SCLK_UART3 26 31#define SCLK_UART4 27 32#define SCLK_UART5 28 33#define SCLK_I2C0 29 34#define SCLK_I2C1 30 35#define SCLK_I2C2 31 36#define SCLK_I2C3 32 37#define SCLK_I2C4 33 38#define SCLK_PWM0 34 39#define SCLK_PWM1 35 40#define SCLK_SPI0 36 41#define SCLK_SPI1 37 42#define SCLK_TIMER0 38 43#define SCLK_TIMER1 39 44#define SCLK_TIMER2 40 45#define SCLK_TIMER3 41 46#define SCLK_TIMER4 42 47#define SCLK_TIMER5 43 48#define SCLK_TSADC 44 49#define SCLK_SARADC 45 50#define SCLK_OTP 46 51#define SCLK_OTP_USR 47 52#define SCLK_CRYPTO 48 53#define SCLK_CRYPTO_APK 49 54#define SCLK_DDRC 50 55#define SCLK_ISP 51 56#define SCLK_CIF_OUT 52 57#define SCLK_RGA_CORE 53 58#define SCLK_VOPB_PWM 54 59#define SCLK_NANDC 55 60#define SCLK_SDIO 56 61#define SCLK_EMMC 57 62#define SCLK_SFC 58 63#define SCLK_SDMMC 59 64#define SCLK_OTG_ADP 60 65#define SCLK_GMAC_SRC 61 66#define SCLK_GMAC 62 67#define SCLK_GMAC_RX_TX 63 68#define SCLK_MAC_REF 64 69#define SCLK_MAC_REFOUT 65 70#define SCLK_MAC_OUT 66 71#define SCLK_SDMMC_DRV 67 72#define SCLK_SDMMC_SAMPLE 68 73#define SCLK_SDIO_DRV 69 74#define SCLK_SDIO_SAMPLE 70 75#define SCLK_EMMC_DRV 71 76#define SCLK_EMMC_SAMPLE 72 77#define SCLK_GPU 73 78#define SCLK_PVTM 74 79#define SCLK_CORE_VPU 75 80#define SCLK_GMAC_RMII 76 81#define SCLK_UART2_SRC 77 82#define SCLK_NANDC_DIV 78 83#define SCLK_NANDC_DIV50 79 84#define SCLK_SDIO_DIV 80 85#define SCLK_SDIO_DIV50 81 86#define SCLK_EMMC_DIV 82 87#define SCLK_EMMC_DIV50 83 88#define SCLK_DDRCLK 84 89#define SCLK_UART1_SRC 85 90#define SCLK_SDMMC_DIV 86 91#define SCLK_SDMMC_DIV50 87 92 93/* dclk gates */ 94#define DCLK_VOPB 150 95#define DCLK_VOPL 151 96 97/* aclk gates */ 98#define ACLK_GPU 170 99#define ACLK_BUS_PRE 171 100#define ACLK_CRYPTO 172 101#define ACLK_VI_PRE 173 102#define ACLK_VO_PRE 174 103#define ACLK_VPU 175 104#define ACLK_PERI_PRE 176 105#define ACLK_GMAC 178 106#define ACLK_CIF 179 107#define ACLK_ISP 180 108#define ACLK_VOPB 181 109#define ACLK_VOPL 182 110#define ACLK_RGA 183 111#define ACLK_GIC 184 112#define ACLK_DCF 186 113#define ACLK_DMAC 187 114#define ACLK_BUS_SRC 188 115#define ACLK_PERI_SRC 189 116 117/* hclk gates */ 118#define HCLK_BUS_PRE 240 119#define HCLK_CRYPTO 241 120#define HCLK_VI_PRE 242 121#define HCLK_VO_PRE 243 122#define HCLK_VPU 244 123#define HCLK_PERI_PRE 245 124#define HCLK_MMC_NAND 246 125#define HCLK_SDMMC 247 126#define HCLK_USB 248 127#define HCLK_CIF 249 128#define HCLK_ISP 250 129#define HCLK_VOPB 251 130#define HCLK_VOPL 252 131#define HCLK_RGA 253 132#define HCLK_NANDC 254 133#define HCLK_SDIO 255 134#define HCLK_EMMC 256 135#define HCLK_SFC 257 136#define HCLK_OTG 258 137#define HCLK_HOST 259 138#define HCLK_HOST_ARB 260 139#define HCLK_PDM 261 140#define HCLK_I2S0 262 141#define HCLK_I2S1 263 142#define HCLK_I2S2 264 143 144/* pclk gates */ 145#define PCLK_BUS_PRE 320 146#define PCLK_DDR 321 147#define PCLK_VO_PRE 322 148#define PCLK_GMAC 323 149#define PCLK_MIPI_DSI 324 150#define PCLK_MIPIDSIPHY 325 151#define PCLK_MIPICSIPHY 326 152#define PCLK_USB_GRF 327 153#define PCLK_DCF 328 154#define PCLK_UART1 329 155#define PCLK_UART2 330 156#define PCLK_UART3 331 157#define PCLK_UART4 332 158#define PCLK_UART5 333 159#define PCLK_I2C0 334 160#define PCLK_I2C1 335 161#define PCLK_I2C2 336 162#define PCLK_I2C3 337 163#define PCLK_I2C4 338 164#define PCLK_PWM0 339 165#define PCLK_PWM1 340 166#define PCLK_SPI0 341 167#define PCLK_SPI1 342 168#define PCLK_SARADC 343 169#define PCLK_TSADC 344 170#define PCLK_TIMER 345 171#define PCLK_OTP_NS 346 172#define PCLK_WDT_NS 347 173#define PCLK_GPIO1 348 174#define PCLK_GPIO2 349 175#define PCLK_GPIO3 350 176#define PCLK_ISP 351 177#define PCLK_CIF 352 178#define PCLK_OTP_PHY 353 179 180#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) 181 182/* pmu-clocks indices */ 183 184#define PLL_GPLL 1 185 186#define SCLK_RTC32K_PMU 4 187#define SCLK_WIFI_PMU 5 188#define SCLK_UART0_PMU 6 189#define SCLK_PVTM_PMU 7 190#define PCLK_PMU_PRE 8 191#define SCLK_REF24M_PMU 9 192#define SCLK_USBPHY_REF 10 193#define SCLK_MIPIDSIPHY_REF 11 194 195#define XIN24M_DIV 12 196 197#define PCLK_GPIO0_PMU 20 198#define PCLK_UART0_PMU 21 199 200#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) 201 202/* soft-reset indices */ 203#define SRST_CORE0_PO 0 204#define SRST_CORE1_PO 1 205#define SRST_CORE2_PO 2 206#define SRST_CORE3_PO 3 207#define SRST_CORE0 4 208#define SRST_CORE1 5 209#define SRST_CORE2 6 210#define SRST_CORE3 7 211#define SRST_CORE0_DBG 8 212#define SRST_CORE1_DBG 9 213#define SRST_CORE2_DBG 10 214#define SRST_CORE3_DBG 11 215#define SRST_TOPDBG 12 216#define SRST_CORE_NOC 13 217#define SRST_STRC_A 14 218#define SRST_L2C 15 219 220#define SRST_DAP 16 221#define SRST_CORE_PVTM 17 222#define SRST_GPU 18 223#define SRST_GPU_NIU 19 224#define SRST_UPCTL2 20 225#define SRST_UPCTL2_A 21 226#define SRST_UPCTL2_P 22 227#define SRST_MSCH 23 228#define SRST_MSCH_P 24 229#define SRST_DDRMON_P 25 230#define SRST_DDRSTDBY_P 26 231#define SRST_DDRSTDBY 27 232#define SRST_DDRGRF_p 28 233#define SRST_AXI_SPLIT_A 29 234#define SRST_AXI_CMD_A 30 235#define SRST_AXI_CMD_P 31 236 237#define SRST_DDRPHY 32 238#define SRST_DDRPHYDIV 33 239#define SRST_DDRPHY_P 34 240#define SRST_VPU_A 36 241#define SRST_VPU_NIU_A 37 242#define SRST_VPU_H 38 243#define SRST_VPU_NIU_H 39 244#define SRST_VI_NIU_A 40 245#define SRST_VI_NIU_H 41 246#define SRST_ISP_H 42 247#define SRST_ISP 43 248#define SRST_CIF_A 44 249#define SRST_CIF_H 45 250#define SRST_CIF_PCLKIN 46 251#define SRST_MIPICSIPHY_P 47 252 253#define SRST_VO_NIU_A 48 254#define SRST_VO_NIU_H 49 255#define SRST_VO_NIU_P 50 256#define SRST_VOPB_A 51 257#define SRST_VOPB_H 52 258#define SRST_VOPB 53 259#define SRST_PWM_VOPB 54 260#define SRST_VOPL_A 55 261#define SRST_VOPL_H 56 262#define SRST_VOPL 57 263#define SRST_RGA_A 58 264#define SRST_RGA_H 59 265#define SRST_RGA 60 266#define SRST_MIPIDSI_HOST_P 61 267#define SRST_MIPIDSIPHY_P 62 268#define SRST_VPU_CORE 63 269 270#define SRST_PERI_NIU_A 64 271#define SRST_USB_NIU_H 65 272#define SRST_USB2OTG_H 66 273#define SRST_USB2OTG 67 274#define SRST_USB2OTG_ADP 68 275#define SRST_USB2HOST_H 69 276#define SRST_USB2HOST_ARB_H 70 277#define SRST_USB2HOST_AUX_H 71 278#define SRST_USB2HOST_EHCI 72 279#define SRST_USB2HOST 73 280#define SRST_USBPHYPOR 74 281#define SRST_USBPHY_OTG_PORT 75 282#define SRST_USBPHY_HOST_PORT 76 283#define SRST_USBPHY_GRF 77 284#define SRST_CPU_BOOST_P 78 285#define SRST_CPU_BOOST 79 286 287#define SRST_MMC_NAND_NIU_H 80 288#define SRST_SDIO_H 81 289#define SRST_EMMC_H 82 290#define SRST_SFC_H 83 291#define SRST_SFC 84 292#define SRST_SDCARD_NIU_H 85 293#define SRST_SDMMC_H 86 294#define SRST_NANDC_H 89 295#define SRST_NANDC 90 296#define SRST_GMAC_NIU_A 92 297#define SRST_GMAC_NIU_P 93 298#define SRST_GMAC_A 94 299 300#define SRST_PMU_NIU_P 96 301#define SRST_PMU_SGRF_P 97 302#define SRST_PMU_GRF_P 98 303#define SRST_PMU 99 304#define SRST_PMU_MEM_P 100 305#define SRST_PMU_GPIO0_P 101 306#define SRST_PMU_UART0_P 102 307#define SRST_PMU_CRU_P 103 308#define SRST_PMU_PVTM 104 309#define SRST_PMU_UART 105 310#define SRST_PMU_NIU_H 106 311#define SRST_PMU_DDR_FAIL_SAVE 107 312#define SRST_PMU_CORE_PERF_A 108 313#define SRST_PMU_CORE_GRF_P 109 314#define SRST_PMU_GPU_PERF_A 110 315#define SRST_PMU_GPU_GRF_P 111 316 317#define SRST_CRYPTO_NIU_A 112 318#define SRST_CRYPTO_NIU_H 113 319#define SRST_CRYPTO_A 114 320#define SRST_CRYPTO_H 115 321#define SRST_CRYPTO 116 322#define SRST_CRYPTO_APK 117 323#define SRST_BUS_NIU_H 120 324#define SRST_USB_NIU_P 121 325#define SRST_BUS_TOP_NIU_P 122 326#define SRST_INTMEM_A 123 327#define SRST_GIC_A 124 328#define SRST_ROM_H 126 329#define SRST_DCF_A 127 330 331#define SRST_DCF_P 128 332#define SRST_PDM_H 129 333#define SRST_PDM 130 334#define SRST_I2S0_H 131 335#define SRST_I2S0_TX 132 336#define SRST_I2S1_H 133 337#define SRST_I2S1 134 338#define SRST_I2S2_H 135 339#define SRST_I2S2 136 340#define SRST_UART1_P 137 341#define SRST_UART1 138 342#define SRST_UART2_P 139 343#define SRST_UART2 140 344#define SRST_UART3_P 141 345#define SRST_UART3 142 346#define SRST_UART4_P 143 347 348#define SRST_UART4 144 349#define SRST_UART5_P 145 350#define SRST_UART5 146 351#define SRST_I2C0_P 147 352#define SRST_I2C0 148 353#define SRST_I2C1_P 149 354#define SRST_I2C1 150 355#define SRST_I2C2_P 151 356#define SRST_I2C2 152 357#define SRST_I2C3_P 153 358#define SRST_I2C3 154 359#define SRST_PWM0_P 157 360#define SRST_PWM0 158 361#define SRST_PWM1_P 159 362 363#define SRST_PWM1 160 364#define SRST_SPI0_P 161 365#define SRST_SPI0 162 366#define SRST_SPI1_P 163 367#define SRST_SPI1 164 368#define SRST_SARADC_P 165 369#define SRST_SARADC 166 370#define SRST_TSADC_P 167 371#define SRST_TSADC 168 372#define SRST_TIMER_P 169 373#define SRST_TIMER0 170 374#define SRST_TIMER1 171 375#define SRST_TIMER2 172 376#define SRST_TIMER3 173 377#define SRST_TIMER4 174 378#define SRST_TIMER5 175 379 380#define SRST_OTP_NS_P 176 381#define SRST_OTP_NS_SBPI 177 382#define SRST_OTP_NS_USR 178 383#define SRST_OTP_PHY_P 179 384#define SRST_OTP_PHY 180 385#define SRST_WDT_NS_P 181 386#define SRST_GPIO1_P 182 387#define SRST_GPIO2_P 183 388#define SRST_GPIO3_P 184 389#define SRST_SGRF_P 185 390#define SRST_GRF_P 186 391#define SRST_I2S0_RX 191 392 393#endif 394