1/* $NetBSD: mt6779-clk.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2019 MediaTek Inc. 6 * Author: Wendell Lin <wendell.lin@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_MT6779_H 10#define _DT_BINDINGS_CLK_MT6779_H 11 12/* TOPCKGEN */ 13#define CLK_TOP_AXI 1 14#define CLK_TOP_MM 2 15#define CLK_TOP_CAM 3 16#define CLK_TOP_MFG 4 17#define CLK_TOP_CAMTG 5 18#define CLK_TOP_UART 6 19#define CLK_TOP_SPI 7 20#define CLK_TOP_MSDC50_0_HCLK 8 21#define CLK_TOP_MSDC50_0 9 22#define CLK_TOP_MSDC30_1 10 23#define CLK_TOP_MSDC30_2 11 24#define CLK_TOP_AUD 12 25#define CLK_TOP_AUD_INTBUS 13 26#define CLK_TOP_FPWRAP_ULPOSC 14 27#define CLK_TOP_SCP 15 28#define CLK_TOP_ATB 16 29#define CLK_TOP_SSPM 17 30#define CLK_TOP_DPI0 18 31#define CLK_TOP_SCAM 19 32#define CLK_TOP_AUD_1 20 33#define CLK_TOP_AUD_2 21 34#define CLK_TOP_DISP_PWM 22 35#define CLK_TOP_SSUSB_TOP_XHCI 23 36#define CLK_TOP_USB_TOP 24 37#define CLK_TOP_SPM 25 38#define CLK_TOP_I2C 26 39#define CLK_TOP_F52M_MFG 27 40#define CLK_TOP_SENINF 28 41#define CLK_TOP_DXCC 29 42#define CLK_TOP_CAMTG2 30 43#define CLK_TOP_AUD_ENG1 31 44#define CLK_TOP_AUD_ENG2 32 45#define CLK_TOP_FAES_UFSFDE 33 46#define CLK_TOP_FUFS 34 47#define CLK_TOP_IMG 35 48#define CLK_TOP_DSP 36 49#define CLK_TOP_DSP1 37 50#define CLK_TOP_DSP2 38 51#define CLK_TOP_IPU_IF 39 52#define CLK_TOP_CAMTG3 40 53#define CLK_TOP_CAMTG4 41 54#define CLK_TOP_PMICSPI 42 55#define CLK_TOP_MAINPLL_CK 43 56#define CLK_TOP_MAINPLL_D2 44 57#define CLK_TOP_MAINPLL_D3 45 58#define CLK_TOP_MAINPLL_D5 46 59#define CLK_TOP_MAINPLL_D7 47 60#define CLK_TOP_MAINPLL_D2_D2 48 61#define CLK_TOP_MAINPLL_D2_D4 49 62#define CLK_TOP_MAINPLL_D2_D8 50 63#define CLK_TOP_MAINPLL_D2_D16 51 64#define CLK_TOP_MAINPLL_D3_D2 52 65#define CLK_TOP_MAINPLL_D3_D4 53 66#define CLK_TOP_MAINPLL_D3_D8 54 67#define CLK_TOP_MAINPLL_D5_D2 55 68#define CLK_TOP_MAINPLL_D5_D4 56 69#define CLK_TOP_MAINPLL_D7_D2 57 70#define CLK_TOP_MAINPLL_D7_D4 58 71#define CLK_TOP_UNIVPLL_CK 59 72#define CLK_TOP_UNIVPLL_D2 60 73#define CLK_TOP_UNIVPLL_D3 61 74#define CLK_TOP_UNIVPLL_D5 62 75#define CLK_TOP_UNIVPLL_D7 63 76#define CLK_TOP_UNIVPLL_D2_D2 64 77#define CLK_TOP_UNIVPLL_D2_D4 65 78#define CLK_TOP_UNIVPLL_D2_D8 66 79#define CLK_TOP_UNIVPLL_D3_D2 67 80#define CLK_TOP_UNIVPLL_D3_D4 68 81#define CLK_TOP_UNIVPLL_D3_D8 69 82#define CLK_TOP_UNIVPLL_D5_D2 70 83#define CLK_TOP_UNIVPLL_D5_D4 71 84#define CLK_TOP_UNIVPLL_D5_D8 72 85#define CLK_TOP_APLL1_CK 73 86#define CLK_TOP_APLL1_D2 74 87#define CLK_TOP_APLL1_D4 75 88#define CLK_TOP_APLL1_D8 76 89#define CLK_TOP_APLL2_CK 77 90#define CLK_TOP_APLL2_D2 78 91#define CLK_TOP_APLL2_D4 79 92#define CLK_TOP_APLL2_D8 80 93#define CLK_TOP_TVDPLL_CK 81 94#define CLK_TOP_TVDPLL_D2 82 95#define CLK_TOP_TVDPLL_D4 83 96#define CLK_TOP_TVDPLL_D8 84 97#define CLK_TOP_TVDPLL_D16 85 98#define CLK_TOP_MSDCPLL_CK 86 99#define CLK_TOP_MSDCPLL_D2 87 100#define CLK_TOP_MSDCPLL_D4 88 101#define CLK_TOP_MSDCPLL_D8 89 102#define CLK_TOP_MSDCPLL_D16 90 103#define CLK_TOP_AD_OSC_CK 91 104#define CLK_TOP_OSC_D2 92 105#define CLK_TOP_OSC_D4 93 106#define CLK_TOP_OSC_D8 94 107#define CLK_TOP_OSC_D16 95 108#define CLK_TOP_F26M_CK_D2 96 109#define CLK_TOP_MFGPLL_CK 97 110#define CLK_TOP_UNIVP_192M_CK 98 111#define CLK_TOP_UNIVP_192M_D2 99 112#define CLK_TOP_UNIVP_192M_D4 100 113#define CLK_TOP_UNIVP_192M_D8 101 114#define CLK_TOP_UNIVP_192M_D16 102 115#define CLK_TOP_UNIVP_192M_D32 103 116#define CLK_TOP_MMPLL_CK 104 117#define CLK_TOP_MMPLL_D4 105 118#define CLK_TOP_MMPLL_D4_D2 106 119#define CLK_TOP_MMPLL_D4_D4 107 120#define CLK_TOP_MMPLL_D5 108 121#define CLK_TOP_MMPLL_D5_D2 109 122#define CLK_TOP_MMPLL_D5_D4 110 123#define CLK_TOP_MMPLL_D6 111 124#define CLK_TOP_MMPLL_D7 112 125#define CLK_TOP_CLK26M 113 126#define CLK_TOP_CLK13M 114 127#define CLK_TOP_ADSP 115 128#define CLK_TOP_DPMAIF 116 129#define CLK_TOP_VENC 117 130#define CLK_TOP_VDEC 118 131#define CLK_TOP_CAMTM 119 132#define CLK_TOP_PWM 120 133#define CLK_TOP_ADSPPLL_CK 121 134#define CLK_TOP_I2S0_M_SEL 122 135#define CLK_TOP_I2S1_M_SEL 123 136#define CLK_TOP_I2S2_M_SEL 124 137#define CLK_TOP_I2S3_M_SEL 125 138#define CLK_TOP_I2S4_M_SEL 126 139#define CLK_TOP_I2S5_M_SEL 127 140#define CLK_TOP_APLL12_DIV0 128 141#define CLK_TOP_APLL12_DIV1 129 142#define CLK_TOP_APLL12_DIV2 130 143#define CLK_TOP_APLL12_DIV3 131 144#define CLK_TOP_APLL12_DIV4 132 145#define CLK_TOP_APLL12_DIVB 133 146#define CLK_TOP_APLL12_DIV5 134 147#define CLK_TOP_IPE 135 148#define CLK_TOP_DPE 136 149#define CLK_TOP_CCU 137 150#define CLK_TOP_DSP3 138 151#define CLK_TOP_SENINF1 139 152#define CLK_TOP_SENINF2 140 153#define CLK_TOP_AUD_H 141 154#define CLK_TOP_CAMTG5 142 155#define CLK_TOP_TVDPLL_MAINPLL_D2_CK 143 156#define CLK_TOP_AD_OSC2_CK 144 157#define CLK_TOP_OSC2_D2 145 158#define CLK_TOP_OSC2_D3 146 159#define CLK_TOP_FMEM_466M_CK 147 160#define CLK_TOP_ADSPPLL_D4 148 161#define CLK_TOP_ADSPPLL_D5 149 162#define CLK_TOP_ADSPPLL_D6 150 163#define CLK_TOP_OSC_D10 151 164#define CLK_TOP_UNIVPLL_D3_D16 152 165#define CLK_TOP_NR_CLK 153 166 167/* APMIXED */ 168#define CLK_APMIXED_ARMPLL_LL 1 169#define CLK_APMIXED_ARMPLL_BL 2 170#define CLK_APMIXED_ARMPLL_BB 3 171#define CLK_APMIXED_CCIPLL 4 172#define CLK_APMIXED_MAINPLL 5 173#define CLK_APMIXED_UNIV2PLL 6 174#define CLK_APMIXED_MSDCPLL 7 175#define CLK_APMIXED_ADSPPLL 8 176#define CLK_APMIXED_MMPLL 9 177#define CLK_APMIXED_MFGPLL 10 178#define CLK_APMIXED_TVDPLL 11 179#define CLK_APMIXED_APLL1 12 180#define CLK_APMIXED_APLL2 13 181#define CLK_APMIXED_SSUSB26M 14 182#define CLK_APMIXED_APPLL26M 15 183#define CLK_APMIXED_MIPIC0_26M 16 184#define CLK_APMIXED_MDPLLGP26M 17 185#define CLK_APMIXED_MM_F26M 18 186#define CLK_APMIXED_UFS26M 19 187#define CLK_APMIXED_MIPIC1_26M 20 188#define CLK_APMIXED_MEMPLL26M 21 189#define CLK_APMIXED_CLKSQ_LVPLL_26M 22 190#define CLK_APMIXED_MIPID0_26M 23 191#define CLK_APMIXED_MIPID1_26M 24 192#define CLK_APMIXED_NR_CLK 25 193 194/* CAMSYS */ 195#define CLK_CAM_LARB10 1 196#define CLK_CAM_DFP_VAD 2 197#define CLK_CAM_LARB11 3 198#define CLK_CAM_LARB9 4 199#define CLK_CAM_CAM 5 200#define CLK_CAM_CAMTG 6 201#define CLK_CAM_SENINF 7 202#define CLK_CAM_CAMSV0 8 203#define CLK_CAM_CAMSV1 9 204#define CLK_CAM_CAMSV2 10 205#define CLK_CAM_CAMSV3 11 206#define CLK_CAM_CCU 12 207#define CLK_CAM_FAKE_ENG 13 208#define CLK_CAM_NR_CLK 14 209 210/* INFRA */ 211#define CLK_INFRA_PMIC_TMR 1 212#define CLK_INFRA_PMIC_AP 2 213#define CLK_INFRA_PMIC_MD 3 214#define CLK_INFRA_PMIC_CONN 4 215#define CLK_INFRA_SCPSYS 5 216#define CLK_INFRA_SEJ 6 217#define CLK_INFRA_APXGPT 7 218#define CLK_INFRA_ICUSB 8 219#define CLK_INFRA_GCE 9 220#define CLK_INFRA_THERM 10 221#define CLK_INFRA_I2C0 11 222#define CLK_INFRA_I2C1 12 223#define CLK_INFRA_I2C2 13 224#define CLK_INFRA_I2C3 14 225#define CLK_INFRA_PWM_HCLK 15 226#define CLK_INFRA_PWM1 16 227#define CLK_INFRA_PWM2 17 228#define CLK_INFRA_PWM3 18 229#define CLK_INFRA_PWM4 19 230#define CLK_INFRA_PWM 20 231#define CLK_INFRA_UART0 21 232#define CLK_INFRA_UART1 22 233#define CLK_INFRA_UART2 23 234#define CLK_INFRA_UART3 24 235#define CLK_INFRA_GCE_26M 25 236#define CLK_INFRA_CQ_DMA_FPC 26 237#define CLK_INFRA_BTIF 27 238#define CLK_INFRA_SPI0 28 239#define CLK_INFRA_MSDC0 29 240#define CLK_INFRA_MSDC1 30 241#define CLK_INFRA_MSDC2 31 242#define CLK_INFRA_MSDC0_SCK 32 243#define CLK_INFRA_DVFSRC 33 244#define CLK_INFRA_GCPU 34 245#define CLK_INFRA_TRNG 35 246#define CLK_INFRA_AUXADC 36 247#define CLK_INFRA_CPUM 37 248#define CLK_INFRA_CCIF1_AP 38 249#define CLK_INFRA_CCIF1_MD 39 250#define CLK_INFRA_AUXADC_MD 40 251#define CLK_INFRA_MSDC1_SCK 41 252#define CLK_INFRA_MSDC2_SCK 42 253#define CLK_INFRA_AP_DMA 43 254#define CLK_INFRA_XIU 44 255#define CLK_INFRA_DEVICE_APC 45 256#define CLK_INFRA_CCIF_AP 46 257#define CLK_INFRA_DEBUGSYS 47 258#define CLK_INFRA_AUD 48 259#define CLK_INFRA_CCIF_MD 49 260#define CLK_INFRA_DXCC_SEC_CORE 50 261#define CLK_INFRA_DXCC_AO 51 262#define CLK_INFRA_DRAMC_F26M 52 263#define CLK_INFRA_IRTX 53 264#define CLK_INFRA_DISP_PWM 54 265#define CLK_INFRA_DPMAIF_CK 55 266#define CLK_INFRA_AUD_26M_BCLK 56 267#define CLK_INFRA_SPI1 57 268#define CLK_INFRA_I2C4 58 269#define CLK_INFRA_MODEM_TEMP_SHARE 59 270#define CLK_INFRA_SPI2 60 271#define CLK_INFRA_SPI3 61 272#define CLK_INFRA_UNIPRO_SCK 62 273#define CLK_INFRA_UNIPRO_TICK 63 274#define CLK_INFRA_UFS_MP_SAP_BCLK 64 275#define CLK_INFRA_MD32_BCLK 65 276#define CLK_INFRA_SSPM 66 277#define CLK_INFRA_UNIPRO_MBIST 67 278#define CLK_INFRA_SSPM_BUS_HCLK 68 279#define CLK_INFRA_I2C5 69 280#define CLK_INFRA_I2C5_ARBITER 70 281#define CLK_INFRA_I2C5_IMM 71 282#define CLK_INFRA_I2C1_ARBITER 72 283#define CLK_INFRA_I2C1_IMM 73 284#define CLK_INFRA_I2C2_ARBITER 74 285#define CLK_INFRA_I2C2_IMM 75 286#define CLK_INFRA_SPI4 76 287#define CLK_INFRA_SPI5 77 288#define CLK_INFRA_CQ_DMA 78 289#define CLK_INFRA_UFS 79 290#define CLK_INFRA_AES_UFSFDE 80 291#define CLK_INFRA_UFS_TICK 81 292#define CLK_INFRA_MSDC0_SELF 82 293#define CLK_INFRA_MSDC1_SELF 83 294#define CLK_INFRA_MSDC2_SELF 84 295#define CLK_INFRA_SSPM_26M_SELF 85 296#define CLK_INFRA_SSPM_32K_SELF 86 297#define CLK_INFRA_UFS_AXI 87 298#define CLK_INFRA_I2C6 88 299#define CLK_INFRA_AP_MSDC0 89 300#define CLK_INFRA_MD_MSDC0 90 301#define CLK_INFRA_USB 91 302#define CLK_INFRA_DEVMPU_BCLK 92 303#define CLK_INFRA_CCIF2_AP 93 304#define CLK_INFRA_CCIF2_MD 94 305#define CLK_INFRA_CCIF3_AP 95 306#define CLK_INFRA_CCIF3_MD 96 307#define CLK_INFRA_SEJ_F13M 97 308#define CLK_INFRA_AES_BCLK 98 309#define CLK_INFRA_I2C7 99 310#define CLK_INFRA_I2C8 100 311#define CLK_INFRA_FBIST2FPC 101 312#define CLK_INFRA_CCIF4_AP 102 313#define CLK_INFRA_CCIF4_MD 103 314#define CLK_INFRA_FADSP 104 315#define CLK_INFRA_SSUSB_XHCI 105 316#define CLK_INFRA_SPI6 106 317#define CLK_INFRA_SPI7 107 318#define CLK_INFRA_NR_CLK 108 319 320/* MFGCFG */ 321#define CLK_MFGCFG_BG3D 1 322#define CLK_MFGCFG_NR_CLK 2 323 324/* IMG */ 325#define CLK_IMG_WPE_A 1 326#define CLK_IMG_MFB 2 327#define CLK_IMG_DIP 3 328#define CLK_IMG_LARB6 4 329#define CLK_IMG_LARB5 5 330#define CLK_IMG_NR_CLK 6 331 332/* IPE */ 333#define CLK_IPE_LARB7 1 334#define CLK_IPE_LARB8 2 335#define CLK_IPE_SMI_SUBCOM 3 336#define CLK_IPE_FD 4 337#define CLK_IPE_FE 5 338#define CLK_IPE_RSC 6 339#define CLK_IPE_DPE 7 340#define CLK_IPE_NR_CLK 8 341 342/* MM_CONFIG */ 343#define CLK_MM_SMI_COMMON 1 344#define CLK_MM_SMI_LARB0 2 345#define CLK_MM_SMI_LARB1 3 346#define CLK_MM_GALS_COMM0 4 347#define CLK_MM_GALS_COMM1 5 348#define CLK_MM_GALS_CCU2MM 6 349#define CLK_MM_GALS_IPU12MM 7 350#define CLK_MM_GALS_IMG2MM 8 351#define CLK_MM_GALS_CAM2MM 9 352#define CLK_MM_GALS_IPU2MM 10 353#define CLK_MM_MDP_DL_TXCK 11 354#define CLK_MM_IPU_DL_TXCK 12 355#define CLK_MM_MDP_RDMA0 13 356#define CLK_MM_MDP_RDMA1 14 357#define CLK_MM_MDP_RSZ0 15 358#define CLK_MM_MDP_RSZ1 16 359#define CLK_MM_MDP_TDSHP 17 360#define CLK_MM_MDP_WROT0 18 361#define CLK_MM_FAKE_ENG 19 362#define CLK_MM_DISP_OVL0 20 363#define CLK_MM_DISP_OVL0_2L 21 364#define CLK_MM_DISP_OVL1_2L 22 365#define CLK_MM_DISP_RDMA0 23 366#define CLK_MM_DISP_RDMA1 24 367#define CLK_MM_DISP_WDMA0 25 368#define CLK_MM_DISP_COLOR0 26 369#define CLK_MM_DISP_CCORR0 27 370#define CLK_MM_DISP_AAL0 28 371#define CLK_MM_DISP_GAMMA0 29 372#define CLK_MM_DISP_DITHER0 30 373#define CLK_MM_DISP_SPLIT 31 374#define CLK_MM_DSI0_MM_CK 32 375#define CLK_MM_DSI0_IF_CK 33 376#define CLK_MM_DPI_MM_CK 34 377#define CLK_MM_DPI_IF_CK 35 378#define CLK_MM_FAKE_ENG2 36 379#define CLK_MM_MDP_DL_RX_CK 37 380#define CLK_MM_IPU_DL_RX_CK 38 381#define CLK_MM_26M 39 382#define CLK_MM_MM_R2Y 40 383#define CLK_MM_DISP_RSZ 41 384#define CLK_MM_MDP_WDMA0 42 385#define CLK_MM_MDP_AAL 43 386#define CLK_MM_MDP_HDR 44 387#define CLK_MM_DBI_MM_CK 45 388#define CLK_MM_DBI_IF_CK 46 389#define CLK_MM_MDP_WROT1 47 390#define CLK_MM_DISP_POSTMASK0 48 391#define CLK_MM_DISP_HRT_BW 49 392#define CLK_MM_DISP_OVL_FBDC 50 393#define CLK_MM_NR_CLK 51 394 395/* VDEC_GCON */ 396#define CLK_VDEC_VDEC 1 397#define CLK_VDEC_LARB1 2 398#define CLK_VDEC_GCON_NR_CLK 3 399 400/* VENC_GCON */ 401#define CLK_VENC_GCON_LARB 1 402#define CLK_VENC_GCON_VENC 2 403#define CLK_VENC_GCON_JPGENC 3 404#define CLK_VENC_GCON_GALS 4 405#define CLK_VENC_GCON_NR_CLK 5 406 407/* AUD */ 408#define CLK_AUD_AFE 1 409#define CLK_AUD_22M 2 410#define CLK_AUD_24M 3 411#define CLK_AUD_APLL2_TUNER 4 412#define CLK_AUD_APLL_TUNER 5 413#define CLK_AUD_TDM 6 414#define CLK_AUD_ADC 7 415#define CLK_AUD_DAC 8 416#define CLK_AUD_DAC_PREDIS 9 417#define CLK_AUD_TML 10 418#define CLK_AUD_NLE 11 419#define CLK_AUD_I2S1_BCLK_SW 12 420#define CLK_AUD_I2S2_BCLK_SW 13 421#define CLK_AUD_I2S3_BCLK_SW 14 422#define CLK_AUD_I2S4_BCLK_SW 15 423#define CLK_AUD_I2S5_BCLK_SW 16 424#define CLK_AUD_CONN_I2S_ASRC 17 425#define CLK_AUD_GENERAL1_ASRC 18 426#define CLK_AUD_GENERAL2_ASRC 19 427#define CLK_AUD_DAC_HIRES 20 428#define CLK_AUD_PDN_ADDA6_ADC 21 429#define CLK_AUD_ADC_HIRES 22 430#define CLK_AUD_ADC_HIRES_TML 23 431#define CLK_AUD_ADDA6_ADC_HIRES 24 432#define CLK_AUD_3RD_DAC 25 433#define CLK_AUD_3RD_DAC_PREDIS 26 434#define CLK_AUD_3RD_DAC_TML 27 435#define CLK_AUD_3RD_DAC_HIRES 28 436#define CLK_AUD_NR_CLK 29 437 438#endif /* _DT_BINDINGS_CLK_MT6779_H */ 439