hi3660-clock.h revision 1.1.1.3 
1/*	$NetBSD: hi3660-clock.h,v 1.1.1.3 2018/04/28 18:25:53 jmcneill Exp $	*/
2
3/*
4 * Copyright (c) 2016-2017 Linaro Ltd.
5 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef __DTS_HI3660_CLOCK_H
14#define __DTS_HI3660_CLOCK_H
15
16/* fixed rate clocks */
17#define HI3660_CLKIN_SYS		0
18#define HI3660_CLKIN_REF		1
19#define HI3660_CLK_FLL_SRC		2
20#define HI3660_CLK_PPLL0		3
21#define HI3660_CLK_PPLL1		4
22#define HI3660_CLK_PPLL2		5
23#define HI3660_CLK_PPLL3		6
24#define HI3660_CLK_SCPLL		7
25#define HI3660_PCLK			8
26#define HI3660_CLK_UART0_DBG		9
27#define HI3660_CLK_UART6		10
28#define HI3660_OSC32K			11
29#define HI3660_OSC19M			12
30#define HI3660_CLK_480M			13
31#define HI3660_CLK_INV			14
32
33/* clk in crgctrl */
34#define HI3660_FACTOR_UART3		15
35#define HI3660_CLK_FACTOR_MMC		16
36#define HI3660_CLK_GATE_I2C0		17
37#define HI3660_CLK_GATE_I2C1		18
38#define HI3660_CLK_GATE_I2C2		19
39#define HI3660_CLK_GATE_I2C6		20
40#define HI3660_CLK_DIV_SYSBUS		21
41#define HI3660_CLK_DIV_320M		22
42#define HI3660_CLK_DIV_A53		23
43#define HI3660_CLK_GATE_SPI0		24
44#define HI3660_CLK_GATE_SPI2		25
45#define HI3660_PCIEPHY_REF		26
46#define HI3660_CLK_ABB_USB		27
47#define HI3660_HCLK_GATE_SDIO0		28
48#define HI3660_HCLK_GATE_SD		29
49#define HI3660_CLK_GATE_AOMM		30
50#define HI3660_PCLK_GPIO0		31
51#define HI3660_PCLK_GPIO1		32
52#define HI3660_PCLK_GPIO2		33
53#define HI3660_PCLK_GPIO3		34
54#define HI3660_PCLK_GPIO4		35
55#define HI3660_PCLK_GPIO5		36
56#define HI3660_PCLK_GPIO6		37
57#define HI3660_PCLK_GPIO7		38
58#define HI3660_PCLK_GPIO8		39
59#define HI3660_PCLK_GPIO9		40
60#define HI3660_PCLK_GPIO10		41
61#define HI3660_PCLK_GPIO11		42
62#define HI3660_PCLK_GPIO12		43
63#define HI3660_PCLK_GPIO13		44
64#define HI3660_PCLK_GPIO14		45
65#define HI3660_PCLK_GPIO15		46
66#define HI3660_PCLK_GPIO16		47
67#define HI3660_PCLK_GPIO17		48
68#define HI3660_PCLK_GPIO18		49
69#define HI3660_PCLK_GPIO19		50
70#define HI3660_PCLK_GPIO20		51
71#define HI3660_PCLK_GPIO21		52
72#define HI3660_CLK_GATE_SPI3		53
73#define HI3660_CLK_GATE_I2C7		54
74#define HI3660_CLK_GATE_I2C3		55
75#define HI3660_CLK_GATE_SPI1		56
76#define HI3660_CLK_GATE_UART1		57
77#define HI3660_CLK_GATE_UART2		58
78#define HI3660_CLK_GATE_UART4		59
79#define HI3660_CLK_GATE_UART5		60
80#define HI3660_CLK_GATE_I2C4		61
81#define HI3660_CLK_GATE_DMAC		62
82#define HI3660_PCLK_GATE_DSS		63
83#define HI3660_ACLK_GATE_DSS		64
84#define HI3660_CLK_GATE_LDI1		65
85#define HI3660_CLK_GATE_LDI0		66
86#define HI3660_CLK_GATE_VIVOBUS		67
87#define HI3660_CLK_GATE_EDC0		68
88#define HI3660_CLK_GATE_TXDPHY0_CFG	69
89#define HI3660_CLK_GATE_TXDPHY0_REF	70
90#define HI3660_CLK_GATE_TXDPHY1_CFG	71
91#define HI3660_CLK_GATE_TXDPHY1_REF	72
92#define HI3660_ACLK_GATE_USB3OTG	73
93#define HI3660_CLK_GATE_SPI4		74
94#define HI3660_CLK_GATE_SD		75
95#define HI3660_CLK_GATE_SDIO0		76
96#define HI3660_CLK_GATE_UFS_SUBSYS	77
97#define HI3660_PCLK_GATE_DSI0		78
98#define HI3660_PCLK_GATE_DSI1		79
99#define HI3660_ACLK_GATE_PCIE		80
100#define HI3660_PCLK_GATE_PCIE_SYS       81
101#define HI3660_CLK_GATE_PCIEAUX		82
102#define HI3660_PCLK_GATE_PCIE_PHY	83
103#define HI3660_CLK_ANDGT_LDI0		84
104#define HI3660_CLK_ANDGT_LDI1		85
105#define HI3660_CLK_ANDGT_EDC0		86
106#define HI3660_CLK_GATE_UFSPHY_GT	87
107#define HI3660_CLK_ANDGT_MMC		88
108#define HI3660_CLK_ANDGT_SD		89
109#define HI3660_CLK_A53HPM_ANDGT		90
110#define HI3660_CLK_ANDGT_SDIO		91
111#define HI3660_CLK_ANDGT_UART0		92
112#define HI3660_CLK_ANDGT_UART1		93
113#define HI3660_CLK_ANDGT_UARTH		94
114#define HI3660_CLK_ANDGT_SPI		95
115#define HI3660_CLK_VIVOBUS_ANDGT	96
116#define HI3660_CLK_AOMM_ANDGT		97
117#define HI3660_CLK_320M_PLL_GT		98
118#define HI3660_AUTODIV_EMMC0BUS		99
119#define HI3660_AUTODIV_SYSBUS		100
120#define HI3660_CLK_GATE_UFSPHY_CFG	101
121#define HI3660_CLK_GATE_UFSIO_REF	102
122#define HI3660_CLK_MUX_SYSBUS		103
123#define HI3660_CLK_MUX_UART0		104
124#define HI3660_CLK_MUX_UART1		105
125#define HI3660_CLK_MUX_UARTH		106
126#define HI3660_CLK_MUX_SPI		107
127#define HI3660_CLK_MUX_I2C		108
128#define HI3660_CLK_MUX_MMC_PLL		109
129#define HI3660_CLK_MUX_LDI1		110
130#define HI3660_CLK_MUX_LDI0		111
131#define HI3660_CLK_MUX_SD_PLL		112
132#define HI3660_CLK_MUX_SD_SYS		113
133#define HI3660_CLK_MUX_EDC0		114
134#define HI3660_CLK_MUX_SDIO_SYS		115
135#define HI3660_CLK_MUX_SDIO_PLL		116
136#define HI3660_CLK_MUX_VIVOBUS		117
137#define HI3660_CLK_MUX_A53HPM		118
138#define HI3660_CLK_MUX_320M		119
139#define HI3660_CLK_MUX_IOPERI		120
140#define HI3660_CLK_DIV_UART0		121
141#define HI3660_CLK_DIV_UART1		122
142#define HI3660_CLK_DIV_UARTH		123
143#define HI3660_CLK_DIV_MMC		124
144#define HI3660_CLK_DIV_SD		125
145#define HI3660_CLK_DIV_EDC0		126
146#define HI3660_CLK_DIV_LDI0		127
147#define HI3660_CLK_DIV_SDIO		128
148#define HI3660_CLK_DIV_LDI1		129
149#define HI3660_CLK_DIV_SPI		130
150#define HI3660_CLK_DIV_VIVOBUS		131
151#define HI3660_CLK_DIV_I2C		132
152#define HI3660_CLK_DIV_UFSPHY		133
153#define HI3660_CLK_DIV_CFGBUS		134
154#define HI3660_CLK_DIV_MMC0BUS		135
155#define HI3660_CLK_DIV_MMC1BUS		136
156#define HI3660_CLK_DIV_UFSPERI		137
157#define HI3660_CLK_DIV_AOMM		138
158#define HI3660_CLK_DIV_IOPERI		139
159#define HI3660_VENC_VOLT_HOLD		140
160#define HI3660_PERI_VOLT_HOLD		141
161#define HI3660_CLK_GATE_VENC		142
162#define HI3660_CLK_GATE_VDEC		143
163#define HI3660_CLK_ANDGT_VENC		144
164#define HI3660_CLK_ANDGT_VDEC		145
165#define HI3660_CLK_MUX_VENC		146
166#define HI3660_CLK_MUX_VDEC		147
167#define HI3660_CLK_DIV_VENC		148
168#define HI3660_CLK_DIV_VDEC		149
169#define HI3660_CLK_FAC_ISP_SNCLK	150
170#define HI3660_CLK_GATE_ISP_SNCLK0	151
171#define HI3660_CLK_GATE_ISP_SNCLK1	152
172#define HI3660_CLK_GATE_ISP_SNCLK2	153
173#define HI3660_CLK_ANGT_ISP_SNCLK	154
174#define HI3660_CLK_MUX_ISP_SNCLK	155
175#define HI3660_CLK_DIV_ISP_SNCLK	156
176
177/* clk in pmuctrl */
178#define HI3660_GATE_ABB_192		0
179
180/* clk in pctrl */
181#define HI3660_GATE_UFS_TCXO_EN		0
182#define HI3660_GATE_USB_TCXO_EN		1
183
184/* clk in sctrl */
185#define HI3660_PCLK_AO_GPIO0		0
186#define HI3660_PCLK_AO_GPIO1		1
187#define HI3660_PCLK_AO_GPIO2		2
188#define HI3660_PCLK_AO_GPIO3		3
189#define HI3660_PCLK_AO_GPIO4		4
190#define HI3660_PCLK_AO_GPIO5		5
191#define HI3660_PCLK_AO_GPIO6		6
192#define HI3660_PCLK_GATE_MMBUF		7
193#define HI3660_CLK_GATE_DSS_AXI_MM	8
194#define HI3660_PCLK_MMBUF_ANDGT		9
195#define HI3660_CLK_MMBUF_PLL_ANDGT	10
196#define HI3660_CLK_FLL_MMBUF_ANDGT	11
197#define HI3660_CLK_SYS_MMBUF_ANDGT	12
198#define HI3660_CLK_GATE_PCIEPHY_GT	13
199#define HI3660_ACLK_MUX_MMBUF		14
200#define HI3660_CLK_SW_MMBUF		15
201#define HI3660_CLK_DIV_AOBUS		16
202#define HI3660_PCLK_DIV_MMBUF		17
203#define HI3660_ACLK_DIV_MMBUF		18
204#define HI3660_CLK_DIV_PCIEPHY		19
205
206/* clk in iomcu */
207#define HI3660_CLK_I2C0_IOMCU		0
208#define HI3660_CLK_I2C1_IOMCU		1
209#define HI3660_CLK_I2C2_IOMCU		2
210#define HI3660_CLK_I2C6_IOMCU		3
211#define HI3660_CLK_IOMCU_PERI0		4
212
213/* clk in stub clock */
214#define HI3660_CLK_STUB_CLUSTER0	0
215#define HI3660_CLK_STUB_CLUSTER1	1
216#define HI3660_CLK_STUB_GPU		2
217#define HI3660_CLK_STUB_DDR		3
218#define HI3660_CLK_STUB_NUM		4
219
220#endif	/* __DTS_HI3660_CLOCK_H */
221