1/* $NetBSD: exynos5433.h,v 1.1.1.3 2019/05/25 11:29:13 jmcneill Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0 */ 4/* 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * Author: Chanwoo Choi <cw00.choi@samsung.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H 10#define _DT_BINDINGS_CLOCK_EXYNOS5433_H 11 12/* CMU_TOP */ 13#define CLK_FOUT_ISP_PLL 1 14#define CLK_FOUT_AUD_PLL 2 15 16#define CLK_MOUT_AUD_PLL 10 17#define CLK_MOUT_ISP_PLL 11 18#define CLK_MOUT_AUD_PLL_USER_T 12 19#define CLK_MOUT_MPHY_PLL_USER 13 20#define CLK_MOUT_MFC_PLL_USER 14 21#define CLK_MOUT_BUS_PLL_USER 15 22#define CLK_MOUT_ACLK_HEVC_400 16 23#define CLK_MOUT_ACLK_CAM1_333 17 24#define CLK_MOUT_ACLK_CAM1_552_B 18 25#define CLK_MOUT_ACLK_CAM1_552_A 19 26#define CLK_MOUT_ACLK_ISP_DIS_400 20 27#define CLK_MOUT_ACLK_ISP_400 21 28#define CLK_MOUT_ACLK_BUS0_400 22 29#define CLK_MOUT_ACLK_MSCL_400_B 23 30#define CLK_MOUT_ACLK_MSCL_400_A 24 31#define CLK_MOUT_ACLK_GSCL_333 25 32#define CLK_MOUT_ACLK_G2D_400_B 26 33#define CLK_MOUT_ACLK_G2D_400_A 27 34#define CLK_MOUT_SCLK_JPEG_C 28 35#define CLK_MOUT_SCLK_JPEG_B 29 36#define CLK_MOUT_SCLK_JPEG_A 30 37#define CLK_MOUT_SCLK_MMC2_B 31 38#define CLK_MOUT_SCLK_MMC2_A 32 39#define CLK_MOUT_SCLK_MMC1_B 33 40#define CLK_MOUT_SCLK_MMC1_A 34 41#define CLK_MOUT_SCLK_MMC0_D 35 42#define CLK_MOUT_SCLK_MMC0_C 36 43#define CLK_MOUT_SCLK_MMC0_B 37 44#define CLK_MOUT_SCLK_MMC0_A 38 45#define CLK_MOUT_SCLK_SPI4 39 46#define CLK_MOUT_SCLK_SPI3 40 47#define CLK_MOUT_SCLK_UART2 41 48#define CLK_MOUT_SCLK_UART1 42 49#define CLK_MOUT_SCLK_UART0 43 50#define CLK_MOUT_SCLK_SPI2 44 51#define CLK_MOUT_SCLK_SPI1 45 52#define CLK_MOUT_SCLK_SPI0 46 53#define CLK_MOUT_ACLK_MFC_400_C 47 54#define CLK_MOUT_ACLK_MFC_400_B 48 55#define CLK_MOUT_ACLK_MFC_400_A 49 56#define CLK_MOUT_SCLK_ISP_SENSOR2 50 57#define CLK_MOUT_SCLK_ISP_SENSOR1 51 58#define CLK_MOUT_SCLK_ISP_SENSOR0 52 59#define CLK_MOUT_SCLK_ISP_UART 53 60#define CLK_MOUT_SCLK_ISP_SPI1 54 61#define CLK_MOUT_SCLK_ISP_SPI0 55 62#define CLK_MOUT_SCLK_PCIE_100 56 63#define CLK_MOUT_SCLK_UFSUNIPRO 57 64#define CLK_MOUT_SCLK_USBHOST30 58 65#define CLK_MOUT_SCLK_USBDRD30 59 66#define CLK_MOUT_SCLK_SLIMBUS 60 67#define CLK_MOUT_SCLK_SPDIF 61 68#define CLK_MOUT_SCLK_AUDIO1 62 69#define CLK_MOUT_SCLK_AUDIO0 63 70#define CLK_MOUT_SCLK_HDMI_SPDIF 64 71 72#define CLK_DIV_ACLK_FSYS_200 100 73#define CLK_DIV_ACLK_IMEM_SSSX_266 101 74#define CLK_DIV_ACLK_IMEM_200 102 75#define CLK_DIV_ACLK_IMEM_266 103 76#define CLK_DIV_ACLK_PERIC_66_B 104 77#define CLK_DIV_ACLK_PERIC_66_A 105 78#define CLK_DIV_ACLK_PERIS_66_B 106 79#define CLK_DIV_ACLK_PERIS_66_A 107 80#define CLK_DIV_SCLK_MMC1_B 108 81#define CLK_DIV_SCLK_MMC1_A 109 82#define CLK_DIV_SCLK_MMC0_B 110 83#define CLK_DIV_SCLK_MMC0_A 111 84#define CLK_DIV_SCLK_MMC2_B 112 85#define CLK_DIV_SCLK_MMC2_A 113 86#define CLK_DIV_SCLK_SPI1_B 114 87#define CLK_DIV_SCLK_SPI1_A 115 88#define CLK_DIV_SCLK_SPI0_B 116 89#define CLK_DIV_SCLK_SPI0_A 117 90#define CLK_DIV_SCLK_SPI2_B 118 91#define CLK_DIV_SCLK_SPI2_A 119 92#define CLK_DIV_SCLK_UART2 120 93#define CLK_DIV_SCLK_UART1 121 94#define CLK_DIV_SCLK_UART0 122 95#define CLK_DIV_SCLK_SPI4_B 123 96#define CLK_DIV_SCLK_SPI4_A 124 97#define CLK_DIV_SCLK_SPI3_B 125 98#define CLK_DIV_SCLK_SPI3_A 126 99#define CLK_DIV_SCLK_I2S1 127 100#define CLK_DIV_SCLK_PCM1 128 101#define CLK_DIV_SCLK_AUDIO1 129 102#define CLK_DIV_SCLK_AUDIO0 130 103#define CLK_DIV_ACLK_GSCL_111 131 104#define CLK_DIV_ACLK_GSCL_333 132 105#define CLK_DIV_ACLK_HEVC_400 133 106#define CLK_DIV_ACLK_MFC_400 134 107#define CLK_DIV_ACLK_G2D_266 135 108#define CLK_DIV_ACLK_G2D_400 136 109#define CLK_DIV_ACLK_G3D_400 137 110#define CLK_DIV_ACLK_BUS0_400 138 111#define CLK_DIV_ACLK_BUS1_400 139 112#define CLK_DIV_SCLK_PCIE_100 140 113#define CLK_DIV_SCLK_USBHOST30 141 114#define CLK_DIV_SCLK_UFSUNIPRO 142 115#define CLK_DIV_SCLK_USBDRD30 143 116#define CLK_DIV_SCLK_JPEG 144 117#define CLK_DIV_ACLK_MSCL_400 145 118#define CLK_DIV_ACLK_ISP_DIS_400 146 119#define CLK_DIV_ACLK_ISP_400 147 120#define CLK_DIV_ACLK_CAM0_333 148 121#define CLK_DIV_ACLK_CAM0_400 149 122#define CLK_DIV_ACLK_CAM0_552 150 123#define CLK_DIV_ACLK_CAM1_333 151 124#define CLK_DIV_ACLK_CAM1_400 152 125#define CLK_DIV_ACLK_CAM1_552 153 126#define CLK_DIV_SCLK_ISP_UART 154 127#define CLK_DIV_SCLK_ISP_SPI1_B 155 128#define CLK_DIV_SCLK_ISP_SPI1_A 156 129#define CLK_DIV_SCLK_ISP_SPI0_B 157 130#define CLK_DIV_SCLK_ISP_SPI0_A 158 131#define CLK_DIV_SCLK_ISP_SENSOR2_B 159 132#define CLK_DIV_SCLK_ISP_SENSOR2_A 160 133#define CLK_DIV_SCLK_ISP_SENSOR1_B 161 134#define CLK_DIV_SCLK_ISP_SENSOR1_A 162 135#define CLK_DIV_SCLK_ISP_SENSOR0_B 163 136#define CLK_DIV_SCLK_ISP_SENSOR0_A 164 137 138#define CLK_ACLK_PERIC_66 200 139#define CLK_ACLK_PERIS_66 201 140#define CLK_ACLK_FSYS_200 202 141#define CLK_SCLK_MMC2_FSYS 203 142#define CLK_SCLK_MMC1_FSYS 204 143#define CLK_SCLK_MMC0_FSYS 205 144#define CLK_SCLK_SPI4_PERIC 206 145#define CLK_SCLK_SPI3_PERIC 207 146#define CLK_SCLK_UART2_PERIC 208 147#define CLK_SCLK_UART1_PERIC 209 148#define CLK_SCLK_UART0_PERIC 210 149#define CLK_SCLK_SPI2_PERIC 211 150#define CLK_SCLK_SPI1_PERIC 212 151#define CLK_SCLK_SPI0_PERIC 213 152#define CLK_SCLK_SPDIF_PERIC 214 153#define CLK_SCLK_I2S1_PERIC 215 154#define CLK_SCLK_PCM1_PERIC 216 155#define CLK_SCLK_SLIMBUS 217 156#define CLK_SCLK_AUDIO1 218 157#define CLK_SCLK_AUDIO0 219 158#define CLK_ACLK_G2D_266 220 159#define CLK_ACLK_G2D_400 221 160#define CLK_ACLK_G3D_400 222 161#define CLK_ACLK_IMEM_SSSX_266 223 162#define CLK_ACLK_BUS0_400 224 163#define CLK_ACLK_BUS1_400 225 164#define CLK_ACLK_IMEM_200 226 165#define CLK_ACLK_IMEM_266 227 166#define CLK_SCLK_PCIE_100_FSYS 228 167#define CLK_SCLK_UFSUNIPRO_FSYS 229 168#define CLK_SCLK_USBHOST30_FSYS 230 169#define CLK_SCLK_USBDRD30_FSYS 231 170#define CLK_ACLK_GSCL_111 232 171#define CLK_ACLK_GSCL_333 233 172#define CLK_SCLK_JPEG_MSCL 234 173#define CLK_ACLK_MSCL_400 235 174#define CLK_ACLK_MFC_400 236 175#define CLK_ACLK_HEVC_400 237 176#define CLK_ACLK_ISP_DIS_400 238 177#define CLK_ACLK_ISP_400 239 178#define CLK_ACLK_CAM0_333 240 179#define CLK_ACLK_CAM0_400 241 180#define CLK_ACLK_CAM0_552 242 181#define CLK_ACLK_CAM1_333 243 182#define CLK_ACLK_CAM1_400 244 183#define CLK_ACLK_CAM1_552 245 184#define CLK_SCLK_ISP_SENSOR2 246 185#define CLK_SCLK_ISP_SENSOR1 247 186#define CLK_SCLK_ISP_SENSOR0 248 187#define CLK_SCLK_ISP_MCTADC_CAM1 249 188#define CLK_SCLK_ISP_UART_CAM1 250 189#define CLK_SCLK_ISP_SPI1_CAM1 251 190#define CLK_SCLK_ISP_SPI0_CAM1 252 191#define CLK_SCLK_HDMI_SPDIF_DISP 253 192 193#define TOP_NR_CLK 254 194 195/* CMU_CPIF */ 196#define CLK_FOUT_MPHY_PLL 1 197 198#define CLK_MOUT_MPHY_PLL 2 199 200#define CLK_DIV_SCLK_MPHY 10 201 202#define CLK_SCLK_MPHY_PLL 11 203#define CLK_SCLK_UFS_MPHY 11 204 205#define CPIF_NR_CLK 12 206 207/* CMU_MIF */ 208#define CLK_FOUT_MEM0_PLL 1 209#define CLK_FOUT_MEM1_PLL 2 210#define CLK_FOUT_BUS_PLL 3 211#define CLK_FOUT_MFC_PLL 4 212#define CLK_DOUT_MFC_PLL 5 213#define CLK_DOUT_BUS_PLL 6 214#define CLK_DOUT_MEM1_PLL 7 215#define CLK_DOUT_MEM0_PLL 8 216 217#define CLK_MOUT_MFC_PLL_DIV2 10 218#define CLK_MOUT_BUS_PLL_DIV2 11 219#define CLK_MOUT_MEM1_PLL_DIV2 12 220#define CLK_MOUT_MEM0_PLL_DIV2 13 221#define CLK_MOUT_MFC_PLL 14 222#define CLK_MOUT_BUS_PLL 15 223#define CLK_MOUT_MEM1_PLL 16 224#define CLK_MOUT_MEM0_PLL 17 225#define CLK_MOUT_CLK2X_PHY_C 18 226#define CLK_MOUT_CLK2X_PHY_B 19 227#define CLK_MOUT_CLK2X_PHY_A 20 228#define CLK_MOUT_CLKM_PHY_C 21 229#define CLK_MOUT_CLKM_PHY_B 22 230#define CLK_MOUT_CLKM_PHY_A 23 231#define CLK_MOUT_ACLK_MIFNM_200 24 232#define CLK_MOUT_ACLK_MIFNM_400 25 233#define CLK_MOUT_ACLK_DISP_333_B 26 234#define CLK_MOUT_ACLK_DISP_333_A 27 235#define CLK_MOUT_SCLK_DECON_VCLK_C 28 236#define CLK_MOUT_SCLK_DECON_VCLK_B 29 237#define CLK_MOUT_SCLK_DECON_VCLK_A 30 238#define CLK_MOUT_SCLK_DECON_ECLK_C 31 239#define CLK_MOUT_SCLK_DECON_ECLK_B 32 240#define CLK_MOUT_SCLK_DECON_ECLK_A 33 241#define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34 242#define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35 243#define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36 244#define CLK_MOUT_SCLK_DSD_C 37 245#define CLK_MOUT_SCLK_DSD_B 38 246#define CLK_MOUT_SCLK_DSD_A 39 247#define CLK_MOUT_SCLK_DSIM0_C 40 248#define CLK_MOUT_SCLK_DSIM0_B 41 249#define CLK_MOUT_SCLK_DSIM0_A 42 250#define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46 251#define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47 252#define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48 253#define CLK_MOUT_SCLK_DSIM1_C 49 254#define CLK_MOUT_SCLK_DSIM1_B 50 255#define CLK_MOUT_SCLK_DSIM1_A 51 256 257#define CLK_DIV_SCLK_HPM_MIF 55 258#define CLK_DIV_ACLK_DREX1 56 259#define CLK_DIV_ACLK_DREX0 57 260#define CLK_DIV_CLK2XPHY 58 261#define CLK_DIV_ACLK_MIF_266 59 262#define CLK_DIV_ACLK_MIFND_133 60 263#define CLK_DIV_ACLK_MIF_133 61 264#define CLK_DIV_ACLK_MIFNM_200 62 265#define CLK_DIV_ACLK_MIF_200 63 266#define CLK_DIV_ACLK_MIF_400 64 267#define CLK_DIV_ACLK_BUS2_400 65 268#define CLK_DIV_ACLK_DISP_333 66 269#define CLK_DIV_ACLK_CPIF_200 67 270#define CLK_DIV_SCLK_DSIM1 68 271#define CLK_DIV_SCLK_DECON_TV_VCLK 69 272#define CLK_DIV_SCLK_DSIM0 70 273#define CLK_DIV_SCLK_DSD 71 274#define CLK_DIV_SCLK_DECON_TV_ECLK 72 275#define CLK_DIV_SCLK_DECON_VCLK 73 276#define CLK_DIV_SCLK_DECON_ECLK 74 277#define CLK_DIV_MIF_PRE 75 278 279#define CLK_CLK2X_PHY1 80 280#define CLK_CLK2X_PHY0 81 281#define CLK_CLKM_PHY1 82 282#define CLK_CLKM_PHY0 83 283#define CLK_RCLK_DREX1 84 284#define CLK_RCLK_DREX0 85 285#define CLK_ACLK_DREX1_TZ 86 286#define CLK_ACLK_DREX0_TZ 87 287#define CLK_ACLK_DREX1_PEREV 88 288#define CLK_ACLK_DREX0_PEREV 89 289#define CLK_ACLK_DREX1_MEMIF 90 290#define CLK_ACLK_DREX0_MEMIF 91 291#define CLK_ACLK_DREX1_SCH 92 292#define CLK_ACLK_DREX0_SCH 93 293#define CLK_ACLK_DREX1_BUSIF 94 294#define CLK_ACLK_DREX0_BUSIF 95 295#define CLK_ACLK_DREX1_BUSIF_RD 96 296#define CLK_ACLK_DREX0_BUSIF_RD 97 297#define CLK_ACLK_DREX1 98 298#define CLK_ACLK_DREX0 99 299#define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100 300#define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101 301#define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102 302#define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103 303#define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104 304#define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105 305#define CLK_ACLK_ASYNCAXIS_CP1 106 306#define CLK_ACLK_ASYNCAXIM_CP1 107 307#define CLK_ACLK_ASYNCAXIS_CP0 108 308#define CLK_ACLK_ASYNCAXIM_CP0 109 309#define CLK_ACLK_ASYNCAXIS_DREX1_3 110 310#define CLK_ACLK_ASYNCAXIM_DREX1_3 111 311#define CLK_ACLK_ASYNCAXIS_DREX1_1 112 312#define CLK_ACLK_ASYNCAXIM_DREX1_1 113 313#define CLK_ACLK_ASYNCAXIS_DREX1_0 114 314#define CLK_ACLK_ASYNCAXIM_DREX1_0 115 315#define CLK_ACLK_ASYNCAXIS_DREX0_3 116 316#define CLK_ACLK_ASYNCAXIM_DREX0_3 117 317#define CLK_ACLK_ASYNCAXIS_DREX0_1 118 318#define CLK_ACLK_ASYNCAXIM_DREX0_1 119 319#define CLK_ACLK_ASYNCAXIS_DREX0_0 120 320#define CLK_ACLK_ASYNCAXIM_DREX0_0 121 321#define CLK_ACLK_AHB2APB_MIF2P 122 322#define CLK_ACLK_AHB2APB_MIF1P 123 323#define CLK_ACLK_AHB2APB_MIF0P 124 324#define CLK_ACLK_IXIU_CCI 125 325#define CLK_ACLK_XIU_MIFSFRX 126 326#define CLK_ACLK_MIFNP_133 127 327#define CLK_ACLK_MIFNM_200 128 328#define CLK_ACLK_MIFND_133 129 329#define CLK_ACLK_MIFND_400 130 330#define CLK_ACLK_CCI 131 331#define CLK_ACLK_MIFND_266 132 332#define CLK_ACLK_PPMU_DREX1S3 133 333#define CLK_ACLK_PPMU_DREX1S1 134 334#define CLK_ACLK_PPMU_DREX1S0 135 335#define CLK_ACLK_PPMU_DREX0S3 136 336#define CLK_ACLK_PPMU_DREX0S1 137 337#define CLK_ACLK_PPMU_DREX0S0 138 338#define CLK_ACLK_BTS_APOLLO 139 339#define CLK_ACLK_BTS_ATLAS 140 340#define CLK_ACLK_ACE_SEL_APOLL 141 341#define CLK_ACLK_ACE_SEL_ATLAS 142 342#define CLK_ACLK_AXIDS_CCI_MIFSFRX 143 343#define CLK_ACLK_AXIUS_ATLAS_CCI 144 344#define CLK_ACLK_AXISYNCDNS_CCI 145 345#define CLK_ACLK_AXISYNCDN_CCI 146 346#define CLK_ACLK_AXISYNCDN_NOC_D 147 347#define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148 348#define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149 349#define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150 350#define CLK_ACLK_BUS2_400 151 351#define CLK_ACLK_DISP_333 152 352#define CLK_ACLK_CPIF_200 153 353#define CLK_PCLK_PPMU_DREX1S3 154 354#define CLK_PCLK_PPMU_DREX1S1 155 355#define CLK_PCLK_PPMU_DREX1S0 156 356#define CLK_PCLK_PPMU_DREX0S3 157 357#define CLK_PCLK_PPMU_DREX0S1 158 358#define CLK_PCLK_PPMU_DREX0S0 159 359#define CLK_PCLK_BTS_APOLLO 160 360#define CLK_PCLK_BTS_ATLAS 161 361#define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162 362#define CLK_PCLK_ASYNCAXI_CP1 163 363#define CLK_PCLK_ASYNCAXI_CP0 164 364#define CLK_PCLK_ASYNCAXI_DREX1_3 165 365#define CLK_PCLK_ASYNCAXI_DREX1_1 166 366#define CLK_PCLK_ASYNCAXI_DREX1_0 167 367#define CLK_PCLK_ASYNCAXI_DREX0_3 168 368#define CLK_PCLK_ASYNCAXI_DREX0_1 169 369#define CLK_PCLK_ASYNCAXI_DREX0_0 170 370#define CLK_PCLK_MIFSRVND_133 171 371#define CLK_PCLK_PMU_MIF 172 372#define CLK_PCLK_SYSREG_MIF 173 373#define CLK_PCLK_GPIO_ALIVE 174 374#define CLK_PCLK_ABB 175 375#define CLK_PCLK_PMU_APBIF 176 376#define CLK_PCLK_DDR_PHY1 177 377#define CLK_PCLK_DREX1 178 378#define CLK_PCLK_DDR_PHY0 179 379#define CLK_PCLK_DREX0 180 380#define CLK_PCLK_DREX0_TZ 181 381#define CLK_PCLK_DREX1_TZ 182 382#define CLK_PCLK_MONOTONIC_CNT 183 383#define CLK_PCLK_RTC 184 384#define CLK_SCLK_DSIM1_DISP 185 385#define CLK_SCLK_DECON_TV_VCLK_DISP 186 386#define CLK_SCLK_FREQ_DET_BUS_PLL 187 387#define CLK_SCLK_FREQ_DET_MFC_PLL 188 388#define CLK_SCLK_FREQ_DET_MEM0_PLL 189 389#define CLK_SCLK_FREQ_DET_MEM1_PLL 190 390#define CLK_SCLK_DSIM0_DISP 191 391#define CLK_SCLK_DSD_DISP 192 392#define CLK_SCLK_DECON_TV_ECLK_DISP 193 393#define CLK_SCLK_DECON_VCLK_DISP 194 394#define CLK_SCLK_DECON_ECLK_DISP 195 395#define CLK_SCLK_HPM_MIF 196 396#define CLK_SCLK_MFC_PLL 197 397#define CLK_SCLK_BUS_PLL 198 398#define CLK_SCLK_BUS_PLL_APOLLO 199 399#define CLK_SCLK_BUS_PLL_ATLAS 200 400 401#define MIF_NR_CLK 201 402 403/* CMU_PERIC */ 404#define CLK_PCLK_SPI2 1 405#define CLK_PCLK_SPI1 2 406#define CLK_PCLK_SPI0 3 407#define CLK_PCLK_UART2 4 408#define CLK_PCLK_UART1 5 409#define CLK_PCLK_UART0 6 410#define CLK_PCLK_HSI2C3 7 411#define CLK_PCLK_HSI2C2 8 412#define CLK_PCLK_HSI2C1 9 413#define CLK_PCLK_HSI2C0 10 414#define CLK_PCLK_I2C7 11 415#define CLK_PCLK_I2C6 12 416#define CLK_PCLK_I2C5 13 417#define CLK_PCLK_I2C4 14 418#define CLK_PCLK_I2C3 15 419#define CLK_PCLK_I2C2 16 420#define CLK_PCLK_I2C1 17 421#define CLK_PCLK_I2C0 18 422#define CLK_PCLK_SPI4 19 423#define CLK_PCLK_SPI3 20 424#define CLK_PCLK_HSI2C11 21 425#define CLK_PCLK_HSI2C10 22 426#define CLK_PCLK_HSI2C9 23 427#define CLK_PCLK_HSI2C8 24 428#define CLK_PCLK_HSI2C7 25 429#define CLK_PCLK_HSI2C6 26 430#define CLK_PCLK_HSI2C5 27 431#define CLK_PCLK_HSI2C4 28 432#define CLK_SCLK_SPI4 29 433#define CLK_SCLK_SPI3 30 434#define CLK_SCLK_SPI2 31 435#define CLK_SCLK_SPI1 32 436#define CLK_SCLK_SPI0 33 437#define CLK_SCLK_UART2 34 438#define CLK_SCLK_UART1 35 439#define CLK_SCLK_UART0 36 440#define CLK_ACLK_AHB2APB_PERIC2P 37 441#define CLK_ACLK_AHB2APB_PERIC1P 38 442#define CLK_ACLK_AHB2APB_PERIC0P 39 443#define CLK_ACLK_PERICNP_66 40 444#define CLK_PCLK_SCI 41 445#define CLK_PCLK_GPIO_FINGER 42 446#define CLK_PCLK_GPIO_ESE 43 447#define CLK_PCLK_PWM 44 448#define CLK_PCLK_SPDIF 45 449#define CLK_PCLK_PCM1 46 450#define CLK_PCLK_I2S1 47 451#define CLK_PCLK_ADCIF 48 452#define CLK_PCLK_GPIO_TOUCH 49 453#define CLK_PCLK_GPIO_NFC 50 454#define CLK_PCLK_GPIO_PERIC 51 455#define CLK_PCLK_PMU_PERIC 52 456#define CLK_PCLK_SYSREG_PERIC 53 457#define CLK_SCLK_IOCLK_SPI4 54 458#define CLK_SCLK_IOCLK_SPI3 55 459#define CLK_SCLK_SCI 56 460#define CLK_SCLK_SC_IN 57 461#define CLK_SCLK_PWM 58 462#define CLK_SCLK_IOCLK_SPI2 59 463#define CLK_SCLK_IOCLK_SPI1 60 464#define CLK_SCLK_IOCLK_SPI0 61 465#define CLK_SCLK_IOCLK_I2S1_BCLK 62 466#define CLK_SCLK_SPDIF 63 467#define CLK_SCLK_PCM1 64 468#define CLK_SCLK_I2S1 65 469 470#define CLK_DIV_SCLK_SCI 70 471#define CLK_DIV_SCLK_SC_IN 71 472 473#define PERIC_NR_CLK 72 474 475/* CMU_PERIS */ 476#define CLK_PCLK_HPM_APBIF 1 477#define CLK_PCLK_TMU1_APBIF 2 478#define CLK_PCLK_TMU0_APBIF 3 479#define CLK_PCLK_PMU_PERIS 4 480#define CLK_PCLK_SYSREG_PERIS 5 481#define CLK_PCLK_CMU_TOP_APBIF 6 482#define CLK_PCLK_WDT_APOLLO 7 483#define CLK_PCLK_WDT_ATLAS 8 484#define CLK_PCLK_MCT 9 485#define CLK_PCLK_HDMI_CEC 10 486#define CLK_ACLK_AHB2APB_PERIS1P 11 487#define CLK_ACLK_AHB2APB_PERIS0P 12 488#define CLK_ACLK_PERISNP_66 13 489#define CLK_PCLK_TZPC12 14 490#define CLK_PCLK_TZPC11 15 491#define CLK_PCLK_TZPC10 16 492#define CLK_PCLK_TZPC9 17 493#define CLK_PCLK_TZPC8 18 494#define CLK_PCLK_TZPC7 19 495#define CLK_PCLK_TZPC6 20 496#define CLK_PCLK_TZPC5 21 497#define CLK_PCLK_TZPC4 22 498#define CLK_PCLK_TZPC3 23 499#define CLK_PCLK_TZPC2 24 500#define CLK_PCLK_TZPC1 25 501#define CLK_PCLK_TZPC0 26 502#define CLK_PCLK_SECKEY_APBIF 27 503#define CLK_PCLK_CHIPID_APBIF 28 504#define CLK_PCLK_TOPRTC 29 505#define CLK_PCLK_CUSTOM_EFUSE_APBIF 30 506#define CLK_PCLK_ANTIRBK_CNT_APBIF 31 507#define CLK_PCLK_OTP_CON_APBIF 32 508#define CLK_SCLK_ASV_TB 33 509#define CLK_SCLK_TMU1 34 510#define CLK_SCLK_TMU0 35 511#define CLK_SCLK_SECKEY 36 512#define CLK_SCLK_CHIPID 37 513#define CLK_SCLK_TOPRTC 38 514#define CLK_SCLK_CUSTOM_EFUSE 39 515#define CLK_SCLK_ANTIRBK_CNT 40 516#define CLK_SCLK_OTP_CON 41 517 518#define PERIS_NR_CLK 42 519 520/* CMU_FSYS */ 521#define CLK_MOUT_ACLK_FSYS_200_USER 1 522#define CLK_MOUT_SCLK_MMC2_USER 2 523#define CLK_MOUT_SCLK_MMC1_USER 3 524#define CLK_MOUT_SCLK_MMC0_USER 4 525#define CLK_MOUT_SCLK_UFS_MPHY_USER 5 526#define CLK_MOUT_SCLK_PCIE_100_USER 6 527#define CLK_MOUT_SCLK_UFSUNIPRO_USER 7 528#define CLK_MOUT_SCLK_USBHOST30_USER 8 529#define CLK_MOUT_SCLK_USBDRD30_USER 9 530#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10 531#define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11 532#define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12 533#define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13 534#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14 535#define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15 536#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16 537#define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17 538#define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18 539#define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19 540#define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20 541#define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21 542#define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22 543#define CLK_MOUT_SCLK_MPHY 23 544 545#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25 546#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26 547#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27 548#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28 549#define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29 550#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30 551#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31 552#define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32 553#define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33 554#define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34 555#define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35 556#define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36 557#define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37 558 559#define CLK_ACLK_PCIE 50 560#define CLK_ACLK_PDMA1 51 561#define CLK_ACLK_TSI 52 562#define CLK_ACLK_MMC2 53 563#define CLK_ACLK_MMC1 54 564#define CLK_ACLK_MMC0 55 565#define CLK_ACLK_UFS 56 566#define CLK_ACLK_USBHOST20 57 567#define CLK_ACLK_USBHOST30 58 568#define CLK_ACLK_USBDRD30 59 569#define CLK_ACLK_PDMA0 60 570#define CLK_SCLK_MMC2 61 571#define CLK_SCLK_MMC1 62 572#define CLK_SCLK_MMC0 63 573#define CLK_PDMA1 64 574#define CLK_PDMA0 65 575#define CLK_ACLK_XIU_FSYSPX 66 576#define CLK_ACLK_AHB_USBLINKH1 67 577#define CLK_ACLK_SMMU_PDMA1 68 578#define CLK_ACLK_BTS_PCIE 69 579#define CLK_ACLK_AXIUS_PDMA1 70 580#define CLK_ACLK_SMMU_PDMA0 71 581#define CLK_ACLK_BTS_UFS 72 582#define CLK_ACLK_BTS_USBHOST30 73 583#define CLK_ACLK_BTS_USBDRD30 74 584#define CLK_ACLK_AXIUS_PDMA0 75 585#define CLK_ACLK_AXIUS_USBHS 76 586#define CLK_ACLK_AXIUS_FSYSSX 77 587#define CLK_ACLK_AHB2APB_FSYSP 78 588#define CLK_ACLK_AHB2AXI_USBHS 79 589#define CLK_ACLK_AHB_USBLINKH0 80 590#define CLK_ACLK_AHB_USBHS 81 591#define CLK_ACLK_AHB_FSYSH 82 592#define CLK_ACLK_XIU_FSYSX 83 593#define CLK_ACLK_XIU_FSYSSX 84 594#define CLK_ACLK_FSYSNP_200 85 595#define CLK_ACLK_FSYSND_200 86 596#define CLK_PCLK_PCIE_CTRL 87 597#define CLK_PCLK_SMMU_PDMA1 88 598#define CLK_PCLK_PCIE_PHY 89 599#define CLK_PCLK_BTS_PCIE 90 600#define CLK_PCLK_SMMU_PDMA0 91 601#define CLK_PCLK_BTS_UFS 92 602#define CLK_PCLK_BTS_USBHOST30 93 603#define CLK_PCLK_BTS_USBDRD30 94 604#define CLK_PCLK_GPIO_FSYS 95 605#define CLK_PCLK_PMU_FSYS 96 606#define CLK_PCLK_SYSREG_FSYS 97 607#define CLK_SCLK_PCIE_100 98 608#define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99 609#define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100 610#define CLK_PHYCLK_UFS_RX1_SYMBOL 101 611#define CLK_PHYCLK_UFS_RX0_SYMBOL 102 612#define CLK_PHYCLK_UFS_TX1_SYMBOL 103 613#define CLK_PHYCLK_UFS_TX0_SYMBOL 104 614#define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105 615#define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106 616#define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107 617#define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108 618#define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109 619#define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110 620#define CLK_SCLK_MPHY 111 621#define CLK_SCLK_UFSUNIPRO 112 622#define CLK_SCLK_USBHOST30 113 623#define CLK_SCLK_USBDRD30 114 624#define CLK_PCIE 115 625 626#define FSYS_NR_CLK 116 627 628/* CMU_G2D */ 629#define CLK_MUX_ACLK_G2D_266_USER 1 630#define CLK_MUX_ACLK_G2D_400_USER 2 631 632#define CLK_DIV_PCLK_G2D 3 633 634#define CLK_ACLK_SMMU_MDMA1 4 635#define CLK_ACLK_BTS_MDMA1 5 636#define CLK_ACLK_BTS_G2D 6 637#define CLK_ACLK_ALB_G2D 7 638#define CLK_ACLK_AXIUS_G2DX 8 639#define CLK_ACLK_ASYNCAXI_SYSX 9 640#define CLK_ACLK_AHB2APB_G2D1P 10 641#define CLK_ACLK_AHB2APB_G2D0P 11 642#define CLK_ACLK_XIU_G2DX 12 643#define CLK_ACLK_G2DNP_133 13 644#define CLK_ACLK_G2DND_400 14 645#define CLK_ACLK_MDMA1 15 646#define CLK_ACLK_G2D 16 647#define CLK_ACLK_SMMU_G2D 17 648#define CLK_PCLK_SMMU_MDMA1 18 649#define CLK_PCLK_BTS_MDMA1 19 650#define CLK_PCLK_BTS_G2D 20 651#define CLK_PCLK_ALB_G2D 21 652#define CLK_PCLK_ASYNCAXI_SYSX 22 653#define CLK_PCLK_PMU_G2D 23 654#define CLK_PCLK_SYSREG_G2D 24 655#define CLK_PCLK_G2D 25 656#define CLK_PCLK_SMMU_G2D 26 657 658#define G2D_NR_CLK 27 659 660/* CMU_DISP */ 661#define CLK_FOUT_DISP_PLL 1 662 663#define CLK_MOUT_DISP_PLL 2 664#define CLK_MOUT_SCLK_DSIM1_USER 3 665#define CLK_MOUT_SCLK_DSIM0_USER 4 666#define CLK_MOUT_SCLK_DSD_USER 5 667#define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6 668#define CLK_MOUT_SCLK_DECON_VCLK_USER 7 669#define CLK_MOUT_SCLK_DECON_ECLK_USER 8 670#define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9 671#define CLK_MOUT_ACLK_DISP_333_USER 10 672#define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11 673#define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12 674#define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13 675#define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14 676#define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15 677#define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16 678#define CLK_MOUT_SCLK_DSIM0 17 679#define CLK_MOUT_SCLK_DECON_TV_ECLK 18 680#define CLK_MOUT_SCLK_DECON_VCLK 19 681#define CLK_MOUT_SCLK_DECON_ECLK 20 682#define CLK_MOUT_SCLK_DSIM1_B_DISP 21 683#define CLK_MOUT_SCLK_DSIM1_A_DISP 22 684#define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23 685#define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24 686#define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25 687 688#define CLK_DIV_SCLK_DSIM1_DISP 30 689#define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31 690#define CLK_DIV_SCLK_DSIM0_DISP 32 691#define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33 692#define CLK_DIV_SCLK_DECON_VCLK_DISP 34 693#define CLK_DIV_SCLK_DECON_ECLK_DISP 35 694#define CLK_DIV_PCLK_DISP 36 695 696#define CLK_ACLK_DECON_TV 40 697#define CLK_ACLK_DECON 41 698#define CLK_ACLK_SMMU_TV1X 42 699#define CLK_ACLK_SMMU_TV0X 43 700#define CLK_ACLK_SMMU_DECON1X 44 701#define CLK_ACLK_SMMU_DECON0X 45 702#define CLK_ACLK_BTS_DECON_TV_M3 46 703#define CLK_ACLK_BTS_DECON_TV_M2 47 704#define CLK_ACLK_BTS_DECON_TV_M1 48 705#define CLK_ACLK_BTS_DECON_TV_M0 49 706#define CLK_ACLK_BTS_DECON_NM4 50 707#define CLK_ACLK_BTS_DECON_NM3 51 708#define CLK_ACLK_BTS_DECON_NM2 52 709#define CLK_ACLK_BTS_DECON_NM1 53 710#define CLK_ACLK_BTS_DECON_NM0 54 711#define CLK_ACLK_AHB2APB_DISPSFR2P 55 712#define CLK_ACLK_AHB2APB_DISPSFR1P 56 713#define CLK_ACLK_AHB2APB_DISPSFR0P 57 714#define CLK_ACLK_AHB_DISPH 58 715#define CLK_ACLK_XIU_TV1X 59 716#define CLK_ACLK_XIU_TV0X 60 717#define CLK_ACLK_XIU_DECON1X 61 718#define CLK_ACLK_XIU_DECON0X 62 719#define CLK_ACLK_XIU_DISP1X 63 720#define CLK_ACLK_XIU_DISPNP_100 64 721#define CLK_ACLK_DISP1ND_333 65 722#define CLK_ACLK_DISP0ND_333 66 723#define CLK_PCLK_SMMU_TV1X 67 724#define CLK_PCLK_SMMU_TV0X 68 725#define CLK_PCLK_SMMU_DECON1X 69 726#define CLK_PCLK_SMMU_DECON0X 70 727#define CLK_PCLK_BTS_DECON_TV_M3 71 728#define CLK_PCLK_BTS_DECON_TV_M2 72 729#define CLK_PCLK_BTS_DECON_TV_M1 73 730#define CLK_PCLK_BTS_DECON_TV_M0 74 731#define CLK_PCLK_BTS_DECONM4 75 732#define CLK_PCLK_BTS_DECONM3 76 733#define CLK_PCLK_BTS_DECONM2 77 734#define CLK_PCLK_BTS_DECONM1 78 735#define CLK_PCLK_BTS_DECONM0 79 736#define CLK_PCLK_MIC1 80 737#define CLK_PCLK_PMU_DISP 81 738#define CLK_PCLK_SYSREG_DISP 82 739#define CLK_PCLK_HDMIPHY 83 740#define CLK_PCLK_HDMI 84 741#define CLK_PCLK_MIC0 85 742#define CLK_PCLK_DSIM1 86 743#define CLK_PCLK_DSIM0 87 744#define CLK_PCLK_DECON_TV 88 745#define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89 746#define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90 747#define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91 748#define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92 749#define CLK_SCLK_DSIM1 93 750#define CLK_SCLK_DECON_TV_VCLK 94 751#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95 752#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96 753#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97 754#define CLK_PHYCLK_HDMI_PIXEL 98 755#define CLK_SCLK_RGB_VCLK_TO_SMIES 99 756#define CLK_SCLK_FREQ_DET_DISP_PLL 100 757#define CLK_SCLK_RGB_VCLK_TO_DSIM0 101 758#define CLK_SCLK_RGB_VCLK_TO_MIC0 102 759#define CLK_SCLK_DSD 103 760#define CLK_SCLK_HDMI_SPDIF 104 761#define CLK_SCLK_DSIM0 105 762#define CLK_SCLK_DECON_TV_ECLK 106 763#define CLK_SCLK_DECON_VCLK 107 764#define CLK_SCLK_DECON_ECLK 108 765#define CLK_SCLK_RGB_VCLK 109 766#define CLK_SCLK_RGB_TV_VCLK 110 767 768#define CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY 111 769#define CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY 112 770 771#define CLK_PCLK_DECON 113 772 773#define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY 114 774#define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY 115 775 776#define DISP_NR_CLK 116 777 778/* CMU_AUD */ 779#define CLK_MOUT_AUD_PLL_USER 1 780#define CLK_MOUT_SCLK_AUD_PCM 2 781#define CLK_MOUT_SCLK_AUD_I2S 3 782 783#define CLK_DIV_ATCLK_AUD 4 784#define CLK_DIV_PCLK_DBG_AUD 5 785#define CLK_DIV_ACLK_AUD 6 786#define CLK_DIV_AUD_CA5 7 787#define CLK_DIV_SCLK_AUD_SLIMBUS 8 788#define CLK_DIV_SCLK_AUD_UART 9 789#define CLK_DIV_SCLK_AUD_PCM 10 790#define CLK_DIV_SCLK_AUD_I2S 11 791 792#define CLK_ACLK_INTR_CTRL 12 793#define CLK_ACLK_AXIDS2_LPASSP 13 794#define CLK_ACLK_AXIDS1_LPASSP 14 795#define CLK_ACLK_AXI2APB1_LPASSP 15 796#define CLK_ACLK_AXI2APH_LPASSP 16 797#define CLK_ACLK_SMMU_LPASSX 17 798#define CLK_ACLK_AXIDS0_LPASSP 18 799#define CLK_ACLK_AXI2APB0_LPASSP 19 800#define CLK_ACLK_XIU_LPASSX 20 801#define CLK_ACLK_AUDNP_133 21 802#define CLK_ACLK_AUDND_133 22 803#define CLK_ACLK_SRAMC 23 804#define CLK_ACLK_DMAC 24 805#define CLK_PCLK_WDT1 25 806#define CLK_PCLK_WDT0 26 807#define CLK_PCLK_SFR1 27 808#define CLK_PCLK_SMMU_LPASSX 28 809#define CLK_PCLK_GPIO_AUD 29 810#define CLK_PCLK_PMU_AUD 30 811#define CLK_PCLK_SYSREG_AUD 31 812#define CLK_PCLK_AUD_SLIMBUS 32 813#define CLK_PCLK_AUD_UART 33 814#define CLK_PCLK_AUD_PCM 34 815#define CLK_PCLK_AUD_I2S 35 816#define CLK_PCLK_TIMER 36 817#define CLK_PCLK_SFR0_CTRL 37 818#define CLK_ATCLK_AUD 38 819#define CLK_PCLK_DBG_AUD 39 820#define CLK_SCLK_AUD_CA5 40 821#define CLK_SCLK_JTAG_TCK 41 822#define CLK_SCLK_SLIMBUS_CLKIN 42 823#define CLK_SCLK_AUD_SLIMBUS 43 824#define CLK_SCLK_AUD_UART 44 825#define CLK_SCLK_AUD_PCM 45 826#define CLK_SCLK_I2S_BCLK 46 827#define CLK_SCLK_AUD_I2S 47 828 829#define AUD_NR_CLK 48 830 831/* CMU_BUS{0|1|2} */ 832#define CLK_DIV_PCLK_BUS_133 1 833 834#define CLK_ACLK_AHB2APB_BUSP 2 835#define CLK_ACLK_BUSNP_133 3 836#define CLK_ACLK_BUSND_400 4 837#define CLK_PCLK_BUSSRVND_133 5 838#define CLK_PCLK_PMU_BUS 6 839#define CLK_PCLK_SYSREG_BUS 7 840 841#define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */ 842#define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */ 843#define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */ 844 845#define BUSx_NR_CLK 11 846 847/* CMU_G3D */ 848#define CLK_FOUT_G3D_PLL 1 849 850#define CLK_MOUT_ACLK_G3D_400 2 851#define CLK_MOUT_G3D_PLL 3 852 853#define CLK_DIV_SCLK_HPM_G3D 4 854#define CLK_DIV_PCLK_G3D 5 855#define CLK_DIV_ACLK_G3D 6 856#define CLK_ACLK_BTS_G3D1 7 857#define CLK_ACLK_BTS_G3D0 8 858#define CLK_ACLK_ASYNCAPBS_G3D 9 859#define CLK_ACLK_ASYNCAPBM_G3D 10 860#define CLK_ACLK_AHB2APB_G3DP 11 861#define CLK_ACLK_G3DNP_150 12 862#define CLK_ACLK_G3DND_600 13 863#define CLK_ACLK_G3D 14 864#define CLK_PCLK_BTS_G3D1 15 865#define CLK_PCLK_BTS_G3D0 16 866#define CLK_PCLK_PMU_G3D 17 867#define CLK_PCLK_SYSREG_G3D 18 868#define CLK_SCLK_HPM_G3D 19 869 870#define G3D_NR_CLK 20 871 872/* CMU_GSCL */ 873#define CLK_MOUT_ACLK_GSCL_111_USER 1 874#define CLK_MOUT_ACLK_GSCL_333_USER 2 875 876#define CLK_ACLK_BTS_GSCL2 3 877#define CLK_ACLK_BTS_GSCL1 4 878#define CLK_ACLK_BTS_GSCL0 5 879#define CLK_ACLK_AHB2APB_GSCLP 6 880#define CLK_ACLK_XIU_GSCLX 7 881#define CLK_ACLK_GSCLNP_111 8 882#define CLK_ACLK_GSCLRTND_333 9 883#define CLK_ACLK_GSCLBEND_333 10 884#define CLK_ACLK_GSD 11 885#define CLK_ACLK_GSCL2 12 886#define CLK_ACLK_GSCL1 13 887#define CLK_ACLK_GSCL0 14 888#define CLK_ACLK_SMMU_GSCL0 15 889#define CLK_ACLK_SMMU_GSCL1 16 890#define CLK_ACLK_SMMU_GSCL2 17 891#define CLK_PCLK_BTS_GSCL2 18 892#define CLK_PCLK_BTS_GSCL1 19 893#define CLK_PCLK_BTS_GSCL0 20 894#define CLK_PCLK_PMU_GSCL 21 895#define CLK_PCLK_SYSREG_GSCL 22 896#define CLK_PCLK_GSCL2 23 897#define CLK_PCLK_GSCL1 24 898#define CLK_PCLK_GSCL0 25 899#define CLK_PCLK_SMMU_GSCL0 26 900#define CLK_PCLK_SMMU_GSCL1 27 901#define CLK_PCLK_SMMU_GSCL2 28 902 903#define GSCL_NR_CLK 29 904 905/* CMU_APOLLO */ 906#define CLK_FOUT_APOLLO_PLL 1 907 908#define CLK_MOUT_APOLLO_PLL 2 909#define CLK_MOUT_BUS_PLL_APOLLO_USER 3 910#define CLK_MOUT_APOLLO 4 911 912#define CLK_DIV_CNTCLK_APOLLO 5 913#define CLK_DIV_PCLK_DBG_APOLLO 6 914#define CLK_DIV_ATCLK_APOLLO 7 915#define CLK_DIV_PCLK_APOLLO 8 916#define CLK_DIV_ACLK_APOLLO 9 917#define CLK_DIV_APOLLO2 10 918#define CLK_DIV_APOLLO1 11 919#define CLK_DIV_SCLK_HPM_APOLLO 12 920#define CLK_DIV_APOLLO_PLL 13 921 922#define CLK_ACLK_ATBDS_APOLLO_3 14 923#define CLK_ACLK_ATBDS_APOLLO_2 15 924#define CLK_ACLK_ATBDS_APOLLO_1 16 925#define CLK_ACLK_ATBDS_APOLLO_0 17 926#define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18 927#define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19 928#define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20 929#define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21 930#define CLK_ACLK_ASYNCACES_APOLLO_CCI 22 931#define CLK_ACLK_AHB2APB_APOLLOP 23 932#define CLK_ACLK_APOLLONP_200 24 933#define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25 934#define CLK_PCLK_PMU_APOLLO 26 935#define CLK_PCLK_SYSREG_APOLLO 27 936#define CLK_CNTCLK_APOLLO 28 937#define CLK_SCLK_HPM_APOLLO 29 938#define CLK_SCLK_APOLLO 30 939 940#define APOLLO_NR_CLK 31 941 942/* CMU_ATLAS */ 943#define CLK_FOUT_ATLAS_PLL 1 944 945#define CLK_MOUT_ATLAS_PLL 2 946#define CLK_MOUT_BUS_PLL_ATLAS_USER 3 947#define CLK_MOUT_ATLAS 4 948 949#define CLK_DIV_CNTCLK_ATLAS 5 950#define CLK_DIV_PCLK_DBG_ATLAS 6 951#define CLK_DIV_ATCLK_ATLASO 7 952#define CLK_DIV_PCLK_ATLAS 8 953#define CLK_DIV_ACLK_ATLAS 9 954#define CLK_DIV_ATLAS2 10 955#define CLK_DIV_ATLAS1 11 956#define CLK_DIV_SCLK_HPM_ATLAS 12 957#define CLK_DIV_ATLAS_PLL 13 958 959#define CLK_ACLK_ATB_AUD_CSSYS 14 960#define CLK_ACLK_ATB_APOLLO3_CSSYS 15 961#define CLK_ACLK_ATB_APOLLO2_CSSYS 16 962#define CLK_ACLK_ATB_APOLLO1_CSSYS 17 963#define CLK_ACLK_ATB_APOLLO0_CSSYS 18 964#define CLK_ACLK_ASYNCAHBS_CSSYS_SSS 19 965#define CLK_ACLK_ASYNCAXIS_CSSYS_CCIX 20 966#define CLK_ACLK_ASYNCACES_ATLAS_CCI 21 967#define CLK_ACLK_AHB2APB_ATLASP 22 968#define CLK_ACLK_ATLASNP_200 23 969#define CLK_PCLK_ASYNCAPB_AUD_CSSYS 24 970#define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25 971#define CLK_PCLK_ASYNCAPB_APOLLO_CSSYS 26 972#define CLK_PCLK_PMU_ATLAS 27 973#define CLK_PCLK_SYSREG_ATLAS 28 974#define CLK_PCLK_SECJTAG 29 975#define CLK_CNTCLK_ATLAS 30 976#define CLK_SCLK_FREQ_DET_ATLAS_PLL 31 977#define CLK_SCLK_HPM_ATLAS 32 978#define CLK_TRACECLK 33 979#define CLK_CTMCLK 34 980#define CLK_HCLK_CSSYS 35 981#define CLK_PCLK_DBG_CSSYS 36 982#define CLK_PCLK_DBG 37 983#define CLK_ATCLK 38 984#define CLK_SCLK_ATLAS 39 985 986#define ATLAS_NR_CLK 40 987 988/* CMU_MSCL */ 989#define CLK_MOUT_SCLK_JPEG_USER 1 990#define CLK_MOUT_ACLK_MSCL_400_USER 2 991#define CLK_MOUT_SCLK_JPEG 3 992 993#define CLK_DIV_PCLK_MSCL 4 994 995#define CLK_ACLK_BTS_JPEG 5 996#define CLK_ACLK_BTS_M2MSCALER1 6 997#define CLK_ACLK_BTS_M2MSCALER0 7 998#define CLK_ACLK_AHB2APB_MSCL0P 8 999#define CLK_ACLK_XIU_MSCLX 9 1000#define CLK_ACLK_MSCLNP_100 10 1001#define CLK_ACLK_MSCLND_400 11 1002#define CLK_ACLK_JPEG 12 1003#define CLK_ACLK_M2MSCALER1 13 1004#define CLK_ACLK_M2MSCALER0 14 1005#define CLK_ACLK_SMMU_M2MSCALER0 15 1006#define CLK_ACLK_SMMU_M2MSCALER1 16 1007#define CLK_ACLK_SMMU_JPEG 17 1008#define CLK_PCLK_BTS_JPEG 18 1009#define CLK_PCLK_BTS_M2MSCALER1 19 1010#define CLK_PCLK_BTS_M2MSCALER0 20 1011#define CLK_PCLK_PMU_MSCL 21 1012#define CLK_PCLK_SYSREG_MSCL 22 1013#define CLK_PCLK_JPEG 23 1014#define CLK_PCLK_M2MSCALER1 24 1015#define CLK_PCLK_M2MSCALER0 25 1016#define CLK_PCLK_SMMU_M2MSCALER0 26 1017#define CLK_PCLK_SMMU_M2MSCALER1 27 1018#define CLK_PCLK_SMMU_JPEG 28 1019#define CLK_SCLK_JPEG 29 1020 1021#define MSCL_NR_CLK 30 1022 1023/* CMU_MFC */ 1024#define CLK_MOUT_ACLK_MFC_400_USER 1 1025 1026#define CLK_DIV_PCLK_MFC 2 1027 1028#define CLK_ACLK_BTS_MFC_1 3 1029#define CLK_ACLK_BTS_MFC_0 4 1030#define CLK_ACLK_AHB2APB_MFCP 5 1031#define CLK_ACLK_XIU_MFCX 6 1032#define CLK_ACLK_MFCNP_100 7 1033#define CLK_ACLK_MFCND_400 8 1034#define CLK_ACLK_MFC 9 1035#define CLK_ACLK_SMMU_MFC_1 10 1036#define CLK_ACLK_SMMU_MFC_0 11 1037#define CLK_PCLK_BTS_MFC_1 12 1038#define CLK_PCLK_BTS_MFC_0 13 1039#define CLK_PCLK_PMU_MFC 14 1040#define CLK_PCLK_SYSREG_MFC 15 1041#define CLK_PCLK_MFC 16 1042#define CLK_PCLK_SMMU_MFC_1 17 1043#define CLK_PCLK_SMMU_MFC_0 18 1044 1045#define MFC_NR_CLK 19 1046 1047/* CMU_HEVC */ 1048#define CLK_MOUT_ACLK_HEVC_400_USER 1 1049 1050#define CLK_DIV_PCLK_HEVC 2 1051 1052#define CLK_ACLK_BTS_HEVC_1 3 1053#define CLK_ACLK_BTS_HEVC_0 4 1054#define CLK_ACLK_AHB2APB_HEVCP 5 1055#define CLK_ACLK_XIU_HEVCX 6 1056#define CLK_ACLK_HEVCNP_100 7 1057#define CLK_ACLK_HEVCND_400 8 1058#define CLK_ACLK_HEVC 9 1059#define CLK_ACLK_SMMU_HEVC_1 10 1060#define CLK_ACLK_SMMU_HEVC_0 11 1061#define CLK_PCLK_BTS_HEVC_1 12 1062#define CLK_PCLK_BTS_HEVC_0 13 1063#define CLK_PCLK_PMU_HEVC 14 1064#define CLK_PCLK_SYSREG_HEVC 15 1065#define CLK_PCLK_HEVC 16 1066#define CLK_PCLK_SMMU_HEVC_1 17 1067#define CLK_PCLK_SMMU_HEVC_0 18 1068 1069#define HEVC_NR_CLK 19 1070 1071/* CMU_ISP */ 1072#define CLK_MOUT_ACLK_ISP_DIS_400_USER 1 1073#define CLK_MOUT_ACLK_ISP_400_USER 2 1074 1075#define CLK_DIV_PCLK_ISP_DIS 3 1076#define CLK_DIV_PCLK_ISP 4 1077#define CLK_DIV_ACLK_ISP_D_200 5 1078#define CLK_DIV_ACLK_ISP_C_200 6 1079 1080#define CLK_ACLK_ISP_D_GLUE 7 1081#define CLK_ACLK_SCALERP 8 1082#define CLK_ACLK_3DNR 9 1083#define CLK_ACLK_DIS 10 1084#define CLK_ACLK_SCALERC 11 1085#define CLK_ACLK_DRC 12 1086#define CLK_ACLK_ISP 13 1087#define CLK_ACLK_AXIUS_SCALERP 14 1088#define CLK_ACLK_AXIUS_SCALERC 15 1089#define CLK_ACLK_AXIUS_DRC 16 1090#define CLK_ACLK_ASYNCAHBM_ISP2P 17 1091#define CLK_ACLK_ASYNCAHBM_ISP1P 18 1092#define CLK_ACLK_ASYNCAXIS_DIS1 19 1093#define CLK_ACLK_ASYNCAXIS_DIS0 20 1094#define CLK_ACLK_ASYNCAXIM_DIS1 21 1095#define CLK_ACLK_ASYNCAXIM_DIS0 22 1096#define CLK_ACLK_ASYNCAXIM_ISP2P 23 1097#define CLK_ACLK_ASYNCAXIM_ISP1P 24 1098#define CLK_ACLK_AHB2APB_ISP2P 25 1099#define CLK_ACLK_AHB2APB_ISP1P 26 1100#define CLK_ACLK_AXI2APB_ISP2P 27 1101#define CLK_ACLK_AXI2APB_ISP1P 28 1102#define CLK_ACLK_XIU_ISPEX1 29 1103#define CLK_ACLK_XIU_ISPEX0 30 1104#define CLK_ACLK_ISPND_400 31 1105#define CLK_ACLK_SMMU_SCALERP 32 1106#define CLK_ACLK_SMMU_3DNR 33 1107#define CLK_ACLK_SMMU_DIS1 34 1108#define CLK_ACLK_SMMU_DIS0 35 1109#define CLK_ACLK_SMMU_SCALERC 36 1110#define CLK_ACLK_SMMU_DRC 37 1111#define CLK_ACLK_SMMU_ISP 38 1112#define CLK_ACLK_BTS_SCALERP 39 1113#define CLK_ACLK_BTS_3DR 40 1114#define CLK_ACLK_BTS_DIS1 41 1115#define CLK_ACLK_BTS_DIS0 42 1116#define CLK_ACLK_BTS_SCALERC 43 1117#define CLK_ACLK_BTS_DRC 44 1118#define CLK_ACLK_BTS_ISP 45 1119#define CLK_PCLK_SMMU_SCALERP 46 1120#define CLK_PCLK_SMMU_3DNR 47 1121#define CLK_PCLK_SMMU_DIS1 48 1122#define CLK_PCLK_SMMU_DIS0 49 1123#define CLK_PCLK_SMMU_SCALERC 50 1124#define CLK_PCLK_SMMU_DRC 51 1125#define CLK_PCLK_SMMU_ISP 52 1126#define CLK_PCLK_BTS_SCALERP 53 1127#define CLK_PCLK_BTS_3DNR 54 1128#define CLK_PCLK_BTS_DIS1 55 1129#define CLK_PCLK_BTS_DIS0 56 1130#define CLK_PCLK_BTS_SCALERC 57 1131#define CLK_PCLK_BTS_DRC 58 1132#define CLK_PCLK_BTS_ISP 59 1133#define CLK_PCLK_ASYNCAXI_DIS1 60 1134#define CLK_PCLK_ASYNCAXI_DIS0 61 1135#define CLK_PCLK_PMU_ISP 62 1136#define CLK_PCLK_SYSREG_ISP 63 1137#define CLK_PCLK_CMU_ISP_LOCAL 64 1138#define CLK_PCLK_SCALERP 65 1139#define CLK_PCLK_3DNR 66 1140#define CLK_PCLK_DIS_CORE 67 1141#define CLK_PCLK_DIS 68 1142#define CLK_PCLK_SCALERC 69 1143#define CLK_PCLK_DRC 70 1144#define CLK_PCLK_ISP 71 1145#define CLK_SCLK_PIXELASYNCS_DIS 72 1146#define CLK_SCLK_PIXELASYNCM_DIS 73 1147#define CLK_SCLK_PIXELASYNCS_SCALERP 74 1148#define CLK_SCLK_PIXELASYNCM_ISPD 75 1149#define CLK_SCLK_PIXELASYNCS_ISPC 76 1150#define CLK_SCLK_PIXELASYNCM_ISPC 77 1151 1152#define ISP_NR_CLK 78 1153 1154/* CMU_CAM0 */ 1155#define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY 1 1156#define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY 2 1157 1158#define CLK_MOUT_ACLK_CAM0_333_USER 3 1159#define CLK_MOUT_ACLK_CAM0_400_USER 4 1160#define CLK_MOUT_ACLK_CAM0_552_USER 5 1161#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER 6 1162#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER 7 1163#define CLK_MOUT_ACLK_LITE_D_B 8 1164#define CLK_MOUT_ACLK_LITE_D_A 9 1165#define CLK_MOUT_ACLK_LITE_B_B 10 1166#define CLK_MOUT_ACLK_LITE_B_A 11 1167#define CLK_MOUT_ACLK_LITE_A_B 12 1168#define CLK_MOUT_ACLK_LITE_A_A 13 1169#define CLK_MOUT_ACLK_CAM0_400 14 1170#define CLK_MOUT_ACLK_CSIS1_B 15 1171#define CLK_MOUT_ACLK_CSIS1_A 16 1172#define CLK_MOUT_ACLK_CSIS0_B 17 1173#define CLK_MOUT_ACLK_CSIS0_A 18 1174#define CLK_MOUT_ACLK_3AA1_B 19 1175#define CLK_MOUT_ACLK_3AA1_A 20 1176#define CLK_MOUT_ACLK_3AA0_B 21 1177#define CLK_MOUT_ACLK_3AA0_A 22 1178#define CLK_MOUT_SCLK_LITE_FREECNT_C 23 1179#define CLK_MOUT_SCLK_LITE_FREECNT_B 24 1180#define CLK_MOUT_SCLK_LITE_FREECNT_A 25 1181#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B 26 1182#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A 27 1183#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B 28 1184#define CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A 29 1185 1186#define CLK_DIV_PCLK_CAM0_50 30 1187#define CLK_DIV_ACLK_CAM0_200 31 1188#define CLK_DIV_ACLK_CAM0_BUS_400 32 1189#define CLK_DIV_PCLK_LITE_D 33 1190#define CLK_DIV_ACLK_LITE_D 34 1191#define CLK_DIV_PCLK_LITE_B 35 1192#define CLK_DIV_ACLK_LITE_B 36 1193#define CLK_DIV_PCLK_LITE_A 37 1194#define CLK_DIV_ACLK_LITE_A 38 1195#define CLK_DIV_ACLK_CSIS1 39 1196#define CLK_DIV_ACLK_CSIS0 40 1197#define CLK_DIV_PCLK_3AA1 41 1198#define CLK_DIV_ACLK_3AA1 42 1199#define CLK_DIV_PCLK_3AA0 43 1200#define CLK_DIV_ACLK_3AA0 44 1201#define CLK_DIV_SCLK_PIXELASYNC_LITE_C 45 1202#define CLK_DIV_PCLK_PIXELASYNC_LITE_C 46 1203#define CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT 47 1204 1205#define CLK_ACLK_CSIS1 50 1206#define CLK_ACLK_CSIS0 51 1207#define CLK_ACLK_3AA1 52 1208#define CLK_ACLK_3AA0 53 1209#define CLK_ACLK_LITE_D 54 1210#define CLK_ACLK_LITE_B 55 1211#define CLK_ACLK_LITE_A 56 1212#define CLK_ACLK_AHBSYNCDN 57 1213#define CLK_ACLK_AXIUS_LITE_D 58 1214#define CLK_ACLK_AXIUS_LITE_B 59 1215#define CLK_ACLK_AXIUS_LITE_A 60 1216#define CLK_ACLK_ASYNCAPBM_3AA1 61 1217#define CLK_ACLK_ASYNCAPBS_3AA1 62 1218#define CLK_ACLK_ASYNCAPBM_3AA0 63 1219#define CLK_ACLK_ASYNCAPBS_3AA0 64 1220#define CLK_ACLK_ASYNCAPBM_LITE_D 65 1221#define CLK_ACLK_ASYNCAPBS_LITE_D 66 1222#define CLK_ACLK_ASYNCAPBM_LITE_B 67 1223#define CLK_ACLK_ASYNCAPBS_LITE_B 68 1224#define CLK_ACLK_ASYNCAPBM_LITE_A 69 1225#define CLK_ACLK_ASYNCAPBS_LITE_A 70 1226#define CLK_ACLK_ASYNCAXIM_ISP0P 71 1227#define CLK_ACLK_ASYNCAXIM_3AA1 72 1228#define CLK_ACLK_ASYNCAXIS_3AA1 73 1229#define CLK_ACLK_ASYNCAXIM_3AA0 74 1230#define CLK_ACLK_ASYNCAXIS_3AA0 75 1231#define CLK_ACLK_ASYNCAXIM_LITE_D 76 1232#define CLK_ACLK_ASYNCAXIS_LITE_D 77 1233#define CLK_ACLK_ASYNCAXIM_LITE_B 78 1234#define CLK_ACLK_ASYNCAXIS_LITE_B 79 1235#define CLK_ACLK_ASYNCAXIM_LITE_A 80 1236#define CLK_ACLK_ASYNCAXIS_LITE_A 81 1237#define CLK_ACLK_AHB2APB_ISPSFRP 82 1238#define CLK_ACLK_AXI2APB_ISP0P 83 1239#define CLK_ACLK_AXI2AHB_ISP0P 84 1240#define CLK_ACLK_XIU_IS0X 85 1241#define CLK_ACLK_XIU_ISP0EX 86 1242#define CLK_ACLK_CAM0NP_276 87 1243#define CLK_ACLK_CAM0ND_400 88 1244#define CLK_ACLK_SMMU_3AA1 89 1245#define CLK_ACLK_SMMU_3AA0 90 1246#define CLK_ACLK_SMMU_LITE_D 91 1247#define CLK_ACLK_SMMU_LITE_B 92 1248#define CLK_ACLK_SMMU_LITE_A 93 1249#define CLK_ACLK_BTS_3AA1 94 1250#define CLK_ACLK_BTS_3AA0 95 1251#define CLK_ACLK_BTS_LITE_D 96 1252#define CLK_ACLK_BTS_LITE_B 97 1253#define CLK_ACLK_BTS_LITE_A 98 1254#define CLK_PCLK_SMMU_3AA1 99 1255#define CLK_PCLK_SMMU_3AA0 100 1256#define CLK_PCLK_SMMU_LITE_D 101 1257#define CLK_PCLK_SMMU_LITE_B 102 1258#define CLK_PCLK_SMMU_LITE_A 103 1259#define CLK_PCLK_BTS_3AA1 104 1260#define CLK_PCLK_BTS_3AA0 105 1261#define CLK_PCLK_BTS_LITE_D 106 1262#define CLK_PCLK_BTS_LITE_B 107 1263#define CLK_PCLK_BTS_LITE_A 108 1264#define CLK_PCLK_ASYNCAXI_CAM1 109 1265#define CLK_PCLK_ASYNCAXI_3AA1 110 1266#define CLK_PCLK_ASYNCAXI_3AA0 111 1267#define CLK_PCLK_ASYNCAXI_LITE_D 112 1268#define CLK_PCLK_ASYNCAXI_LITE_B 113 1269#define CLK_PCLK_ASYNCAXI_LITE_A 114 1270#define CLK_PCLK_PMU_CAM0 115 1271#define CLK_PCLK_SYSREG_CAM0 116 1272#define CLK_PCLK_CMU_CAM0_LOCAL 117 1273#define CLK_PCLK_CSIS1 118 1274#define CLK_PCLK_CSIS0 119 1275#define CLK_PCLK_3AA1 120 1276#define CLK_PCLK_3AA0 121 1277#define CLK_PCLK_LITE_D 122 1278#define CLK_PCLK_LITE_B 123 1279#define CLK_PCLK_LITE_A 124 1280#define CLK_PHYCLK_RXBYTECLKHS0_S4 125 1281#define CLK_PHYCLK_RXBYTECLKHS0_S2A 126 1282#define CLK_SCLK_LITE_FREECNT 127 1283#define CLK_SCLK_PIXELASYNCM_3AA1 128 1284#define CLK_SCLK_PIXELASYNCM_3AA0 129 1285#define CLK_SCLK_PIXELASYNCS_3AA0 130 1286#define CLK_SCLK_PIXELASYNCM_LITE_C 131 1287#define CLK_SCLK_PIXELASYNCM_LITE_C_INIT 132 1288#define CLK_SCLK_PIXELASYNCS_LITE_C_INIT 133 1289 1290#define CAM0_NR_CLK 134 1291 1292/* CMU_CAM1 */ 1293#define CLK_PHYCLK_RXBYTEECLKHS0_S2B 1 1294 1295#define CLK_MOUT_SCLK_ISP_UART_USER 2 1296#define CLK_MOUT_SCLK_ISP_SPI1_USER 3 1297#define CLK_MOUT_SCLK_ISP_SPI0_USER 4 1298#define CLK_MOUT_ACLK_CAM1_333_USER 5 1299#define CLK_MOUT_ACLK_CAM1_400_USER 6 1300#define CLK_MOUT_ACLK_CAM1_552_USER 7 1301#define CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER 8 1302#define CLK_MOUT_ACLK_CSIS2_B 9 1303#define CLK_MOUT_ACLK_CSIS2_A 10 1304#define CLK_MOUT_ACLK_FD_B 11 1305#define CLK_MOUT_ACLK_FD_A 12 1306#define CLK_MOUT_ACLK_LITE_C_B 13 1307#define CLK_MOUT_ACLK_LITE_C_A 14 1308 1309#define CLK_DIV_SCLK_ISP_MPWM 15 1310#define CLK_DIV_PCLK_CAM1_83 16 1311#define CLK_DIV_PCLK_CAM1_166 17 1312#define CLK_DIV_PCLK_DBG_CAM1 18 1313#define CLK_DIV_ATCLK_CAM1 19 1314#define CLK_DIV_ACLK_CSIS2 20 1315#define CLK_DIV_PCLK_FD 21 1316#define CLK_DIV_ACLK_FD 22 1317#define CLK_DIV_PCLK_LITE_C 23 1318#define CLK_DIV_ACLK_LITE_C 24 1319 1320#define CLK_ACLK_ISP_GIC 25 1321#define CLK_ACLK_FD 26 1322#define CLK_ACLK_LITE_C 27 1323#define CLK_ACLK_CSIS2 28 1324#define CLK_ACLK_ASYNCAPBM_FD 29 1325#define CLK_ACLK_ASYNCAPBS_FD 30 1326#define CLK_ACLK_ASYNCAPBM_LITE_C 31 1327#define CLK_ACLK_ASYNCAPBS_LITE_C 32 1328#define CLK_ACLK_ASYNCAHBS_SFRISP2H2 33 1329#define CLK_ACLK_ASYNCAHBS_SFRISP2H1 34 1330#define CLK_ACLK_ASYNCAXIM_CA5 35 1331#define CLK_ACLK_ASYNCAXIS_CA5 36 1332#define CLK_ACLK_ASYNCAXIS_ISPX2 37 1333#define CLK_ACLK_ASYNCAXIS_ISPX1 38 1334#define CLK_ACLK_ASYNCAXIS_ISPX0 39 1335#define CLK_ACLK_ASYNCAXIM_ISPEX 40 1336#define CLK_ACLK_ASYNCAXIM_ISP3P 41 1337#define CLK_ACLK_ASYNCAXIS_ISP3P 42 1338#define CLK_ACLK_ASYNCAXIM_FD 43 1339#define CLK_ACLK_ASYNCAXIS_FD 44 1340#define CLK_ACLK_ASYNCAXIM_LITE_C 45 1341#define CLK_ACLK_ASYNCAXIS_LITE_C 46 1342#define CLK_ACLK_AHB2APB_ISP5P 47 1343#define CLK_ACLK_AHB2APB_ISP3P 48 1344#define CLK_ACLK_AXI2APB_ISP3P 49 1345#define CLK_ACLK_AHB_SFRISP2H 50 1346#define CLK_ACLK_AXI_ISP_HX_R 51 1347#define CLK_ACLK_AXI_ISP_CX_R 52 1348#define CLK_ACLK_AXI_ISP_HX 53 1349#define CLK_ACLK_AXI_ISP_CX 54 1350#define CLK_ACLK_XIU_ISPX 55 1351#define CLK_ACLK_XIU_ISPEX 56 1352#define CLK_ACLK_CAM1NP_333 57 1353#define CLK_ACLK_CAM1ND_400 58 1354#define CLK_ACLK_SMMU_ISPCPU 59 1355#define CLK_ACLK_SMMU_FD 60 1356#define CLK_ACLK_SMMU_LITE_C 61 1357#define CLK_ACLK_BTS_ISP3P 62 1358#define CLK_ACLK_BTS_FD 63 1359#define CLK_ACLK_BTS_LITE_C 64 1360#define CLK_ACLK_AHBDN_SFRISP2H 65 1361#define CLK_ACLK_AHBDN_ISP5P 66 1362#define CLK_ACLK_AXIUS_ISP3P 67 1363#define CLK_ACLK_AXIUS_FD 68 1364#define CLK_ACLK_AXIUS_LITE_C 69 1365#define CLK_PCLK_SMMU_ISPCPU 70 1366#define CLK_PCLK_SMMU_FD 71 1367#define CLK_PCLK_SMMU_LITE_C 72 1368#define CLK_PCLK_BTS_ISP3P 73 1369#define CLK_PCLK_BTS_FD 74 1370#define CLK_PCLK_BTS_LITE_C 75 1371#define CLK_PCLK_ASYNCAXIM_CA5 76 1372#define CLK_PCLK_ASYNCAXIM_ISPEX 77 1373#define CLK_PCLK_ASYNCAXIM_ISP3P 78 1374#define CLK_PCLK_ASYNCAXIM_FD 79 1375#define CLK_PCLK_ASYNCAXIM_LITE_C 80 1376#define CLK_PCLK_PMU_CAM1 81 1377#define CLK_PCLK_SYSREG_CAM1 82 1378#define CLK_PCLK_CMU_CAM1_LOCAL 83 1379#define CLK_PCLK_ISP_MCTADC 84 1380#define CLK_PCLK_ISP_WDT 85 1381#define CLK_PCLK_ISP_PWM 86 1382#define CLK_PCLK_ISP_UART 87 1383#define CLK_PCLK_ISP_MCUCTL 88 1384#define CLK_PCLK_ISP_SPI1 89 1385#define CLK_PCLK_ISP_SPI0 90 1386#define CLK_PCLK_ISP_I2C2 91 1387#define CLK_PCLK_ISP_I2C1 92 1388#define CLK_PCLK_ISP_I2C0 93 1389#define CLK_PCLK_ISP_MPWM 94 1390#define CLK_PCLK_FD 95 1391#define CLK_PCLK_LITE_C 96 1392#define CLK_PCLK_CSIS2 97 1393#define CLK_SCLK_ISP_I2C2 98 1394#define CLK_SCLK_ISP_I2C1 99 1395#define CLK_SCLK_ISP_I2C0 100 1396#define CLK_SCLK_ISP_PWM 101 1397#define CLK_PHYCLK_RXBYTECLKHS0_S2B 102 1398#define CLK_SCLK_LITE_C_FREECNT 103 1399#define CLK_SCLK_PIXELASYNCM_FD 104 1400#define CLK_SCLK_ISP_MCTADC 105 1401#define CLK_SCLK_ISP_UART 106 1402#define CLK_SCLK_ISP_SPI1 107 1403#define CLK_SCLK_ISP_SPI0 108 1404#define CLK_SCLK_ISP_MPWM 109 1405#define CLK_PCLK_DBG_ISP 110 1406#define CLK_ATCLK_ISP 111 1407#define CLK_SCLK_ISP_CA5 112 1408 1409#define CAM1_NR_CLK 113 1410 1411/* CMU_IMEM */ 1412#define CLK_ACLK_SLIMSSS 2 1413#define CLK_PCLK_SLIMSSS 35 1414 1415#define IMEM_NR_CLK 36 1416 1417#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ 1418