1/*	$NetBSD: bcm-nsp.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/
2
3/*
4 *  BSD LICENSE
5 *
6 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
7 *
8 *  Redistribution and use in source and binary forms, with or without
9 *  modification, are permitted provided that the following conditions
10 *  are met:
11 *
12 *	* Redistributions of source code must retain the above copyright
13 *	  notice, this list of conditions and the following disclaimer.
14 *	* Redistributions in binary form must reproduce the above copyright
15 *	  notice, this list of conditions and the following disclaimer in
16 *	  the documentation and/or other materials provided with the
17 *	  distribution.
18 *	* Neither the name of Broadcom Corporation nor the names of its
19 *	  contributors may be used to endorse or promote products derived
20 *	  from this software without specific prior written permission.
21 *
22 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
25 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
26 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
28 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
32 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#ifndef _CLOCK_BCM_NSP_H
36#define _CLOCK_BCM_NSP_H
37
38/* GENPLL clock channel ID */
39#define BCM_NSP_GENPLL			0
40#define BCM_NSP_GENPLL_PHY_CLK		1
41#define BCM_NSP_GENPLL_ENET_SW_CLK	2
42#define BCM_NSP_GENPLL_USB_PHY_REF_CLK	3
43#define BCM_NSP_GENPLL_IPROCFAST_CLK	4
44#define BCM_NSP_GENPLL_SATA1_CLK	5
45#define BCM_NSP_GENPLL_SATA2_CLK	6
46
47/* LCPLL0 clock channel ID */
48#define BCM_NSP_LCPLL0			0
49#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK	1
50#define BCM_NSP_LCPLL0_SDIO_CLK		2
51#define BCM_NSP_LCPLL0_DDR_PHY_CLK	3
52
53#endif /* _CLOCK_BCM_NSP_H */
54