radeon_ttm.c revision 1.6
1/* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26/* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32#include <ttm/ttm_bo_api.h> 33#include <ttm/ttm_bo_driver.h> 34#include <ttm/ttm_placement.h> 35#include <ttm/ttm_module.h> 36#include <ttm/ttm_page_alloc.h> 37#include <drm/drmP.h> 38#include <drm/radeon_drm.h> 39#include <linux/seq_file.h> 40#include <linux/slab.h> 41#include <linux/swiotlb.h> 42#include <linux/debugfs.h> 43#include "radeon_reg.h" 44#include "radeon.h" 45 46#ifdef __NetBSD__ 47#include <uvm/uvm_extern.h> 48#include <uvm/uvm_fault.h> 49#include <uvm/uvm_param.h> 50#include <drm/bus_dma_hacks.h> 51#endif 52 53#ifdef _LP64 54#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) 55#else 56#define DRM_FILE_PAGE_OFFSET (0xa0000000UL >> PAGE_SHIFT) 57#endif 58 59static int radeon_ttm_debugfs_init(struct radeon_device *rdev); 60static void radeon_ttm_debugfs_fini(struct radeon_device *rdev); 61 62static struct radeon_device *radeon_get_rdev(struct ttm_bo_device *bdev) 63{ 64 struct radeon_mman *mman; 65 struct radeon_device *rdev; 66 67 mman = container_of(bdev, struct radeon_mman, bdev); 68 rdev = container_of(mman, struct radeon_device, mman); 69 return rdev; 70} 71 72 73/* 74 * Global memory. 75 */ 76static int radeon_ttm_mem_global_init(struct drm_global_reference *ref) 77{ 78 return ttm_mem_global_init(ref->object); 79} 80 81static void radeon_ttm_mem_global_release(struct drm_global_reference *ref) 82{ 83 ttm_mem_global_release(ref->object); 84} 85 86static int radeon_ttm_global_init(struct radeon_device *rdev) 87{ 88 struct drm_global_reference *global_ref; 89 int r; 90 91 rdev->mman.mem_global_referenced = false; 92 global_ref = &rdev->mman.mem_global_ref; 93 global_ref->global_type = DRM_GLOBAL_TTM_MEM; 94 global_ref->size = sizeof(struct ttm_mem_global); 95 global_ref->init = &radeon_ttm_mem_global_init; 96 global_ref->release = &radeon_ttm_mem_global_release; 97 r = drm_global_item_ref(global_ref); 98 if (r != 0) { 99 DRM_ERROR("Failed setting up TTM memory accounting " 100 "subsystem.\n"); 101 return r; 102 } 103 104 rdev->mman.bo_global_ref.mem_glob = 105 rdev->mman.mem_global_ref.object; 106 global_ref = &rdev->mman.bo_global_ref.ref; 107 global_ref->global_type = DRM_GLOBAL_TTM_BO; 108 global_ref->size = sizeof(struct ttm_bo_global); 109 global_ref->init = &ttm_bo_global_init; 110 global_ref->release = &ttm_bo_global_release; 111 r = drm_global_item_ref(global_ref); 112 if (r != 0) { 113 DRM_ERROR("Failed setting up TTM BO subsystem.\n"); 114 drm_global_item_unref(&rdev->mman.mem_global_ref); 115 return r; 116 } 117 118 rdev->mman.mem_global_referenced = true; 119 return 0; 120} 121 122static void radeon_ttm_global_fini(struct radeon_device *rdev) 123{ 124 if (rdev->mman.mem_global_referenced) { 125 drm_global_item_unref(&rdev->mman.bo_global_ref.ref); 126 drm_global_item_unref(&rdev->mman.mem_global_ref); 127 rdev->mman.mem_global_referenced = false; 128 } 129} 130 131static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) 132{ 133 return 0; 134} 135 136static int radeon_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, 137 struct ttm_mem_type_manager *man) 138{ 139 struct radeon_device *rdev; 140 141 rdev = radeon_get_rdev(bdev); 142 143 switch (type) { 144 case TTM_PL_SYSTEM: 145 /* System memory */ 146 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 147 man->available_caching = TTM_PL_MASK_CACHING; 148 man->default_caching = TTM_PL_FLAG_CACHED; 149 break; 150 case TTM_PL_TT: 151 man->func = &ttm_bo_manager_func; 152 man->gpu_offset = rdev->mc.gtt_start; 153 man->available_caching = TTM_PL_MASK_CACHING; 154 man->default_caching = TTM_PL_FLAG_CACHED; 155 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA; 156#if __OS_HAS_AGP 157 if (rdev->flags & RADEON_IS_AGP) { 158 if (!rdev->ddev->agp) { 159 DRM_ERROR("AGP is not enabled for memory type %u\n", 160 (unsigned)type); 161 return -EINVAL; 162 } 163 if (!rdev->ddev->agp->cant_use_aperture) 164 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; 165 man->available_caching = TTM_PL_FLAG_UNCACHED | 166 TTM_PL_FLAG_WC; 167 man->default_caching = TTM_PL_FLAG_WC; 168 } 169#endif 170 break; 171 case TTM_PL_VRAM: 172 /* "On-card" video ram */ 173 man->func = &ttm_bo_manager_func; 174 man->gpu_offset = rdev->mc.vram_start; 175 man->flags = TTM_MEMTYPE_FLAG_FIXED | 176 TTM_MEMTYPE_FLAG_MAPPABLE; 177 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC; 178 man->default_caching = TTM_PL_FLAG_WC; 179 break; 180 default: 181 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type); 182 return -EINVAL; 183 } 184 return 0; 185} 186 187static void radeon_evict_flags(struct ttm_buffer_object *bo, 188 struct ttm_placement *placement) 189{ 190 struct radeon_bo *rbo; 191 static u32 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM; 192 193 if (!radeon_ttm_bo_is_radeon_bo(bo)) { 194 placement->fpfn = 0; 195 placement->lpfn = 0; 196 placement->placement = &placements; 197 placement->busy_placement = &placements; 198 placement->num_placement = 1; 199 placement->num_busy_placement = 1; 200 return; 201 } 202 rbo = container_of(bo, struct radeon_bo, tbo); 203 switch (bo->mem.mem_type) { 204 case TTM_PL_VRAM: 205 if (rbo->rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready == false) 206 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 207 else 208 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 209 break; 210 case TTM_PL_TT: 211 default: 212 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); 213 } 214 *placement = rbo->placement; 215} 216 217static int radeon_verify_access(struct ttm_buffer_object *bo, struct file *filp) 218{ 219 struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); 220 221 return drm_vma_node_verify_access(&rbo->gem_base.vma_node, filp); 222} 223 224static void radeon_move_null(struct ttm_buffer_object *bo, 225 struct ttm_mem_reg *new_mem) 226{ 227 struct ttm_mem_reg *old_mem = &bo->mem; 228 229 BUG_ON(old_mem->mm_node != NULL); 230 *old_mem = *new_mem; 231 new_mem->mm_node = NULL; 232} 233 234static int radeon_move_blit(struct ttm_buffer_object *bo, 235 bool evict, bool no_wait_gpu, 236 struct ttm_mem_reg *new_mem, 237 struct ttm_mem_reg *old_mem) 238{ 239 struct radeon_device *rdev; 240 uint64_t old_start, new_start; 241 struct radeon_fence *fence; 242 int r, ridx; 243 244 rdev = radeon_get_rdev(bo->bdev); 245 ridx = radeon_copy_ring_index(rdev); 246 old_start = old_mem->start << PAGE_SHIFT; 247 new_start = new_mem->start << PAGE_SHIFT; 248 249 switch (old_mem->mem_type) { 250 case TTM_PL_VRAM: 251 old_start += rdev->mc.vram_start; 252 break; 253 case TTM_PL_TT: 254 old_start += rdev->mc.gtt_start; 255 break; 256 default: 257 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 258 return -EINVAL; 259 } 260 switch (new_mem->mem_type) { 261 case TTM_PL_VRAM: 262 new_start += rdev->mc.vram_start; 263 break; 264 case TTM_PL_TT: 265 new_start += rdev->mc.gtt_start; 266 break; 267 default: 268 DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); 269 return -EINVAL; 270 } 271 if (!rdev->ring[ridx].ready) { 272 DRM_ERROR("Trying to move memory with ring turned off.\n"); 273 return -EINVAL; 274 } 275 276 BUILD_BUG_ON((PAGE_SIZE % RADEON_GPU_PAGE_SIZE) != 0); 277 278 /* sync other rings */ 279 fence = bo->sync_obj; 280 r = radeon_copy(rdev, old_start, new_start, 281 new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ 282 &fence); 283 /* FIXME: handle copy error */ 284 r = ttm_bo_move_accel_cleanup(bo, (void *)fence, 285 evict, no_wait_gpu, new_mem); 286 radeon_fence_unref(&fence); 287 return r; 288} 289 290static int radeon_move_vram_ram(struct ttm_buffer_object *bo, 291 bool evict, bool interruptible, 292 bool no_wait_gpu, 293 struct ttm_mem_reg *new_mem) 294{ 295 struct radeon_device *rdev __unused; 296 struct ttm_mem_reg *old_mem = &bo->mem; 297 struct ttm_mem_reg tmp_mem; 298 u32 placements; 299 struct ttm_placement placement; 300 int r; 301 302 rdev = radeon_get_rdev(bo->bdev); 303 tmp_mem = *new_mem; 304 tmp_mem.mm_node = NULL; 305 placement.fpfn = 0; 306 placement.lpfn = 0; 307 placement.num_placement = 1; 308 placement.placement = &placements; 309 placement.num_busy_placement = 1; 310 placement.busy_placement = &placements; 311 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 312 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 313 interruptible, no_wait_gpu); 314 if (unlikely(r)) { 315 return r; 316 } 317 318 r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement); 319 if (unlikely(r)) { 320 goto out_cleanup; 321 } 322 323 r = ttm_tt_bind(bo->ttm, &tmp_mem); 324 if (unlikely(r)) { 325 goto out_cleanup; 326 } 327 r = radeon_move_blit(bo, true, no_wait_gpu, &tmp_mem, old_mem); 328 if (unlikely(r)) { 329 goto out_cleanup; 330 } 331 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); 332out_cleanup: 333 ttm_bo_mem_put(bo, &tmp_mem); 334 return r; 335} 336 337static int radeon_move_ram_vram(struct ttm_buffer_object *bo, 338 bool evict, bool interruptible, 339 bool no_wait_gpu, 340 struct ttm_mem_reg *new_mem) 341{ 342 struct radeon_device *rdev __unused; 343 struct ttm_mem_reg *old_mem = &bo->mem; 344 struct ttm_mem_reg tmp_mem; 345 struct ttm_placement placement; 346 u32 placements; 347 int r; 348 349 rdev = radeon_get_rdev(bo->bdev); 350 tmp_mem = *new_mem; 351 tmp_mem.mm_node = NULL; 352 placement.fpfn = 0; 353 placement.lpfn = 0; 354 placement.num_placement = 1; 355 placement.placement = &placements; 356 placement.num_busy_placement = 1; 357 placement.busy_placement = &placements; 358 placements = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT; 359 r = ttm_bo_mem_space(bo, &placement, &tmp_mem, 360 interruptible, no_wait_gpu); 361 if (unlikely(r)) { 362 return r; 363 } 364 r = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); 365 if (unlikely(r)) { 366 goto out_cleanup; 367 } 368 r = radeon_move_blit(bo, true, no_wait_gpu, new_mem, old_mem); 369 if (unlikely(r)) { 370 goto out_cleanup; 371 } 372out_cleanup: 373 ttm_bo_mem_put(bo, &tmp_mem); 374 return r; 375} 376 377static int radeon_bo_move(struct ttm_buffer_object *bo, 378 bool evict, bool interruptible, 379 bool no_wait_gpu, 380 struct ttm_mem_reg *new_mem) 381{ 382 struct radeon_device *rdev; 383 struct ttm_mem_reg *old_mem = &bo->mem; 384 int r; 385 386 rdev = radeon_get_rdev(bo->bdev); 387 if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) { 388 radeon_move_null(bo, new_mem); 389 return 0; 390 } 391 if ((old_mem->mem_type == TTM_PL_TT && 392 new_mem->mem_type == TTM_PL_SYSTEM) || 393 (old_mem->mem_type == TTM_PL_SYSTEM && 394 new_mem->mem_type == TTM_PL_TT)) { 395 /* bind is enough */ 396 radeon_move_null(bo, new_mem); 397 return 0; 398 } 399 if (!rdev->ring[radeon_copy_ring_index(rdev)].ready || 400 rdev->asic->copy.copy == NULL) { 401 /* use memcpy */ 402 goto memcpy; 403 } 404 405 if (old_mem->mem_type == TTM_PL_VRAM && 406 new_mem->mem_type == TTM_PL_SYSTEM) { 407 r = radeon_move_vram_ram(bo, evict, interruptible, 408 no_wait_gpu, new_mem); 409 } else if (old_mem->mem_type == TTM_PL_SYSTEM && 410 new_mem->mem_type == TTM_PL_VRAM) { 411 r = radeon_move_ram_vram(bo, evict, interruptible, 412 no_wait_gpu, new_mem); 413 } else { 414 r = radeon_move_blit(bo, evict, no_wait_gpu, new_mem, old_mem); 415 } 416 417 if (r) { 418memcpy: 419 r = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); 420 if (r) { 421 return r; 422 } 423 } 424 425 /* update statistics */ 426 atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &rdev->num_bytes_moved); 427 return 0; 428} 429 430static int radeon_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 431{ 432 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; 433 struct radeon_device *rdev = radeon_get_rdev(bdev); 434 435 mem->bus.addr = NULL; 436 mem->bus.offset = 0; 437 mem->bus.size = mem->num_pages << PAGE_SHIFT; 438 mem->bus.base = 0; 439 mem->bus.is_iomem = false; 440 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) 441 return -EINVAL; 442 switch (mem->mem_type) { 443 case TTM_PL_SYSTEM: 444 /* system memory */ 445 return 0; 446 case TTM_PL_TT: 447#if __OS_HAS_AGP 448 if (rdev->flags & RADEON_IS_AGP) { 449 /* RADEON_IS_AGP is set only if AGP is active */ 450 mem->bus.offset = mem->start << PAGE_SHIFT; 451 mem->bus.base = rdev->mc.agp_base; 452 mem->bus.is_iomem = !rdev->ddev->agp->cant_use_aperture; 453 } 454#endif 455 break; 456 case TTM_PL_VRAM: 457 mem->bus.offset = mem->start << PAGE_SHIFT; 458 /* check if it's visible */ 459 if ((mem->bus.offset + mem->bus.size) > rdev->mc.visible_vram_size) 460 return -EINVAL; 461 mem->bus.base = rdev->mc.aper_base; 462 mem->bus.is_iomem = true; 463#ifdef __alpha__ 464 /* 465 * Alpha: use bus.addr to hold the ioremap() return, 466 * so we can modify bus.base below. 467 */ 468 if (mem->placement & TTM_PL_FLAG_WC) 469 mem->bus.addr = 470 ioremap_wc(mem->bus.base + mem->bus.offset, 471 mem->bus.size); 472 else 473 mem->bus.addr = 474 ioremap_nocache(mem->bus.base + mem->bus.offset, 475 mem->bus.size); 476 477 /* 478 * Alpha: Use just the bus offset plus 479 * the hose/domain memory base for bus.base. 480 * It then can be used to build PTEs for VRAM 481 * access, as done in ttm_bo_vm_fault(). 482 */ 483 mem->bus.base = (mem->bus.base & 0x0ffffffffUL) + 484 rdev->ddev->hose->dense_mem_base; 485#endif 486 break; 487 default: 488 return -EINVAL; 489 } 490 return 0; 491} 492 493static void radeon_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) 494{ 495} 496 497static int radeon_sync_obj_wait(void *sync_obj, bool lazy, bool interruptible) 498{ 499 return radeon_fence_wait((struct radeon_fence *)sync_obj, interruptible); 500} 501 502static int radeon_sync_obj_flush(void *sync_obj) 503{ 504 return 0; 505} 506 507static void radeon_sync_obj_unref(void **sync_obj) 508{ 509 radeon_fence_unref((struct radeon_fence **)sync_obj); 510} 511 512static void *radeon_sync_obj_ref(void *sync_obj) 513{ 514 return radeon_fence_ref((struct radeon_fence *)sync_obj); 515} 516 517static bool radeon_sync_obj_signaled(void *sync_obj) 518{ 519 return radeon_fence_signaled((struct radeon_fence *)sync_obj); 520} 521 522/* 523 * TTM backend functions. 524 */ 525struct radeon_ttm_tt { 526 struct ttm_dma_tt ttm; 527 struct radeon_device *rdev; 528 u64 offset; 529}; 530 531static int radeon_ttm_backend_bind(struct ttm_tt *ttm, 532 struct ttm_mem_reg *bo_mem) 533{ 534 struct radeon_ttm_tt *gtt = (void*)ttm; 535 int r; 536 537 gtt->offset = (unsigned long)(bo_mem->start << PAGE_SHIFT); 538 if (!ttm->num_pages) { 539 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n", 540 ttm->num_pages, bo_mem, ttm); 541 } 542 r = radeon_gart_bind(gtt->rdev, gtt->offset, 543 ttm->num_pages, ttm->pages, gtt->ttm.dma_address); 544 if (r) { 545 DRM_ERROR("failed to bind %lu pages at 0x%08X\n", 546 ttm->num_pages, (unsigned)gtt->offset); 547 return r; 548 } 549 return 0; 550} 551 552static int radeon_ttm_backend_unbind(struct ttm_tt *ttm) 553{ 554 struct radeon_ttm_tt *gtt = (void *)ttm; 555 556 radeon_gart_unbind(gtt->rdev, gtt->offset, ttm->num_pages); 557 return 0; 558} 559 560static void radeon_ttm_backend_destroy(struct ttm_tt *ttm) 561{ 562 struct radeon_ttm_tt *gtt = (void *)ttm; 563 564 ttm_dma_tt_fini(>t->ttm); 565 kfree(gtt); 566} 567 568static struct ttm_backend_func radeon_backend_func = { 569 .bind = &radeon_ttm_backend_bind, 570 .unbind = &radeon_ttm_backend_unbind, 571 .destroy = &radeon_ttm_backend_destroy, 572}; 573 574static struct ttm_tt *radeon_ttm_tt_create(struct ttm_bo_device *bdev, 575 unsigned long size, uint32_t page_flags, 576 struct page *dummy_read_page) 577{ 578 struct radeon_device *rdev; 579 struct radeon_ttm_tt *gtt; 580 581 rdev = radeon_get_rdev(bdev); 582#if __OS_HAS_AGP 583 if (rdev->flags & RADEON_IS_AGP) { 584 return ttm_agp_tt_create(bdev, rdev->ddev->agp->bridge, 585 size, page_flags, dummy_read_page); 586 } 587#endif 588 589 gtt = kzalloc(sizeof(struct radeon_ttm_tt), GFP_KERNEL); 590 if (gtt == NULL) { 591 return NULL; 592 } 593 gtt->ttm.ttm.func = &radeon_backend_func; 594 gtt->rdev = rdev; 595 if (ttm_dma_tt_init(>t->ttm, bdev, size, page_flags, dummy_read_page)) { 596 kfree(gtt); 597 return NULL; 598 } 599 return >t->ttm.ttm; 600} 601 602static int radeon_ttm_tt_populate(struct ttm_tt *ttm) 603{ 604 struct radeon_device *rdev; 605 struct radeon_ttm_tt *gtt = (void *)ttm; 606#ifndef __NetBSD__ 607 unsigned i; 608 int r; 609#endif 610 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 611 612 if (ttm->state != tt_unpopulated) 613 return 0; 614 615 if (slave && ttm->sg) { 616#ifdef __NetBSD__ /* XXX drm prime */ 617 return -EINVAL; 618#else 619 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, 620 gtt->ttm.dma_address, ttm->num_pages); 621 ttm->state = tt_unbound; 622 return 0; 623#endif 624 } 625 626 rdev = radeon_get_rdev(ttm->bdev); 627#if __OS_HAS_AGP 628 if (rdev->flags & RADEON_IS_AGP) { 629 return ttm_agp_tt_populate(ttm); 630 } 631#endif 632 633#ifdef __NetBSD__ 634 /* XXX errno NetBSD->Linux */ 635 return ttm_bus_dma_populate(>t->ttm); 636#else 637 638#ifdef CONFIG_SWIOTLB 639 if (swiotlb_nr_tbl()) { 640 return ttm_dma_populate(>t->ttm, rdev->dev); 641 } 642#endif 643 644 r = ttm_pool_populate(ttm); 645 if (r) { 646 return r; 647 } 648 649 for (i = 0; i < ttm->num_pages; i++) { 650 gtt->ttm.dma_address[i] = pci_map_page(rdev->pdev, ttm->pages[i], 651 0, PAGE_SIZE, 652 PCI_DMA_BIDIRECTIONAL); 653 if (pci_dma_mapping_error(rdev->pdev, gtt->ttm.dma_address[i])) { 654 while (--i) { 655 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 656 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 657 gtt->ttm.dma_address[i] = 0; 658 } 659 ttm_pool_unpopulate(ttm); 660 return -EFAULT; 661 } 662 } 663 return 0; 664#endif 665} 666 667static void radeon_ttm_tt_unpopulate(struct ttm_tt *ttm) 668{ 669 struct radeon_device *rdev; 670 struct radeon_ttm_tt *gtt = (void *)ttm; 671#ifndef __NetBSD__ 672 unsigned i; 673#endif 674 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); 675 676 if (slave) 677 return; 678 679 rdev = radeon_get_rdev(ttm->bdev); 680#if __OS_HAS_AGP 681 if (rdev->flags & RADEON_IS_AGP) { 682 ttm_agp_tt_unpopulate(ttm); 683 return; 684 } 685#endif 686 687#ifdef __NetBSD__ 688 ttm_bus_dma_unpopulate(>t->ttm); 689 return; 690#else 691 692#ifdef CONFIG_SWIOTLB 693 if (swiotlb_nr_tbl()) { 694 ttm_dma_unpopulate(>t->ttm, rdev->dev); 695 return; 696 } 697#endif 698 699 for (i = 0; i < ttm->num_pages; i++) { 700 if (gtt->ttm.dma_address[i]) { 701 pci_unmap_page(rdev->pdev, gtt->ttm.dma_address[i], 702 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 703 } 704 } 705 706 ttm_pool_unpopulate(ttm); 707#endif 708} 709 710#ifdef __NetBSD__ 711static int radeon_ttm_fault(struct uvm_faultinfo *, vaddr_t, 712 struct vm_page **, int, int, vm_prot_t, int); 713 714static const struct uvm_pagerops radeon_uvm_ops = { 715 .pgo_reference = &ttm_bo_uvm_reference, 716 .pgo_detach = &ttm_bo_uvm_detach, 717 .pgo_fault = &radeon_ttm_fault, 718}; 719#endif 720 721static struct ttm_bo_driver radeon_bo_driver = { 722 .ttm_tt_create = &radeon_ttm_tt_create, 723 .ttm_tt_populate = &radeon_ttm_tt_populate, 724 .ttm_tt_unpopulate = &radeon_ttm_tt_unpopulate, 725#ifdef __NetBSD__ 726 .ttm_uvm_ops = &radeon_uvm_ops, 727#endif 728 .invalidate_caches = &radeon_invalidate_caches, 729 .init_mem_type = &radeon_init_mem_type, 730 .evict_flags = &radeon_evict_flags, 731 .move = &radeon_bo_move, 732 .verify_access = &radeon_verify_access, 733 .sync_obj_signaled = &radeon_sync_obj_signaled, 734 .sync_obj_wait = &radeon_sync_obj_wait, 735 .sync_obj_flush = &radeon_sync_obj_flush, 736 .sync_obj_unref = &radeon_sync_obj_unref, 737 .sync_obj_ref = &radeon_sync_obj_ref, 738 .move_notify = &radeon_bo_move_notify, 739 .fault_reserve_notify = &radeon_bo_fault_reserve_notify, 740 .io_mem_reserve = &radeon_ttm_io_mem_reserve, 741 .io_mem_free = &radeon_ttm_io_mem_free, 742}; 743 744int radeon_ttm_init(struct radeon_device *rdev) 745{ 746 int r; 747 748 r = radeon_ttm_global_init(rdev); 749 if (r) { 750 return r; 751 } 752 /* No others user of address space so set it to 0 */ 753 r = ttm_bo_device_init(&rdev->mman.bdev, 754 rdev->mman.bo_global_ref.ref.object, 755 &radeon_bo_driver, 756#ifdef __NetBSD__ 757 rdev->ddev->bst, 758 rdev->ddev->dmat, 759#else 760 rdev->ddev->anon_inode->i_mapping, 761#endif 762 DRM_FILE_PAGE_OFFSET, 763 rdev->need_dma32); 764 if (r) { 765 DRM_ERROR("failed initializing buffer object driver(%d).\n", r); 766 return r; 767 } 768 rdev->mman.initialized = true; 769 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_VRAM, 770 rdev->mc.real_vram_size >> PAGE_SHIFT); 771 if (r) { 772 DRM_ERROR("Failed initializing VRAM heap.\n"); 773 return r; 774 } 775 /* Change the size here instead of the init above so only lpfn is affected */ 776 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); 777 778 r = radeon_bo_create(rdev, 256 * 1024, PAGE_SIZE, true, 779 RADEON_GEM_DOMAIN_VRAM, 780 NULL, &rdev->stollen_vga_memory); 781 if (r) { 782 return r; 783 } 784 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 785 if (r) 786 return r; 787 r = radeon_bo_pin(rdev->stollen_vga_memory, RADEON_GEM_DOMAIN_VRAM, NULL); 788 radeon_bo_unreserve(rdev->stollen_vga_memory); 789 if (r) { 790 radeon_bo_unref(&rdev->stollen_vga_memory); 791 return r; 792 } 793 DRM_INFO("radeon: %uM of VRAM memory ready\n", 794 (unsigned) (rdev->mc.real_vram_size / (1024 * 1024))); 795 r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, 796 rdev->mc.gtt_size >> PAGE_SHIFT); 797 if (r) { 798 DRM_ERROR("Failed initializing GTT heap.\n"); 799 return r; 800 } 801 DRM_INFO("radeon: %uM of GTT memory ready.\n", 802 (unsigned)(rdev->mc.gtt_size / (1024 * 1024))); 803 804 r = radeon_ttm_debugfs_init(rdev); 805 if (r) { 806 DRM_ERROR("Failed to init debugfs\n"); 807 return r; 808 } 809 return 0; 810} 811 812void radeon_ttm_fini(struct radeon_device *rdev) 813{ 814 int r; 815 816 if (!rdev->mman.initialized) 817 return; 818 radeon_ttm_debugfs_fini(rdev); 819 if (rdev->stollen_vga_memory) { 820 r = radeon_bo_reserve(rdev->stollen_vga_memory, false); 821 if (r == 0) { 822 radeon_bo_unpin(rdev->stollen_vga_memory); 823 radeon_bo_unreserve(rdev->stollen_vga_memory); 824 } 825 radeon_bo_unref(&rdev->stollen_vga_memory); 826 } 827 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_VRAM); 828 ttm_bo_clean_mm(&rdev->mman.bdev, TTM_PL_TT); 829 ttm_bo_device_release(&rdev->mman.bdev); 830 radeon_gart_fini(rdev); 831 radeon_ttm_global_fini(rdev); 832 rdev->mman.initialized = false; 833 DRM_INFO("radeon: ttm finalized\n"); 834} 835 836/* this should only be called at bootup or when userspace 837 * isn't running */ 838void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size) 839{ 840 struct ttm_mem_type_manager *man; 841 842 if (!rdev->mman.initialized) 843 return; 844 845 man = &rdev->mman.bdev.man[TTM_PL_VRAM]; 846 /* this just adjusts TTM size idea, which sets lpfn to the correct value */ 847 man->size = size >> PAGE_SHIFT; 848} 849 850#ifdef __NetBSD__ 851 852static int 853radeon_ttm_fault(struct uvm_faultinfo *ufi, vaddr_t vaddr, 854 struct vm_page **pps, int npages, int centeridx, vm_prot_t access_type, 855 int flags) 856{ 857 struct uvm_object *const uobj = ufi->entry->object.uvm_obj; 858 struct ttm_buffer_object *const bo = container_of(uobj, 859 struct ttm_buffer_object, uvmobj); 860 struct radeon_device *const rdev = radeon_get_rdev(bo->bdev); 861 int error; 862 863 KASSERT(rdev != NULL); 864 down_read(&rdev->pm.mclk_lock); 865 error = ttm_bo_uvm_fault(ufi, vaddr, pps, npages, centeridx, 866 access_type, flags); 867 up_read(&rdev->pm.mclk_lock); 868 869 return error; 870} 871 872int 873radeon_mmap_object(struct drm_device *dev, off_t offset, size_t size, 874 vm_prot_t prot, struct uvm_object **uobjp, voff_t *uoffsetp, 875 struct file *file) 876{ 877 struct radeon_device *rdev = dev->dev_private; 878 879 KASSERT(0 == (offset & (PAGE_SIZE - 1))); 880 881 if (__predict_false(rdev == NULL)) /* XXX How?? */ 882 return -EINVAL; 883 884 if (__predict_false((offset >> PAGE_SHIFT) < DRM_FILE_PAGE_OFFSET)) 885 return drm_mmap_object(dev, offset, size, prot, uobjp, 886 uoffsetp, file); 887 else 888 return ttm_bo_mmap_object(&rdev->mman.bdev, offset, size, prot, 889 uobjp, uoffsetp, file); 890} 891 892#else 893 894static struct vm_operations_struct radeon_ttm_vm_ops; 895static const struct vm_operations_struct *ttm_vm_ops = NULL; 896 897static int radeon_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 898{ 899 struct ttm_buffer_object *bo; 900 struct radeon_device *rdev; 901 int r; 902 903 bo = (struct ttm_buffer_object *)vma->vm_private_data; 904 if (bo == NULL) { 905 return VM_FAULT_NOPAGE; 906 } 907 rdev = radeon_get_rdev(bo->bdev); 908 down_read(&rdev->pm.mclk_lock); 909 r = ttm_vm_ops->fault(vma, vmf); 910 up_read(&rdev->pm.mclk_lock); 911 return r; 912} 913 914int radeon_mmap(struct file *filp, struct vm_area_struct *vma) 915{ 916 struct drm_file *file_priv; 917 struct radeon_device *rdev; 918 int r; 919 920 if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET)) { 921 return drm_mmap(filp, vma); 922 } 923 924 file_priv = filp->private_data; 925 rdev = file_priv->minor->dev->dev_private; 926 if (rdev == NULL) { 927 return -EINVAL; 928 } 929 r = ttm_bo_mmap(filp, vma, &rdev->mman.bdev); 930 if (unlikely(r != 0)) { 931 return r; 932 } 933 if (unlikely(ttm_vm_ops == NULL)) { 934 ttm_vm_ops = vma->vm_ops; 935 radeon_ttm_vm_ops = *ttm_vm_ops; 936 radeon_ttm_vm_ops.fault = &radeon_ttm_fault; 937 } 938 vma->vm_ops = &radeon_ttm_vm_ops; 939 return 0; 940} 941 942#endif /* __NetBSD__ */ 943 944#if defined(CONFIG_DEBUG_FS) 945 946static int radeon_mm_dump_table(struct seq_file *m, void *data) 947{ 948 struct drm_info_node *node = (struct drm_info_node *)m->private; 949 unsigned ttm_pl = *(int *)node->info_ent->data; 950 struct drm_device *dev = node->minor->dev; 951 struct radeon_device *rdev = dev->dev_private; 952 struct drm_mm *mm = (struct drm_mm *)rdev->mman.bdev.man[ttm_pl].priv; 953 int ret; 954 struct ttm_bo_global *glob = rdev->mman.bdev.glob; 955 956 spin_lock(&glob->lru_lock); 957 ret = drm_mm_dump_table(m, mm); 958 spin_unlock(&glob->lru_lock); 959 return ret; 960} 961 962static int ttm_pl_vram = TTM_PL_VRAM; 963static int ttm_pl_tt = TTM_PL_TT; 964 965static struct drm_info_list radeon_ttm_debugfs_list[] = { 966 {"radeon_vram_mm", radeon_mm_dump_table, 0, &ttm_pl_vram}, 967 {"radeon_gtt_mm", radeon_mm_dump_table, 0, &ttm_pl_tt}, 968 {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL}, 969#ifdef CONFIG_SWIOTLB 970 {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL} 971#endif 972}; 973 974static int radeon_ttm_vram_open(struct inode *inode, struct file *filep) 975{ 976 struct radeon_device *rdev = inode->i_private; 977 i_size_write(inode, rdev->mc.mc_vram_size); 978 filep->private_data = inode->i_private; 979 return 0; 980} 981 982static ssize_t radeon_ttm_vram_read(struct file *f, char __user *buf, 983 size_t size, loff_t *pos) 984{ 985 struct radeon_device *rdev = f->private_data; 986 ssize_t result = 0; 987 int r; 988 989 if (size & 0x3 || *pos & 0x3) 990 return -EINVAL; 991 992 while (size) { 993 unsigned long flags; 994 uint32_t value; 995 996 if (*pos >= rdev->mc.mc_vram_size) 997 return result; 998 999 spin_lock_irqsave(&rdev->mmio_idx_lock, flags); 1000 WREG32(RADEON_MM_INDEX, ((uint32_t)*pos) | 0x80000000); 1001 if (rdev->family >= CHIP_CEDAR) 1002 WREG32(EVERGREEN_MM_INDEX_HI, *pos >> 31); 1003 value = RREG32(RADEON_MM_DATA); 1004 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags); 1005 1006 r = put_user(value, (uint32_t *)buf); 1007 if (r) 1008 return r; 1009 1010 result += 4; 1011 buf += 4; 1012 *pos += 4; 1013 size -= 4; 1014 } 1015 1016 return result; 1017} 1018 1019static const struct file_operations radeon_ttm_vram_fops = { 1020 .owner = THIS_MODULE, 1021 .open = radeon_ttm_vram_open, 1022 .read = radeon_ttm_vram_read, 1023 .llseek = default_llseek 1024}; 1025 1026static int radeon_ttm_gtt_open(struct inode *inode, struct file *filep) 1027{ 1028 struct radeon_device *rdev = inode->i_private; 1029 i_size_write(inode, rdev->mc.gtt_size); 1030 filep->private_data = inode->i_private; 1031 return 0; 1032} 1033 1034static ssize_t radeon_ttm_gtt_read(struct file *f, char __user *buf, 1035 size_t size, loff_t *pos) 1036{ 1037 struct radeon_device *rdev = f->private_data; 1038 ssize_t result = 0; 1039 int r; 1040 1041 while (size) { 1042 loff_t p = *pos / PAGE_SIZE; 1043 unsigned off = *pos & ~PAGE_MASK; 1044 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off); 1045 struct page *page; 1046 void *ptr; 1047 1048 if (p >= rdev->gart.num_cpu_pages) 1049 return result; 1050 1051 page = rdev->gart.pages[p]; 1052 if (page) { 1053 ptr = kmap(page); 1054 ptr += off; 1055 1056 r = copy_to_user(buf, ptr, cur_size); 1057 kunmap(rdev->gart.pages[p]); 1058 } else 1059 r = clear_user(buf, cur_size); 1060 1061 if (r) 1062 return -EFAULT; 1063 1064 result += cur_size; 1065 buf += cur_size; 1066 *pos += cur_size; 1067 size -= cur_size; 1068 } 1069 1070 return result; 1071} 1072 1073static const struct file_operations radeon_ttm_gtt_fops = { 1074 .owner = THIS_MODULE, 1075 .open = radeon_ttm_gtt_open, 1076 .read = radeon_ttm_gtt_read, 1077 .llseek = default_llseek 1078}; 1079 1080#endif 1081 1082static int radeon_ttm_debugfs_init(struct radeon_device *rdev) 1083{ 1084#if defined(CONFIG_DEBUG_FS) 1085 unsigned count; 1086 1087 struct drm_minor *minor = rdev->ddev->primary; 1088 struct dentry *ent, *root = minor->debugfs_root; 1089 1090 ent = debugfs_create_file("radeon_vram", S_IFREG | S_IRUGO, root, 1091 rdev, &radeon_ttm_vram_fops); 1092 if (IS_ERR(ent)) 1093 return PTR_ERR(ent); 1094 rdev->mman.vram = ent; 1095 1096 ent = debugfs_create_file("radeon_gtt", S_IFREG | S_IRUGO, root, 1097 rdev, &radeon_ttm_gtt_fops); 1098 if (IS_ERR(ent)) 1099 return PTR_ERR(ent); 1100 rdev->mman.gtt = ent; 1101 1102 count = ARRAY_SIZE(radeon_ttm_debugfs_list); 1103 1104#ifdef CONFIG_SWIOTLB 1105 if (!swiotlb_nr_tbl()) 1106 --count; 1107#endif 1108 1109 return radeon_debugfs_add_files(rdev, radeon_ttm_debugfs_list, count); 1110#else 1111 1112 return 0; 1113#endif 1114} 1115 1116static void radeon_ttm_debugfs_fini(struct radeon_device *rdev) 1117{ 1118#if defined(CONFIG_DEBUG_FS) 1119 1120 debugfs_remove(rdev->mman.vram); 1121 rdev->mman.vram = NULL; 1122 1123 debugfs_remove(rdev->mman.gtt); 1124 rdev->mman.gtt = NULL; 1125#endif 1126} 1127