1/* $NetBSD: radeon_r600_hdmi.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3/* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Christian K��nig. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Christian K��nig 27 */ 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: radeon_r600_hdmi.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 30 31#include <linux/hdmi.h> 32#include <linux/gcd.h> 33 34#include <drm/radeon_drm.h> 35#include "radeon.h" 36#include "radeon_asic.h" 37#include "radeon_audio.h" 38#include "r600d.h" 39#include "atom.h" 40 41/* 42 * HDMI color format 43 */ 44enum r600_hdmi_color_format { 45 RGB = 0, 46 YCC_422 = 1, 47 YCC_444 = 2 48}; 49 50/* 51 * IEC60958 status bits 52 */ 53enum r600_hdmi_iec_status_bits { 54 AUDIO_STATUS_DIG_ENABLE = 0x01, 55 AUDIO_STATUS_V = 0x02, 56 AUDIO_STATUS_VCFG = 0x04, 57 AUDIO_STATUS_EMPHASIS = 0x08, 58 AUDIO_STATUS_COPYRIGHT = 0x10, 59 AUDIO_STATUS_NONAUDIO = 0x20, 60 AUDIO_STATUS_PROFESSIONAL = 0x40, 61 AUDIO_STATUS_LEVEL = 0x80 62}; 63 64static struct r600_audio_pin r600_audio_status(struct radeon_device *rdev) 65{ 66 struct r600_audio_pin status = {}; 67 uint32_t value; 68 69 value = RREG32(R600_AUDIO_RATE_BPS_CHANNEL); 70 71 /* number of channels */ 72 status.channels = (value & 0x7) + 1; 73 74 /* bits per sample */ 75 switch ((value & 0xF0) >> 4) { 76 case 0x0: 77 status.bits_per_sample = 8; 78 break; 79 case 0x1: 80 status.bits_per_sample = 16; 81 break; 82 case 0x2: 83 status.bits_per_sample = 20; 84 break; 85 case 0x3: 86 status.bits_per_sample = 24; 87 break; 88 case 0x4: 89 status.bits_per_sample = 32; 90 break; 91 default: 92 dev_err(rdev->dev, "Unknown bits per sample 0x%x, using 16\n", 93 (int)value); 94 status.bits_per_sample = 16; 95 } 96 97 /* current sampling rate in HZ */ 98 if (value & 0x4000) 99 status.rate = 44100; 100 else 101 status.rate = 48000; 102 status.rate *= ((value >> 11) & 0x7) + 1; 103 status.rate /= ((value >> 8) & 0x7) + 1; 104 105 value = RREG32(R600_AUDIO_STATUS_BITS); 106 107 /* iec 60958 status bits */ 108 status.status_bits = value & 0xff; 109 110 /* iec 60958 category code */ 111 status.category_code = (value >> 8) & 0xff; 112 113 return status; 114} 115 116/* 117 * update all hdmi interfaces with current audio parameters 118 */ 119void r600_audio_update_hdmi(struct work_struct *work) 120{ 121 struct radeon_device *rdev = container_of(work, struct radeon_device, 122 audio_work); 123 struct drm_device *dev = rdev->ddev; 124 struct r600_audio_pin audio_status = r600_audio_status(rdev); 125 struct drm_encoder *encoder; 126 bool changed = false; 127 128 if (rdev->audio.pin[0].channels != audio_status.channels || 129 rdev->audio.pin[0].rate != audio_status.rate || 130 rdev->audio.pin[0].bits_per_sample != audio_status.bits_per_sample || 131 rdev->audio.pin[0].status_bits != audio_status.status_bits || 132 rdev->audio.pin[0].category_code != audio_status.category_code) { 133 rdev->audio.pin[0] = audio_status; 134 changed = true; 135 } 136 137 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 138 if (!radeon_encoder_is_digital(encoder)) 139 continue; 140 if (changed || r600_hdmi_buffer_status_changed(encoder)) 141 r600_hdmi_update_audio_settings(encoder); 142 } 143} 144 145/* enable the audio stream */ 146void r600_audio_enable(struct radeon_device *rdev, 147 struct r600_audio_pin *pin, 148 u8 enable_mask) 149{ 150 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL); 151 152 if (!pin) 153 return; 154 155 if (enable_mask) { 156 tmp |= AUDIO_ENABLED; 157 if (enable_mask & 1) 158 tmp |= PIN0_AUDIO_ENABLED; 159 if (enable_mask & 2) 160 tmp |= PIN1_AUDIO_ENABLED; 161 if (enable_mask & 4) 162 tmp |= PIN2_AUDIO_ENABLED; 163 if (enable_mask & 8) 164 tmp |= PIN3_AUDIO_ENABLED; 165 } else { 166 tmp &= ~(AUDIO_ENABLED | 167 PIN0_AUDIO_ENABLED | 168 PIN1_AUDIO_ENABLED | 169 PIN2_AUDIO_ENABLED | 170 PIN3_AUDIO_ENABLED); 171 } 172 173 WREG32(AZ_HOT_PLUG_CONTROL, tmp); 174} 175 176struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev) 177{ 178 /* only one pin on 6xx-NI */ 179 return &rdev->audio.pin[0]; 180} 181 182void r600_hdmi_update_acr(struct drm_encoder *encoder, long offset, 183 const struct radeon_hdmi_acr *acr) 184{ 185 struct drm_device *dev = encoder->dev; 186 struct radeon_device *rdev = dev->dev_private; 187 188 /* DCE 3.0 uses register that's normally for CRC_CONTROL */ 189 uint32_t acr_ctl = ASIC_IS_DCE3(rdev) ? DCE3_HDMI0_ACR_PACKET_CONTROL : 190 HDMI0_ACR_PACKET_CONTROL; 191 WREG32_P(acr_ctl + offset, 192 HDMI0_ACR_SOURCE | /* select SW CTS value */ 193 HDMI0_ACR_AUTO_SEND, /* allow hw to sent ACR packets when required */ 194 ~(HDMI0_ACR_SOURCE | 195 HDMI0_ACR_AUTO_SEND)); 196 197 WREG32_P(HDMI0_ACR_32_0 + offset, 198 HDMI0_ACR_CTS_32(acr->cts_32khz), 199 ~HDMI0_ACR_CTS_32_MASK); 200 WREG32_P(HDMI0_ACR_32_1 + offset, 201 HDMI0_ACR_N_32(acr->n_32khz), 202 ~HDMI0_ACR_N_32_MASK); 203 204 WREG32_P(HDMI0_ACR_44_0 + offset, 205 HDMI0_ACR_CTS_44(acr->cts_44_1khz), 206 ~HDMI0_ACR_CTS_44_MASK); 207 WREG32_P(HDMI0_ACR_44_1 + offset, 208 HDMI0_ACR_N_44(acr->n_44_1khz), 209 ~HDMI0_ACR_N_44_MASK); 210 211 WREG32_P(HDMI0_ACR_48_0 + offset, 212 HDMI0_ACR_CTS_48(acr->cts_48khz), 213 ~HDMI0_ACR_CTS_48_MASK); 214 WREG32_P(HDMI0_ACR_48_1 + offset, 215 HDMI0_ACR_N_48(acr->n_48khz), 216 ~HDMI0_ACR_N_48_MASK); 217} 218 219/* 220 * build a HDMI Video Info Frame 221 */ 222void r600_set_avi_packet(struct radeon_device *rdev, u32 offset, 223 unsigned char *buffer, size_t size) 224{ 225 uint8_t *frame = buffer + 3; 226 227 WREG32(HDMI0_AVI_INFO0 + offset, 228 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 229 WREG32(HDMI0_AVI_INFO1 + offset, 230 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); 231 WREG32(HDMI0_AVI_INFO2 + offset, 232 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); 233 WREG32(HDMI0_AVI_INFO3 + offset, 234 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24)); 235 236 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset, 237 HDMI0_AVI_INFO_LINE(2)); /* anything other than 0 */ 238 239 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 240 HDMI0_AVI_INFO_SEND | /* enable AVI info frames */ 241 HDMI0_AVI_INFO_CONT); /* send AVI info frames every frame/field */ 242 243} 244 245/* 246 * build a Audio Info Frame 247 */ 248static void r600_hdmi_update_audio_infoframe(struct drm_encoder *encoder, 249 const void *buffer, size_t size) 250{ 251 struct drm_device *dev = encoder->dev; 252 struct radeon_device *rdev = dev->dev_private; 253 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 254 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 255 uint32_t offset = dig->afmt->offset; 256 const u8 *frame = (const u8 *)buffer + 3; 257 258 WREG32(HDMI0_AUDIO_INFO0 + offset, 259 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); 260 WREG32(HDMI0_AUDIO_INFO1 + offset, 261 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x8] << 24)); 262} 263 264/* 265 * test if audio buffer is filled enough to start playing 266 */ 267static bool r600_hdmi_is_audio_buffer_filled(struct drm_encoder *encoder) 268{ 269 struct drm_device *dev = encoder->dev; 270 struct radeon_device *rdev = dev->dev_private; 271 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 272 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 273 uint32_t offset = dig->afmt->offset; 274 275 return (RREG32(HDMI0_STATUS + offset) & 0x10) != 0; 276} 277 278/* 279 * have buffer status changed since last call? 280 */ 281int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder) 282{ 283 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 284 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 285 int status, result; 286 287 if (!dig->afmt || !dig->afmt->enabled) 288 return 0; 289 290 status = r600_hdmi_is_audio_buffer_filled(encoder); 291 result = dig->afmt->last_buffer_filled_status != status; 292 dig->afmt->last_buffer_filled_status = status; 293 294 return result; 295} 296 297/* 298 * write the audio workaround status to the hardware 299 */ 300void r600_hdmi_audio_workaround(struct drm_encoder *encoder) 301{ 302 struct drm_device *dev = encoder->dev; 303 struct radeon_device *rdev = dev->dev_private; 304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 305 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 306 uint32_t offset = dig->afmt->offset; 307 bool hdmi_audio_workaround = false; /* FIXME */ 308 u32 value; 309 310 if (!hdmi_audio_workaround || 311 r600_hdmi_is_audio_buffer_filled(encoder)) 312 value = 0; /* disable workaround */ 313 else 314 value = HDMI0_AUDIO_TEST_EN; /* enable workaround */ 315 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 316 value, ~HDMI0_AUDIO_TEST_EN); 317} 318 319void r600_hdmi_audio_set_dto(struct radeon_device *rdev, 320 struct radeon_crtc *crtc, unsigned int clock) 321{ 322 struct radeon_encoder *radeon_encoder; 323 struct radeon_encoder_atom_dig *dig; 324 325 if (!crtc) 326 return; 327 328 radeon_encoder = to_radeon_encoder(crtc->encoder); 329 dig = radeon_encoder->enc_priv; 330 331 if (!dig) 332 return; 333 334 if (dig->dig_encoder == 0) { 335 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000 * 100); 336 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100); 337 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */ 338 } else { 339 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000 * 100); 340 WREG32(DCCG_AUDIO_DTO1_MODULE, clock * 100); 341 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */ 342 } 343} 344 345void r600_set_vbi_packet(struct drm_encoder *encoder, u32 offset) 346{ 347 struct drm_device *dev = encoder->dev; 348 struct radeon_device *rdev = dev->dev_private; 349 350 WREG32_OR(HDMI0_VBI_PACKET_CONTROL + offset, 351 HDMI0_NULL_SEND | /* send null packets when required */ 352 HDMI0_GC_SEND | /* send general control packets */ 353 HDMI0_GC_CONT); /* send general control packets every frame */ 354} 355 356void r600_set_audio_packet(struct drm_encoder *encoder, u32 offset) 357{ 358 struct drm_device *dev = encoder->dev; 359 struct radeon_device *rdev = dev->dev_private; 360 361 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, 362 HDMI0_AUDIO_SAMPLE_SEND | /* send audio packets */ 363 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */ 364 HDMI0_AUDIO_PACKETS_PER_LINE(3) | /* should be suffient for all audio modes and small enough for all hblanks */ 365 HDMI0_60958_CS_UPDATE, /* allow 60958 channel status fields to be updated */ 366 ~(HDMI0_AUDIO_SAMPLE_SEND | 367 HDMI0_AUDIO_DELAY_EN_MASK | 368 HDMI0_AUDIO_PACKETS_PER_LINE_MASK | 369 HDMI0_60958_CS_UPDATE)); 370 371 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 372 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 373 HDMI0_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 374 375 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, 376 HDMI0_AUDIO_INFO_LINE(2), /* anything other than 0 */ 377 ~HDMI0_AUDIO_INFO_LINE_MASK); 378 379 WREG32_AND(HDMI0_GENERIC_PACKET_CONTROL + offset, 380 ~(HDMI0_GENERIC0_SEND | 381 HDMI0_GENERIC0_CONT | 382 HDMI0_GENERIC0_UPDATE | 383 HDMI0_GENERIC1_SEND | 384 HDMI0_GENERIC1_CONT | 385 HDMI0_GENERIC0_LINE_MASK | 386 HDMI0_GENERIC1_LINE_MASK)); 387 388 WREG32_P(HDMI0_60958_0 + offset, 389 HDMI0_60958_CS_CHANNEL_NUMBER_L(1), 390 ~(HDMI0_60958_CS_CHANNEL_NUMBER_L_MASK | 391 HDMI0_60958_CS_CLOCK_ACCURACY_MASK)); 392 393 WREG32_P(HDMI0_60958_1 + offset, 394 HDMI0_60958_CS_CHANNEL_NUMBER_R(2), 395 ~HDMI0_60958_CS_CHANNEL_NUMBER_R_MASK); 396} 397 398void r600_set_mute(struct drm_encoder *encoder, u32 offset, bool mute) 399{ 400 struct drm_device *dev = encoder->dev; 401 struct radeon_device *rdev = dev->dev_private; 402 403 if (mute) 404 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE); 405 else 406 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE); 407} 408 409/** 410 * r600_hdmi_update_audio_settings - Update audio infoframe 411 * 412 * @encoder: drm encoder 413 * 414 * Gets info about current audio stream and updates audio infoframe. 415 */ 416void r600_hdmi_update_audio_settings(struct drm_encoder *encoder) 417{ 418 struct drm_device *dev = encoder->dev; 419 struct radeon_device *rdev = dev->dev_private; 420 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 421 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 422 struct r600_audio_pin audio = r600_audio_status(rdev); 423 uint8_t buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE]; 424 struct hdmi_audio_infoframe frame; 425 uint32_t offset; 426 uint32_t value; 427 ssize_t err; 428 429 if (!dig->afmt || !dig->afmt->enabled) 430 return; 431 offset = dig->afmt->offset; 432 433 DRM_DEBUG("%s with %d channels, %d Hz sampling rate, %d bits per sample,\n", 434 r600_hdmi_is_audio_buffer_filled(encoder) ? "playing" : "stopped", 435 audio.channels, audio.rate, audio.bits_per_sample); 436 DRM_DEBUG("0x%02X IEC60958 status bits and 0x%02X category code\n", 437 (int)audio.status_bits, (int)audio.category_code); 438 439 err = hdmi_audio_infoframe_init(&frame); 440 if (err < 0) { 441 DRM_ERROR("failed to setup audio infoframe\n"); 442 return; 443 } 444 445 frame.channels = audio.channels; 446 447 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 448 if (err < 0) { 449 DRM_ERROR("failed to pack audio infoframe\n"); 450 return; 451 } 452 453 value = RREG32(HDMI0_AUDIO_PACKET_CONTROL + offset); 454 if (value & HDMI0_AUDIO_TEST_EN) 455 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset, 456 value & ~HDMI0_AUDIO_TEST_EN); 457 458 WREG32_OR(HDMI0_CONTROL + offset, 459 HDMI0_ERROR_ACK); 460 461 WREG32_AND(HDMI0_INFOFRAME_CONTROL0 + offset, 462 ~HDMI0_AUDIO_INFO_SOURCE); 463 464 r600_hdmi_update_audio_infoframe(encoder, buffer, sizeof(buffer)); 465 466 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset, 467 HDMI0_AUDIO_INFO_CONT | 468 HDMI0_AUDIO_INFO_UPDATE); 469} 470 471/* 472 * enable the HDMI engine 473 */ 474void r600_hdmi_enable(struct drm_encoder *encoder, bool enable) 475{ 476 struct drm_device *dev = encoder->dev; 477 struct radeon_device *rdev = dev->dev_private; 478 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 479 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 480 u32 hdmi = HDMI0_ERROR_ACK; 481 482 if (!dig || !dig->afmt) 483 return; 484 485 /* Older chipsets require setting HDMI and routing manually */ 486 if (!ASIC_IS_DCE3(rdev)) { 487 if (enable) 488 hdmi |= HDMI0_ENABLE; 489 switch (radeon_encoder->encoder_id) { 490 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 491 if (enable) { 492 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN); 493 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 494 } else { 495 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN); 496 } 497 break; 498 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 499 if (enable) { 500 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN); 501 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 502 } else { 503 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN); 504 } 505 break; 506 case ENCODER_OBJECT_ID_INTERNAL_DDI: 507 if (enable) { 508 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN); 509 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 510 } else { 511 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN); 512 } 513 break; 514 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 515 if (enable) 516 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 517 break; 518 default: 519 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 520 radeon_encoder->encoder_id); 521 break; 522 } 523 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi); 524 } 525 526 if (rdev->irq.installed) { 527 /* if irq is available use it */ 528 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */ 529 if (enable) 530 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 531 else 532 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id); 533 } 534 535 dig->afmt->enabled = enable; 536 537 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n", 538 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id); 539} 540 541