radeon_r600_blit_shaders.c revision 1.1 
1/*	$NetBSD: radeon_r600_blit_shaders.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $	*/
2
3/*
4 * Copyright 2009 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 *     Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include <sys/cdefs.h>
30__KERNEL_RCSID(0, "$NetBSD: radeon_r600_blit_shaders.c,v 1.1 2018/08/27 14:38:20 riastradh Exp $");
31
32#include <linux/bug.h>
33#include <linux/types.h>
34#include <linux/kernel.h>
35
36/*
37 * R6xx+ cards need to use the 3D engine to blit data which requires
38 * quite a bit of hw state setup.  Rather than pull the whole 3D driver
39 * (which normally generates the 3D state) into the DRM, we opt to use
40 * statically generated state tables.  The register state and shaders
41 * were hand generated to support blitting functionality.  See the 3D
42 * driver or documentation for descriptions of the registers and
43 * shader instructions.
44 */
45
46const u32 r6xx_default_state[] =
47{
48	0xc0002400, /* START_3D_CMDBUF */
49	0x00000000,
50
51	0xc0012800, /* CONTEXT_CONTROL */
52	0x80000000,
53	0x80000000,
54
55	0xc0016800,
56	0x00000010,
57	0x00008000, /* WAIT_UNTIL */
58
59	0xc0016800,
60	0x00000542,
61	0x07000003, /* TA_CNTL_AUX */
62
63	0xc0016800,
64	0x000005c5,
65	0x00000000, /* VC_ENHANCE */
66
67	0xc0016800,
68	0x00000363,
69	0x00000000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
70
71	0xc0016800,
72	0x0000060c,
73	0x82000000, /* DB_DEBUG */
74
75	0xc0016800,
76	0x0000060e,
77	0x01020204, /* DB_WATERMARKS */
78
79	0xc0026f00,
80	0x00000000,
81	0x00000000, /* SQ_VTX_BASE_VTX_LOC */
82	0x00000000, /* SQ_VTX_START_INST_LOC */
83
84	0xc0096900,
85	0x0000022a,
86	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
87	0x00000000,
88	0x00000000,
89	0x00000000,
90	0x00000000,
91	0x00000000,
92	0x00000000,
93	0x00000000,
94	0x00000000,
95
96	0xc0016900,
97	0x00000004,
98	0x00000000, /* DB_DEPTH_INFO */
99
100	0xc0026900,
101	0x0000000a,
102	0x00000000, /* DB_STENCIL_CLEAR */
103	0x00000000, /* DB_DEPTH_CLEAR */
104
105	0xc0016900,
106	0x00000200,
107	0x00000000, /* DB_DEPTH_CONTROL */
108
109	0xc0026900,
110	0x00000343,
111	0x00000060, /* DB_RENDER_CONTROL */
112	0x00000040, /* DB_RENDER_OVERRIDE */
113
114	0xc0016900,
115	0x00000351,
116	0x0000aa00, /* DB_ALPHA_TO_MASK */
117
118	0xc00f6900,
119	0x00000100,
120	0x00000800, /* VGT_MAX_VTX_INDX */
121	0x00000000, /* VGT_MIN_VTX_INDX */
122	0x00000000, /* VGT_INDX_OFFSET */
123	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
124	0x00000000, /* SX_ALPHA_TEST_CONTROL */
125	0x00000000, /* CB_BLEND_RED */
126	0x00000000,
127	0x00000000,
128	0x00000000,
129	0x00000000, /* CB_FOG_RED */
130	0x00000000,
131	0x00000000,
132	0x00000000, /* DB_STENCILREFMASK */
133	0x00000000, /* DB_STENCILREFMASK_BF */
134	0x00000000, /* SX_ALPHA_REF */
135
136	0xc0046900,
137	0x0000030c,
138	0x01000000, /* CB_CLRCMP_CNTL */
139	0x00000000,
140	0x00000000,
141	0x00000000,
142
143	0xc0046900,
144	0x00000048,
145	0x3f800000, /* CB_CLEAR_RED */
146	0x00000000,
147	0x3f800000,
148	0x3f800000,
149
150	0xc0016900,
151	0x00000080,
152	0x00000000, /* PA_SC_WINDOW_OFFSET */
153
154	0xc00a6900,
155	0x00000083,
156	0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
157	0x00000000, /* PA_SC_CLIPRECT_0_TL */
158	0x20002000,
159	0x00000000,
160	0x20002000,
161	0x00000000,
162	0x20002000,
163	0x00000000,
164	0x20002000,
165	0x00000000, /* PA_SC_EDGERULE */
166
167	0xc0406900,
168	0x00000094,
169	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
170	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
171	0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
172	0x20002000,
173	0x80000000,
174	0x20002000,
175	0x80000000,
176	0x20002000,
177	0x80000000,
178	0x20002000,
179	0x80000000,
180	0x20002000,
181	0x80000000,
182	0x20002000,
183	0x80000000,
184	0x20002000,
185	0x80000000,
186	0x20002000,
187	0x80000000,
188	0x20002000,
189	0x80000000,
190	0x20002000,
191	0x80000000,
192	0x20002000,
193	0x80000000,
194	0x20002000,
195	0x80000000,
196	0x20002000,
197	0x80000000,
198	0x20002000,
199	0x80000000,
200	0x20002000,
201	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
202	0x3f800000,
203	0x00000000,
204	0x3f800000,
205	0x00000000,
206	0x3f800000,
207	0x00000000,
208	0x3f800000,
209	0x00000000,
210	0x3f800000,
211	0x00000000,
212	0x3f800000,
213	0x00000000,
214	0x3f800000,
215	0x00000000,
216	0x3f800000,
217	0x00000000,
218	0x3f800000,
219	0x00000000,
220	0x3f800000,
221	0x00000000,
222	0x3f800000,
223	0x00000000,
224	0x3f800000,
225	0x00000000,
226	0x3f800000,
227	0x00000000,
228	0x3f800000,
229	0x00000000,
230	0x3f800000,
231	0x00000000,
232	0x3f800000,
233
234	0xc0026900,
235	0x00000292,
236	0x00000000, /* PA_SC_MPASS_PS_CNTL */
237	0x00004010, /* PA_SC_MODE_CNTL */
238
239	0xc0096900,
240	0x00000300,
241	0x00000000, /* PA_SC_LINE_CNTL */
242	0x00000000, /* PA_SC_AA_CONFIG */
243	0x0000002d, /* PA_SU_VTX_CNTL */
244	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
245	0x3f800000,
246	0x3f800000,
247	0x3f800000,
248	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
249	0x00000000,
250
251	0xc0016900,
252	0x00000312,
253	0xffffffff, /* PA_SC_AA_MASK */
254
255	0xc0066900,
256	0x0000037e,
257	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
258	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
259	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
260	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
261	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
262	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
263
264	0xc0046900,
265	0x000001b6,
266	0x00000000, /* SPI_INPUT_Z */
267	0x00000000, /* SPI_FOG_CNTL */
268	0x00000000, /* SPI_FOG_FUNC_SCALE */
269	0x00000000, /* SPI_FOG_FUNC_BIAS */
270
271	0xc0016900,
272	0x00000225,
273	0x00000000, /* SQ_PGM_START_FS */
274
275	0xc0016900,
276	0x00000229,
277	0x00000000, /* SQ_PGM_RESOURCES_FS */
278
279	0xc0016900,
280	0x00000237,
281	0x00000000, /* SQ_PGM_CF_OFFSET_FS */
282
283	0xc0026900,
284	0x000002a8,
285	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
286	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
287
288	0xc0116900,
289	0x00000280,
290	0x00000000, /* PA_SU_POINT_SIZE */
291	0x00000000, /* PA_SU_POINT_MINMAX */
292	0x00000008, /* PA_SU_LINE_CNTL */
293	0x00000000, /* PA_SC_LINE_STIPPLE */
294	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
295	0x00000000, /* VGT_HOS_CNTL */
296	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
297	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
298	0x00000000, /* VGT_HOS_REUSE_DEPTH */
299	0x00000000, /* VGT_GROUP_PRIM_TYPE */
300	0x00000000, /* VGT_GROUP_FIRST_DECR */
301	0x00000000, /* VGT_GROUP_DECR */
302	0x00000000, /* VGT_GROUP_VECT_0_CNTL */
303	0x00000000, /* VGT_GROUP_VECT_1_CNTL */
304	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
305	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
306	0x00000000, /* VGT_GS_MODE */
307
308	0xc0016900,
309	0x000002a1,
310	0x00000000, /* VGT_PRIMITIVEID_EN */
311
312	0xc0016900,
313	0x000002a5,
314	0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
315
316	0xc0036900,
317	0x000002ac,
318	0x00000000, /* VGT_STRMOUT_EN */
319	0x00000000, /* VGT_REUSE_OFF */
320	0x00000000, /* VGT_VTX_CNT_EN */
321
322	0xc0016900,
323	0x000000d4,
324	0x00000000, /* SX_MISC */
325
326	0xc0016900,
327	0x000002c8,
328	0x00000000, /* VGT_STRMOUT_BUFFER_EN */
329
330	0xc0076900,
331	0x00000202,
332	0x00cc0000, /* CB_COLOR_CONTROL */
333	0x00000210, /* DB_SHADER_CNTL */
334	0x00010000, /* PA_CL_CLIP_CNTL */
335	0x00000244, /* PA_SU_SC_MODE_CNTL */
336	0x00000100, /* PA_CL_VTE_CNTL */
337	0x00000000, /* PA_CL_VS_OUT_CNTL */
338	0x00000000, /* PA_CL_NANINF_CNTL */
339
340	0xc0026900,
341	0x0000008e,
342	0x0000000f, /* CB_TARGET_MASK */
343	0x0000000f, /* CB_SHADER_MASK */
344
345	0xc0016900,
346	0x000001e8,
347	0x00000001, /* CB_SHADER_CONTROL */
348
349	0xc0016900,
350	0x00000185,
351	0x00000000, /* SPI_VS_OUT_ID_0 */
352
353	0xc0016900,
354	0x00000191,
355	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
356
357	0xc0056900,
358	0x000001b1,
359	0x00000000, /* SPI_VS_OUT_CONFIG */
360	0x00000000, /* SPI_THREAD_GROUPING */
361	0x00000001, /* SPI_PS_IN_CONTROL_0 */
362	0x00000000, /* SPI_PS_IN_CONTROL_1 */
363	0x00000000, /* SPI_INTERP_CONTROL_0 */
364
365	0xc0036e00, /* SET_SAMPLER */
366	0x00000000,
367	0x00000012,
368	0x00000000,
369	0x00000000,
370};
371
372const u32 r7xx_default_state[] =
373{
374	0xc0012800, /* CONTEXT_CONTROL */
375	0x80000000,
376	0x80000000,
377
378	0xc0016800,
379	0x00000010,
380	0x00008000, /* WAIT_UNTIL */
381
382	0xc0016800,
383	0x00000542,
384	0x07000002, /* TA_CNTL_AUX */
385
386	0xc0016800,
387	0x000005c5,
388	0x00000000, /* VC_ENHANCE */
389
390	0xc0016800,
391	0x00000363,
392	0x00004000, /* SQ_DYN_GPR_CNTL_PS_FLUSH_REQ */
393
394	0xc0016800,
395	0x0000060c,
396	0x00000000, /* DB_DEBUG */
397
398	0xc0016800,
399	0x0000060e,
400	0x00420204, /* DB_WATERMARKS */
401
402	0xc0026f00,
403	0x00000000,
404	0x00000000, /* SQ_VTX_BASE_VTX_LOC */
405	0x00000000, /* SQ_VTX_START_INST_LOC */
406
407	0xc0096900,
408	0x0000022a,
409	0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
410	0x00000000,
411	0x00000000,
412	0x00000000,
413	0x00000000,
414	0x00000000,
415	0x00000000,
416	0x00000000,
417	0x00000000,
418
419	0xc0016900,
420	0x00000004,
421	0x00000000, /* DB_DEPTH_INFO */
422
423	0xc0026900,
424	0x0000000a,
425	0x00000000, /* DB_STENCIL_CLEAR */
426	0x00000000, /* DB_DEPTH_CLEAR */
427
428	0xc0016900,
429	0x00000200,
430	0x00000000, /* DB_DEPTH_CONTROL */
431
432	0xc0026900,
433	0x00000343,
434	0x00000060, /* DB_RENDER_CONTROL */
435	0x00000000, /* DB_RENDER_OVERRIDE */
436
437	0xc0016900,
438	0x00000351,
439	0x0000aa00, /* DB_ALPHA_TO_MASK */
440
441	0xc0096900,
442	0x00000100,
443	0x00000800, /* VGT_MAX_VTX_INDX */
444	0x00000000, /* VGT_MIN_VTX_INDX */
445	0x00000000, /* VGT_INDX_OFFSET */
446	0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
447	0x00000000, /* SX_ALPHA_TEST_CONTROL */
448	0x00000000, /* CB_BLEND_RED */
449	0x00000000,
450	0x00000000,
451	0x00000000,
452
453	0xc0036900,
454	0x0000010c,
455	0x00000000, /* DB_STENCILREFMASK */
456	0x00000000, /* DB_STENCILREFMASK_BF */
457	0x00000000, /* SX_ALPHA_REF */
458
459	0xc0046900,
460	0x0000030c, /* CB_CLRCMP_CNTL */
461	0x01000000,
462	0x00000000,
463	0x00000000,
464	0x00000000,
465
466	0xc0016900,
467	0x00000080,
468	0x00000000, /* PA_SC_WINDOW_OFFSET */
469
470	0xc00a6900,
471	0x00000083,
472	0x0000ffff, /* PA_SC_CLIP_RECT_RULE */
473	0x00000000, /* PA_SC_CLIPRECT_0_TL */
474	0x20002000,
475	0x00000000,
476	0x20002000,
477	0x00000000,
478	0x20002000,
479	0x00000000,
480	0x20002000,
481	0xaaaaaaaa, /* PA_SC_EDGERULE */
482
483	0xc0406900,
484	0x00000094,
485	0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
486	0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
487	0x80000000, /* PA_SC_VPORT_SCISSOR_1_TL */
488	0x20002000,
489	0x80000000,
490	0x20002000,
491	0x80000000,
492	0x20002000,
493	0x80000000,
494	0x20002000,
495	0x80000000,
496	0x20002000,
497	0x80000000,
498	0x20002000,
499	0x80000000,
500	0x20002000,
501	0x80000000,
502	0x20002000,
503	0x80000000,
504	0x20002000,
505	0x80000000,
506	0x20002000,
507	0x80000000,
508	0x20002000,
509	0x80000000,
510	0x20002000,
511	0x80000000,
512	0x20002000,
513	0x80000000,
514	0x20002000,
515	0x80000000,
516	0x20002000,
517	0x00000000, /* PA_SC_VPORT_ZMIN_0 */
518	0x3f800000,
519	0x00000000,
520	0x3f800000,
521	0x00000000,
522	0x3f800000,
523	0x00000000,
524	0x3f800000,
525	0x00000000,
526	0x3f800000,
527	0x00000000,
528	0x3f800000,
529	0x00000000,
530	0x3f800000,
531	0x00000000,
532	0x3f800000,
533	0x00000000,
534	0x3f800000,
535	0x00000000,
536	0x3f800000,
537	0x00000000,
538	0x3f800000,
539	0x00000000,
540	0x3f800000,
541	0x00000000,
542	0x3f800000,
543	0x00000000,
544	0x3f800000,
545	0x00000000,
546	0x3f800000,
547	0x00000000,
548	0x3f800000,
549
550	0xc0026900,
551	0x00000292,
552	0x00000000, /* PA_SC_MPASS_PS_CNTL */
553	0x00514000, /* PA_SC_MODE_CNTL */
554
555	0xc0096900,
556	0x00000300,
557	0x00000000, /* PA_SC_LINE_CNTL */
558	0x00000000, /* PA_SC_AA_CONFIG */
559	0x0000002d, /* PA_SU_VTX_CNTL */
560	0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
561	0x3f800000,
562	0x3f800000,
563	0x3f800000,
564	0x00000000, /* PA_SC_SAMPLE_LOCS_MCTX */
565	0x00000000,
566
567	0xc0016900,
568	0x00000312,
569	0xffffffff, /* PA_SC_AA_MASK */
570
571	0xc0066900,
572	0x0000037e,
573	0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
574	0x00000000, /* PA_SU_POLY_OFFSET_CLAMP */
575	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_SCALE */
576	0x00000000, /* PA_SU_POLY_OFFSET_FRONT_OFFSET */
577	0x00000000, /* PA_SU_POLY_OFFSET_BACK_SCALE */
578	0x00000000, /* PA_SU_POLY_OFFSET_BACK_OFFSET */
579
580	0xc0046900,
581	0x000001b6,
582	0x00000000, /* SPI_INPUT_Z */
583	0x00000000, /* SPI_FOG_CNTL */
584	0x00000000, /* SPI_FOG_FUNC_SCALE */
585	0x00000000, /* SPI_FOG_FUNC_BIAS */
586
587	0xc0016900,
588	0x00000225,
589	0x00000000, /* SQ_PGM_START_FS */
590
591	0xc0016900,
592	0x00000229,
593	0x00000000, /* SQ_PGM_RESOURCES_FS */
594
595	0xc0016900,
596	0x00000237,
597	0x00000000, /* SQ_PGM_CF_OFFSET_FS */
598
599	0xc0026900,
600	0x000002a8,
601	0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
602	0x00000000, /* VGT_INSTANCE_STEP_RATE_1 */
603
604	0xc0116900,
605	0x00000280,
606	0x00000000, /* PA_SU_POINT_SIZE */
607	0x00000000, /* PA_SU_POINT_MINMAX */
608	0x00000008, /* PA_SU_LINE_CNTL */
609	0x00000000, /* PA_SC_LINE_STIPPLE */
610	0x00000000, /* VGT_OUTPUT_PATH_CNTL */
611	0x00000000, /* VGT_HOS_CNTL */
612	0x00000000, /* VGT_HOS_MAX_TESS_LEVEL */
613	0x00000000, /* VGT_HOS_MIN_TESS_LEVEL */
614	0x00000000, /* VGT_HOS_REUSE_DEPTH */
615	0x00000000, /* VGT_GROUP_PRIM_TYPE */
616	0x00000000, /* VGT_GROUP_FIRST_DECR */
617	0x00000000, /* VGT_GROUP_DECR */
618	0x00000000, /* VGT_GROUP_VECT_0_CNTL */
619	0x00000000, /* VGT_GROUP_VECT_1_CNTL */
620	0x00000000, /* VGT_GROUP_VECT_0_FMT_CNTL */
621	0x00000000, /* VGT_GROUP_VECT_1_FMT_CNTL */
622	0x00000000, /* VGT_GS_MODE */
623
624	0xc0016900,
625	0x000002a1,
626	0x00000000, /* VGT_PRIMITIVEID_EN */
627
628	0xc0016900,
629	0x000002a5,
630	0x00000000, /* VGT_MULTI_PRIM_ID_RESET_EN */
631
632	0xc0036900,
633	0x000002ac,
634	0x00000000, /* VGT_STRMOUT_EN */
635	0x00000000, /* VGT_REUSE_OFF */
636	0x00000000, /* VGT_VTX_CNT_EN */
637
638	0xc0016900,
639	0x000000d4,
640	0x00000000, /* SX_MISC */
641
642	0xc0016900,
643	0x000002c8,
644	0x00000000, /* VGT_STRMOUT_BUFFER_EN */
645
646	0xc0076900,
647	0x00000202,
648	0x00cc0000, /* CB_COLOR_CONTROL */
649	0x00000210, /* DB_SHADER_CNTL */
650	0x00010000, /* PA_CL_CLIP_CNTL */
651	0x00000244, /* PA_SU_SC_MODE_CNTL */
652	0x00000100, /* PA_CL_VTE_CNTL */
653	0x00000000, /* PA_CL_VS_OUT_CNTL */
654	0x00000000, /* PA_CL_NANINF_CNTL */
655
656	0xc0026900,
657	0x0000008e,
658	0x0000000f, /* CB_TARGET_MASK */
659	0x0000000f, /* CB_SHADER_MASK */
660
661	0xc0016900,
662	0x000001e8,
663	0x00000001, /* CB_SHADER_CONTROL */
664
665	0xc0016900,
666	0x00000185,
667	0x00000000, /* SPI_VS_OUT_ID_0 */
668
669	0xc0016900,
670	0x00000191,
671	0x00000b00, /* SPI_PS_INPUT_CNTL_0 */
672
673	0xc0056900,
674	0x000001b1,
675	0x00000000, /* SPI_VS_OUT_CONFIG */
676	0x00000001, /* SPI_THREAD_GROUPING */
677	0x00000001, /* SPI_PS_IN_CONTROL_0 */
678	0x00000000, /* SPI_PS_IN_CONTROL_1 */
679	0x00000000, /* SPI_INTERP_CONTROL_0 */
680
681	0xc0036e00, /* SET_SAMPLER */
682	0x00000000,
683	0x00000012,
684	0x00000000,
685	0x00000000,
686};
687
688/* same for r6xx/r7xx */
689const u32 r6xx_vs[] =
690{
691	0x00000004,
692	0x81000000,
693	0x0000203c,
694	0x94000b08,
695	0x00004000,
696	0x14200b1a,
697	0x00000000,
698	0x00000000,
699	0x3c000000,
700	0x68cd1000,
701#ifdef __BIG_ENDIAN
702	0x000a0000,
703#else
704	0x00080000,
705#endif
706	0x00000000,
707};
708
709const u32 r6xx_ps[] =
710{
711	0x00000002,
712	0x80800000,
713	0x00000000,
714	0x94200688,
715	0x00000010,
716	0x000d1000,
717	0xb0800000,
718	0x00000000,
719};
720
721const u32 r6xx_ps_size = ARRAY_SIZE(r6xx_ps);
722const u32 r6xx_vs_size = ARRAY_SIZE(r6xx_vs);
723const u32 r6xx_default_size = ARRAY_SIZE(r6xx_default_state);
724const u32 r7xx_default_size = ARRAY_SIZE(r7xx_default_state);
725