1/* $NetBSD: radeon_legacy_tv.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $ */ 2 3// SPDX-License-Identifier: MIT 4 5#include <sys/cdefs.h> 6__KERNEL_RCSID(0, "$NetBSD: radeon_legacy_tv.c,v 1.4 2021/12/18 23:45:43 riastradh Exp $"); 7 8#include <drm/drm_crtc_helper.h> 9#include <drm/drm_device.h> 10 11#include "radeon.h" 12 13/* 14 * Integrated TV out support based on the GATOS code by 15 * Federico Ulivi <fulivi@lycos.com> 16 */ 17 18 19/* 20 * Limits of h/v positions (hPos & vPos) 21 */ 22#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 23#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 24 25/* 26 * Unit for hPos (in TV clock periods) 27 */ 28#define H_POS_UNIT 10 29 30/* 31 * Indexes in h. code timing table for horizontal line position adjustment 32 */ 33#define H_TABLE_POS1 6 34#define H_TABLE_POS2 8 35 36/* 37 * Limits of hor. size (hSize) 38 */ 39#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 40 41/* tv standard constants */ 42#define NTSC_TV_CLOCK_T 233 43#define NTSC_TV_VFTOTAL 1 44#define NTSC_TV_LINES_PER_FRAME 525 45#define NTSC_TV_ZERO_H_SIZE 479166 46#define NTSC_TV_H_SIZE_UNIT 9478 47 48#define PAL_TV_CLOCK_T 188 49#define PAL_TV_VFTOTAL 3 50#define PAL_TV_LINES_PER_FRAME 625 51#define PAL_TV_ZERO_H_SIZE 473200 52#define PAL_TV_H_SIZE_UNIT 9360 53 54/* tv pll setting for 27 mhz ref clk */ 55#define NTSC_TV_PLL_M_27 22 56#define NTSC_TV_PLL_N_27 175 57#define NTSC_TV_PLL_P_27 5 58 59#define PAL_TV_PLL_M_27 113 60#define PAL_TV_PLL_N_27 668 61#define PAL_TV_PLL_P_27 3 62 63/* tv pll setting for 14 mhz ref clk */ 64#define NTSC_TV_PLL_M_14 33 65#define NTSC_TV_PLL_N_14 693 66#define NTSC_TV_PLL_P_14 7 67 68#define PAL_TV_PLL_M_14 19 69#define PAL_TV_PLL_N_14 353 70#define PAL_TV_PLL_P_14 5 71 72#define VERT_LEAD_IN_LINES 2 73#define FRAC_BITS 0xe 74#define FRAC_MASK 0x3fff 75 76struct radeon_tv_mode_constants { 77 uint16_t hor_resolution; 78 uint16_t ver_resolution; 79 enum radeon_tv_std standard; 80 uint16_t hor_total; 81 uint16_t ver_total; 82 uint16_t hor_start; 83 uint16_t hor_syncstart; 84 uint16_t ver_syncstart; 85 unsigned def_restart; 86 uint16_t crtcPLL_N; 87 uint8_t crtcPLL_M; 88 uint8_t crtcPLL_post_div; 89 unsigned pix_to_tv; 90}; 91 92static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 93 0x0007, 94 0x003f, 95 0x0263, 96 0x0a24, 97 0x2a6b, 98 0x0a36, 99 0x126d, /* H_TABLE_POS1 */ 100 0x1bfe, 101 0x1a8f, /* H_TABLE_POS2 */ 102 0x1ec7, 103 0x3863, 104 0x1bfe, 105 0x1bfe, 106 0x1a2a, 107 0x1e95, 108 0x0e31, 109 0x201b, 110 0 111}; 112 113static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 114 0x2001, 115 0x200d, 116 0x1006, 117 0x0c06, 118 0x1006, 119 0x1818, 120 0x21e3, 121 0x1006, 122 0x0c06, 123 0x1006, 124 0x1817, 125 0x21d4, 126 0x0002, 127 0 128}; 129 130static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 131 0x0007, 132 0x0058, 133 0x027c, 134 0x0a31, 135 0x2a77, 136 0x0a95, 137 0x124f, /* H_TABLE_POS1 */ 138 0x1bfe, 139 0x1b22, /* H_TABLE_POS2 */ 140 0x1ef9, 141 0x387c, 142 0x1bfe, 143 0x1bfe, 144 0x1b31, 145 0x1eb5, 146 0x0e43, 147 0x201b, 148 0 149}; 150 151static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 152 0x2001, 153 0x200c, 154 0x1005, 155 0x0c05, 156 0x1005, 157 0x1401, 158 0x1821, 159 0x2240, 160 0x1005, 161 0x0c05, 162 0x1005, 163 0x1401, 164 0x1822, 165 0x2230, 166 0x0002, 167 0 168}; 169 170/********************************************************************** 171 * 172 * availableModes 173 * 174 * Table of all allowed modes for tv output 175 * 176 **********************************************************************/ 177static const struct radeon_tv_mode_constants available_tv_modes[] = { 178 { /* NTSC timing for 27 Mhz ref clk */ 179 800, /* horResolution */ 180 600, /* verResolution */ 181 TV_STD_NTSC, /* standard */ 182 990, /* horTotal */ 183 740, /* verTotal */ 184 813, /* horStart */ 185 824, /* horSyncStart */ 186 632, /* verSyncStart */ 187 625592, /* defRestart */ 188 592, /* crtcPLL_N */ 189 91, /* crtcPLL_M */ 190 4, /* crtcPLL_postDiv */ 191 1022, /* pixToTV */ 192 }, 193 { /* PAL timing for 27 Mhz ref clk */ 194 800, /* horResolution */ 195 600, /* verResolution */ 196 TV_STD_PAL, /* standard */ 197 1144, /* horTotal */ 198 706, /* verTotal */ 199 812, /* horStart */ 200 824, /* horSyncStart */ 201 669, /* verSyncStart */ 202 696700, /* defRestart */ 203 1382, /* crtcPLL_N */ 204 231, /* crtcPLL_M */ 205 4, /* crtcPLL_postDiv */ 206 759, /* pixToTV */ 207 }, 208 { /* NTSC timing for 14 Mhz ref clk */ 209 800, /* horResolution */ 210 600, /* verResolution */ 211 TV_STD_NTSC, /* standard */ 212 1018, /* horTotal */ 213 727, /* verTotal */ 214 813, /* horStart */ 215 840, /* horSyncStart */ 216 633, /* verSyncStart */ 217 630627, /* defRestart */ 218 347, /* crtcPLL_N */ 219 14, /* crtcPLL_M */ 220 8, /* crtcPLL_postDiv */ 221 1022, /* pixToTV */ 222 }, 223 { /* PAL timing for 14 Mhz ref clk */ 224 800, /* horResolution */ 225 600, /* verResolution */ 226 TV_STD_PAL, /* standard */ 227 1131, /* horTotal */ 228 742, /* verTotal */ 229 813, /* horStart */ 230 840, /* horSyncStart */ 231 633, /* verSyncStart */ 232 708369, /* defRestart */ 233 211, /* crtcPLL_N */ 234 9, /* crtcPLL_M */ 235 8, /* crtcPLL_postDiv */ 236 759, /* pixToTV */ 237 }, 238}; 239 240#define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) 241 242static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 243 uint16_t *pll_ref_freq) 244{ 245 struct drm_device *dev = radeon_encoder->base.dev; 246 struct radeon_device *rdev = dev->dev_private; 247 struct radeon_crtc *radeon_crtc; 248 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 249 const struct radeon_tv_mode_constants *const_ptr; 250 struct radeon_pll *pll; 251 252 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 253 if (radeon_crtc->crtc_id == 1) 254 pll = &rdev->clock.p2pll; 255 else 256 pll = &rdev->clock.p1pll; 257 258 if (pll_ref_freq) 259 *pll_ref_freq = pll->reference_freq; 260 261 if (tv_dac->tv_std == TV_STD_NTSC || 262 tv_dac->tv_std == TV_STD_NTSC_J || 263 tv_dac->tv_std == TV_STD_PAL_M) { 264 if (pll->reference_freq == 2700) 265 const_ptr = &available_tv_modes[0]; 266 else 267 const_ptr = &available_tv_modes[2]; 268 } else { 269 if (pll->reference_freq == 2700) 270 const_ptr = &available_tv_modes[1]; 271 else 272 const_ptr = &available_tv_modes[3]; 273 } 274 return const_ptr; 275} 276 277static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 278static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 279static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 280static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 281 282static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 283 unsigned n_wait_loops, unsigned cnt_threshold) 284{ 285 struct drm_device *dev = encoder->dev; 286 struct radeon_device *rdev = dev->dev_private; 287 uint32_t save_pll_test; 288 unsigned int i, j; 289 290 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 291 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 292 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 293 294 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 295 for (i = 0; i < n_tests; i++) { 296 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 297 for (j = 0; j < n_wait_loops; j++) 298 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 299 break; 300 } 301 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 302 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 303} 304 305 306static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 307 uint16_t addr, uint32_t value) 308{ 309 struct drm_device *dev = radeon_encoder->base.dev; 310 struct radeon_device *rdev = dev->dev_private; 311 uint32_t tmp; 312 int i = 0; 313 314 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 315 316 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 317 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 318 319 do { 320 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 321 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 322 break; 323 i++; 324 } while (i < 10000); 325 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 326} 327 328#if 0 /* included for completeness */ 329static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 330{ 331 struct drm_device *dev = radeon_encoder->base.dev; 332 struct radeon_device *rdev = dev->dev_private; 333 uint32_t tmp; 334 int i = 0; 335 336 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 337 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 338 339 do { 340 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 341 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 342 break; 343 i++; 344 } while (i < 10000); 345 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 346 return RREG32(RADEON_TV_HOST_READ_DATA); 347} 348#endif 349 350static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 351{ 352 uint16_t h_table; 353 354 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 355 case 0: 356 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 357 break; 358 case 1: 359 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 360 break; 361 case 2: 362 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 363 break; 364 default: 365 h_table = 0; 366 break; 367 } 368 return h_table; 369} 370 371static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 372{ 373 uint16_t v_table; 374 375 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 376 case 0: 377 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 378 break; 379 case 1: 380 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 381 break; 382 case 2: 383 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 384 break; 385 default: 386 v_table = 0; 387 break; 388 } 389 return v_table; 390} 391 392static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 393{ 394 struct drm_device *dev = radeon_encoder->base.dev; 395 struct radeon_device *rdev = dev->dev_private; 396 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 397 uint16_t h_table, v_table; 398 uint32_t tmp; 399 int i; 400 401 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 402 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 403 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 404 405 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 406 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 407 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 408 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 409 break; 410 } 411 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 412 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 413 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 414 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 415 break; 416 } 417} 418 419static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 420{ 421 struct drm_device *dev = radeon_encoder->base.dev; 422 struct radeon_device *rdev = dev->dev_private; 423 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 424 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 425 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 426 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 427} 428 429static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 430{ 431 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 432 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 433 int restart; 434 unsigned int h_total, v_total, f_total; 435 int v_offset, h_offset; 436 u16 p1, p2, h_inc; 437 bool h_changed; 438 const struct radeon_tv_mode_constants *const_ptr; 439 440 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 441 if (!const_ptr) 442 return false; 443 444 h_total = const_ptr->hor_total; 445 v_total = const_ptr->ver_total; 446 447 if (tv_dac->tv_std == TV_STD_NTSC || 448 tv_dac->tv_std == TV_STD_NTSC_J || 449 tv_dac->tv_std == TV_STD_PAL_M || 450 tv_dac->tv_std == TV_STD_PAL_60) 451 f_total = NTSC_TV_VFTOTAL + 1; 452 else 453 f_total = PAL_TV_VFTOTAL + 1; 454 455 /* adjust positions 1&2 in hor. cod timing table */ 456 h_offset = tv_dac->h_pos * H_POS_UNIT; 457 458 if (tv_dac->tv_std == TV_STD_NTSC || 459 tv_dac->tv_std == TV_STD_NTSC_J || 460 tv_dac->tv_std == TV_STD_PAL_M) { 461 h_offset -= 50; 462 p1 = hor_timing_NTSC[H_TABLE_POS1]; 463 p2 = hor_timing_NTSC[H_TABLE_POS2]; 464 } else { 465 p1 = hor_timing_PAL[H_TABLE_POS1]; 466 p2 = hor_timing_PAL[H_TABLE_POS2]; 467 } 468 469 p1 = (u16)((int)p1 + h_offset); 470 p2 = (u16)((int)p2 - h_offset); 471 472 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 473 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 474 475 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 476 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 477 478 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 479 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 480 481 /* adjust restart */ 482 restart = const_ptr->def_restart; 483 484 /* 485 * convert v_pos TV lines to n. of CRTC pixels 486 */ 487 if (tv_dac->tv_std == TV_STD_NTSC || 488 tv_dac->tv_std == TV_STD_NTSC_J || 489 tv_dac->tv_std == TV_STD_PAL_M || 490 tv_dac->tv_std == TV_STD_PAL_60) 491 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 492 else 493 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 494 495 restart -= v_offset + h_offset; 496 497 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 498 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 499 500 tv_dac->tv.hrestart = restart % h_total; 501 restart /= h_total; 502 tv_dac->tv.vrestart = restart % v_total; 503 restart /= v_total; 504 tv_dac->tv.frestart = restart % f_total; 505 506 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 507 (unsigned)tv_dac->tv.frestart, 508 (unsigned)tv_dac->tv.vrestart, 509 (unsigned)tv_dac->tv.hrestart); 510 511 /* compute h_inc from hsize */ 512 if (tv_dac->tv_std == TV_STD_NTSC || 513 tv_dac->tv_std == TV_STD_NTSC_J || 514 tv_dac->tv_std == TV_STD_PAL_M) 515 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 516 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 517 else 518 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 519 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 520 521 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 522 ((u32)h_inc << RADEON_H_INC_SHIFT); 523 524 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 525 526 return h_changed; 527} 528 529void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 530 struct drm_display_mode *mode, 531 struct drm_display_mode *adjusted_mode) 532{ 533 struct drm_device *dev = encoder->dev; 534 struct radeon_device *rdev = dev->dev_private; 535 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 536 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 537 const struct radeon_tv_mode_constants *const_ptr; 538 struct radeon_crtc *radeon_crtc; 539 int i; 540 uint16_t pll_ref_freq; 541 uint32_t vert_space, flicker_removal, tmp; 542 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 543 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 544 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 545 uint32_t tv_pll_cntl, tv_ftotal; 546 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 547 uint32_t m, n, p; 548 const uint16_t *hor_timing; 549 const uint16_t *vert_timing; 550 551 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 552 if (!const_ptr) 553 return; 554 555 radeon_crtc = to_radeon_crtc(encoder->crtc); 556 557 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 558 RADEON_CRT_FIFO_CE_EN | 559 RADEON_TV_FIFO_CE_EN | 560 RADEON_TV_ON); 561 562 if (!ASIC_IS_R300(rdev)) 563 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 564 565 if (tv_dac->tv_std == TV_STD_NTSC || 566 tv_dac->tv_std == TV_STD_NTSC_J) 567 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 568 569 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 570 RADEON_SYNC_TIP_LEVEL | 571 RADEON_YFLT_EN | 572 RADEON_UVFLT_EN | 573 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 574 575 if (tv_dac->tv_std == TV_STD_NTSC || 576 tv_dac->tv_std == TV_STD_NTSC_J) { 577 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 578 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 579 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 580 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 581 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 582 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 583 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 584 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 585 } else { 586 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 587 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 588 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 589 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 590 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 591 } 592 593 594 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 595 | RADEON_TVOUT_SCALE_EN 596 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 597 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 598 | RADEON_RGB_ATTEN_SEL(0x3) 599 | RADEON_RGB_ATTEN_VAL(0xc)); 600 601 if (radeon_crtc->crtc_id == 1) 602 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 603 else { 604 if (radeon_crtc->rmx_type != RMX_OFF) 605 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 606 else 607 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 608 } 609 610 if (tv_dac->tv_std == TV_STD_NTSC || 611 tv_dac->tv_std == TV_STD_NTSC_J || 612 tv_dac->tv_std == TV_STD_PAL_M || 613 tv_dac->tv_std == TV_STD_PAL_60) 614 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 615 else 616 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 617 618 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 619 tmp &= 0xe3ff0000; 620 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 621 tv_vscaler_cntl1 = tmp; 622 623 if (pll_ref_freq == 2700) 624 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 625 626 if (const_ptr->hor_resolution == 1024) 627 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 628 else 629 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 630 631 /* scale up for int divide */ 632 tmp = const_ptr->ver_total * 2 * 1000; 633 if (tv_dac->tv_std == TV_STD_NTSC || 634 tv_dac->tv_std == TV_STD_NTSC_J || 635 tv_dac->tv_std == TV_STD_PAL_M || 636 tv_dac->tv_std == TV_STD_PAL_60) { 637 tmp /= NTSC_TV_LINES_PER_FRAME; 638 } else { 639 tmp /= PAL_TV_LINES_PER_FRAME; 640 } 641 flicker_removal = (tmp + 500) / 1000; 642 643 if (flicker_removal < 3) 644 flicker_removal = 3; 645 for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) { 646 if (flicker_removal == SLOPE_limit[i]) 647 break; 648 } 649 650 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 651 5001) / 10000 / 8 | ((SLOPE_value[i] * 652 (1 << (FRAC_BITS - 1)) / 8) << 16); 653 tv_y_fall_cntl = 654 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 655 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 656 1024; 657 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 658 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 659 660 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 661 tv_vscaler_cntl2 |= (0x10 << 24) | 662 RADEON_DITHER_MODE | 663 RADEON_Y_OUTPUT_DITHER_EN | 664 RADEON_UV_OUTPUT_DITHER_EN | 665 RADEON_UV_TO_BUF_DITHER_EN; 666 667 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 668 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 669 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 670 tv_dac->tv.timing_cntl = tmp; 671 672 if (tv_dac->tv_std == TV_STD_NTSC || 673 tv_dac->tv_std == TV_STD_NTSC_J || 674 tv_dac->tv_std == TV_STD_PAL_M || 675 tv_dac->tv_std == TV_STD_PAL_60) 676 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 677 else 678 tv_dac_cntl = tv_dac->pal_tvdac_adj; 679 680 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 681 682 if (tv_dac->tv_std == TV_STD_NTSC || 683 tv_dac->tv_std == TV_STD_NTSC_J) 684 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 685 else 686 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 687 688 if (tv_dac->tv_std == TV_STD_NTSC || 689 tv_dac->tv_std == TV_STD_NTSC_J) { 690 if (pll_ref_freq == 2700) { 691 m = NTSC_TV_PLL_M_27; 692 n = NTSC_TV_PLL_N_27; 693 p = NTSC_TV_PLL_P_27; 694 } else { 695 m = NTSC_TV_PLL_M_14; 696 n = NTSC_TV_PLL_N_14; 697 p = NTSC_TV_PLL_P_14; 698 } 699 } else { 700 if (pll_ref_freq == 2700) { 701 m = PAL_TV_PLL_M_27; 702 n = PAL_TV_PLL_N_27; 703 p = PAL_TV_PLL_P_27; 704 } else { 705 m = PAL_TV_PLL_M_14; 706 n = PAL_TV_PLL_N_14; 707 p = PAL_TV_PLL_P_14; 708 } 709 } 710 711 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 712 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 713 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 714 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 715 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 716 717 tv_dac->tv.tv_uv_adr = 0xc8; 718 719 if (tv_dac->tv_std == TV_STD_NTSC || 720 tv_dac->tv_std == TV_STD_NTSC_J || 721 tv_dac->tv_std == TV_STD_PAL_M || 722 tv_dac->tv_std == TV_STD_PAL_60) { 723 tv_ftotal = NTSC_TV_VFTOTAL; 724 hor_timing = hor_timing_NTSC; 725 vert_timing = vert_timing_NTSC; 726 } else { 727 hor_timing = hor_timing_PAL; 728 vert_timing = vert_timing_PAL; 729 tv_ftotal = PAL_TV_VFTOTAL; 730 } 731 732 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 733 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 734 break; 735 } 736 737 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 738 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 739 break; 740 } 741 742 radeon_legacy_tv_init_restarts(encoder); 743 744 /* play with DAC_CNTL */ 745 /* play with GPIOPAD_A */ 746 /* DISP_OUTPUT_CNTL */ 747 /* use reference freq */ 748 749 /* program the TV registers */ 750 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 751 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 752 753 tmp = RREG32(RADEON_TV_DAC_CNTL); 754 tmp &= ~RADEON_TV_DAC_NBLANK; 755 tmp |= RADEON_TV_DAC_BGSLEEP | 756 RADEON_TV_DAC_RDACPD | 757 RADEON_TV_DAC_GDACPD | 758 RADEON_TV_DAC_BDACPD; 759 WREG32(RADEON_TV_DAC_CNTL, tmp); 760 761 /* TV PLL */ 762 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 763 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 764 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 765 766 radeon_wait_pll_lock(encoder, 200, 800, 135); 767 768 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 769 770 radeon_wait_pll_lock(encoder, 300, 160, 27); 771 radeon_wait_pll_lock(encoder, 200, 800, 135); 772 773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 774 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 775 776 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 777 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 778 779 /* TV HV */ 780 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 781 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 782 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 783 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 784 785 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 786 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 787 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 788 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 789 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 790 791 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 792 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 793 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 794 795 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 796 RADEON_CRT_ASYNC_RST)); 797 798 /* TV restarts */ 799 radeon_legacy_write_tv_restarts(radeon_encoder); 800 801 /* tv timings */ 802 radeon_restore_tv_timing_tables(radeon_encoder); 803 804 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 805 806 /* tv std */ 807 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 808 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 809 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 810 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 811 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 812 RADEON_C_GRN_EN | 813 RADEON_CMP_BLU_EN | 814 RADEON_DAC_DITHER_EN)); 815 816 WREG32(RADEON_TV_CRC_CNTL, 0); 817 818 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 819 820 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 821 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 822 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 823 (0x100 << RADEON_Y_GAIN_SHIFT))); 824 825 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 826 827} 828 829void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 830 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 831 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 832{ 833 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 834 const struct radeon_tv_mode_constants *const_ptr; 835 uint32_t tmp; 836 837 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 838 if (!const_ptr) 839 return; 840 841 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 842 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 843 844 tmp = *h_sync_strt_wid; 845 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 846 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 847 (const_ptr->hor_syncstart & 7); 848 *h_sync_strt_wid = tmp; 849 850 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 851 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 852 853 tmp = *v_sync_strt_wid; 854 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 855 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 856 *v_sync_strt_wid = tmp; 857} 858 859static int get_post_div(int value) 860{ 861 int post_div; 862 switch (value) { 863 case 1: post_div = 0; break; 864 case 2: post_div = 1; break; 865 case 3: post_div = 4; break; 866 case 4: post_div = 2; break; 867 case 6: post_div = 6; break; 868 case 8: post_div = 3; break; 869 case 12: post_div = 7; break; 870 case 16: 871 default: post_div = 5; break; 872 } 873 return post_div; 874} 875 876void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 877 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 878 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 879{ 880 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 881 const struct radeon_tv_mode_constants *const_ptr; 882 883 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 884 if (!const_ptr) 885 return; 886 887 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 888 889 *ppll_ref_div = const_ptr->crtcPLL_M; 890 891 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 892 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 893 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 894} 895 896void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 897 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 898 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 899{ 900 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 901 const struct radeon_tv_mode_constants *const_ptr; 902 903 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 904 if (!const_ptr) 905 return; 906 907 *htotal2_cntl = (const_ptr->hor_total & 0x7); 908 909 *p2pll_ref_div = const_ptr->crtcPLL_M; 910 911 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 912 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 913 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 914} 915 916