radeon_device.c revision 1.4
1/* $NetBSD: radeon_device.c,v 1.4 2018/08/27 04:58:36 riastradh Exp $ */ 2 3/* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30#include <sys/cdefs.h> 31__KERNEL_RCSID(0, "$NetBSD: radeon_device.c,v 1.4 2018/08/27 04:58:36 riastradh Exp $"); 32 33#include <linux/console.h> 34#include <linux/slab.h> 35#include <drm/drmP.h> 36#include <drm/drm_crtc_helper.h> 37#include <drm/radeon_drm.h> 38#include <linux/vgaarb.h> 39#include <linux/vga_switcheroo.h> 40#include <linux/efi.h> 41#include <linux/bitops.h> 42#include "radeon_reg.h" 43#include "radeon.h" 44#include "atom.h" 45 46static const char radeon_family_name[][16] = { 47 "R100", 48 "RV100", 49 "RS100", 50 "RV200", 51 "RS200", 52 "R200", 53 "RV250", 54 "RS300", 55 "RV280", 56 "R300", 57 "R350", 58 "RV350", 59 "RV380", 60 "R420", 61 "R423", 62 "RV410", 63 "RS400", 64 "RS480", 65 "RS600", 66 "RS690", 67 "RS740", 68 "RV515", 69 "R520", 70 "RV530", 71 "RV560", 72 "RV570", 73 "R580", 74 "R600", 75 "RV610", 76 "RV630", 77 "RV670", 78 "RV620", 79 "RV635", 80 "RS780", 81 "RS880", 82 "RV770", 83 "RV730", 84 "RV710", 85 "RV740", 86 "CEDAR", 87 "REDWOOD", 88 "JUNIPER", 89 "CYPRESS", 90 "HEMLOCK", 91 "PALM", 92 "SUMO", 93 "SUMO2", 94 "BARTS", 95 "TURKS", 96 "CAICOS", 97 "CAYMAN", 98 "ARUBA", 99 "TAHITI", 100 "PITCAIRN", 101 "VERDE", 102 "OLAND", 103 "HAINAN", 104 "BONAIRE", 105 "KAVERI", 106 "KABINI", 107 "HAWAII", 108 "MULLINS", 109 "LAST", 110}; 111 112#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0) 113#define RADEON_PX_QUIRK_LONG_WAKEUP (1 << 1) 114 115struct radeon_px_quirk { 116 u32 chip_vendor; 117 u32 chip_device; 118 u32 subsys_vendor; 119 u32 subsys_device; 120 u32 px_quirk_flags; 121}; 122 123static struct radeon_px_quirk radeon_px_quirk_list[] = { 124 /* Acer aspire 5560g (CPU: AMD A4-3305M; GPU: AMD Radeon HD 6480g + 7470m) 125 * https://bugzilla.kernel.org/show_bug.cgi?id=74551 126 */ 127 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX }, 128 /* Asus K73TA laptop with AMD A6-3400M APU and Radeon 6550 GPU 129 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 130 */ 131 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX }, 132 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 133 * https://bugzilla.kernel.org/show_bug.cgi?id=51381 134 */ 135 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 136 /* Asus K53TK laptop with AMD A6-3420M APU and Radeon 7670m GPU 137 * https://bugs.freedesktop.org/show_bug.cgi?id=101491 138 */ 139 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX }, 140 /* macbook pro 8.2 */ 141 { PCI_VENDOR_ID_ATI, 0x6741, PCI_VENDOR_ID_APPLE, 0x00e2, RADEON_PX_QUIRK_LONG_WAKEUP }, 142 { 0, 0, 0, 0, 0 }, 143}; 144 145bool radeon_is_px(struct drm_device *dev) 146{ 147 struct radeon_device *rdev = dev->dev_private; 148 149 if (rdev->flags & RADEON_IS_PX) 150 return true; 151 return false; 152} 153 154static void radeon_device_handle_px_quirks(struct radeon_device *rdev) 155{ 156 struct radeon_px_quirk *p = radeon_px_quirk_list; 157 158 /* Apply PX quirks */ 159 while (p && p->chip_device != 0) { 160 if (rdev->pdev->vendor == p->chip_vendor && 161 rdev->pdev->device == p->chip_device && 162 rdev->pdev->subsystem_vendor == p->subsys_vendor && 163 rdev->pdev->subsystem_device == p->subsys_device) { 164 rdev->px_quirk_flags = p->px_quirk_flags; 165 break; 166 } 167 ++p; 168 } 169 170 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX) 171 rdev->flags &= ~RADEON_IS_PX; 172} 173 174/** 175 * radeon_program_register_sequence - program an array of registers. 176 * 177 * @rdev: radeon_device pointer 178 * @registers: pointer to the register array 179 * @array_size: size of the register array 180 * 181 * Programs an array or registers with and and or masks. 182 * This is a helper for setting golden registers. 183 */ 184void radeon_program_register_sequence(struct radeon_device *rdev, 185 const u32 *registers, 186 const u32 array_size) 187{ 188 u32 tmp, reg, and_mask, or_mask; 189 int i; 190 191 if (array_size % 3) 192 return; 193 194 for (i = 0; i < array_size; i +=3) { 195 reg = registers[i + 0]; 196 and_mask = registers[i + 1]; 197 or_mask = registers[i + 2]; 198 199 if (and_mask == 0xffffffff) { 200 tmp = or_mask; 201 } else { 202 tmp = RREG32(reg); 203 tmp &= ~and_mask; 204 tmp |= or_mask; 205 } 206 WREG32(reg, tmp); 207 } 208} 209 210void radeon_pci_config_reset(struct radeon_device *rdev) 211{ 212 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA); 213} 214 215/** 216 * radeon_surface_init - Clear GPU surface registers. 217 * 218 * @rdev: radeon_device pointer 219 * 220 * Clear GPU surface registers (r1xx-r5xx). 221 */ 222void radeon_surface_init(struct radeon_device *rdev) 223{ 224 /* FIXME: check this out */ 225 if (rdev->family < CHIP_R600) { 226 int i; 227 228 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 229 if (rdev->surface_regs[i].bo) 230 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo); 231 else 232 radeon_clear_surface_reg(rdev, i); 233 } 234 /* enable surfaces */ 235 WREG32(RADEON_SURFACE_CNTL, 0); 236 } 237} 238 239/* 240 * GPU scratch registers helpers function. 241 */ 242/** 243 * radeon_scratch_init - Init scratch register driver information. 244 * 245 * @rdev: radeon_device pointer 246 * 247 * Init CP scratch register driver information (r1xx-r5xx) 248 */ 249void radeon_scratch_init(struct radeon_device *rdev) 250{ 251 int i; 252 253 /* FIXME: check this out */ 254 if (rdev->family < CHIP_R300) { 255 rdev->scratch.num_reg = 5; 256 } else { 257 rdev->scratch.num_reg = 7; 258 } 259 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; 260 for (i = 0; i < rdev->scratch.num_reg; i++) { 261 rdev->scratch.free[i] = true; 262 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); 263 } 264} 265 266/** 267 * radeon_scratch_get - Allocate a scratch register 268 * 269 * @rdev: radeon_device pointer 270 * @reg: scratch register mmio offset 271 * 272 * Allocate a CP scratch register for use by the driver (all asics). 273 * Returns 0 on success or -EINVAL on failure. 274 */ 275int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) 276{ 277 int i; 278 279 for (i = 0; i < rdev->scratch.num_reg; i++) { 280 if (rdev->scratch.free[i]) { 281 rdev->scratch.free[i] = false; 282 *reg = rdev->scratch.reg[i]; 283 return 0; 284 } 285 } 286 return -EINVAL; 287} 288 289/** 290 * radeon_scratch_free - Free a scratch register 291 * 292 * @rdev: radeon_device pointer 293 * @reg: scratch register mmio offset 294 * 295 * Free a CP scratch register allocated for use by the driver (all asics) 296 */ 297void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) 298{ 299 int i; 300 301 for (i = 0; i < rdev->scratch.num_reg; i++) { 302 if (rdev->scratch.reg[i] == reg) { 303 rdev->scratch.free[i] = true; 304 return; 305 } 306 } 307} 308 309/* 310 * GPU doorbell aperture helpers function. 311 */ 312/** 313 * radeon_doorbell_init - Init doorbell driver information. 314 * 315 * @rdev: radeon_device pointer 316 * 317 * Init doorbell driver information (CIK) 318 * Returns 0 on success, error on failure. 319 */ 320static int radeon_doorbell_init(struct radeon_device *rdev) 321{ 322#ifdef __NetBSD__ 323 int r; 324#endif 325 326 /* doorbell bar mapping */ 327 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2); 328 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2); 329 330 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS); 331 if (rdev->doorbell.num_doorbells == 0) 332 return -EINVAL; 333 334#ifdef __NetBSD__ 335 /* XXX errno NetBSD->Linux */ 336 rdev->doorbell.bst = rdev->pdev->pd_pa.pa_memt; 337 r = -bus_space_map(rdev->doorbell.bst, rdev->doorbell.base, 338 (rdev->doorbell.num_doorbells * sizeof(uint32_t)), 339 0, &rdev->doorbell.bsh); 340 if (r) 341 return r; 342#else 343 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32)); 344 if (rdev->doorbell.ptr == NULL) { 345 return -ENOMEM; 346 } 347#endif 348 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base); 349 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size); 350 351 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used)); 352 353 return 0; 354} 355 356/** 357 * radeon_doorbell_fini - Tear down doorbell driver information. 358 * 359 * @rdev: radeon_device pointer 360 * 361 * Tear down doorbell driver information (CIK) 362 */ 363static void radeon_doorbell_fini(struct radeon_device *rdev) 364{ 365#ifdef __NetBSD__ 366 bus_space_unmap(rdev->doorbell.bst, rdev->doorbell.bsh, 367 (rdev->doorbell.num_doorbells * sizeof(uint32_t))); 368#else 369 iounmap(rdev->doorbell.ptr); 370 rdev->doorbell.ptr = NULL; 371#endif 372} 373 374/** 375 * radeon_doorbell_get - Allocate a doorbell entry 376 * 377 * @rdev: radeon_device pointer 378 * @doorbell: doorbell index 379 * 380 * Allocate a doorbell for use by the driver (all asics). 381 * Returns 0 on success or -EINVAL on failure. 382 */ 383int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell) 384{ 385 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells); 386 if (offset < rdev->doorbell.num_doorbells) { 387 __set_bit(offset, rdev->doorbell.used); 388 *doorbell = offset; 389 return 0; 390 } else { 391 return -EINVAL; 392 } 393} 394 395/** 396 * radeon_doorbell_free - Free a doorbell entry 397 * 398 * @rdev: radeon_device pointer 399 * @doorbell: doorbell index 400 * 401 * Free a doorbell allocated for use by the driver (all asics) 402 */ 403void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell) 404{ 405 if (doorbell < rdev->doorbell.num_doorbells) 406 __clear_bit(doorbell, rdev->doorbell.used); 407} 408 409/** 410 * radeon_doorbell_get_kfd_info - Report doorbell configuration required to 411 * setup KFD 412 * 413 * @rdev: radeon_device pointer 414 * @aperture_base: output returning doorbell aperture base physical address 415 * @aperture_size: output returning doorbell aperture size in bytes 416 * @start_offset: output returning # of doorbell bytes reserved for radeon. 417 * 418 * Radeon and the KFD share the doorbell aperture. Radeon sets it up, 419 * takes doorbells required for its own rings and reports the setup to KFD. 420 * Radeon reserved doorbells are at the start of the doorbell aperture. 421 */ 422void radeon_doorbell_get_kfd_info(struct radeon_device *rdev, 423 phys_addr_t *aperture_base, 424 size_t *aperture_size, 425 size_t *start_offset) 426{ 427 /* The first num_doorbells are used by radeon. 428 * KFD takes whatever's left in the aperture. */ 429 if (rdev->doorbell.size > rdev->doorbell.num_doorbells * sizeof(u32)) { 430 *aperture_base = rdev->doorbell.base; 431 *aperture_size = rdev->doorbell.size; 432 *start_offset = rdev->doorbell.num_doorbells * sizeof(u32); 433 } else { 434 *aperture_base = 0; 435 *aperture_size = 0; 436 *start_offset = 0; 437 } 438} 439 440/* 441 * radeon_wb_*() 442 * Writeback is the the method by which the the GPU updates special pages 443 * in memory with the status of certain GPU events (fences, ring pointers, 444 * etc.). 445 */ 446 447/** 448 * radeon_wb_disable - Disable Writeback 449 * 450 * @rdev: radeon_device pointer 451 * 452 * Disables Writeback (all asics). Used for suspend. 453 */ 454void radeon_wb_disable(struct radeon_device *rdev) 455{ 456 rdev->wb.enabled = false; 457} 458 459/** 460 * radeon_wb_fini - Disable Writeback and free memory 461 * 462 * @rdev: radeon_device pointer 463 * 464 * Disables Writeback and frees the Writeback memory (all asics). 465 * Used at driver shutdown. 466 */ 467void radeon_wb_fini(struct radeon_device *rdev) 468{ 469 radeon_wb_disable(rdev); 470 if (rdev->wb.wb_obj) { 471 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) { 472 radeon_bo_kunmap(rdev->wb.wb_obj); 473 radeon_bo_unpin(rdev->wb.wb_obj); 474 radeon_bo_unreserve(rdev->wb.wb_obj); 475 } 476 radeon_bo_unref(&rdev->wb.wb_obj); 477 rdev->wb.wb = NULL; 478 rdev->wb.wb_obj = NULL; 479 } 480} 481 482/** 483 * radeon_wb_init- Init Writeback driver info and allocate memory 484 * 485 * @rdev: radeon_device pointer 486 * 487 * Disables Writeback and frees the Writeback memory (all asics). 488 * Used at driver startup. 489 * Returns 0 on success or an -error on failure. 490 */ 491int radeon_wb_init(struct radeon_device *rdev) 492{ 493 int r; 494 495 if (rdev->wb.wb_obj == NULL) { 496 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, 497 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL, 498 &rdev->wb.wb_obj); 499 if (r) { 500 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); 501 return r; 502 } 503 r = radeon_bo_reserve(rdev->wb.wb_obj, false); 504 if (unlikely(r != 0)) { 505 radeon_wb_fini(rdev); 506 return r; 507 } 508 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, 509 &rdev->wb.gpu_addr); 510 if (r) { 511 radeon_bo_unreserve(rdev->wb.wb_obj); 512 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); 513 radeon_wb_fini(rdev); 514 return r; 515 } 516 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)__UNVOLATILE(&rdev->wb.wb)); 517 radeon_bo_unreserve(rdev->wb.wb_obj); 518 if (r) { 519 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); 520 radeon_wb_fini(rdev); 521 return r; 522 } 523 } 524 525 /* clear wb memory */ 526 memset(__UNVOLATILE(rdev->wb.wb), 0, RADEON_GPU_PAGE_SIZE); 527 /* disable event_write fences */ 528 rdev->wb.use_event = false; 529 /* disabled via module param */ 530 if (radeon_no_wb == 1) { 531 rdev->wb.enabled = false; 532 } else { 533 if (rdev->flags & RADEON_IS_AGP) { 534 /* often unreliable on AGP */ 535 rdev->wb.enabled = false; 536 } else if (rdev->family < CHIP_R300) { 537 /* often unreliable on pre-r300 */ 538 rdev->wb.enabled = false; 539 } else { 540 rdev->wb.enabled = true; 541 /* event_write fences are only available on r600+ */ 542 if (rdev->family >= CHIP_R600) { 543 rdev->wb.use_event = true; 544 } 545 } 546 } 547 /* always use writeback/events on NI, APUs */ 548 if (rdev->family >= CHIP_PALM) { 549 rdev->wb.enabled = true; 550 rdev->wb.use_event = true; 551 } 552 553 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); 554 555 return 0; 556} 557 558/** 559 * radeon_vram_location - try to find VRAM location 560 * @rdev: radeon device structure holding all necessary informations 561 * @mc: memory controller structure holding memory informations 562 * @base: base address at which to put VRAM 563 * 564 * Function will place try to place VRAM at base address provided 565 * as parameter (which is so far either PCI aperture address or 566 * for IGP TOM base address). 567 * 568 * If there is not enough space to fit the unvisible VRAM in the 32bits 569 * address space then we limit the VRAM size to the aperture. 570 * 571 * If we are using AGP and if the AGP aperture doesn't allow us to have 572 * room for all the VRAM than we restrict the VRAM to the PCI aperture 573 * size and print a warning. 574 * 575 * This function will never fails, worst case are limiting VRAM. 576 * 577 * Note: GTT start, end, size should be initialized before calling this 578 * function on AGP platform. 579 * 580 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, 581 * this shouldn't be a problem as we are using the PCI aperture as a reference. 582 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but 583 * not IGP. 584 * 585 * Note: we use mc_vram_size as on some board we need to program the mc to 586 * cover the whole aperture even if VRAM size is inferior to aperture size 587 * Novell bug 204882 + along with lots of ubuntu ones 588 * 589 * Note: when limiting vram it's safe to overwritte real_vram_size because 590 * we are not in case where real_vram_size is inferior to mc_vram_size (ie 591 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu 592 * ones) 593 * 594 * Note: IGP TOM addr should be the same as the aperture addr, we don't 595 * explicitly check for that thought. 596 * 597 * FIXME: when reducing VRAM size align new size on power of 2. 598 */ 599void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) 600{ 601 uint64_t limit = (uint64_t)radeon_vram_limit << 20; 602 603 mc->vram_start = base; 604 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) { 605 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 606 mc->real_vram_size = mc->aper_size; 607 mc->mc_vram_size = mc->aper_size; 608 } 609 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 610 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { 611 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); 612 mc->real_vram_size = mc->aper_size; 613 mc->mc_vram_size = mc->aper_size; 614 } 615 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; 616 if (limit && limit < mc->real_vram_size) 617 mc->real_vram_size = limit; 618 dev_info(rdev->dev, "VRAM: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64" (%"PRIu64"M used)\n", 619 mc->mc_vram_size >> 20, mc->vram_start, 620 mc->vram_end, mc->real_vram_size >> 20); 621} 622 623/** 624 * radeon_gtt_location - try to find GTT location 625 * @rdev: radeon device structure holding all necessary informations 626 * @mc: memory controller structure holding memory informations 627 * 628 * Function will place try to place GTT before or after VRAM. 629 * 630 * If GTT size is bigger than space left then we ajust GTT size. 631 * Thus function will never fails. 632 * 633 * FIXME: when reducing GTT size align new size on power of 2. 634 */ 635void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) 636{ 637 u64 size_af, size_bf; 638 639 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; 640 size_bf = mc->vram_start & ~mc->gtt_base_align; 641 if (size_bf > size_af) { 642 if (mc->gtt_size > size_bf) { 643 dev_warn(rdev->dev, "limiting GTT\n"); 644 mc->gtt_size = size_bf; 645 } 646 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; 647 } else { 648 if (mc->gtt_size > size_af) { 649 dev_warn(rdev->dev, "limiting GTT\n"); 650 mc->gtt_size = size_af; 651 } 652 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; 653 } 654 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; 655 dev_info(rdev->dev, "GTT: %"PRIu64"M 0x%016"PRIX64" - 0x%016"PRIX64"\n", 656 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); 657} 658 659/* 660 * GPU helpers function. 661 */ 662 663/** 664 * radeon_device_is_virtual - check if we are running is a virtual environment 665 * 666 * Check if the asic has been passed through to a VM (all asics). 667 * Used at driver startup. 668 * Returns true if virtual or false if not. 669 */ 670static bool radeon_device_is_virtual(void) 671{ 672#ifdef CONFIG_X86 673 return boot_cpu_has(X86_FEATURE_HYPERVISOR); 674#else 675 return false; 676#endif 677} 678 679/** 680 * radeon_card_posted - check if the hw has already been initialized 681 * 682 * @rdev: radeon_device pointer 683 * 684 * Check if the asic has been initialized (all asics). 685 * Used at driver startup. 686 * Returns true if initialized or false if not. 687 */ 688bool radeon_card_posted(struct radeon_device *rdev) 689{ 690 uint32_t reg; 691 692 /* for pass through, always force asic_init for CI */ 693 if (rdev->family >= CHIP_BONAIRE && 694 radeon_device_is_virtual()) 695 return false; 696 697#ifndef __NetBSD__ /* XXX radeon efi */ 698 /* required for EFI mode on macbook2,1 which uses an r5xx asic */ 699 if (efi_enabled(EFI_BOOT) && 700 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) && 701 (rdev->family < CHIP_R600)) 702 return false; 703#endif 704 705 if (ASIC_IS_NODCE(rdev)) 706 goto check_memsize; 707 708 /* first check CRTCs */ 709 if (ASIC_IS_DCE4(rdev)) { 710 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 711 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 712 if (rdev->num_crtc >= 4) { 713 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 714 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 715 } 716 if (rdev->num_crtc >= 6) { 717 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 718 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 719 } 720 if (reg & EVERGREEN_CRTC_MASTER_EN) 721 return true; 722 } else if (ASIC_IS_AVIVO(rdev)) { 723 reg = RREG32(AVIVO_D1CRTC_CONTROL) | 724 RREG32(AVIVO_D2CRTC_CONTROL); 725 if (reg & AVIVO_CRTC_EN) { 726 return true; 727 } 728 } else { 729 reg = RREG32(RADEON_CRTC_GEN_CNTL) | 730 RREG32(RADEON_CRTC2_GEN_CNTL); 731 if (reg & RADEON_CRTC_EN) { 732 return true; 733 } 734 } 735 736check_memsize: 737 /* then check MEM_SIZE, in case the crtcs are off */ 738 if (rdev->family >= CHIP_R600) 739 reg = RREG32(R600_CONFIG_MEMSIZE); 740 else 741 reg = RREG32(RADEON_CONFIG_MEMSIZE); 742 743 if (reg) 744 return true; 745 746 return false; 747 748} 749 750/** 751 * radeon_update_bandwidth_info - update display bandwidth params 752 * 753 * @rdev: radeon_device pointer 754 * 755 * Used when sclk/mclk are switched or display modes are set. 756 * params are used to calculate display watermarks (all asics) 757 */ 758void radeon_update_bandwidth_info(struct radeon_device *rdev) 759{ 760 fixed20_12 a; 761 u32 sclk = rdev->pm.current_sclk; 762 u32 mclk = rdev->pm.current_mclk; 763 764 /* sclk/mclk in Mhz */ 765 a.full = dfixed_const(100); 766 rdev->pm.sclk.full = dfixed_const(sclk); 767 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); 768 rdev->pm.mclk.full = dfixed_const(mclk); 769 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); 770 771 if (rdev->flags & RADEON_IS_IGP) { 772 a.full = dfixed_const(16); 773 /* core_bandwidth = sclk(Mhz) * 16 */ 774 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); 775 } 776} 777 778/** 779 * radeon_boot_test_post_card - check and possibly initialize the hw 780 * 781 * @rdev: radeon_device pointer 782 * 783 * Check if the asic is initialized and if not, attempt to initialize 784 * it (all asics). 785 * Returns true if initialized or false if not. 786 */ 787bool radeon_boot_test_post_card(struct radeon_device *rdev) 788{ 789 if (radeon_card_posted(rdev)) 790 return true; 791 792 if (rdev->bios) { 793 DRM_INFO("GPU not posted. posting now...\n"); 794 if (rdev->is_atom_bios) 795 atom_asic_init(rdev->mode_info.atom_context); 796 else 797 radeon_combios_asic_init(rdev->ddev); 798 return true; 799 } else { 800 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); 801 return false; 802 } 803} 804 805/** 806 * radeon_dummy_page_init - init dummy page used by the driver 807 * 808 * @rdev: radeon_device pointer 809 * 810 * Allocate the dummy page used by the driver (all asics). 811 * This dummy page is used by the driver as a filler for gart entries 812 * when pages are taken out of the GART 813 * Returns 0 on sucess, -ENOMEM on failure. 814 */ 815int radeon_dummy_page_init(struct radeon_device *rdev) 816{ 817#ifdef __NetBSD__ 818 int rsegs; 819 int error; 820 821 /* XXX Can this be called more than once?? */ 822 if (rdev->dummy_page.rdp_map != NULL) 823 return 0; 824 825 error = bus_dmamem_alloc(rdev->ddev->dmat, PAGE_SIZE, PAGE_SIZE, 0, 826 &rdev->dummy_page.rdp_seg, 1, &rsegs, BUS_DMA_WAITOK); 827 if (error) 828 goto fail0; 829 KASSERT(rsegs == 1); 830 error = bus_dmamap_create(rdev->ddev->dmat, PAGE_SIZE, 1, PAGE_SIZE, 0, 831 BUS_DMA_WAITOK, &rdev->dummy_page.rdp_map); 832 if (error) 833 goto fail1; 834 error = bus_dmamap_load_raw(rdev->ddev->dmat, rdev->dummy_page.rdp_map, 835 &rdev->dummy_page.rdp_seg, 1, PAGE_SIZE, BUS_DMA_WAITOK); 836 if (error) 837 goto fail2; 838 839 /* Success! */ 840 rdev->dummy_page.addr = rdev->dummy_page.rdp_map->dm_segs[0].ds_addr; 841 rdev->dummy_page.entry = radeon_gart_get_page_entry( 842 rdev->dummy_page.addr, RADEON_GART_PAGE_DUMMY); 843 return 0; 844 845fail3: __unused 846 bus_dmamap_unload(rdev->ddev->dmat, rdev->dummy_page.rdp_map); 847fail2: bus_dmamap_destroy(rdev->ddev->dmat, rdev->dummy_page.rdp_map); 848fail1: bus_dmamem_free(rdev->ddev->dmat, &rdev->dummy_page.rdp_seg, 1); 849fail0: KASSERT(error); 850 rdev->dummy_page.rdp_map = NULL; 851 /* XXX errno NetBSD->Linux */ 852 return -error; 853#else 854 if (rdev->dummy_page.page) 855 return 0; 856 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO); 857 if (rdev->dummy_page.page == NULL) 858 return -ENOMEM; 859 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page, 860 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 861 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) { 862 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n"); 863 __free_page(rdev->dummy_page.page); 864 rdev->dummy_page.page = NULL; 865 return -ENOMEM; 866 } 867 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr, 868 RADEON_GART_PAGE_DUMMY); 869 return 0; 870#endif 871} 872 873/** 874 * radeon_dummy_page_fini - free dummy page used by the driver 875 * 876 * @rdev: radeon_device pointer 877 * 878 * Frees the dummy page used by the driver (all asics). 879 */ 880void radeon_dummy_page_fini(struct radeon_device *rdev) 881{ 882#ifdef __NetBSD__ 883 884 if (rdev->dummy_page.rdp_map == NULL) 885 return; 886 bus_dmamap_unload(rdev->ddev->dmat, rdev->dummy_page.rdp_map); 887 bus_dmamap_destroy(rdev->ddev->dmat, rdev->dummy_page.rdp_map); 888 bus_dmamem_free(rdev->ddev->dmat, &rdev->dummy_page.rdp_seg, 1); 889 rdev->dummy_page.rdp_map = NULL; 890#else 891 if (rdev->dummy_page.page == NULL) 892 return; 893 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr, 894 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 895 __free_page(rdev->dummy_page.page); 896 rdev->dummy_page.page = NULL; 897#endif 898} 899 900 901/* ATOM accessor methods */ 902/* 903 * ATOM is an interpreted byte code stored in tables in the vbios. The 904 * driver registers callbacks to access registers and the interpreter 905 * in the driver parses the tables and executes then to program specific 906 * actions (set display modes, asic init, etc.). See radeon_atombios.c, 907 * atombios.h, and atom.c 908 */ 909 910/** 911 * cail_pll_read - read PLL register 912 * 913 * @info: atom card_info pointer 914 * @reg: PLL register offset 915 * 916 * Provides a PLL register accessor for the atom interpreter (r4xx+). 917 * Returns the value of the PLL register. 918 */ 919static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 920{ 921 struct radeon_device *rdev = info->dev->dev_private; 922 uint32_t r; 923 924 r = rdev->pll_rreg(rdev, reg); 925 return r; 926} 927 928/** 929 * cail_pll_write - write PLL register 930 * 931 * @info: atom card_info pointer 932 * @reg: PLL register offset 933 * @val: value to write to the pll register 934 * 935 * Provides a PLL register accessor for the atom interpreter (r4xx+). 936 */ 937static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 938{ 939 struct radeon_device *rdev = info->dev->dev_private; 940 941 rdev->pll_wreg(rdev, reg, val); 942} 943 944/** 945 * cail_mc_read - read MC (Memory Controller) register 946 * 947 * @info: atom card_info pointer 948 * @reg: MC register offset 949 * 950 * Provides an MC register accessor for the atom interpreter (r4xx+). 951 * Returns the value of the MC register. 952 */ 953static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 954{ 955 struct radeon_device *rdev = info->dev->dev_private; 956 uint32_t r; 957 958 r = rdev->mc_rreg(rdev, reg); 959 return r; 960} 961 962/** 963 * cail_mc_write - write MC (Memory Controller) register 964 * 965 * @info: atom card_info pointer 966 * @reg: MC register offset 967 * @val: value to write to the pll register 968 * 969 * Provides a MC register accessor for the atom interpreter (r4xx+). 970 */ 971static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 972{ 973 struct radeon_device *rdev = info->dev->dev_private; 974 975 rdev->mc_wreg(rdev, reg, val); 976} 977 978/** 979 * cail_reg_write - write MMIO register 980 * 981 * @info: atom card_info pointer 982 * @reg: MMIO register offset 983 * @val: value to write to the pll register 984 * 985 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 986 */ 987static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 988{ 989 struct radeon_device *rdev = info->dev->dev_private; 990 991 WREG32(reg*4, val); 992} 993 994/** 995 * cail_reg_read - read MMIO register 996 * 997 * @info: atom card_info pointer 998 * @reg: MMIO register offset 999 * 1000 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 1001 * Returns the value of the MMIO register. 1002 */ 1003static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 1004{ 1005 struct radeon_device *rdev = info->dev->dev_private; 1006 uint32_t r; 1007 1008 r = RREG32(reg*4); 1009 return r; 1010} 1011 1012/** 1013 * cail_ioreg_write - write IO register 1014 * 1015 * @info: atom card_info pointer 1016 * @reg: IO register offset 1017 * @val: value to write to the pll register 1018 * 1019 * Provides a IO register accessor for the atom interpreter (r4xx+). 1020 */ 1021static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 1022{ 1023 struct radeon_device *rdev = info->dev->dev_private; 1024 1025 WREG32_IO(reg*4, val); 1026} 1027 1028/** 1029 * cail_ioreg_read - read IO register 1030 * 1031 * @info: atom card_info pointer 1032 * @reg: IO register offset 1033 * 1034 * Provides an IO register accessor for the atom interpreter (r4xx+). 1035 * Returns the value of the IO register. 1036 */ 1037static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 1038{ 1039 struct radeon_device *rdev = info->dev->dev_private; 1040 uint32_t r; 1041 1042 r = RREG32_IO(reg*4); 1043 return r; 1044} 1045 1046/** 1047 * radeon_atombios_init - init the driver info and callbacks for atombios 1048 * 1049 * @rdev: radeon_device pointer 1050 * 1051 * Initializes the driver info and register access callbacks for the 1052 * ATOM interpreter (r4xx+). 1053 * Returns 0 on sucess, -ENOMEM on failure. 1054 * Called at driver startup. 1055 */ 1056int radeon_atombios_init(struct radeon_device *rdev) 1057{ 1058 struct card_info *atom_card_info = 1059 kzalloc(sizeof(struct card_info), GFP_KERNEL); 1060 1061 if (!atom_card_info) 1062 return -ENOMEM; 1063 1064 rdev->mode_info.atom_card_info = atom_card_info; 1065 atom_card_info->dev = rdev->ddev; 1066 atom_card_info->reg_read = cail_reg_read; 1067 atom_card_info->reg_write = cail_reg_write; 1068 /* needed for iio ops */ 1069#ifdef __NetBSD__ 1070 if (rdev->rio_mem_size) 1071#else 1072 if (rdev->rio_mem) 1073#endif 1074 { 1075 atom_card_info->ioreg_read = cail_ioreg_read; 1076 atom_card_info->ioreg_write = cail_ioreg_write; 1077 } else { 1078 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); 1079 atom_card_info->ioreg_read = cail_reg_read; 1080 atom_card_info->ioreg_write = cail_reg_write; 1081 } 1082 atom_card_info->mc_read = cail_mc_read; 1083 atom_card_info->mc_write = cail_mc_write; 1084 atom_card_info->pll_read = cail_pll_read; 1085 atom_card_info->pll_write = cail_pll_write; 1086 1087 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); 1088 if (!rdev->mode_info.atom_context) { 1089 radeon_atombios_fini(rdev); 1090 return -ENOMEM; 1091 } 1092 1093#ifdef __NetBSD__ 1094 linux_mutex_init(&rdev->mode_info.atom_context->mutex); 1095 linux_mutex_init(&rdev->mode_info.atom_context->scratch_mutex); 1096#else 1097 mutex_init(&rdev->mode_info.atom_context->mutex); 1098 mutex_init(&rdev->mode_info.atom_context->scratch_mutex); 1099#endif 1100 radeon_atom_initialize_bios_scratch_regs(rdev->ddev); 1101 atom_allocate_fb_scratch(rdev->mode_info.atom_context); 1102 return 0; 1103} 1104 1105/** 1106 * radeon_atombios_fini - free the driver info and callbacks for atombios 1107 * 1108 * @rdev: radeon_device pointer 1109 * 1110 * Frees the driver info and register access callbacks for the ATOM 1111 * interpreter (r4xx+). 1112 * Called at driver shutdown. 1113 */ 1114void radeon_atombios_fini(struct radeon_device *rdev) 1115{ 1116 if (rdev->mode_info.atom_context) { 1117#ifdef __NetBSD__ 1118 linux_mutex_destroy(&rdev->mode_info.atom_context->scratch_mutex); 1119 linux_mutex_destroy(&rdev->mode_info.atom_context->mutex); 1120#else 1121 mutex_destroy(&rdev->mode_info.atom_context->scratch_mutex); 1122 mutex_destroy(&rdev->mode_info.atom_context->mutex); 1123#endif 1124 kfree(rdev->mode_info.atom_context->scratch); 1125 } 1126 kfree(rdev->mode_info.atom_context); 1127 rdev->mode_info.atom_context = NULL; 1128 kfree(rdev->mode_info.atom_card_info); 1129 rdev->mode_info.atom_card_info = NULL; 1130} 1131 1132/* COMBIOS */ 1133/* 1134 * COMBIOS is the bios format prior to ATOM. It provides 1135 * command tables similar to ATOM, but doesn't have a unified 1136 * parser. See radeon_combios.c 1137 */ 1138 1139/** 1140 * radeon_combios_init - init the driver info for combios 1141 * 1142 * @rdev: radeon_device pointer 1143 * 1144 * Initializes the driver info for combios (r1xx-r3xx). 1145 * Returns 0 on sucess. 1146 * Called at driver startup. 1147 */ 1148int radeon_combios_init(struct radeon_device *rdev) 1149{ 1150 radeon_combios_initialize_bios_scratch_regs(rdev->ddev); 1151 return 0; 1152} 1153 1154/** 1155 * radeon_combios_fini - free the driver info for combios 1156 * 1157 * @rdev: radeon_device pointer 1158 * 1159 * Frees the driver info for combios (r1xx-r3xx). 1160 * Called at driver shutdown. 1161 */ 1162void radeon_combios_fini(struct radeon_device *rdev) 1163{ 1164} 1165 1166#ifndef __NetBSD__ /* XXX radeon vga */ 1167/* if we get transitioned to only one device, take VGA back */ 1168/** 1169 * radeon_vga_set_decode - enable/disable vga decode 1170 * 1171 * @cookie: radeon_device pointer 1172 * @state: enable/disable vga decode 1173 * 1174 * Enable/disable vga decode (all asics). 1175 * Returns VGA resource flags. 1176 */ 1177static unsigned int radeon_vga_set_decode(void *cookie, bool state) 1178{ 1179 struct radeon_device *rdev = cookie; 1180 radeon_vga_set_state(rdev, state); 1181 if (state) 1182 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | 1183 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1184 else 1185 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; 1186} 1187#endif 1188 1189/** 1190 * radeon_check_pot_argument - check that argument is a power of two 1191 * 1192 * @arg: value to check 1193 * 1194 * Validates that a certain argument is a power of two (all asics). 1195 * Returns true if argument is valid. 1196 */ 1197static bool radeon_check_pot_argument(int arg) 1198{ 1199 return (arg & (arg - 1)) == 0; 1200} 1201 1202/** 1203 * Determine a sensible default GART size according to ASIC family. 1204 * 1205 * @family ASIC family name 1206 */ 1207static int radeon_gart_size_auto(enum radeon_family family) 1208{ 1209 /* default to a larger gart size on newer asics */ 1210 if (family >= CHIP_TAHITI) 1211 return 2048; 1212 else if (family >= CHIP_RV770) 1213 return 1024; 1214 else 1215 return 512; 1216} 1217 1218/** 1219 * radeon_check_arguments - validate module params 1220 * 1221 * @rdev: radeon_device pointer 1222 * 1223 * Validates certain module parameters and updates 1224 * the associated values used by the driver (all asics). 1225 */ 1226static void radeon_check_arguments(struct radeon_device *rdev) 1227{ 1228 /* vramlimit must be a power of two */ 1229 if (!radeon_check_pot_argument(radeon_vram_limit)) { 1230 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", 1231 radeon_vram_limit); 1232 radeon_vram_limit = 0; 1233 } 1234 1235 if (radeon_gart_size == -1) { 1236 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1237 } 1238 /* gtt size must be power of two and greater or equal to 32M */ 1239 if (radeon_gart_size < 32) { 1240 dev_warn(rdev->dev, "gart size (%d) too small\n", 1241 radeon_gart_size); 1242 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1243 } else if (!radeon_check_pot_argument(radeon_gart_size)) { 1244 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", 1245 radeon_gart_size); 1246 radeon_gart_size = radeon_gart_size_auto(rdev->family); 1247 } 1248 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; 1249 1250 /* AGP mode can only be -1, 1, 2, 4, 8 */ 1251 switch (radeon_agpmode) { 1252 case -1: 1253 case 0: 1254 case 1: 1255 case 2: 1256 case 4: 1257 case 8: 1258 break; 1259 default: 1260 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " 1261 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); 1262 radeon_agpmode = 0; 1263 break; 1264 } 1265 1266 if (!radeon_check_pot_argument(radeon_vm_size)) { 1267 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n", 1268 radeon_vm_size); 1269 radeon_vm_size = 4; 1270 } 1271 1272 if (radeon_vm_size < 1) { 1273 dev_warn(rdev->dev, "VM size (%d) to small, min is 1GB\n", 1274 radeon_vm_size); 1275 radeon_vm_size = 4; 1276 } 1277 1278 /* 1279 * Max GPUVM size for Cayman, SI and CI are 40 bits. 1280 */ 1281 if (radeon_vm_size > 1024) { 1282 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n", 1283 radeon_vm_size); 1284 radeon_vm_size = 4; 1285 } 1286 1287 /* defines number of bits in page table versus page directory, 1288 * a page is 4KB so we have 12 bits offset, minimum 9 bits in the 1289 * page table and the remaining bits are in the page directory */ 1290 if (radeon_vm_block_size == -1) { 1291 1292 /* Total bits covered by PD + PTs */ 1293 unsigned bits = ilog2(radeon_vm_size) + 18; 1294 1295 /* Make sure the PD is 4K in size up to 8GB address space. 1296 Above that split equal between PD and PTs */ 1297 if (radeon_vm_size <= 8) 1298 radeon_vm_block_size = bits - 9; 1299 else 1300 radeon_vm_block_size = (bits + 3) / 2; 1301 1302 } else if (radeon_vm_block_size < 9) { 1303 dev_warn(rdev->dev, "VM page table size (%d) too small\n", 1304 radeon_vm_block_size); 1305 radeon_vm_block_size = 9; 1306 } 1307 1308 if (radeon_vm_block_size > 24 || 1309 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) { 1310 dev_warn(rdev->dev, "VM page table size (%d) too large\n", 1311 radeon_vm_block_size); 1312 radeon_vm_block_size = 9; 1313 } 1314} 1315 1316#ifndef __NetBSD__ /* XXX radeon vga */ 1317/** 1318 * radeon_switcheroo_set_state - set switcheroo state 1319 * 1320 * @pdev: pci dev pointer 1321 * @state: vga_switcheroo state 1322 * 1323 * Callback for the switcheroo driver. Suspends or resumes the 1324 * the asics before or after it is powered up using ACPI methods. 1325 */ 1326static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state) 1327{ 1328 struct drm_device *dev = pci_get_drvdata(pdev); 1329 struct radeon_device *rdev = dev->dev_private; 1330 1331 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF) 1332 return; 1333 1334 if (state == VGA_SWITCHEROO_ON) { 1335 unsigned d3_delay = dev->pdev->d3_delay; 1336 1337 printk(KERN_INFO "radeon: switched on\n"); 1338 /* don't suspend or resume card normally */ 1339 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1340 1341 if (d3_delay < 20 && (rdev->px_quirk_flags & RADEON_PX_QUIRK_LONG_WAKEUP)) 1342 dev->pdev->d3_delay = 20; 1343 1344 radeon_resume_kms(dev, true, true); 1345 1346 dev->pdev->d3_delay = d3_delay; 1347 1348 dev->switch_power_state = DRM_SWITCH_POWER_ON; 1349 drm_kms_helper_poll_enable(dev); 1350 } else { 1351 printk(KERN_INFO "radeon: switched off\n"); 1352 drm_kms_helper_poll_disable(dev); 1353 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1354 radeon_suspend_kms(dev, true, true); 1355 dev->switch_power_state = DRM_SWITCH_POWER_OFF; 1356 } 1357} 1358 1359/** 1360 * radeon_switcheroo_can_switch - see if switcheroo state can change 1361 * 1362 * @pdev: pci dev pointer 1363 * 1364 * Callback for the switcheroo driver. Check of the switcheroo 1365 * state can be changed. 1366 * Returns true if the state can be changed, false if not. 1367 */ 1368static bool radeon_switcheroo_can_switch(struct pci_dev *pdev) 1369{ 1370 struct drm_device *dev = pci_get_drvdata(pdev); 1371 1372 /* 1373 * FIXME: open_count is protected by drm_global_mutex but that would lead to 1374 * locking inversion with the driver load path. And the access here is 1375 * completely racy anyway. So don't bother with locking for now. 1376 */ 1377 return dev->open_count == 0; 1378} 1379 1380static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = { 1381 .set_gpu_state = radeon_switcheroo_set_state, 1382 .reprobe = NULL, 1383 .can_switch = radeon_switcheroo_can_switch, 1384}; 1385#endif 1386 1387/** 1388 * radeon_device_init - initialize the driver 1389 * 1390 * @rdev: radeon_device pointer 1391 * @pdev: drm dev pointer 1392 * @pdev: pci dev pointer 1393 * @flags: driver flags 1394 * 1395 * Initializes the driver info and hw (all asics). 1396 * Returns 0 for success or an error on failure. 1397 * Called at driver startup. 1398 */ 1399int radeon_device_init(struct radeon_device *rdev, 1400 struct drm_device *ddev, 1401 struct pci_dev *pdev, 1402 uint32_t flags) 1403{ 1404 int r, i; 1405 int dma_bits; 1406#ifndef __NetBSD__ 1407 bool runtime = false; 1408#endif 1409 1410 rdev->shutdown = false; 1411 rdev->dev = ddev->dev; 1412 rdev->ddev = ddev; 1413 rdev->pdev = pdev; 1414 rdev->flags = flags; 1415 rdev->family = flags & RADEON_FAMILY_MASK; 1416 rdev->is_atom_bios = false; 1417 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; 1418 rdev->mc.gtt_size = 512 * 1024 * 1024; 1419 rdev->accel_working = false; 1420 /* set up ring ids */ 1421 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1422 rdev->ring[i].idx = i; 1423 } 1424 rdev->fence_context = fence_context_alloc(RADEON_NUM_RINGS); 1425 1426 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", 1427 radeon_family_name[rdev->family], pdev->vendor, pdev->device, 1428 pdev->subsystem_vendor, pdev->subsystem_device); 1429 1430 /* mutex initialization are all done here so we 1431 * can recall function without having locking issues */ 1432#ifdef __NetBSD__ 1433 linux_mutex_init(&rdev->ring_lock); 1434 linux_mutex_init(&rdev->dc_hw_i2c_mutex); 1435#else 1436 mutex_init(&rdev->ring_lock); 1437 mutex_init(&rdev->dc_hw_i2c_mutex); 1438#endif 1439 atomic_set(&rdev->ih.lock, 0); 1440#ifdef __NetBSD__ 1441 linux_mutex_init(&rdev->gem.mutex); 1442 linux_mutex_init(&rdev->pm.mutex); 1443 linux_mutex_init(&rdev->gpu_clock_mutex); 1444 linux_mutex_init(&rdev->srbm_mutex); 1445 linux_mutex_init(&rdev->grbm_idx_mutex); 1446#else 1447 mutex_init(&rdev->gem.mutex); 1448 mutex_init(&rdev->pm.mutex); 1449 mutex_init(&rdev->gpu_clock_mutex); 1450 mutex_init(&rdev->srbm_mutex); 1451 mutex_init(&rdev->grbm_idx_mutex); 1452#endif 1453 init_rwsem(&rdev->pm.mclk_lock); 1454 init_rwsem(&rdev->exclusive_lock); 1455#ifdef __NetBSD__ 1456 spin_lock_init(&rdev->irq.vblank_lock); 1457 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue, "radvblnk"); 1458 linux_mutex_init(&rdev->mn_lock); 1459#else 1460 init_waitqueue_head(&rdev->irq.vblank_queue); 1461 mutex_init(&rdev->mn_lock); 1462#endif 1463 hash_init(rdev->mn_hash); 1464 r = radeon_gem_init(rdev); 1465 if (r) 1466 return r; 1467 1468 radeon_check_arguments(rdev); 1469 /* Adjust VM size here. 1470 * Max GPUVM size for cayman+ is 40 bits. 1471 */ 1472 rdev->vm_manager.max_pfn = radeon_vm_size << 18; 1473 1474 /* Set asic functions */ 1475 r = radeon_asic_init(rdev); 1476 if (r) 1477 return r; 1478 1479 /* all of the newer IGP chips have an internal gart 1480 * However some rs4xx report as AGP, so remove that here. 1481 */ 1482 if ((rdev->family >= CHIP_RS400) && 1483 (rdev->flags & RADEON_IS_IGP)) { 1484 rdev->flags &= ~RADEON_IS_AGP; 1485 } 1486 1487 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { 1488 radeon_agp_disable(rdev); 1489 } 1490 1491 /* Set the internal MC address mask 1492 * This is the max address of the GPU's 1493 * internal address space. 1494 */ 1495 if (rdev->family >= CHIP_CAYMAN) 1496 rdev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ 1497 else if (rdev->family >= CHIP_CEDAR) 1498 rdev->mc.mc_mask = 0xfffffffffULL; /* 36 bit MC */ 1499 else 1500 rdev->mc.mc_mask = 0xffffffffULL; /* 32 bit MC */ 1501 1502 /* set DMA mask + need_dma32 flags. 1503 * PCIE - can handle 40-bits. 1504 * IGP - can handle 40-bits 1505 * AGP - generally dma32 is safest 1506 * PCI - dma32 for legacy pci gart, 40 bits on newer asics 1507 */ 1508 rdev->need_dma32 = false; 1509 if (rdev->flags & RADEON_IS_AGP) 1510 rdev->need_dma32 = true; 1511 if ((rdev->flags & RADEON_IS_PCI) && 1512 (rdev->family <= CHIP_RS740)) 1513 rdev->need_dma32 = true; 1514 1515 dma_bits = rdev->need_dma32 ? 32 : 40; 1516#ifdef __NetBSD__ 1517 r = drm_limit_dma_space(rdev->ddev, 0, __BITS(dma_bits - 1, 0)); 1518 if (r) 1519 DRM_ERROR("No suitable DMA available.\n"); 1520#else 1521 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1522 if (r) { 1523 rdev->need_dma32 = true; 1524 dma_bits = 32; 1525 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 1526 } 1527 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); 1528 if (r) { 1529 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 1530 printk(KERN_WARNING "radeon: No coherent DMA available.\n"); 1531 } 1532#endif 1533 1534 /* Registers mapping */ 1535 /* TODO: block userspace mapping of io register */ 1536 /* XXX Destroy these locks on detach... */ 1537 spin_lock_init(&rdev->mmio_idx_lock); 1538 spin_lock_init(&rdev->smc_idx_lock); 1539 spin_lock_init(&rdev->pll_idx_lock); 1540 spin_lock_init(&rdev->mc_idx_lock); 1541 spin_lock_init(&rdev->pcie_idx_lock); 1542 spin_lock_init(&rdev->pciep_idx_lock); 1543 spin_lock_init(&rdev->pif_idx_lock); 1544 spin_lock_init(&rdev->cg_idx_lock); 1545 spin_lock_init(&rdev->uvd_idx_lock); 1546 spin_lock_init(&rdev->rcu_idx_lock); 1547 spin_lock_init(&rdev->didt_idx_lock); 1548 spin_lock_init(&rdev->end_idx_lock); 1549#ifdef __NetBSD__ 1550 { 1551 pcireg_t bar; 1552 1553 if (rdev->family >= CHIP_BONAIRE) 1554 bar = 5; 1555 else 1556 bar = 2; 1557 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(bar), 1558 pci_mapreg_type(rdev->pdev->pd_pa.pa_pc, 1559 rdev->pdev->pd_pa.pa_tag, PCI_BAR(bar)), 1560 0, 1561 &rdev->rmmio_bst, &rdev->rmmio_bsh, 1562 &rdev->rmmio_addr, &rdev->rmmio_size)) 1563 return -EIO; 1564 } 1565 DRM_INFO("register mmio base: 0x%"PRIxMAX"\n", 1566 (uintmax_t)rdev->rmmio_addr); 1567 DRM_INFO("register mmio size: %"PRIuMAX"\n", 1568 (uintmax_t)rdev->rmmio_size); 1569#else 1570 if (rdev->family >= CHIP_BONAIRE) { 1571 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5); 1572 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5); 1573 } else { 1574 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); 1575 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); 1576 } 1577 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); 1578 if (rdev->rmmio == NULL) { 1579 return -ENOMEM; 1580 } 1581 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); 1582 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); 1583#endif 1584 1585 /* doorbell bar mapping */ 1586 if (rdev->family >= CHIP_BONAIRE) 1587 radeon_doorbell_init(rdev); 1588 1589 /* io port mapping */ 1590 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { 1591#ifdef __NetBSD__ 1592 if (pci_mapreg_map(&rdev->pdev->pd_pa, PCI_BAR(i), 1593 PCI_MAPREG_TYPE_IO, 0, 1594 &rdev->rio_mem_bst, &rdev->rio_mem_bsh, 1595 NULL, &rdev->rio_mem_size)) 1596 continue; 1597 break; 1598#else 1599 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { 1600 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); 1601 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); 1602 break; 1603 } 1604#endif 1605 } 1606#ifdef __NetBSD__ 1607 if (i == DEVICE_COUNT_RESOURCE) 1608 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1609#else 1610 if (rdev->rio_mem == NULL) 1611 DRM_ERROR("Unable to find PCI I/O BAR\n"); 1612#endif 1613 1614 if (rdev->flags & RADEON_IS_PX) 1615 radeon_device_handle_px_quirks(rdev); 1616 1617#ifndef __NetBSD__ /* XXX radeon vga */ 1618 /* if we have > 1 VGA cards, then disable the radeon VGA resources */ 1619 /* this will fail for cards that aren't VGA class devices, just 1620 * ignore it */ 1621 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); 1622 1623 if (rdev->flags & RADEON_IS_PX) 1624 runtime = true; 1625 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops, runtime); 1626 if (runtime) 1627 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain); 1628#endif 1629 1630 r = radeon_init(rdev); 1631 if (r) 1632 goto failed; 1633 1634 r = radeon_gem_debugfs_init(rdev); 1635 if (r) { 1636 DRM_ERROR("registering gem debugfs failed (%d).\n", r); 1637 } 1638 1639 r = radeon_mst_debugfs_init(rdev); 1640 if (r) { 1641 DRM_ERROR("registering mst debugfs failed (%d).\n", r); 1642 } 1643 1644 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { 1645 /* Acceleration not working on AGP card try again 1646 * with fallback to PCI or PCIE GART 1647 */ 1648 radeon_asic_reset(rdev); 1649 radeon_fini(rdev); 1650 radeon_agp_disable(rdev); 1651 r = radeon_init(rdev); 1652 if (r) 1653 goto failed; 1654 } 1655 1656 r = radeon_ib_ring_tests(rdev); 1657 if (r) 1658 DRM_ERROR("ib ring test failed (%d).\n", r); 1659 1660 /* 1661 * Turks/Thames GPU will freeze whole laptop if DPM is not restarted 1662 * after the CP ring have chew one packet at least. Hence here we stop 1663 * and restart DPM after the radeon_ib_ring_tests(). 1664 */ 1665 if (rdev->pm.dpm_enabled && 1666 (rdev->pm.pm_method == PM_METHOD_DPM) && 1667 (rdev->family == CHIP_TURKS) && 1668 (rdev->flags & RADEON_IS_MOBILITY)) { 1669 mutex_lock(&rdev->pm.mutex); 1670 radeon_dpm_disable(rdev); 1671 radeon_dpm_enable(rdev); 1672 mutex_unlock(&rdev->pm.mutex); 1673 } 1674 1675 if ((radeon_testing & 1)) { 1676 if (rdev->accel_working) 1677 radeon_test_moves(rdev); 1678 else 1679 DRM_INFO("radeon: acceleration disabled, skipping move tests\n"); 1680 } 1681 if ((radeon_testing & 2)) { 1682 if (rdev->accel_working) 1683 radeon_test_syncing(rdev); 1684 else 1685 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n"); 1686 } 1687 if (radeon_benchmarking) { 1688 if (rdev->accel_working) 1689 radeon_benchmark(rdev, radeon_benchmarking); 1690 else 1691 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n"); 1692 } 1693 return 0; 1694 1695failed: 1696 if (runtime) 1697 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1698 return r; 1699} 1700 1701static void radeon_debugfs_remove_files(struct radeon_device *rdev); 1702 1703/** 1704 * radeon_device_fini - tear down the driver 1705 * 1706 * @rdev: radeon_device pointer 1707 * 1708 * Tear down the driver info (all asics). 1709 * Called at driver shutdown. 1710 */ 1711void radeon_device_fini(struct radeon_device *rdev) 1712{ 1713 DRM_INFO("radeon: finishing device.\n"); 1714 rdev->shutdown = true; 1715 /* evict vram memory */ 1716 radeon_bo_evict_vram(rdev); 1717 radeon_fini(rdev); 1718#ifndef __NetBSD__ 1719 vga_switcheroo_unregister_client(rdev->pdev); 1720 if (rdev->flags & RADEON_IS_PX) 1721 vga_switcheroo_fini_domain_pm_ops(rdev->dev); 1722 vga_client_register(rdev->pdev, NULL, NULL, NULL); 1723#endif 1724#ifdef __NetBSD__ 1725 if (rdev->rio_mem_size) 1726 bus_space_unmap(rdev->rio_mem_bst, rdev->rio_mem_bsh, 1727 rdev->rio_mem_size); 1728 rdev->rio_mem_size = 0; 1729 bus_space_unmap(rdev->rmmio_bst, rdev->rmmio_bsh, rdev->rmmio_size); 1730#else 1731 if (rdev->rio_mem) 1732 pci_iounmap(rdev->pdev, rdev->rio_mem); 1733 rdev->rio_mem = NULL; 1734 iounmap(rdev->rmmio); 1735 rdev->rmmio = NULL; 1736#endif 1737 if (rdev->family >= CHIP_BONAIRE) 1738 radeon_doorbell_fini(rdev); 1739 radeon_debugfs_remove_files(rdev); 1740 1741#ifdef __NetBSD__ 1742 DRM_DESTROY_WAITQUEUE(&rdev->irq.vblank_queue); 1743 spin_lock_destroy(&rdev->irq.vblank_lock); 1744 destroy_rwsem(&rdev->exclusive_lock); 1745 destroy_rwsem(&rdev->pm.mclk_lock); 1746 linux_mutex_destroy(&rdev->srbm_mutex); 1747 linux_mutex_destroy(&rdev->gpu_clock_mutex); 1748 linux_mutex_destroy(&rdev->pm.mutex); 1749 linux_mutex_destroy(&rdev->gem.mutex); 1750 linux_mutex_destroy(&rdev->dc_hw_i2c_mutex); 1751 linux_mutex_destroy(&rdev->ring_lock); 1752#else 1753 mutex_destroy(&rdev->srbm_mutex); 1754 mutex_destroy(&rdev->gpu_clock_mutex); 1755 mutex_destroy(&rdev->pm.mutex); 1756 mutex_destroy(&rdev->gem.mutex); 1757 mutex_destroy(&rdev->dc_hw_i2c_mutex); 1758 mutex_destroy(&rdev->ring_lock); 1759#endif 1760} 1761 1762 1763/* 1764 * Suspend & resume. 1765 */ 1766/** 1767 * radeon_suspend_kms - initiate device suspend 1768 * 1769 * @pdev: drm dev pointer 1770 * @state: suspend state 1771 * 1772 * Puts the hw in the suspend state (all asics). 1773 * Returns 0 for success or an error on failure. 1774 * Called at driver suspend. 1775 */ 1776int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon) 1777{ 1778 struct radeon_device *rdev; 1779 struct drm_crtc *crtc; 1780 struct drm_connector *connector; 1781 int i, r; 1782 1783 if (dev == NULL || dev->dev_private == NULL) { 1784 return -ENODEV; 1785 } 1786 1787 rdev = dev->dev_private; 1788 1789 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1790 return 0; 1791 1792 drm_kms_helper_poll_disable(dev); 1793 1794 drm_modeset_lock_all(dev); 1795 /* turn off display hw */ 1796 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1797 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); 1798 } 1799 drm_modeset_unlock_all(dev); 1800 1801 /* unpin the front buffers and cursors */ 1802 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1803 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1804 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb); 1805 struct radeon_bo *robj; 1806 1807 if (radeon_crtc->cursor_bo) { 1808 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1809 r = radeon_bo_reserve(robj, false); 1810 if (r == 0) { 1811 radeon_bo_unpin(robj); 1812 radeon_bo_unreserve(robj); 1813 } 1814 } 1815 1816 if (rfb == NULL || rfb->obj == NULL) { 1817 continue; 1818 } 1819 robj = gem_to_radeon_bo(rfb->obj); 1820 /* don't unpin kernel fb objects */ 1821 if (!radeon_fbdev_robj_is_fb(rdev, robj)) { 1822 r = radeon_bo_reserve(robj, false); 1823 if (r == 0) { 1824 radeon_bo_unpin(robj); 1825 radeon_bo_unreserve(robj); 1826 } 1827 } 1828 } 1829 /* evict vram memory */ 1830 radeon_bo_evict_vram(rdev); 1831 1832 /* wait for gpu to finish processing current batch */ 1833 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1834 r = radeon_fence_wait_empty(rdev, i); 1835 if (r) { 1836 /* delay GPU reset to resume */ 1837 radeon_fence_driver_force_completion(rdev, i); 1838 } 1839 } 1840 1841 radeon_save_bios_scratch_regs(rdev); 1842 1843 radeon_suspend(rdev); 1844 radeon_hpd_fini(rdev); 1845 /* evict remaining vram memory */ 1846 radeon_bo_evict_vram(rdev); 1847 1848 radeon_agp_suspend(rdev); 1849 1850#ifndef __NetBSD__ /* pmf handles this for us. */ 1851 pci_save_state(dev->pdev); 1852 if (suspend) { 1853 /* Shut down the device */ 1854 pci_disable_device(dev->pdev); 1855 pci_set_power_state(dev->pdev, PCI_D3hot); 1856 } 1857#endif 1858 1859#ifndef __NetBSD__ /* XXX radeon fb */ 1860 if (fbcon) { 1861 console_lock(); 1862 radeon_fbdev_set_suspend(rdev, 1); 1863 console_unlock(); 1864 } 1865#endif 1866 return 0; 1867} 1868 1869/** 1870 * radeon_resume_kms - initiate device resume 1871 * 1872 * @pdev: drm dev pointer 1873 * 1874 * Bring the hw back to operating state (all asics). 1875 * Returns 0 for success or an error on failure. 1876 * Called at driver resume. 1877 */ 1878int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon) 1879{ 1880 struct drm_connector *connector; 1881 struct radeon_device *rdev = dev->dev_private; 1882 struct drm_crtc *crtc; 1883 int r; 1884 1885 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) 1886 return 0; 1887 1888#ifndef __NetBSD__ /* XXX radeon fb */ 1889 if (fbcon) { 1890 console_lock(); 1891 } 1892#endif 1893#ifndef __NetBSD__ /* pmf handles this for us. */ 1894 if (resume) { 1895 pci_set_power_state(dev->pdev, PCI_D0); 1896 pci_restore_state(dev->pdev); 1897 if (pci_enable_device(dev->pdev)) { 1898 if (fbcon) 1899 console_unlock(); 1900 return -1; 1901 } 1902 } 1903#endif 1904 /* resume AGP if in use */ 1905 radeon_agp_resume(rdev); 1906 radeon_resume(rdev); 1907 1908 r = radeon_ib_ring_tests(rdev); 1909 if (r) 1910 DRM_ERROR("ib ring test failed (%d).\n", r); 1911 1912 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 1913 /* do dpm late init */ 1914 r = radeon_pm_late_init(rdev); 1915 if (r) { 1916 rdev->pm.dpm_enabled = false; 1917 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1918 } 1919 } else { 1920 /* resume old pm late */ 1921 radeon_pm_resume(rdev); 1922 } 1923 1924 radeon_restore_bios_scratch_regs(rdev); 1925 1926 /* pin cursors */ 1927 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1928 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1929 1930 if (radeon_crtc->cursor_bo) { 1931 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo); 1932 r = radeon_bo_reserve(robj, false); 1933 if (r == 0) { 1934 /* Only 27 bit offset for legacy cursor */ 1935 r = radeon_bo_pin_restricted(robj, 1936 RADEON_GEM_DOMAIN_VRAM, 1937 ASIC_IS_AVIVO(rdev) ? 1938 0 : 1 << 27, 1939 &radeon_crtc->cursor_addr); 1940 if (r != 0) 1941 DRM_ERROR("Failed to pin cursor BO (%d)\n", r); 1942 radeon_bo_unreserve(robj); 1943 } 1944 } 1945 } 1946 1947 /* init dig PHYs, disp eng pll */ 1948 if (rdev->is_atom_bios) { 1949 radeon_atom_encoder_init(rdev); 1950 radeon_atom_disp_eng_pll_init(rdev); 1951 /* turn on the BL */ 1952 if (rdev->mode_info.bl_encoder) { 1953 u8 bl_level = radeon_get_backlight_level(rdev, 1954 rdev->mode_info.bl_encoder); 1955 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 1956 bl_level); 1957 } 1958 } 1959 /* reset hpd state */ 1960 radeon_hpd_init(rdev); 1961 /* blat the mode back in */ 1962 if (fbcon) { 1963 drm_helper_resume_force_mode(dev); 1964 /* turn on display hw */ 1965 drm_modeset_lock_all(dev); 1966 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 1967 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); 1968 } 1969 drm_modeset_unlock_all(dev); 1970 } 1971 1972 drm_kms_helper_poll_enable(dev); 1973 1974 /* set the power state here in case we are a PX system or headless */ 1975 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 1976 radeon_pm_compute_clocks(rdev); 1977 1978#ifndef __NetBSD__ /* XXX radeon fb */ 1979 if (fbcon) { 1980 radeon_fbdev_set_suspend(rdev, 0); 1981 console_unlock(); 1982 } 1983#endif 1984 1985 return 0; 1986} 1987 1988/** 1989 * radeon_gpu_reset - reset the asic 1990 * 1991 * @rdev: radeon device pointer 1992 * 1993 * Attempt the reset the GPU if it has hung (all asics). 1994 * Returns 0 for success or an error on failure. 1995 */ 1996int radeon_gpu_reset(struct radeon_device *rdev) 1997{ 1998 unsigned ring_sizes[RADEON_NUM_RINGS]; 1999 uint32_t *ring_data[RADEON_NUM_RINGS]; 2000 2001 bool saved = false; 2002 2003 int i, r; 2004 int resched; 2005 2006 down_write(&rdev->exclusive_lock); 2007 2008 if (!rdev->needs_reset) { 2009 up_write(&rdev->exclusive_lock); 2010 return 0; 2011 } 2012 2013 atomic_inc(&rdev->gpu_reset_counter); 2014 2015 radeon_save_bios_scratch_regs(rdev); 2016 /* block TTM */ 2017 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 2018 radeon_suspend(rdev); 2019 radeon_hpd_fini(rdev); 2020 2021 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 2022 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], 2023 &ring_data[i]); 2024 if (ring_sizes[i]) { 2025 saved = true; 2026 dev_info(rdev->dev, "Saved %d dwords of commands " 2027 "on ring %d.\n", ring_sizes[i], i); 2028 } 2029 } 2030 2031 r = radeon_asic_reset(rdev); 2032 if (!r) { 2033 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); 2034 radeon_resume(rdev); 2035 } 2036 2037 radeon_restore_bios_scratch_regs(rdev); 2038 2039 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 2040 if (!r && ring_data[i]) { 2041 radeon_ring_restore(rdev, &rdev->ring[i], 2042 ring_sizes[i], ring_data[i]); 2043 } else { 2044 radeon_fence_driver_force_completion(rdev, i); 2045 kfree(ring_data[i]); 2046 } 2047 } 2048 2049 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 2050 /* do dpm late init */ 2051 r = radeon_pm_late_init(rdev); 2052 if (r) { 2053 rdev->pm.dpm_enabled = false; 2054 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 2055 } 2056 } else { 2057 /* resume old pm late */ 2058 radeon_pm_resume(rdev); 2059 } 2060 2061 /* init dig PHYs, disp eng pll */ 2062 if (rdev->is_atom_bios) { 2063 radeon_atom_encoder_init(rdev); 2064 radeon_atom_disp_eng_pll_init(rdev); 2065 /* turn on the BL */ 2066 if (rdev->mode_info.bl_encoder) { 2067 u8 bl_level = radeon_get_backlight_level(rdev, 2068 rdev->mode_info.bl_encoder); 2069 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder, 2070 bl_level); 2071 } 2072 } 2073 /* reset hpd state */ 2074 radeon_hpd_init(rdev); 2075 2076 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 2077 2078 rdev->in_reset = true; 2079 rdev->needs_reset = false; 2080 2081 downgrade_write(&rdev->exclusive_lock); 2082 2083 drm_helper_resume_force_mode(rdev->ddev); 2084 2085 /* set the power state here in case we are a PX system or headless */ 2086 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) 2087 radeon_pm_compute_clocks(rdev); 2088 2089 if (!r) { 2090 r = radeon_ib_ring_tests(rdev); 2091 if (r && saved) 2092 r = -EAGAIN; 2093 } else { 2094 /* bad news, how to tell it to userspace ? */ 2095 dev_info(rdev->dev, "GPU reset failed\n"); 2096 } 2097 2098 rdev->needs_reset = r == -EAGAIN; 2099 rdev->in_reset = false; 2100 2101 up_read(&rdev->exclusive_lock); 2102 return r; 2103} 2104 2105 2106/* 2107 * Debugfs 2108 */ 2109int radeon_debugfs_add_files(struct radeon_device *rdev, 2110 struct drm_info_list *files, 2111 unsigned nfiles) 2112{ 2113 unsigned i; 2114 2115 for (i = 0; i < rdev->debugfs_count; i++) { 2116 if (rdev->debugfs[i].files == files) { 2117 /* Already registered */ 2118 return 0; 2119 } 2120 } 2121 2122 i = rdev->debugfs_count + 1; 2123 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) { 2124 DRM_ERROR("Reached maximum number of debugfs components.\n"); 2125 DRM_ERROR("Report so we increase " 2126 "RADEON_DEBUGFS_MAX_COMPONENTS.\n"); 2127 return -EINVAL; 2128 } 2129 rdev->debugfs[rdev->debugfs_count].files = files; 2130 rdev->debugfs[rdev->debugfs_count].num_files = nfiles; 2131 rdev->debugfs_count = i; 2132#if defined(CONFIG_DEBUG_FS) 2133 drm_debugfs_create_files(files, nfiles, 2134 rdev->ddev->control->debugfs_root, 2135 rdev->ddev->control); 2136 drm_debugfs_create_files(files, nfiles, 2137 rdev->ddev->primary->debugfs_root, 2138 rdev->ddev->primary); 2139#endif 2140 return 0; 2141} 2142 2143static void radeon_debugfs_remove_files(struct radeon_device *rdev) 2144{ 2145#if defined(CONFIG_DEBUG_FS) 2146 unsigned i; 2147 2148 for (i = 0; i < rdev->debugfs_count; i++) { 2149 drm_debugfs_remove_files(rdev->debugfs[i].files, 2150 rdev->debugfs[i].num_files, 2151 rdev->ddev->control); 2152 drm_debugfs_remove_files(rdev->debugfs[i].files, 2153 rdev->debugfs[i].num_files, 2154 rdev->ddev->primary); 2155 } 2156#endif 2157} 2158 2159#if defined(CONFIG_DEBUG_FS) 2160int radeon_debugfs_init(struct drm_minor *minor) 2161{ 2162 return 0; 2163} 2164 2165void radeon_debugfs_cleanup(struct drm_minor *minor) 2166{ 2167} 2168#endif 2169