radeon_atombios_crtc.c revision 1.2
1/* $NetBSD: radeon_atombios_crtc.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3/* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29#include <sys/cdefs.h> 30__KERNEL_RCSID(0, "$NetBSD: radeon_atombios_crtc.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 31 32#include <drm/drm_crtc_helper.h> 33#include <drm/drm_fb_helper.h> 34#include <drm/drm_fixed.h> 35#include <drm/drm_fourcc.h> 36#include <drm/drm_vblank.h> 37#include <drm/radeon_drm.h> 38 39#include "radeon.h" 40#include "radeon_asic.h" 41#include "atom.h" 42#include "atom-bits.h" 43 44static void atombios_overscan_setup(struct drm_crtc *crtc, 45 struct drm_display_mode *mode, 46 struct drm_display_mode *adjusted_mode) 47{ 48 struct drm_device *dev = crtc->dev; 49 struct radeon_device *rdev = dev->dev_private; 50 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 51 SET_CRTC_OVERSCAN_PS_ALLOCATION args; 52 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); 53 int a1, a2; 54 55 memset(&args, 0, sizeof(args)); 56 57 args.ucCRTC = radeon_crtc->crtc_id; 58 59 switch (radeon_crtc->rmx_type) { 60 case RMX_CENTER: 61 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 62 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); 63 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 64 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); 65 break; 66 case RMX_ASPECT: 67 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; 68 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; 69 70 if (a1 > a2) { 71 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 72 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2); 73 } else if (a2 > a1) { 74 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 75 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2); 76 } 77 break; 78 case RMX_FULL: 79 default: 80 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border); 81 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border); 82 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border); 83 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border); 84 break; 85 } 86 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 87} 88 89static void atombios_scaler_setup(struct drm_crtc *crtc) 90{ 91 struct drm_device *dev = crtc->dev; 92 struct radeon_device *rdev = dev->dev_private; 93 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 94 ENABLE_SCALER_PS_ALLOCATION args; 95 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); 96 struct radeon_encoder *radeon_encoder = 97 to_radeon_encoder(radeon_crtc->encoder); 98 /* fixme - fill in enc_priv for atom dac */ 99 enum radeon_tv_std tv_std = TV_STD_NTSC; 100 bool is_tv = false, is_cv = false; 101 102 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) 103 return; 104 105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { 106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; 107 tv_std = tv_dac->tv_std; 108 is_tv = true; 109 } 110 111 memset(&args, 0, sizeof(args)); 112 113 args.ucScaler = radeon_crtc->crtc_id; 114 115 if (is_tv) { 116 switch (tv_std) { 117 case TV_STD_NTSC: 118 default: 119 args.ucTVStandard = ATOM_TV_NTSC; 120 break; 121 case TV_STD_PAL: 122 args.ucTVStandard = ATOM_TV_PAL; 123 break; 124 case TV_STD_PAL_M: 125 args.ucTVStandard = ATOM_TV_PALM; 126 break; 127 case TV_STD_PAL_60: 128 args.ucTVStandard = ATOM_TV_PAL60; 129 break; 130 case TV_STD_NTSC_J: 131 args.ucTVStandard = ATOM_TV_NTSCJ; 132 break; 133 case TV_STD_SCART_PAL: 134 args.ucTVStandard = ATOM_TV_PAL; /* ??? */ 135 break; 136 case TV_STD_SECAM: 137 args.ucTVStandard = ATOM_TV_SECAM; 138 break; 139 case TV_STD_PAL_CN: 140 args.ucTVStandard = ATOM_TV_PALCN; 141 break; 142 } 143 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 144 } else if (is_cv) { 145 args.ucTVStandard = ATOM_TV_CV; 146 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; 147 } else { 148 switch (radeon_crtc->rmx_type) { 149 case RMX_FULL: 150 args.ucEnable = ATOM_SCALER_EXPANSION; 151 break; 152 case RMX_CENTER: 153 args.ucEnable = ATOM_SCALER_CENTER; 154 break; 155 case RMX_ASPECT: 156 args.ucEnable = ATOM_SCALER_EXPANSION; 157 break; 158 default: 159 if (ASIC_IS_AVIVO(rdev)) 160 args.ucEnable = ATOM_SCALER_DISABLE; 161 else 162 args.ucEnable = ATOM_SCALER_CENTER; 163 break; 164 } 165 } 166 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 167 if ((is_tv || is_cv) 168 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { 169 atom_rv515_force_tv_scaler(rdev, radeon_crtc); 170 } 171} 172 173static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) 174{ 175 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 176 struct drm_device *dev = crtc->dev; 177 struct radeon_device *rdev = dev->dev_private; 178 int index = 179 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); 180 ENABLE_CRTC_PS_ALLOCATION args; 181 182 memset(&args, 0, sizeof(args)); 183 184 args.ucCRTC = radeon_crtc->crtc_id; 185 args.ucEnable = lock; 186 187 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 188} 189 190static void atombios_enable_crtc(struct drm_crtc *crtc, int state) 191{ 192 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 193 struct drm_device *dev = crtc->dev; 194 struct radeon_device *rdev = dev->dev_private; 195 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); 196 ENABLE_CRTC_PS_ALLOCATION args; 197 198 memset(&args, 0, sizeof(args)); 199 200 args.ucCRTC = radeon_crtc->crtc_id; 201 args.ucEnable = state; 202 203 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 204} 205 206static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) 207{ 208 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 209 struct drm_device *dev = crtc->dev; 210 struct radeon_device *rdev = dev->dev_private; 211 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); 212 ENABLE_CRTC_PS_ALLOCATION args; 213 214 memset(&args, 0, sizeof(args)); 215 216 args.ucCRTC = radeon_crtc->crtc_id; 217 args.ucEnable = state; 218 219 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 220} 221 222static const u32 vga_control_regs[6] = 223{ 224 AVIVO_D1VGA_CONTROL, 225 AVIVO_D2VGA_CONTROL, 226 EVERGREEN_D3VGA_CONTROL, 227 EVERGREEN_D4VGA_CONTROL, 228 EVERGREEN_D5VGA_CONTROL, 229 EVERGREEN_D6VGA_CONTROL, 230}; 231 232static void atombios_blank_crtc(struct drm_crtc *crtc, int state) 233{ 234 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 235 struct drm_device *dev = crtc->dev; 236 struct radeon_device *rdev = dev->dev_private; 237 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); 238 BLANK_CRTC_PS_ALLOCATION args; 239 u32 vga_control = 0; 240 241 memset(&args, 0, sizeof(args)); 242 243 if (ASIC_IS_DCE8(rdev)) { 244 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]); 245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1); 246 } 247 248 args.ucCRTC = radeon_crtc->crtc_id; 249 args.ucBlanking = state; 250 251 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 252 253 if (ASIC_IS_DCE8(rdev)) 254 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control); 255} 256 257static void atombios_powergate_crtc(struct drm_crtc *crtc, int state) 258{ 259 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 260 struct drm_device *dev = crtc->dev; 261 struct radeon_device *rdev = dev->dev_private; 262 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating); 263 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args; 264 265 memset(&args, 0, sizeof(args)); 266 267 args.ucDispPipeId = radeon_crtc->crtc_id; 268 args.ucEnable = state; 269 270 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 271} 272 273void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) 274{ 275 struct drm_device *dev = crtc->dev; 276 struct radeon_device *rdev = dev->dev_private; 277 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 278 279 switch (mode) { 280 case DRM_MODE_DPMS_ON: 281 radeon_crtc->enabled = true; 282 atombios_enable_crtc(crtc, ATOM_ENABLE); 283 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 284 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); 285 atombios_blank_crtc(crtc, ATOM_DISABLE); 286 if (dev->num_crtcs > radeon_crtc->crtc_id) 287 drm_crtc_vblank_on(crtc); 288 radeon_crtc_load_lut(crtc); 289 break; 290 case DRM_MODE_DPMS_STANDBY: 291 case DRM_MODE_DPMS_SUSPEND: 292 case DRM_MODE_DPMS_OFF: 293 if (dev->num_crtcs > radeon_crtc->crtc_id) 294 drm_crtc_vblank_off(crtc); 295 if (radeon_crtc->enabled) 296 atombios_blank_crtc(crtc, ATOM_ENABLE); 297 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev)) 298 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); 299 atombios_enable_crtc(crtc, ATOM_DISABLE); 300 radeon_crtc->enabled = false; 301 break; 302 } 303 /* adjust pm to dpms */ 304 radeon_pm_compute_clocks(rdev); 305} 306 307static void 308atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, 309 struct drm_display_mode *mode) 310{ 311 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 312 struct drm_device *dev = crtc->dev; 313 struct radeon_device *rdev = dev->dev_private; 314 SET_CRTC_USING_DTD_TIMING_PARAMETERS args; 315 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); 316 u16 misc = 0; 317 318 memset(&args, 0, sizeof(args)); 319 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2)); 320 args.usH_Blanking_Time = 321 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2)); 322 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2)); 323 args.usV_Blanking_Time = 324 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2)); 325 args.usH_SyncOffset = 326 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border); 327 args.usH_SyncWidth = 328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 329 args.usV_SyncOffset = 330 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border); 331 args.usV_SyncWidth = 332 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 333 args.ucH_Border = radeon_crtc->h_border; 334 args.ucV_Border = radeon_crtc->v_border; 335 336 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 337 misc |= ATOM_VSYNC_POLARITY; 338 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 339 misc |= ATOM_HSYNC_POLARITY; 340 if (mode->flags & DRM_MODE_FLAG_CSYNC) 341 misc |= ATOM_COMPOSITESYNC; 342 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 343 misc |= ATOM_INTERLACE; 344 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 345 misc |= ATOM_DOUBLE_CLOCK_MODE; 346 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 347 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 348 349 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 350 args.ucCRTC = radeon_crtc->crtc_id; 351 352 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 353} 354 355static void atombios_crtc_set_timing(struct drm_crtc *crtc, 356 struct drm_display_mode *mode) 357{ 358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 359 struct drm_device *dev = crtc->dev; 360 struct radeon_device *rdev = dev->dev_private; 361 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args; 362 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); 363 u16 misc = 0; 364 365 memset(&args, 0, sizeof(args)); 366 args.usH_Total = cpu_to_le16(mode->crtc_htotal); 367 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay); 368 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start); 369 args.usH_SyncWidth = 370 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start); 371 args.usV_Total = cpu_to_le16(mode->crtc_vtotal); 372 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay); 373 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start); 374 args.usV_SyncWidth = 375 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start); 376 377 args.ucOverscanRight = radeon_crtc->h_border; 378 args.ucOverscanLeft = radeon_crtc->h_border; 379 args.ucOverscanBottom = radeon_crtc->v_border; 380 args.ucOverscanTop = radeon_crtc->v_border; 381 382 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 383 misc |= ATOM_VSYNC_POLARITY; 384 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 385 misc |= ATOM_HSYNC_POLARITY; 386 if (mode->flags & DRM_MODE_FLAG_CSYNC) 387 misc |= ATOM_COMPOSITESYNC; 388 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 389 misc |= ATOM_INTERLACE; 390 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 391 misc |= ATOM_DOUBLE_CLOCK_MODE; 392 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 393 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2; 394 395 args.susModeMiscInfo.usAccess = cpu_to_le16(misc); 396 args.ucCRTC = radeon_crtc->crtc_id; 397 398 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 399} 400 401static void atombios_disable_ss(struct radeon_device *rdev, int pll_id) 402{ 403 u32 ss_cntl; 404 405 if (ASIC_IS_DCE4(rdev)) { 406 switch (pll_id) { 407 case ATOM_PPLL1: 408 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); 409 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 410 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl); 411 break; 412 case ATOM_PPLL2: 413 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL); 414 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; 415 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl); 416 break; 417 case ATOM_DCPLL: 418 case ATOM_PPLL_INVALID: 419 return; 420 } 421 } else if (ASIC_IS_AVIVO(rdev)) { 422 switch (pll_id) { 423 case ATOM_PPLL1: 424 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); 425 ss_cntl &= ~1; 426 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl); 427 break; 428 case ATOM_PPLL2: 429 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); 430 ss_cntl &= ~1; 431 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl); 432 break; 433 case ATOM_DCPLL: 434 case ATOM_PPLL_INVALID: 435 return; 436 } 437 } 438} 439 440 441union atom_enable_ss { 442 ENABLE_LVDS_SS_PARAMETERS lvds_ss; 443 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2; 444 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1; 445 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2; 446 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; 447}; 448 449static void atombios_crtc_program_ss(struct radeon_device *rdev, 450 int enable, 451 int pll_id, 452 int crtc_id, 453 struct radeon_atom_ss *ss) 454{ 455 unsigned i; 456 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL); 457 union atom_enable_ss args; 458 459 if (enable) { 460 /* Don't mess with SS if percentage is 0 or external ss. 461 * SS is already disabled previously, and disabling it 462 * again can cause display problems if the pll is already 463 * programmed. 464 */ 465 if (ss->percentage == 0) 466 return; 467 if (ss->type & ATOM_EXTERNAL_SS_MASK) 468 return; 469 } else { 470 for (i = 0; i < rdev->num_crtc; i++) { 471 if (rdev->mode_info.crtcs[i] && 472 rdev->mode_info.crtcs[i]->enabled && 473 i != crtc_id && 474 pll_id == rdev->mode_info.crtcs[i]->pll_id) { 475 /* one other crtc is using this pll don't turn 476 * off spread spectrum as it might turn off 477 * display on active crtc 478 */ 479 return; 480 } 481 } 482 } 483 484 memset(&args, 0, sizeof(args)); 485 486 if (ASIC_IS_DCE5(rdev)) { 487 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); 488 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 489 switch (pll_id) { 490 case ATOM_PPLL1: 491 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; 492 break; 493 case ATOM_PPLL2: 494 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; 495 break; 496 case ATOM_DCPLL: 497 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; 498 break; 499 case ATOM_PPLL_INVALID: 500 return; 501 } 502 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 503 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); 504 args.v3.ucEnable = enable; 505 } else if (ASIC_IS_DCE4(rdev)) { 506 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 507 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 508 switch (pll_id) { 509 case ATOM_PPLL1: 510 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL; 511 break; 512 case ATOM_PPLL2: 513 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL; 514 break; 515 case ATOM_DCPLL: 516 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL; 517 break; 518 case ATOM_PPLL_INVALID: 519 return; 520 } 521 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); 522 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step); 523 args.v2.ucEnable = enable; 524 } else if (ASIC_IS_DCE3(rdev)) { 525 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 526 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 527 args.v1.ucSpreadSpectrumStep = ss->step; 528 args.v1.ucSpreadSpectrumDelay = ss->delay; 529 args.v1.ucSpreadSpectrumRange = ss->range; 530 args.v1.ucPpll = pll_id; 531 args.v1.ucEnable = enable; 532 } else if (ASIC_IS_AVIVO(rdev)) { 533 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || 534 (ss->type & ATOM_EXTERNAL_SS_MASK)) { 535 atombios_disable_ss(rdev, pll_id); 536 return; 537 } 538 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 539 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 540 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step; 541 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay; 542 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range; 543 args.lvds_ss_2.ucEnable = enable; 544 } else { 545 if (enable == ATOM_DISABLE) { 546 atombios_disable_ss(rdev, pll_id); 547 return; 548 } 549 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); 550 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; 551 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2; 552 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4; 553 args.lvds_ss.ucEnable = enable; 554 } 555 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 556} 557 558union adjust_pixel_clock { 559 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1; 560 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; 561}; 562 563static u32 atombios_adjust_pll(struct drm_crtc *crtc, 564 struct drm_display_mode *mode) 565{ 566 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 567 struct drm_device *dev = crtc->dev; 568 struct radeon_device *rdev = dev->dev_private; 569 struct drm_encoder *encoder = radeon_crtc->encoder; 570 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 571 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder); 572 u32 adjusted_clock = mode->clock; 573 int encoder_mode = atombios_get_encoder_mode(encoder); 574 u32 dp_clock = mode->clock; 575 u32 clock = mode->clock; 576 int bpc = radeon_crtc->bpc; 577 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); 578 579 /* reset the pll flags */ 580 radeon_crtc->pll_flags = 0; 581 582 if (ASIC_IS_AVIVO(rdev)) { 583 if ((rdev->family == CHIP_RS600) || 584 (rdev->family == CHIP_RS690) || 585 (rdev->family == CHIP_RS740)) 586 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/ 587 RADEON_PLL_PREFER_CLOSEST_LOWER); 588 589 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ 590 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 591 else 592 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 593 594 if (rdev->family < CHIP_RV770) 595 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; 596 /* use frac fb div on APUs */ 597 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 598 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 599 /* use frac fb div on RS780/RS880 */ 600 if (((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880)) 601 && !radeon_crtc->ss_enabled) 602 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 603 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000) 604 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 605 } else { 606 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY; 607 608 if (mode->clock > 200000) /* range limits??? */ 609 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; 610 else 611 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; 612 } 613 614 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 615 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { 616 if (connector) { 617 struct radeon_connector *radeon_connector = to_radeon_connector(connector); 618 struct radeon_connector_atom_dig *dig_connector = 619 radeon_connector->con_priv; 620 621 dp_clock = dig_connector->dp_clock; 622 } 623 } 624 625 if (radeon_encoder->is_mst_encoder) { 626 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv; 627 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv; 628 629 dp_clock = dig_connector->dp_clock; 630 } 631 632 /* use recommended ref_div for ss */ 633 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 634 if (radeon_crtc->ss_enabled) { 635 if (radeon_crtc->ss.refdiv) { 636 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 637 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; 638 if (ASIC_IS_AVIVO(rdev) && 639 rdev->family != CHIP_RS780 && 640 rdev->family != CHIP_RS880) 641 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 642 } 643 } 644 } 645 646 if (ASIC_IS_AVIVO(rdev)) { 647 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */ 648 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1) 649 adjusted_clock = mode->clock * 2; 650 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 651 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER; 652 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) 653 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD; 654 } else { 655 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC) 656 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; 657 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) 658 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 659 } 660 661 /* adjust pll for deep color modes */ 662 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 663 switch (bpc) { 664 case 8: 665 default: 666 break; 667 case 10: 668 clock = (clock * 5) / 4; 669 break; 670 case 12: 671 clock = (clock * 3) / 2; 672 break; 673 case 16: 674 clock = clock * 2; 675 break; 676 } 677 } 678 679 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock 680 * accordingly based on the encoder/transmitter to work around 681 * special hw requirements. 682 */ 683 if (ASIC_IS_DCE3(rdev)) { 684 union adjust_pixel_clock args; 685 u8 frev, crev; 686 int index; 687 688 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll); 689 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 690 &crev)) 691 return adjusted_clock; 692 693 memset(&args, 0, sizeof(args)); 694 695 switch (frev) { 696 case 1: 697 switch (crev) { 698 case 1: 699 case 2: 700 args.v1.usPixelClock = cpu_to_le16(clock / 10); 701 args.v1.ucTransmitterID = radeon_encoder->encoder_id; 702 args.v1.ucEncodeMode = encoder_mode; 703 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 704 args.v1.ucConfig |= 705 ADJUST_DISPLAY_CONFIG_SS_ENABLE; 706 707 atom_execute_table(rdev->mode_info.atom_context, 708 index, (uint32_t *)&args); 709 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10; 710 break; 711 case 3: 712 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10); 713 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; 714 args.v3.sInput.ucEncodeMode = encoder_mode; 715 args.v3.sInput.ucDispPllConfig = 0; 716 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage) 717 args.v3.sInput.ucDispPllConfig |= 718 DISPPLL_CONFIG_SS_ENABLE; 719 if (ENCODER_MODE_IS_DP(encoder_mode)) { 720 args.v3.sInput.ucDispPllConfig |= 721 DISPPLL_CONFIG_COHERENT_MODE; 722 /* 16200 or 27000 */ 723 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); 724 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 725 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 726 if (dig->coherent_mode) 727 args.v3.sInput.ucDispPllConfig |= 728 DISPPLL_CONFIG_COHERENT_MODE; 729 if (is_duallink) 730 args.v3.sInput.ucDispPllConfig |= 731 DISPPLL_CONFIG_DUAL_LINK; 732 } 733 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != 734 ENCODER_OBJECT_ID_NONE) 735 args.v3.sInput.ucExtTransmitterID = 736 radeon_encoder_get_dp_bridge_encoder_id(encoder); 737 else 738 args.v3.sInput.ucExtTransmitterID = 0; 739 740 atom_execute_table(rdev->mode_info.atom_context, 741 index, (uint32_t *)&args); 742 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10; 743 if (args.v3.sOutput.ucRefDiv) { 744 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 745 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV; 746 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv; 747 } 748 if (args.v3.sOutput.ucPostDiv) { 749 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV; 750 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV; 751 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv; 752 } 753 break; 754 default: 755 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 756 return adjusted_clock; 757 } 758 break; 759 default: 760 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 761 return adjusted_clock; 762 } 763 } 764 return adjusted_clock; 765} 766 767union set_pixel_clock { 768 SET_PIXEL_CLOCK_PS_ALLOCATION base; 769 PIXEL_CLOCK_PARAMETERS v1; 770 PIXEL_CLOCK_PARAMETERS_V2 v2; 771 PIXEL_CLOCK_PARAMETERS_V3 v3; 772 PIXEL_CLOCK_PARAMETERS_V5 v5; 773 PIXEL_CLOCK_PARAMETERS_V6 v6; 774}; 775 776/* on DCE5, make sure the voltage is high enough to support the 777 * required disp clk. 778 */ 779static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev, 780 u32 dispclk) 781{ 782 u8 frev, crev; 783 int index; 784 union set_pixel_clock args; 785 786 memset(&args, 0, sizeof(args)); 787 788 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 789 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 790 &crev)) 791 return; 792 793 switch (frev) { 794 case 1: 795 switch (crev) { 796 case 5: 797 /* if the default dcpll clock is specified, 798 * SetPixelClock provides the dividers 799 */ 800 args.v5.ucCRTC = ATOM_CRTC_INVALID; 801 args.v5.usPixelClock = cpu_to_le16(dispclk); 802 args.v5.ucPpll = ATOM_DCPLL; 803 break; 804 case 6: 805 /* if the default dcpll clock is specified, 806 * SetPixelClock provides the dividers 807 */ 808 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); 809 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev)) 810 args.v6.ucPpll = ATOM_EXT_PLL1; 811 else if (ASIC_IS_DCE6(rdev)) 812 args.v6.ucPpll = ATOM_PPLL0; 813 else 814 args.v6.ucPpll = ATOM_DCPLL; 815 break; 816 default: 817 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 818 return; 819 } 820 break; 821 default: 822 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 823 return; 824 } 825 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 826} 827 828static void atombios_crtc_program_pll(struct drm_crtc *crtc, 829 u32 crtc_id, 830 int pll_id, 831 u32 encoder_mode, 832 u32 encoder_id, 833 u32 clock, 834 u32 ref_div, 835 u32 fb_div, 836 u32 frac_fb_div, 837 u32 post_div, 838 int bpc, 839 bool ss_enabled, 840 struct radeon_atom_ss *ss) 841{ 842 struct drm_device *dev = crtc->dev; 843 struct radeon_device *rdev = dev->dev_private; 844 u8 frev, crev; 845 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); 846 union set_pixel_clock args; 847 848 memset(&args, 0, sizeof(args)); 849 850 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, 851 &crev)) 852 return; 853 854 switch (frev) { 855 case 1: 856 switch (crev) { 857 case 1: 858 if (clock == ATOM_DISABLE) 859 return; 860 args.v1.usPixelClock = cpu_to_le16(clock / 10); 861 args.v1.usRefDiv = cpu_to_le16(ref_div); 862 args.v1.usFbDiv = cpu_to_le16(fb_div); 863 args.v1.ucFracFbDiv = frac_fb_div; 864 args.v1.ucPostDiv = post_div; 865 args.v1.ucPpll = pll_id; 866 args.v1.ucCRTC = crtc_id; 867 args.v1.ucRefDivSrc = 1; 868 break; 869 case 2: 870 args.v2.usPixelClock = cpu_to_le16(clock / 10); 871 args.v2.usRefDiv = cpu_to_le16(ref_div); 872 args.v2.usFbDiv = cpu_to_le16(fb_div); 873 args.v2.ucFracFbDiv = frac_fb_div; 874 args.v2.ucPostDiv = post_div; 875 args.v2.ucPpll = pll_id; 876 args.v2.ucCRTC = crtc_id; 877 args.v2.ucRefDivSrc = 1; 878 break; 879 case 3: 880 args.v3.usPixelClock = cpu_to_le16(clock / 10); 881 args.v3.usRefDiv = cpu_to_le16(ref_div); 882 args.v3.usFbDiv = cpu_to_le16(fb_div); 883 args.v3.ucFracFbDiv = frac_fb_div; 884 args.v3.ucPostDiv = post_div; 885 args.v3.ucPpll = pll_id; 886 if (crtc_id == ATOM_CRTC2) 887 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2; 888 else 889 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1; 890 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 891 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC; 892 args.v3.ucTransmitterId = encoder_id; 893 args.v3.ucEncoderMode = encoder_mode; 894 break; 895 case 5: 896 args.v5.ucCRTC = crtc_id; 897 args.v5.usPixelClock = cpu_to_le16(clock / 10); 898 args.v5.ucRefDiv = ref_div; 899 args.v5.usFbDiv = cpu_to_le16(fb_div); 900 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 901 args.v5.ucPostDiv = post_div; 902 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */ 903 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 904 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC; 905 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 906 switch (bpc) { 907 case 8: 908 default: 909 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP; 910 break; 911 case 10: 912 /* yes this is correct, the atom define is wrong */ 913 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP; 914 break; 915 case 12: 916 /* yes this is correct, the atom define is wrong */ 917 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP; 918 break; 919 } 920 } 921 args.v5.ucTransmitterID = encoder_id; 922 args.v5.ucEncoderMode = encoder_mode; 923 args.v5.ucPpll = pll_id; 924 break; 925 case 6: 926 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10); 927 args.v6.ucRefDiv = ref_div; 928 args.v6.usFbDiv = cpu_to_le16(fb_div); 929 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000); 930 args.v6.ucPostDiv = post_div; 931 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */ 932 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) 933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC; 934 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) { 935 switch (bpc) { 936 case 8: 937 default: 938 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP; 939 break; 940 case 10: 941 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6; 942 break; 943 case 12: 944 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6; 945 break; 946 case 16: 947 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP; 948 break; 949 } 950 } 951 args.v6.ucTransmitterID = encoder_id; 952 args.v6.ucEncoderMode = encoder_mode; 953 args.v6.ucPpll = pll_id; 954 break; 955 default: 956 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 957 return; 958 } 959 break; 960 default: 961 DRM_ERROR("Unknown table version %d %d\n", frev, crev); 962 return; 963 } 964 965 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 966} 967 968static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 969{ 970 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 971 struct drm_device *dev = crtc->dev; 972 struct radeon_device *rdev = dev->dev_private; 973 struct radeon_encoder *radeon_encoder = 974 to_radeon_encoder(radeon_crtc->encoder); 975 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 976 977 radeon_crtc->bpc = 8; 978 radeon_crtc->ss_enabled = false; 979 980 if (radeon_encoder->is_mst_encoder) { 981 radeon_dp_mst_prepare_pll(crtc, mode); 982 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || 983 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) { 984 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 985 struct drm_connector *connector = 986 radeon_get_connector_for_encoder(radeon_crtc->encoder); 987 struct radeon_connector *radeon_connector = 988 to_radeon_connector(connector); 989 struct radeon_connector_atom_dig *dig_connector = 990 radeon_connector->con_priv; 991 int dp_clock; 992 993 /* Assign mode clock for hdmi deep color max clock limit check */ 994 radeon_connector->pixelclock_for_modeset = mode->clock; 995 radeon_crtc->bpc = radeon_get_monitor_bpc(connector); 996 997 switch (encoder_mode) { 998 case ATOM_ENCODER_MODE_DP_MST: 999 case ATOM_ENCODER_MODE_DP: 1000 /* DP/eDP */ 1001 dp_clock = dig_connector->dp_clock / 10; 1002 if (ASIC_IS_DCE4(rdev)) 1003 radeon_crtc->ss_enabled = 1004 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss, 1005 ASIC_INTERNAL_SS_ON_DP, 1006 dp_clock); 1007 else { 1008 if (dp_clock == 16200) { 1009 radeon_crtc->ss_enabled = 1010 radeon_atombios_get_ppll_ss_info(rdev, 1011 &radeon_crtc->ss, 1012 ATOM_DP_SS_ID2); 1013 if (!radeon_crtc->ss_enabled) 1014 radeon_crtc->ss_enabled = 1015 radeon_atombios_get_ppll_ss_info(rdev, 1016 &radeon_crtc->ss, 1017 ATOM_DP_SS_ID1); 1018 } else { 1019 radeon_crtc->ss_enabled = 1020 radeon_atombios_get_ppll_ss_info(rdev, 1021 &radeon_crtc->ss, 1022 ATOM_DP_SS_ID1); 1023 } 1024 /* disable spread spectrum on DCE3 DP */ 1025 radeon_crtc->ss_enabled = false; 1026 } 1027 break; 1028 case ATOM_ENCODER_MODE_LVDS: 1029 if (ASIC_IS_DCE4(rdev)) 1030 radeon_crtc->ss_enabled = 1031 radeon_atombios_get_asic_ss_info(rdev, 1032 &radeon_crtc->ss, 1033 dig->lcd_ss_id, 1034 mode->clock / 10); 1035 else 1036 radeon_crtc->ss_enabled = 1037 radeon_atombios_get_ppll_ss_info(rdev, 1038 &radeon_crtc->ss, 1039 dig->lcd_ss_id); 1040 break; 1041 case ATOM_ENCODER_MODE_DVI: 1042 if (ASIC_IS_DCE4(rdev)) 1043 radeon_crtc->ss_enabled = 1044 radeon_atombios_get_asic_ss_info(rdev, 1045 &radeon_crtc->ss, 1046 ASIC_INTERNAL_SS_ON_TMDS, 1047 mode->clock / 10); 1048 break; 1049 case ATOM_ENCODER_MODE_HDMI: 1050 if (ASIC_IS_DCE4(rdev)) 1051 radeon_crtc->ss_enabled = 1052 radeon_atombios_get_asic_ss_info(rdev, 1053 &radeon_crtc->ss, 1054 ASIC_INTERNAL_SS_ON_HDMI, 1055 mode->clock / 10); 1056 break; 1057 default: 1058 break; 1059 } 1060 } 1061 1062 /* adjust pixel clock as needed */ 1063 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode); 1064 1065 return true; 1066} 1067 1068static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) 1069{ 1070 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1071 struct drm_device *dev = crtc->dev; 1072 struct radeon_device *rdev = dev->dev_private; 1073 struct radeon_encoder *radeon_encoder = 1074 to_radeon_encoder(radeon_crtc->encoder); 1075 u32 pll_clock = mode->clock; 1076 u32 clock = mode->clock; 1077 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; 1078 struct radeon_pll *pll; 1079 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder); 1080 1081 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */ 1082 if (ASIC_IS_DCE5(rdev) && 1083 (encoder_mode == ATOM_ENCODER_MODE_HDMI) && 1084 (radeon_crtc->bpc > 8)) 1085 clock = radeon_crtc->adjusted_clock; 1086 1087 switch (radeon_crtc->pll_id) { 1088 case ATOM_PPLL1: 1089 pll = &rdev->clock.p1pll; 1090 break; 1091 case ATOM_PPLL2: 1092 pll = &rdev->clock.p2pll; 1093 break; 1094 case ATOM_DCPLL: 1095 case ATOM_PPLL_INVALID: 1096 default: 1097 pll = &rdev->clock.dcpll; 1098 break; 1099 } 1100 1101 /* update pll params */ 1102 pll->flags = radeon_crtc->pll_flags; 1103 pll->reference_div = radeon_crtc->pll_reference_div; 1104 pll->post_div = radeon_crtc->pll_post_div; 1105 1106 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) 1107 /* TV seems to prefer the legacy algo on some boards */ 1108 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1109 &fb_div, &frac_fb_div, &ref_div, &post_div); 1110 else if (ASIC_IS_AVIVO(rdev)) 1111 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, 1112 &fb_div, &frac_fb_div, &ref_div, &post_div); 1113 else 1114 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, 1115 &fb_div, &frac_fb_div, &ref_div, &post_div); 1116 1117 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, 1118 radeon_crtc->crtc_id, &radeon_crtc->ss); 1119 1120 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 1121 encoder_mode, radeon_encoder->encoder_id, clock, 1122 ref_div, fb_div, frac_fb_div, post_div, 1123 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss); 1124 1125 if (radeon_crtc->ss_enabled) { 1126 /* calculate ss amount and step size */ 1127 if (ASIC_IS_DCE4(rdev)) { 1128 u32 step_size; 1129 u32 amount = (((fb_div * 10) + frac_fb_div) * 1130 (u32)radeon_crtc->ss.percentage) / 1131 (100 * (u32)radeon_crtc->ss.percentage_divider); 1132 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK; 1133 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) & 1134 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK; 1135 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD) 1136 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1137 (125 * 25 * pll->reference_freq / 100); 1138 else 1139 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / 1140 (125 * 25 * pll->reference_freq / 100); 1141 radeon_crtc->ss.step = step_size; 1142 } 1143 1144 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, 1145 radeon_crtc->crtc_id, &radeon_crtc->ss); 1146 } 1147} 1148 1149static int dce4_crtc_do_set_base(struct drm_crtc *crtc, 1150 struct drm_framebuffer *fb, 1151 int x, int y, int atomic) 1152{ 1153 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1154 struct drm_device *dev = crtc->dev; 1155 struct radeon_device *rdev = dev->dev_private; 1156 struct drm_framebuffer *target_fb; 1157 struct drm_gem_object *obj; 1158 struct radeon_bo *rbo; 1159 uint64_t fb_location; 1160 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1161 unsigned bankw, bankh, mtaspect, tile_split; 1162 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1163 u32 tmp, viewport_w, viewport_h; 1164 int r; 1165 bool bypass_lut = false; 1166 struct drm_format_name_buf format_name; 1167 1168 /* no fb bound */ 1169 if (!atomic && !crtc->primary->fb) { 1170 DRM_DEBUG_KMS("No FB bound\n"); 1171 return 0; 1172 } 1173 1174 if (atomic) 1175 target_fb = fb; 1176 else 1177 target_fb = crtc->primary->fb; 1178 1179 /* If atomic, assume fb object is pinned & idle & fenced and 1180 * just update base pointers 1181 */ 1182 obj = target_fb->obj[0]; 1183 rbo = gem_to_radeon_bo(obj); 1184 1185 if (atomic) { 1186 BUG_ON(rbo->pin_count == 0); 1187 fb_location = radeon_bo_gpu_offset(rbo); 1188 tiling_flags = 0; 1189 } else { 1190 r = radeon_bo_reserve(rbo, false); 1191 if (unlikely(r != 0)) 1192 return r; 1193 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1194 if (unlikely(r != 0)) { 1195 radeon_bo_unreserve(rbo); 1196 return -EINVAL; 1197 } 1198 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1199 radeon_bo_unreserve(rbo); 1200 } 1201 1202 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1203 radeon_bo_unreserve(rbo); 1204 1205 switch (target_fb->format->format) { 1206 case DRM_FORMAT_C8: 1207 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) | 1208 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED)); 1209 break; 1210 case DRM_FORMAT_XRGB4444: 1211 case DRM_FORMAT_ARGB4444: 1212 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1213 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444)); 1214#ifdef __BIG_ENDIAN 1215 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1216#endif 1217 break; 1218 case DRM_FORMAT_XRGB1555: 1219 case DRM_FORMAT_ARGB1555: 1220 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1221 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555)); 1222#ifdef __BIG_ENDIAN 1223 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1224#endif 1225 break; 1226 case DRM_FORMAT_BGRX5551: 1227 case DRM_FORMAT_BGRA5551: 1228 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1229 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551)); 1230#ifdef __BIG_ENDIAN 1231 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1232#endif 1233 break; 1234 case DRM_FORMAT_RGB565: 1235 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) | 1236 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565)); 1237#ifdef __BIG_ENDIAN 1238 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16); 1239#endif 1240 break; 1241 case DRM_FORMAT_XRGB8888: 1242 case DRM_FORMAT_ARGB8888: 1243 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1244 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1245#ifdef __BIG_ENDIAN 1246 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1247#endif 1248 break; 1249 case DRM_FORMAT_XRGB2101010: 1250 case DRM_FORMAT_ARGB2101010: 1251 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1252 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010)); 1253#ifdef __BIG_ENDIAN 1254 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1255#endif 1256 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1257 bypass_lut = true; 1258 break; 1259 case DRM_FORMAT_BGRX1010102: 1260 case DRM_FORMAT_BGRA1010102: 1261 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1262 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102)); 1263#ifdef __BIG_ENDIAN 1264 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1265#endif 1266 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1267 bypass_lut = true; 1268 break; 1269 case DRM_FORMAT_XBGR8888: 1270 case DRM_FORMAT_ABGR8888: 1271 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | 1272 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); 1273 fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) | 1274 EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R)); 1275#ifdef __BIG_ENDIAN 1276 fb_swap |= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); 1277#endif 1278 break; 1279 default: 1280 DRM_ERROR("Unsupported screen format %s\n", 1281 drm_get_format_name(target_fb->format->format, &format_name)); 1282 return -EINVAL; 1283 } 1284 1285 if (tiling_flags & RADEON_TILING_MACRO) { 1286 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); 1287 1288 /* Set NUM_BANKS. */ 1289 if (rdev->family >= CHIP_TAHITI) { 1290 unsigned index, num_banks; 1291 1292 if (rdev->family >= CHIP_BONAIRE) { 1293 unsigned tileb, tile_split_bytes; 1294 1295 /* Calculate the macrotile mode index. */ 1296 tile_split_bytes = 64 << tile_split; 1297 tileb = 8 * 8 * target_fb->format->cpp[0]; 1298 tileb = min(tile_split_bytes, tileb); 1299 1300 for (index = 0; tileb > 64; index++) 1301 tileb >>= 1; 1302 1303 if (index >= 16) { 1304 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n", 1305 target_fb->format->cpp[0] * 8, 1306 tile_split); 1307 return -EINVAL; 1308 } 1309 1310 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; 1311 } else { 1312 switch (target_fb->format->cpp[0] * 8) { 1313 case 8: 1314 index = 10; 1315 break; 1316 case 16: 1317 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP; 1318 break; 1319 default: 1320 case 32: 1321 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP; 1322 break; 1323 } 1324 1325 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; 1326 } 1327 1328 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); 1329 } else { 1330 /* NI and older. */ 1331 if (rdev->family >= CHIP_CAYMAN) 1332 tmp = rdev->config.cayman.tile_config; 1333 else 1334 tmp = rdev->config.evergreen.tile_config; 1335 1336 switch ((tmp & 0xf0) >> 4) { 1337 case 0: /* 4 banks */ 1338 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK); 1339 break; 1340 case 1: /* 8 banks */ 1341 default: 1342 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK); 1343 break; 1344 case 2: /* 16 banks */ 1345 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK); 1346 break; 1347 } 1348 } 1349 1350 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1); 1351 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split); 1352 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); 1353 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh); 1354 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect); 1355 if (rdev->family >= CHIP_BONAIRE) { 1356 /* XXX need to know more about the surface tiling mode */ 1357 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING); 1358 } 1359 } else if (tiling_flags & RADEON_TILING_MICRO) 1360 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); 1361 1362 if (rdev->family >= CHIP_BONAIRE) { 1363 /* Read the pipe config from the 2D TILED SCANOUT mode. 1364 * It should be the same for the other modes too, but not all 1365 * modes set the pipe config field. */ 1366 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f; 1367 1368 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config); 1369 } else if ((rdev->family == CHIP_TAHITI) || 1370 (rdev->family == CHIP_PITCAIRN)) 1371 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16); 1372 else if ((rdev->family == CHIP_VERDE) || 1373 (rdev->family == CHIP_OLAND) || 1374 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */ 1375 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16); 1376 1377 switch (radeon_crtc->crtc_id) { 1378 case 0: 1379 WREG32(AVIVO_D1VGA_CONTROL, 0); 1380 break; 1381 case 1: 1382 WREG32(AVIVO_D2VGA_CONTROL, 0); 1383 break; 1384 case 2: 1385 WREG32(EVERGREEN_D3VGA_CONTROL, 0); 1386 break; 1387 case 3: 1388 WREG32(EVERGREEN_D4VGA_CONTROL, 0); 1389 break; 1390 case 4: 1391 WREG32(EVERGREEN_D5VGA_CONTROL, 0); 1392 break; 1393 case 5: 1394 WREG32(EVERGREEN_D6VGA_CONTROL, 0); 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 /* Make sure surface address is updated at vertical blank rather than 1401 * horizontal blank 1402 */ 1403 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1404 1405 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1406 upper_32_bits(fb_location)); 1407 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, 1408 upper_32_bits(fb_location)); 1409 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1410 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1411 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1412 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK); 1413 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1414 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1415 1416 /* 1417 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT 1418 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to 1419 * retain the full precision throughout the pipeline. 1420 */ 1421 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, 1422 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0), 1423 ~EVERGREEN_LUT_10BIT_BYPASS_EN); 1424 1425 if (bypass_lut) 1426 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1427 1428 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1429 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1430 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); 1431 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1432 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1433 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1434 1435 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1436 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1437 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1438 1439 if (rdev->family >= CHIP_BONAIRE) 1440 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1441 target_fb->height); 1442 else 1443 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1444 target_fb->height); 1445 x &= ~3; 1446 y &= ~1; 1447 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1448 (x << 16) | y); 1449 viewport_w = crtc->mode.hdisplay; 1450 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1451 if ((rdev->family >= CHIP_BONAIRE) && 1452 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)) 1453 viewport_h *= 2; 1454 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1455 (viewport_w << 16) | viewport_h); 1456 1457 /* set pageflip to happen anywhere in vblank interval */ 1458 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); 1459 1460 if (!atomic && fb && fb != crtc->primary->fb) { 1461 rbo = gem_to_radeon_bo(fb->obj[0]); 1462 r = radeon_bo_reserve(rbo, false); 1463 if (unlikely(r != 0)) 1464 return r; 1465 radeon_bo_unpin(rbo); 1466 radeon_bo_unreserve(rbo); 1467 } 1468 1469 /* Bytes per pixel may have changed */ 1470 radeon_bandwidth_update(rdev); 1471 1472 return 0; 1473} 1474 1475static int avivo_crtc_do_set_base(struct drm_crtc *crtc, 1476 struct drm_framebuffer *fb, 1477 int x, int y, int atomic) 1478{ 1479 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1480 struct drm_device *dev = crtc->dev; 1481 struct radeon_device *rdev = dev->dev_private; 1482 struct drm_gem_object *obj; 1483 struct radeon_bo *rbo; 1484 struct drm_framebuffer *target_fb; 1485 uint64_t fb_location; 1486 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1487 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1488 u32 viewport_w, viewport_h; 1489 int r; 1490 bool bypass_lut = false; 1491 struct drm_format_name_buf format_name; 1492 1493 /* no fb bound */ 1494 if (!atomic && !crtc->primary->fb) { 1495 DRM_DEBUG_KMS("No FB bound\n"); 1496 return 0; 1497 } 1498 1499 if (atomic) 1500 target_fb = fb; 1501 else 1502 target_fb = crtc->primary->fb; 1503 1504 obj = target_fb->obj[0]; 1505 rbo = gem_to_radeon_bo(obj); 1506 1507 /* If atomic, assume fb object is pinned & idle & fenced and 1508 * just update base pointers 1509 */ 1510 if (atomic) { 1511 BUG_ON(rbo->pin_count == 0); 1512 fb_location = radeon_bo_gpu_offset(rbo); 1513 tiling_flags = 0; 1514 } else { 1515 r = radeon_bo_reserve(rbo, false); 1516 if (unlikely(r != 0)) 1517 return r; 1518 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); 1519 if (unlikely(r != 0)) { 1520 radeon_bo_unreserve(rbo); 1521 return -EINVAL; 1522 } 1523 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); 1524 radeon_bo_unreserve(rbo); 1525 } 1526 1527 switch (target_fb->format->format) { 1528 case DRM_FORMAT_C8: 1529 fb_format = 1530 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | 1531 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; 1532 break; 1533 case DRM_FORMAT_XRGB4444: 1534 case DRM_FORMAT_ARGB4444: 1535 fb_format = 1536 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1537 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444; 1538#ifdef __BIG_ENDIAN 1539 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1540#endif 1541 break; 1542 case DRM_FORMAT_XRGB1555: 1543 fb_format = 1544 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1545 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; 1546#ifdef __BIG_ENDIAN 1547 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1548#endif 1549 break; 1550 case DRM_FORMAT_RGB565: 1551 fb_format = 1552 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | 1553 AVIVO_D1GRPH_CONTROL_16BPP_RGB565; 1554#ifdef __BIG_ENDIAN 1555 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; 1556#endif 1557 break; 1558 case DRM_FORMAT_XRGB8888: 1559 case DRM_FORMAT_ARGB8888: 1560 fb_format = 1561 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1562 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1563#ifdef __BIG_ENDIAN 1564 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1565#endif 1566 break; 1567 case DRM_FORMAT_XRGB2101010: 1568 case DRM_FORMAT_ARGB2101010: 1569 fb_format = 1570 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1571 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010; 1572#ifdef __BIG_ENDIAN 1573 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; 1574#endif 1575 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ 1576 bypass_lut = true; 1577 break; 1578 case DRM_FORMAT_XBGR8888: 1579 case DRM_FORMAT_ABGR8888: 1580 fb_format = 1581 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | 1582 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; 1583 if (rdev->family >= CHIP_R600) 1584 fb_swap = 1585 (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) | 1586 R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_R)); 1587 else /* DCE1 (R5xx) */ 1588 fb_format |= AVIVO_D1GRPH_SWAP_RB; 1589#ifdef __BIG_ENDIAN 1590 fb_swap |= R600_D1GRPH_SWAP_ENDIAN_32BIT; 1591#endif 1592 break; 1593 default: 1594 DRM_ERROR("Unsupported screen format %s\n", 1595 drm_get_format_name(target_fb->format->format, &format_name)); 1596 return -EINVAL; 1597 } 1598 1599 if (rdev->family >= CHIP_R600) { 1600 if (tiling_flags & RADEON_TILING_MACRO) 1601 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1; 1602 else if (tiling_flags & RADEON_TILING_MICRO) 1603 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1; 1604 } else { 1605 if (tiling_flags & RADEON_TILING_MACRO) 1606 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; 1607 1608 if (tiling_flags & RADEON_TILING_MICRO) 1609 fb_format |= AVIVO_D1GRPH_TILED; 1610 } 1611 1612 if (radeon_crtc->crtc_id == 0) 1613 WREG32(AVIVO_D1VGA_CONTROL, 0); 1614 else 1615 WREG32(AVIVO_D2VGA_CONTROL, 0); 1616 1617 /* Make sure surface address is update at vertical blank rather than 1618 * horizontal blank 1619 */ 1620 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); 1621 1622 if (rdev->family >= CHIP_RV770) { 1623 if (radeon_crtc->crtc_id) { 1624 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1625 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1626 } else { 1627 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1628 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location)); 1629 } 1630 } 1631 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, 1632 (u32) fb_location); 1633 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + 1634 radeon_crtc->crtc_offset, (u32) fb_location); 1635 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); 1636 if (rdev->family >= CHIP_R600) 1637 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); 1638 1639 /* LUT only has 256 slots for 8 bpc fb. Bypass for > 8 bpc scanout for precision */ 1640 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, 1641 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN); 1642 1643 if (bypass_lut) 1644 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); 1645 1646 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); 1647 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); 1648 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); 1649 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); 1650 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); 1651 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); 1652 1653 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; 1654 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); 1655 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); 1656 1657 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, 1658 target_fb->height); 1659 x &= ~3; 1660 y &= ~1; 1661 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1662 (x << 16) | y); 1663 viewport_w = crtc->mode.hdisplay; 1664 viewport_h = (crtc->mode.vdisplay + 1) & ~1; 1665 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1666 (viewport_w << 16) | viewport_h); 1667 1668 /* set pageflip to happen only at start of vblank interval (front porch) */ 1669 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); 1670 1671 if (!atomic && fb && fb != crtc->primary->fb) { 1672 rbo = gem_to_radeon_bo(fb->obj[0]); 1673 r = radeon_bo_reserve(rbo, false); 1674 if (unlikely(r != 0)) 1675 return r; 1676 radeon_bo_unpin(rbo); 1677 radeon_bo_unreserve(rbo); 1678 } 1679 1680 /* Bytes per pixel may have changed */ 1681 radeon_bandwidth_update(rdev); 1682 1683 return 0; 1684} 1685 1686int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, 1687 struct drm_framebuffer *old_fb) 1688{ 1689 struct drm_device *dev = crtc->dev; 1690 struct radeon_device *rdev = dev->dev_private; 1691 1692 if (ASIC_IS_DCE4(rdev)) 1693 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0); 1694 else if (ASIC_IS_AVIVO(rdev)) 1695 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0); 1696 else 1697 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0); 1698} 1699 1700int atombios_crtc_set_base_atomic(struct drm_crtc *crtc, 1701 struct drm_framebuffer *fb, 1702 int x, int y, enum mode_set_atomic state) 1703{ 1704 struct drm_device *dev = crtc->dev; 1705 struct radeon_device *rdev = dev->dev_private; 1706 1707 if (ASIC_IS_DCE4(rdev)) 1708 return dce4_crtc_do_set_base(crtc, fb, x, y, 1); 1709 else if (ASIC_IS_AVIVO(rdev)) 1710 return avivo_crtc_do_set_base(crtc, fb, x, y, 1); 1711 else 1712 return radeon_crtc_do_set_base(crtc, fb, x, y, 1); 1713} 1714 1715/* properly set additional regs when using atombios */ 1716static void radeon_legacy_atom_fixup(struct drm_crtc *crtc) 1717{ 1718 struct drm_device *dev = crtc->dev; 1719 struct radeon_device *rdev = dev->dev_private; 1720 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1721 u32 disp_merge_cntl; 1722 1723 switch (radeon_crtc->crtc_id) { 1724 case 0: 1725 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL); 1726 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN; 1727 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl); 1728 break; 1729 case 1: 1730 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL); 1731 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN; 1732 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl); 1733 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID)); 1734 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID)); 1735 break; 1736 } 1737} 1738 1739/** 1740 * radeon_get_pll_use_mask - look up a mask of which pplls are in use 1741 * 1742 * @crtc: drm crtc 1743 * 1744 * Returns the mask of which PPLLs (Pixel PLLs) are in use. 1745 */ 1746static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc) 1747{ 1748 struct drm_device *dev = crtc->dev; 1749 struct drm_crtc *test_crtc; 1750 struct radeon_crtc *test_radeon_crtc; 1751 u32 pll_in_use = 0; 1752 1753 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1754 if (crtc == test_crtc) 1755 continue; 1756 1757 test_radeon_crtc = to_radeon_crtc(test_crtc); 1758 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1759 pll_in_use |= (1 << test_radeon_crtc->pll_id); 1760 } 1761 return pll_in_use; 1762} 1763 1764/** 1765 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP 1766 * 1767 * @crtc: drm crtc 1768 * 1769 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 1770 * also in DP mode. For DP, a single PPLL can be used for all DP 1771 * crtcs/encoders. 1772 */ 1773static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc) 1774{ 1775 struct drm_device *dev = crtc->dev; 1776 struct radeon_device *rdev = dev->dev_private; 1777 struct drm_crtc *test_crtc; 1778 struct radeon_crtc *test_radeon_crtc; 1779 1780 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1781 if (crtc == test_crtc) 1782 continue; 1783 test_radeon_crtc = to_radeon_crtc(test_crtc); 1784 if (test_radeon_crtc->encoder && 1785 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1786 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1787 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1788 test_radeon_crtc->pll_id == ATOM_PPLL2) 1789 continue; 1790 /* for DP use the same PLL for all */ 1791 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1792 return test_radeon_crtc->pll_id; 1793 } 1794 } 1795 return ATOM_PPLL_INVALID; 1796} 1797 1798/** 1799 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 1800 * 1801 * @crtc: drm crtc 1802 * @encoder: drm encoder 1803 * 1804 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 1805 * be shared (i.e., same clock). 1806 */ 1807static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc) 1808{ 1809 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1810 struct drm_device *dev = crtc->dev; 1811 struct radeon_device *rdev = dev->dev_private; 1812 struct drm_crtc *test_crtc; 1813 struct radeon_crtc *test_radeon_crtc; 1814 u32 adjusted_clock, test_adjusted_clock; 1815 1816 adjusted_clock = radeon_crtc->adjusted_clock; 1817 1818 if (adjusted_clock == 0) 1819 return ATOM_PPLL_INVALID; 1820 1821 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 1822 if (crtc == test_crtc) 1823 continue; 1824 test_radeon_crtc = to_radeon_crtc(test_crtc); 1825 if (test_radeon_crtc->encoder && 1826 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) { 1827 /* PPLL2 is exclusive to UNIPHYA on DCE61 */ 1828 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) && 1829 test_radeon_crtc->pll_id == ATOM_PPLL2) 1830 continue; 1831 /* check if we are already driving this connector with another crtc */ 1832 if (test_radeon_crtc->connector == radeon_crtc->connector) { 1833 /* if we are, return that pll */ 1834 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID) 1835 return test_radeon_crtc->pll_id; 1836 } 1837 /* for non-DP check the clock */ 1838 test_adjusted_clock = test_radeon_crtc->adjusted_clock; 1839 if ((crtc->mode.clock == test_crtc->mode.clock) && 1840 (adjusted_clock == test_adjusted_clock) && 1841 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) && 1842 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) 1843 return test_radeon_crtc->pll_id; 1844 } 1845 } 1846 return ATOM_PPLL_INVALID; 1847} 1848 1849/** 1850 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc. 1851 * 1852 * @crtc: drm crtc 1853 * 1854 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors 1855 * a single PPLL can be used for all DP crtcs/encoders. For non-DP 1856 * monitors a dedicated PPLL must be used. If a particular board has 1857 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming 1858 * as there is no need to program the PLL itself. If we are not able to 1859 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to 1860 * avoid messing up an existing monitor. 1861 * 1862 * Asic specific PLL information 1863 * 1864 * DCE 8.x 1865 * KB/KV 1866 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) 1867 * CI 1868 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1869 * 1870 * DCE 6.1 1871 * - PPLL2 is only available to UNIPHYA (both DP and non-DP) 1872 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP) 1873 * 1874 * DCE 6.0 1875 * - PPLL0 is available to all UNIPHY (DP only) 1876 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1877 * 1878 * DCE 5.0 1879 * - DCPLL is available to all UNIPHY (DP only) 1880 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1881 * 1882 * DCE 3.0/4.0/4.1 1883 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC 1884 * 1885 */ 1886static int radeon_atom_pick_pll(struct drm_crtc *crtc) 1887{ 1888 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1889 struct drm_device *dev = crtc->dev; 1890 struct radeon_device *rdev = dev->dev_private; 1891 struct radeon_encoder *radeon_encoder = 1892 to_radeon_encoder(radeon_crtc->encoder); 1893 u32 pll_in_use; 1894 int pll; 1895 1896 if (ASIC_IS_DCE8(rdev)) { 1897 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1898 if (rdev->clock.dp_extclk) 1899 /* skip PPLL programming if using ext clock */ 1900 return ATOM_PPLL_INVALID; 1901 else { 1902 /* use the same PPLL for all DP monitors */ 1903 pll = radeon_get_shared_dp_ppll(crtc); 1904 if (pll != ATOM_PPLL_INVALID) 1905 return pll; 1906 } 1907 } else { 1908 /* use the same PPLL for all monitors with the same clock */ 1909 pll = radeon_get_shared_nondp_ppll(crtc); 1910 if (pll != ATOM_PPLL_INVALID) 1911 return pll; 1912 } 1913 /* otherwise, pick one of the plls */ 1914 if ((rdev->family == CHIP_KABINI) || 1915 (rdev->family == CHIP_MULLINS)) { 1916 /* KB/ML has PPLL1 and PPLL2 */ 1917 pll_in_use = radeon_get_pll_use_mask(crtc); 1918 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1919 return ATOM_PPLL2; 1920 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1921 return ATOM_PPLL1; 1922 DRM_ERROR("unable to allocate a PPLL\n"); 1923 return ATOM_PPLL_INVALID; 1924 } else { 1925 /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 1926 pll_in_use = radeon_get_pll_use_mask(crtc); 1927 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1928 return ATOM_PPLL2; 1929 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1930 return ATOM_PPLL1; 1931 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1932 return ATOM_PPLL0; 1933 DRM_ERROR("unable to allocate a PPLL\n"); 1934 return ATOM_PPLL_INVALID; 1935 } 1936 } else if (ASIC_IS_DCE61(rdev)) { 1937 struct radeon_encoder_atom_dig *dig = 1938 radeon_encoder->enc_priv; 1939 1940 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) && 1941 (dig->linkb == false)) 1942 /* UNIPHY A uses PPLL2 */ 1943 return ATOM_PPLL2; 1944 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1945 /* UNIPHY B/C/D/E/F */ 1946 if (rdev->clock.dp_extclk) 1947 /* skip PPLL programming if using ext clock */ 1948 return ATOM_PPLL_INVALID; 1949 else { 1950 /* use the same PPLL for all DP monitors */ 1951 pll = radeon_get_shared_dp_ppll(crtc); 1952 if (pll != ATOM_PPLL_INVALID) 1953 return pll; 1954 } 1955 } else { 1956 /* use the same PPLL for all monitors with the same clock */ 1957 pll = radeon_get_shared_nondp_ppll(crtc); 1958 if (pll != ATOM_PPLL_INVALID) 1959 return pll; 1960 } 1961 /* UNIPHY B/C/D/E/F */ 1962 pll_in_use = radeon_get_pll_use_mask(crtc); 1963 if (!(pll_in_use & (1 << ATOM_PPLL0))) 1964 return ATOM_PPLL0; 1965 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1966 return ATOM_PPLL1; 1967 DRM_ERROR("unable to allocate a PPLL\n"); 1968 return ATOM_PPLL_INVALID; 1969 } else if (ASIC_IS_DCE41(rdev)) { 1970 /* Don't share PLLs on DCE4.1 chips */ 1971 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1972 if (rdev->clock.dp_extclk) 1973 /* skip PPLL programming if using ext clock */ 1974 return ATOM_PPLL_INVALID; 1975 } 1976 pll_in_use = radeon_get_pll_use_mask(crtc); 1977 if (!(pll_in_use & (1 << ATOM_PPLL1))) 1978 return ATOM_PPLL1; 1979 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1980 return ATOM_PPLL2; 1981 DRM_ERROR("unable to allocate a PPLL\n"); 1982 return ATOM_PPLL_INVALID; 1983 } else if (ASIC_IS_DCE4(rdev)) { 1984 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, 1985 * depending on the asic: 1986 * DCE4: PPLL or ext clock 1987 * DCE5: PPLL, DCPLL, or ext clock 1988 * DCE6: PPLL, PPLL0, or ext clock 1989 * 1990 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip 1991 * PPLL/DCPLL programming and only program the DP DTO for the 1992 * crtc virtual pixel clock. 1993 */ 1994 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { 1995 if (rdev->clock.dp_extclk) 1996 /* skip PPLL programming if using ext clock */ 1997 return ATOM_PPLL_INVALID; 1998 else if (ASIC_IS_DCE6(rdev)) 1999 /* use PPLL0 for all DP */ 2000 return ATOM_PPLL0; 2001 else if (ASIC_IS_DCE5(rdev)) 2002 /* use DCPLL for all DP */ 2003 return ATOM_DCPLL; 2004 else { 2005 /* use the same PPLL for all DP monitors */ 2006 pll = radeon_get_shared_dp_ppll(crtc); 2007 if (pll != ATOM_PPLL_INVALID) 2008 return pll; 2009 } 2010 } else { 2011 /* use the same PPLL for all monitors with the same clock */ 2012 pll = radeon_get_shared_nondp_ppll(crtc); 2013 if (pll != ATOM_PPLL_INVALID) 2014 return pll; 2015 } 2016 /* all other cases */ 2017 pll_in_use = radeon_get_pll_use_mask(crtc); 2018 if (!(pll_in_use & (1 << ATOM_PPLL1))) 2019 return ATOM_PPLL1; 2020 if (!(pll_in_use & (1 << ATOM_PPLL2))) 2021 return ATOM_PPLL2; 2022 DRM_ERROR("unable to allocate a PPLL\n"); 2023 return ATOM_PPLL_INVALID; 2024 } else { 2025 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */ 2026 /* some atombios (observed in some DCE2/DCE3) code have a bug, 2027 * the matching btw pll and crtc is done through 2028 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the 2029 * pll (1 or 2) to select which register to write. ie if using 2030 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2 2031 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to 2032 * choose which value to write. Which is reverse order from 2033 * register logic. So only case that works is when pllid is 2034 * same as crtcid or when both pll and crtc are enabled and 2035 * both use same clock. 2036 * 2037 * So just return crtc id as if crtc and pll were hard linked 2038 * together even if they aren't 2039 */ 2040 return radeon_crtc->crtc_id; 2041 } 2042} 2043 2044void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev) 2045{ 2046 /* always set DCPLL */ 2047 if (ASIC_IS_DCE6(rdev)) 2048 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2049 else if (ASIC_IS_DCE4(rdev)) { 2050 struct radeon_atom_ss ss; 2051 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss, 2052 ASIC_INTERNAL_SS_ON_DCPLL, 2053 rdev->clock.default_dispclk); 2054 if (ss_enabled) 2055 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss); 2056 /* XXX: DCE5, make sure voltage, dispclk is high enough */ 2057 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk); 2058 if (ss_enabled) 2059 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss); 2060 } 2061 2062} 2063 2064int atombios_crtc_mode_set(struct drm_crtc *crtc, 2065 struct drm_display_mode *mode, 2066 struct drm_display_mode *adjusted_mode, 2067 int x, int y, struct drm_framebuffer *old_fb) 2068{ 2069 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2070 struct drm_device *dev = crtc->dev; 2071 struct radeon_device *rdev = dev->dev_private; 2072 struct radeon_encoder *radeon_encoder = 2073 to_radeon_encoder(radeon_crtc->encoder); 2074 bool is_tvcv = false; 2075 2076 if (radeon_encoder->active_device & 2077 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) 2078 is_tvcv = true; 2079 2080 if (!radeon_crtc->adjusted_clock) 2081 return -EINVAL; 2082 2083 atombios_crtc_set_pll(crtc, adjusted_mode); 2084 2085 if (ASIC_IS_DCE4(rdev)) 2086 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2087 else if (ASIC_IS_AVIVO(rdev)) { 2088 if (is_tvcv) 2089 atombios_crtc_set_timing(crtc, adjusted_mode); 2090 else 2091 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2092 } else { 2093 atombios_crtc_set_timing(crtc, adjusted_mode); 2094 if (radeon_crtc->crtc_id == 0) 2095 atombios_set_crtc_dtd_timing(crtc, adjusted_mode); 2096 radeon_legacy_atom_fixup(crtc); 2097 } 2098 atombios_crtc_set_base(crtc, x, y, old_fb); 2099 atombios_overscan_setup(crtc, mode, adjusted_mode); 2100 atombios_scaler_setup(crtc); 2101 radeon_cursor_reset(crtc); 2102 /* update the hw version fpr dpm */ 2103 radeon_crtc->hw_mode = *adjusted_mode; 2104 2105 return 0; 2106} 2107 2108static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, 2109 const struct drm_display_mode *mode, 2110 struct drm_display_mode *adjusted_mode) 2111{ 2112 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2113 struct drm_device *dev = crtc->dev; 2114 struct drm_encoder *encoder; 2115 2116 /* assign the encoder to the radeon crtc to avoid repeated lookups later */ 2117 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 2118 if (encoder->crtc == crtc) { 2119 radeon_crtc->encoder = encoder; 2120 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder); 2121 break; 2122 } 2123 } 2124 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) { 2125 radeon_crtc->encoder = NULL; 2126 radeon_crtc->connector = NULL; 2127 return false; 2128 } 2129 if (radeon_crtc->encoder) { 2130 struct radeon_encoder *radeon_encoder = 2131 to_radeon_encoder(radeon_crtc->encoder); 2132 2133 radeon_crtc->output_csc = radeon_encoder->output_csc; 2134 } 2135 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) 2136 return false; 2137 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode)) 2138 return false; 2139 /* pick pll */ 2140 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc); 2141 /* if we can't get a PPLL for a non-DP encoder, fail */ 2142 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) && 2143 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) 2144 return false; 2145 2146 return true; 2147} 2148 2149static void atombios_crtc_prepare(struct drm_crtc *crtc) 2150{ 2151 struct drm_device *dev = crtc->dev; 2152 struct radeon_device *rdev = dev->dev_private; 2153 2154 /* disable crtc pair power gating before programming */ 2155 if (ASIC_IS_DCE6(rdev)) 2156 atombios_powergate_crtc(crtc, ATOM_DISABLE); 2157 2158 atombios_lock_crtc(crtc, ATOM_ENABLE); 2159 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2160} 2161 2162static void atombios_crtc_commit(struct drm_crtc *crtc) 2163{ 2164 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); 2165 atombios_lock_crtc(crtc, ATOM_DISABLE); 2166} 2167 2168static void atombios_crtc_disable(struct drm_crtc *crtc) 2169{ 2170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 2171 struct drm_device *dev = crtc->dev; 2172 struct radeon_device *rdev = dev->dev_private; 2173 struct radeon_atom_ss ss; 2174 int i; 2175 2176 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); 2177 if (crtc->primary->fb) { 2178 int r; 2179 struct radeon_bo *rbo; 2180 2181 rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); 2182 r = radeon_bo_reserve(rbo, false); 2183 if (unlikely(r)) 2184 DRM_ERROR("failed to reserve rbo before unpin\n"); 2185 else { 2186 radeon_bo_unpin(rbo); 2187 radeon_bo_unreserve(rbo); 2188 } 2189 } 2190 /* disable the GRPH */ 2191 if (ASIC_IS_DCE4(rdev)) 2192 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2193 else if (ASIC_IS_AVIVO(rdev)) 2194 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); 2195 2196 if (ASIC_IS_DCE6(rdev)) 2197 atombios_powergate_crtc(crtc, ATOM_ENABLE); 2198 2199 for (i = 0; i < rdev->num_crtc; i++) { 2200 if (rdev->mode_info.crtcs[i] && 2201 rdev->mode_info.crtcs[i]->enabled && 2202 i != radeon_crtc->crtc_id && 2203 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) { 2204 /* one other crtc is using this pll don't turn 2205 * off the pll 2206 */ 2207 goto done; 2208 } 2209 } 2210 2211 switch (radeon_crtc->pll_id) { 2212 case ATOM_PPLL1: 2213 case ATOM_PPLL2: 2214 /* disable the ppll */ 2215 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2216 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2217 break; 2218 case ATOM_PPLL0: 2219 /* disable the ppll */ 2220 if ((rdev->family == CHIP_ARUBA) || 2221 (rdev->family == CHIP_KAVERI) || 2222 (rdev->family == CHIP_BONAIRE) || 2223 (rdev->family == CHIP_HAWAII)) 2224 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 2225 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); 2226 break; 2227 default: 2228 break; 2229 } 2230done: 2231 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2232 radeon_crtc->adjusted_clock = 0; 2233 radeon_crtc->encoder = NULL; 2234 radeon_crtc->connector = NULL; 2235} 2236 2237static const struct drm_crtc_helper_funcs atombios_helper_funcs = { 2238 .dpms = atombios_crtc_dpms, 2239 .mode_fixup = atombios_crtc_mode_fixup, 2240 .mode_set = atombios_crtc_mode_set, 2241 .mode_set_base = atombios_crtc_set_base, 2242 .mode_set_base_atomic = atombios_crtc_set_base_atomic, 2243 .prepare = atombios_crtc_prepare, 2244 .commit = atombios_crtc_commit, 2245 .disable = atombios_crtc_disable, 2246}; 2247 2248void radeon_atombios_init_crtc(struct drm_device *dev, 2249 struct radeon_crtc *radeon_crtc) 2250{ 2251 struct radeon_device *rdev = dev->dev_private; 2252 2253 if (ASIC_IS_DCE4(rdev)) { 2254 switch (radeon_crtc->crtc_id) { 2255 case 0: 2256 default: 2257 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; 2258 break; 2259 case 1: 2260 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; 2261 break; 2262 case 2: 2263 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; 2264 break; 2265 case 3: 2266 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; 2267 break; 2268 case 4: 2269 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; 2270 break; 2271 case 5: 2272 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; 2273 break; 2274 } 2275 } else { 2276 if (radeon_crtc->crtc_id == 1) 2277 radeon_crtc->crtc_offset = 2278 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; 2279 else 2280 radeon_crtc->crtc_offset = 0; 2281 } 2282 radeon_crtc->pll_id = ATOM_PPLL_INVALID; 2283 radeon_crtc->adjusted_clock = 0; 2284 radeon_crtc->encoder = NULL; 2285 radeon_crtc->connector = NULL; 2286 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); 2287} 2288