1/* $NetBSD: nouveau_nvkm_engine_gr_ctxgk20a.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $ */ 2 3/* 4 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24#include <sys/cdefs.h> 25__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_gr_ctxgk20a.c,v 1.3 2021/12/18 23:45:36 riastradh Exp $"); 26 27#include "ctxgf100.h" 28#include "gf100.h" 29 30#include <subdev/mc.h> 31 32static void 33gk20a_grctx_generate_main(struct gf100_gr *gr, struct gf100_grctx *info) 34{ 35 struct nvkm_device *device = gr->base.engine.subdev.device; 36 const struct gf100_grctx_func *grctx = gr->func->grctx; 37 u32 idle_timeout; 38 int i; 39 40 gf100_gr_mmio(gr, gr->sw_ctx); 41 42 gf100_gr_wait_idle(gr); 43 44 idle_timeout = nvkm_mask(device, 0x404154, 0xffffffff, 0x00000000); 45 46 grctx->attrib(info); 47 48 grctx->unkn(gr); 49 50 gf100_grctx_generate_floorsweep(gr); 51 52 for (i = 0; i < 8; i++) 53 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); 54 55 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); 56 57 nvkm_mask(device, 0x5044b0, 0x08000000, 0x08000000); 58 59 gf100_gr_wait_idle(gr); 60 61 nvkm_wr32(device, 0x404154, idle_timeout); 62 gf100_gr_wait_idle(gr); 63 64 gf100_gr_mthd(gr, gr->method); 65 gf100_gr_wait_idle(gr); 66 67 gf100_gr_icmd(gr, gr->bundle); 68 grctx->pagepool(info); 69 grctx->bundle(info); 70} 71 72const struct gf100_grctx_func 73gk20a_grctx = { 74 .main = gk20a_grctx_generate_main, 75 .unkn = gk104_grctx_generate_unkn, 76 .bundle = gk104_grctx_generate_bundle, 77 .bundle_size = 0x1800, 78 .bundle_min_gpm_fifo_depth = 0x62, 79 .bundle_token_limit = 0x100, 80 .pagepool = gk104_grctx_generate_pagepool, 81 .pagepool_size = 0x8000, 82 .attrib = gf117_grctx_generate_attrib, 83 .attrib_nr_max = 0x240, 84 .attrib_nr = 0x240, 85 .alpha_nr_max = 0x648 + (0x648 / 2), 86 .alpha_nr = 0x648, 87 .sm_id = gf100_grctx_generate_sm_id, 88 .tpc_nr = gf100_grctx_generate_tpc_nr, 89 .rop_mapping = gf117_grctx_generate_rop_mapping, 90 .alpha_beta_tables = gk104_grctx_generate_alpha_beta_tables, 91}; 92