1/*	$NetBSD: nouveau_nvkm_engine_fifo_tu102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2018 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24#include <sys/cdefs.h>
25__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_tu102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $");
26
27#include "gk104.h"
28#include "cgrp.h"
29#include "changk104.h"
30#include "user.h"
31
32#include <core/gpuobj.h>
33
34#include <nvif/class.h>
35
36static void
37tu102_fifo_runlist_commit(struct gk104_fifo *fifo, int runl,
38			  struct nvkm_memory *mem, int nr)
39{
40	struct nvkm_device *device = fifo->base.engine.subdev.device;
41	u64 addr = nvkm_memory_addr(mem);
42	/*XXX: target? */
43
44	nvkm_wr32(device, 0x002b00 + (runl * 0x10), lower_32_bits(addr));
45	nvkm_wr32(device, 0x002b04 + (runl * 0x10), upper_32_bits(addr));
46	nvkm_wr32(device, 0x002b08 + (runl * 0x10), nr);
47
48	/*XXX: how to wait? can you even wait? */
49}
50
51const struct gk104_fifo_runlist_func
52tu102_fifo_runlist = {
53	.size = 16,
54	.cgrp = gv100_fifo_runlist_cgrp,
55	.chan = gv100_fifo_runlist_chan,
56	.commit = tu102_fifo_runlist_commit,
57};
58
59static const struct nvkm_enum
60tu102_fifo_fault_engine[] = {
61	{ 0x01, "DISPLAY" },
62	{ 0x03, "PTP" },
63	{ 0x06, "PWR_PMU" },
64	{ 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
65	{ 0x09, "PERF" },
66	{ 0x1f, "PHYSICAL" },
67	{ 0x20, "HOST0" },
68	{ 0x21, "HOST1" },
69	{ 0x22, "HOST2" },
70	{ 0x23, "HOST3" },
71	{ 0x24, "HOST4" },
72	{ 0x25, "HOST5" },
73	{ 0x26, "HOST6" },
74	{ 0x27, "HOST7" },
75	{ 0x28, "HOST8" },
76	{ 0x29, "HOST9" },
77	{ 0x2a, "HOST10" },
78	{ 0x2b, "HOST11" },
79	{ 0x2c, "HOST12" },
80	{ 0x2d, "HOST13" },
81	{ 0x2e, "HOST14" },
82	{ 0x80, "BAR1", NULL, NVKM_SUBDEV_BAR },
83	{ 0xc0, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
84	{}
85};
86
87static void
88tu102_fifo_pbdma_init(struct gk104_fifo *fifo)
89{
90	struct nvkm_device *device = fifo->base.engine.subdev.device;
91	const u32 mask = (1 << fifo->pbdma_nr) - 1;
92	/*XXX: this is a bit of a guess at this point in time. */
93	nvkm_mask(device, 0xb65000, 0x80000fff, 0x80000000 | mask);
94}
95
96static const struct gk104_fifo_pbdma_func
97tu102_fifo_pbdma = {
98	.nr = gm200_fifo_pbdma_nr,
99	.init = tu102_fifo_pbdma_init,
100	.init_timeout = gk208_fifo_pbdma_init_timeout,
101};
102
103static const struct gk104_fifo_func
104tu102_fifo = {
105	.pbdma = &tu102_fifo_pbdma,
106	.fault.access = gv100_fifo_fault_access,
107	.fault.engine = tu102_fifo_fault_engine,
108	.fault.reason = gv100_fifo_fault_reason,
109	.fault.hubclient = gv100_fifo_fault_hubclient,
110	.fault.gpcclient = gv100_fifo_fault_gpcclient,
111	.runlist = &tu102_fifo_runlist,
112	.user = {{-1,-1,VOLTA_USERMODE_A       }, tu102_fifo_user_new   },
113	.chan = {{ 0, 0,TURING_CHANNEL_GPFIFO_A}, tu102_fifo_gpfifo_new },
114	.cgrp_force = true,
115};
116
117int
118tu102_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
119{
120	return gk104_fifo_new_(&tu102_fifo, device, index, 4096, pfifo);
121}
122