1/*	$NetBSD: nouveau_nvkm_engine_fifo_nv17.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_nv17.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29#include "nv04.h"
30#include "channv04.h"
31#include "regsnv04.h"
32
33#include <core/ramht.h>
34#include <subdev/instmem.h>
35
36static const struct nv04_fifo_ramfc
37nv17_fifo_ramfc[] = {
38	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
39	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
40	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
41	{ 16,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
42	{ 16, 16, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
43	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_STATE },
44	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
45	{ 32,  0, 0x18,  0, NV04_PFIFO_CACHE1_ENGINE },
46	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_PULL1 },
47	{ 32,  0, 0x20,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
48	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
49	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
50	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
51	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
52	{}
53};
54
55static void
56nv17_fifo_init(struct nvkm_fifo *base)
57{
58	struct nv04_fifo *fifo = nv04_fifo(base);
59	struct nvkm_device *device = fifo->base.engine.subdev.device;
60	struct nvkm_instmem *imem = device->imem;
61	struct nvkm_ramht *ramht = imem->ramht;
62	struct nvkm_memory *ramro = imem->ramro;
63	struct nvkm_memory *ramfc = imem->ramfc;
64
65	nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff);
66	nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff);
67
68	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
69					    ((ramht->bits - 9) << 16) |
70					    (ramht->gpuobj->addr >> 8));
71	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
72	nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 |
73					    0x00010000);
74
75	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);
76
77	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
78	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
79
80	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
81	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
82	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
83}
84
85static const struct nvkm_fifo_func
86nv17_fifo = {
87	.init = nv17_fifo_init,
88	.intr = nv04_fifo_intr,
89	.pause = nv04_fifo_pause,
90	.start = nv04_fifo_start,
91	.chan = {
92		&nv17_fifo_dma_oclass,
93		NULL
94	},
95};
96
97int
98nv17_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
99{
100	return nv04_fifo_new_(&nv17_fifo, device, index, 32,
101			      nv17_fifo_ramfc, pfifo);
102}
103