nouveau_nvkm_engine_fifo_dmanv10.c revision 1.2 
1/*	$NetBSD: nouveau_nvkm_engine_fifo_dmanv10.c,v 1.2 2018/08/27 04:58:31 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_fifo_dmanv10.c,v 1.2 2018/08/27 04:58:31 riastradh Exp $");
28
29#include "channv04.h"
30#include "regsnv04.h"
31
32#include <core/client.h>
33#include <core/gpuobj.h>
34#include <subdev/instmem.h>
35
36#include <nvif/class.h>
37#include <nvif/unpack.h>
38
39static int
40nv10_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
41		  void *data, u32 size, struct nvkm_object **pobject)
42{
43	struct nvkm_object *parent = oclass->parent;
44	union {
45		struct nv03_channel_dma_v0 v0;
46	} *args = data;
47	struct nv04_fifo *fifo = nv04_fifo(base);
48	struct nv04_fifo_chan *chan = NULL;
49	struct nvkm_device *device = fifo->base.engine.subdev.device;
50	struct nvkm_instmem *imem = device->imem;
51	int ret;
52
53	nvif_ioctl(parent, "create channel dma size %d\n", size);
54	if (nvif_unpack(args->v0, 0, 0, false)) {
55		nvif_ioctl(parent, "create channel dma vers %d pushbuf %"PRIx64" "
56				   "offset %08x\n", args->v0.version,
57			   args->v0.pushbuf, args->v0.offset);
58		if (!args->v0.pushbuf)
59			return -EINVAL;
60	} else
61		return ret;
62
63	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
64		return -ENOMEM;
65	*pobject = &chan->base.object;
66
67	ret = nvkm_fifo_chan_ctor(&nv04_fifo_dma_func, &fifo->base,
68				  0x1000, 0x1000, false, 0, args->v0.pushbuf,
69				  (1ULL << NVKM_ENGINE_DMAOBJ) |
70				  (1ULL << NVKM_ENGINE_GR) |
71				  (1ULL << NVKM_ENGINE_SW),
72				  0, 0x800000, 0x10000, oclass, &chan->base);
73	chan->fifo = fifo;
74	if (ret)
75		return ret;
76
77	args->v0.chid = chan->base.chid;
78	chan->ramfc = chan->base.chid * 32;
79
80	nvkm_kmap(imem->ramfc);
81	nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset);
82	nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset);
83	nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4);
84	nvkm_wo32(imem->ramfc, chan->ramfc + 0x14,
85			       NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
86			       NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
87#ifdef __BIG_ENDIAN
88			       NV_PFIFO_CACHE1_BIG_ENDIAN |
89#endif
90			       NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
91	nvkm_done(imem->ramfc);
92	return 0;
93}
94
95const struct nvkm_fifo_chan_oclass
96nv10_fifo_dma_oclass = {
97	.base.oclass = NV10_CHANNEL_DMA,
98	.base.minver = 0,
99	.base.maxver = 0,
100	.ctor = nv10_fifo_dma_new,
101};
102