1/*	$NetBSD: nouveau_nvkm_engine_disp_gp102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2016 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs <bskeggs@redhat.com>
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_gp102.c,v 1.2 2021/12/18 23:45:35 riastradh Exp $");
28
29#include "nv50.h"
30#include "head.h"
31#include "ior.h"
32#include "channv50.h"
33#include "rootnv50.h"
34
35static void
36gp102_disp_intr_error(struct nv50_disp *disp, int chid)
37{
38	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
39	struct nvkm_device *device = subdev->device;
40	u32 mthd = nvkm_rd32(device, 0x6111f0 + (chid * 12));
41	u32 data = nvkm_rd32(device, 0x6111f4 + (chid * 12));
42	u32 unkn = nvkm_rd32(device, 0x6111f8 + (chid * 12));
43
44	nvkm_error(subdev, "chid %d mthd %04x data %08x %08x %08x\n",
45		   chid, (mthd & 0x0000ffc), data, mthd, unkn);
46
47	if (chid < ARRAY_SIZE(disp->chan)) {
48		switch (mthd & 0xffc) {
49		case 0x0080:
50			nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);
51			break;
52		default:
53			break;
54		}
55	}
56
57	nvkm_wr32(device, 0x61009c, (1 << chid));
58	nvkm_wr32(device, 0x6111f0 + (chid * 12), 0x90000000);
59}
60
61static const struct nv50_disp_func
62gp102_disp = {
63	.init = gf119_disp_init,
64	.fini = gf119_disp_fini,
65	.intr = gf119_disp_intr,
66	.intr_error = gp102_disp_intr_error,
67	.uevent = &gf119_disp_chan_uevent,
68	.super = gf119_disp_super,
69	.root = &gp102_disp_root_oclass,
70	.head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
71	.sor = { .cnt = gf119_sor_cnt, .new = gm200_sor_new },
72};
73
74int
75gp102_disp_new(struct nvkm_device *device, int index, struct nvkm_disp **pdisp)
76{
77	return nv50_disp_new_(&gp102_disp, device, index, pdisp);
78}
79