1/* $NetBSD: nouveau_nvkm_engine_disp_dacnv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_dacnv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $"); 28 29#include "ior.h" 30 31#include <subdev/timer.h> 32 33static void 34nv50_dac_clock(struct nvkm_ior *dac) 35{ 36 struct nvkm_device *device = dac->disp->engine.subdev.device; 37 const u32 doff = nv50_ior_base(dac); 38 nvkm_mask(device, 0x614280 + doff, 0x07070707, 0x00000000); 39} 40 41int 42nv50_dac_sense(struct nvkm_ior *dac, u32 loadval) 43{ 44 struct nvkm_device *device = dac->disp->engine.subdev.device; 45 const u32 doff = nv50_ior_base(dac); 46 47 dac->func->power(dac, false, true, false, false, false); 48 49 nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval); 50 mdelay(9); 51 udelay(500); 52 loadval = nvkm_mask(device, 0x61a00c + doff, 0xffffffff, 0x00000000); 53 54 dac->func->power(dac, false, false, false, false, false); 55 if (!(loadval & 0x80000000)) 56 return -ETIMEDOUT; 57 58 return (loadval & 0x38000000) >> 27; 59} 60 61static void 62nv50_dac_power_wait(struct nvkm_device *device, const u32 doff) 63{ 64 nvkm_msec(device, 2000, 65 if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000)) 66 break; 67 ); 68} 69 70void 71nv50_dac_power(struct nvkm_ior *dac, bool normal, bool pu, 72 bool data, bool vsync, bool hsync) 73{ 74 struct nvkm_device *device = dac->disp->engine.subdev.device; 75 const u32 doff = nv50_ior_base(dac); 76 const u32 shift = normal ? 0 : 16; 77 const u32 state = 0x80000000 | (0x00000040 * ! pu | 78 0x00000010 * ! data | 79 0x00000004 * ! vsync | 80 0x00000001 * ! hsync) << shift; 81 const u32 field = 0xc0000000 | (0x00000055 << shift); 82 83 nv50_dac_power_wait(device, doff); 84 nvkm_mask(device, 0x61a004 + doff, field, state); 85 nv50_dac_power_wait(device, doff); 86} 87 88static void 89nv50_dac_state(struct nvkm_ior *dac, struct nvkm_ior_state *state) 90{ 91 struct nvkm_device *device = dac->disp->engine.subdev.device; 92 const u32 coff = dac->id * 8 + (state == &dac->arm) * 4; 93 u32 ctrl = nvkm_rd32(device, 0x610b58 + coff); 94 95 state->proto_evo = (ctrl & 0x00000f00) >> 8; 96 switch (state->proto_evo) { 97 case 0: state->proto = CRT; break; 98 default: 99 state->proto = UNKNOWN; 100 break; 101 } 102 103 state->head = ctrl & 0x00000003; 104} 105 106static const struct nvkm_ior_func 107nv50_dac = { 108 .state = nv50_dac_state, 109 .power = nv50_dac_power, 110 .sense = nv50_dac_sense, 111 .clock = nv50_dac_clock, 112}; 113 114int 115nv50_dac_new(struct nvkm_disp *disp, int id) 116{ 117 return nvkm_ior_new_(&nv50_dac, disp, DAC, id); 118} 119 120int 121nv50_dac_cnt(struct nvkm_disp *disp, unsigned long *pmask) 122{ 123 struct nvkm_device *device = disp->engine.subdev.device; 124 *pmask = (nvkm_rd32(device, 0x610184) & 0x00700000) >> 20; 125 return 3; 126} 127