1/*	$NetBSD: nouveau_nvkm_engine_disp_corenv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $	*/
2
3/*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26#include <sys/cdefs.h>
27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_disp_corenv50.c,v 1.3 2021/12/18 23:45:35 riastradh Exp $");
28
29#include "channv50.h"
30
31#include <core/client.h>
32#include <subdev/timer.h>
33
34#include <nvif/cl507d.h>
35#include <nvif/unpack.h>
36
37int
38nv50_disp_core_new_(const struct nv50_disp_chan_func *func,
39		    const struct nv50_disp_chan_mthd *mthd,
40		    struct nv50_disp *disp, int chid,
41		    const struct nvkm_oclass *oclass, void *argv, u32 argc,
42		    struct nvkm_object **pobject)
43{
44	union {
45		struct nv50_disp_core_channel_dma_v0 v0;
46	} *args = argv;
47	struct nvkm_object *parent = oclass->parent;
48	u64 push;
49	int ret = -ENOSYS;
50
51	nvif_ioctl(parent, "create disp core channel dma size %d\n", argc);
52	if (!(ret = nvif_unpack(ret, &argv, &argc, args->v0, 0, 0, false))) {
53		nvif_ioctl(parent, "create disp core channel dma vers %d "
54				   "pushbuf %016"PRIx64"\n",
55			   args->v0.version, args->v0.pushbuf);
56		push = args->v0.pushbuf;
57	} else
58		return ret;
59
60	return nv50_disp_dmac_new_(func, mthd, disp, chid, 0,
61				   push, oclass, pobject);
62}
63
64const struct nv50_disp_mthd_list
65nv50_disp_core_mthd_base = {
66	.mthd = 0x0000,
67	.addr = 0x000000,
68	.data = {
69		{ 0x0080, 0x000000 },
70		{ 0x0084, 0x610bb8 },
71		{ 0x0088, 0x610b9c },
72		{ 0x008c, 0x000000 },
73		{}
74	}
75};
76
77static const struct nv50_disp_mthd_list
78nv50_disp_core_mthd_dac = {
79	.mthd = 0x0080,
80	.addr = 0x000008,
81	.data = {
82		{ 0x0400, 0x610b58 },
83		{ 0x0404, 0x610bdc },
84		{ 0x0420, 0x610828 },
85		{}
86	}
87};
88
89const struct nv50_disp_mthd_list
90nv50_disp_core_mthd_sor = {
91	.mthd = 0x0040,
92	.addr = 0x000008,
93	.data = {
94		{ 0x0600, 0x610b70 },
95		{}
96	}
97};
98
99const struct nv50_disp_mthd_list
100nv50_disp_core_mthd_pior = {
101	.mthd = 0x0040,
102	.addr = 0x000008,
103	.data = {
104		{ 0x0700, 0x610b80 },
105		{}
106	}
107};
108
109static const struct nv50_disp_mthd_list
110nv50_disp_core_mthd_head = {
111	.mthd = 0x0400,
112	.addr = 0x000540,
113	.data = {
114		{ 0x0800, 0x610ad8 },
115		{ 0x0804, 0x610ad0 },
116		{ 0x0808, 0x610a48 },
117		{ 0x080c, 0x610a78 },
118		{ 0x0810, 0x610ac0 },
119		{ 0x0814, 0x610af8 },
120		{ 0x0818, 0x610b00 },
121		{ 0x081c, 0x610ae8 },
122		{ 0x0820, 0x610af0 },
123		{ 0x0824, 0x610b08 },
124		{ 0x0828, 0x610b10 },
125		{ 0x082c, 0x610a68 },
126		{ 0x0830, 0x610a60 },
127		{ 0x0834, 0x000000 },
128		{ 0x0838, 0x610a40 },
129		{ 0x0840, 0x610a24 },
130		{ 0x0844, 0x610a2c },
131		{ 0x0848, 0x610aa8 },
132		{ 0x084c, 0x610ab0 },
133		{ 0x0860, 0x610a84 },
134		{ 0x0864, 0x610a90 },
135		{ 0x0868, 0x610b18 },
136		{ 0x086c, 0x610b20 },
137		{ 0x0870, 0x610ac8 },
138		{ 0x0874, 0x610a38 },
139		{ 0x0880, 0x610a58 },
140		{ 0x0884, 0x610a9c },
141		{ 0x08a0, 0x610a70 },
142		{ 0x08a4, 0x610a50 },
143		{ 0x08a8, 0x610ae0 },
144		{ 0x08c0, 0x610b28 },
145		{ 0x08c4, 0x610b30 },
146		{ 0x08c8, 0x610b40 },
147		{ 0x08d4, 0x610b38 },
148		{ 0x08d8, 0x610b48 },
149		{ 0x08dc, 0x610b50 },
150		{ 0x0900, 0x610a18 },
151		{ 0x0904, 0x610ab8 },
152		{}
153	}
154};
155
156static const struct nv50_disp_chan_mthd
157nv50_disp_core_mthd = {
158	.name = "Core",
159	.addr = 0x000000,
160	.prev = 0x000004,
161	.data = {
162		{ "Global", 1, &nv50_disp_core_mthd_base },
163		{    "DAC", 3, &nv50_disp_core_mthd_dac  },
164		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
165		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
166		{   "HEAD", 2, &nv50_disp_core_mthd_head },
167		{}
168	}
169};
170
171static void
172nv50_disp_core_fini(struct nv50_disp_chan *chan)
173{
174	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
175	struct nvkm_device *device = subdev->device;
176
177	/* deactivate channel */
178	nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
179	nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
180	if (nvkm_msec(device, 2000,
181		if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
182			break;
183	) < 0) {
184		nvkm_error(subdev, "core fini: %08x\n",
185			   nvkm_rd32(device, 0x610200));
186	}
187}
188
189static int
190nv50_disp_core_init(struct nv50_disp_chan *chan)
191{
192	struct nvkm_subdev *subdev = &chan->disp->base.engine.subdev;
193	struct nvkm_device *device = subdev->device;
194
195	/* attempt to unstick channel from some unknown state */
196	if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
197		nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
198	if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
199		nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
200
201	/* initialise channel for dma command submission */
202	nvkm_wr32(device, 0x610204, chan->push);
203	nvkm_wr32(device, 0x610208, 0x00010000);
204	nvkm_wr32(device, 0x61020c, 0x00000000);
205	nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
206	nvkm_wr32(device, 0x640000, 0x00000000);
207	nvkm_wr32(device, 0x610200, 0x01000013);
208
209	/* wait for it to go inactive */
210	if (nvkm_msec(device, 2000,
211		if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
212			break;
213	) < 0) {
214		nvkm_error(subdev, "core init: %08x\n",
215			   nvkm_rd32(device, 0x610200));
216		return -EBUSY;
217	}
218
219	return 0;
220}
221
222const struct nv50_disp_chan_func
223nv50_disp_core_func = {
224	.init = nv50_disp_core_init,
225	.fini = nv50_disp_core_fini,
226	.intr = nv50_disp_chan_intr,
227	.user = nv50_disp_chan_user,
228	.bind = nv50_disp_dmac_bind,
229};
230
231int
232nv50_disp_core_new(const struct nvkm_oclass *oclass, void *argv, u32 argc,
233		   struct nv50_disp *disp, struct nvkm_object **pobject)
234{
235	return nv50_disp_core_new_(&nv50_disp_core_func, &nv50_disp_core_mthd,
236				   disp, 0, oclass, argv, argc, pobject);
237}
238