nouveau_nvkm_engine_device_base.c revision 1.4
1/* $NetBSD: nouveau_nvkm_engine_device_base.c,v 1.4 2018/08/27 07:39:20 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_device_base.c,v 1.4 2018/08/27 07:39:20 riastradh Exp $"); 28 29#include "priv.h" 30#include "acpi.h" 31 32#include <core/notify.h> 33#include <core/option.h> 34 35#include <subdev/bios.h> 36 37#ifdef __NetBSD__ 38static struct mutex nv_devices_mutex; 39static struct list_head nv_devices = LIST_HEAD_INIT(nv_devices); 40 41void 42nouveau_devices_init(void) 43{ 44 45 linux_mutex_init(&nv_devices_mutex); 46} 47 48void 49nouveau_devices_fini(void) 50{ 51 52 linux_mutex_destroy(&nv_devices_mutex); 53} 54#else 55static DEFINE_MUTEX(nv_devices_mutex); 56static LIST_HEAD(nv_devices); 57#endif 58 59static struct nvkm_device * 60nvkm_device_find_locked(u64 handle) 61{ 62 struct nvkm_device *device; 63 list_for_each_entry(device, &nv_devices, head) { 64 if (device->handle == handle) 65 return device; 66 } 67 return NULL; 68} 69 70struct nvkm_device * 71nvkm_device_find(u64 handle) 72{ 73 struct nvkm_device *device; 74 mutex_lock(&nv_devices_mutex); 75 device = nvkm_device_find_locked(handle); 76 mutex_unlock(&nv_devices_mutex); 77 return device; 78} 79 80int 81nvkm_device_list(u64 *name, int size) 82{ 83 struct nvkm_device *device; 84 int nr = 0; 85 mutex_lock(&nv_devices_mutex); 86 list_for_each_entry(device, &nv_devices, head) { 87 if (nr++ < size) 88 name[nr - 1] = device->handle; 89 } 90 mutex_unlock(&nv_devices_mutex); 91 return nr; 92} 93 94static const struct nvkm_device_chip 95null_chipset = { 96 .name = "NULL", 97 .bios = nvkm_bios_new, 98}; 99 100static const struct nvkm_device_chip 101nv4_chipset = { 102 .name = "NV04", 103 .bios = nvkm_bios_new, 104 .bus = nv04_bus_new, 105 .clk = nv04_clk_new, 106 .devinit = nv04_devinit_new, 107 .fb = nv04_fb_new, 108 .i2c = nv04_i2c_new, 109 .imem = nv04_instmem_new, 110 .mc = nv04_mc_new, 111 .mmu = nv04_mmu_new, 112 .pci = nv04_pci_new, 113 .timer = nv04_timer_new, 114 .disp = nv04_disp_new, 115 .dma = nv04_dma_new, 116 .fifo = nv04_fifo_new, 117 .gr = nv04_gr_new, 118 .sw = nv04_sw_new, 119}; 120 121static const struct nvkm_device_chip 122nv5_chipset = { 123 .name = "NV05", 124 .bios = nvkm_bios_new, 125 .bus = nv04_bus_new, 126 .clk = nv04_clk_new, 127 .devinit = nv05_devinit_new, 128 .fb = nv04_fb_new, 129 .i2c = nv04_i2c_new, 130 .imem = nv04_instmem_new, 131 .mc = nv04_mc_new, 132 .mmu = nv04_mmu_new, 133 .pci = nv04_pci_new, 134 .timer = nv04_timer_new, 135 .disp = nv04_disp_new, 136 .dma = nv04_dma_new, 137 .fifo = nv04_fifo_new, 138 .gr = nv04_gr_new, 139 .sw = nv04_sw_new, 140}; 141 142static const struct nvkm_device_chip 143nv10_chipset = { 144 .name = "NV10", 145 .bios = nvkm_bios_new, 146 .bus = nv04_bus_new, 147 .clk = nv04_clk_new, 148 .devinit = nv10_devinit_new, 149 .fb = nv10_fb_new, 150 .gpio = nv10_gpio_new, 151 .i2c = nv04_i2c_new, 152 .imem = nv04_instmem_new, 153 .mc = nv04_mc_new, 154 .mmu = nv04_mmu_new, 155 .pci = nv04_pci_new, 156 .timer = nv04_timer_new, 157 .disp = nv04_disp_new, 158 .dma = nv04_dma_new, 159 .gr = nv10_gr_new, 160}; 161 162static const struct nvkm_device_chip 163nv11_chipset = { 164 .name = "NV11", 165 .bios = nvkm_bios_new, 166 .bus = nv04_bus_new, 167 .clk = nv04_clk_new, 168 .devinit = nv10_devinit_new, 169 .fb = nv10_fb_new, 170 .gpio = nv10_gpio_new, 171 .i2c = nv04_i2c_new, 172 .imem = nv04_instmem_new, 173 .mc = nv04_mc_new, 174 .mmu = nv04_mmu_new, 175 .pci = nv04_pci_new, 176 .timer = nv04_timer_new, 177 .disp = nv04_disp_new, 178 .dma = nv04_dma_new, 179 .fifo = nv10_fifo_new, 180 .gr = nv15_gr_new, 181 .sw = nv10_sw_new, 182}; 183 184static const struct nvkm_device_chip 185nv15_chipset = { 186 .name = "NV15", 187 .bios = nvkm_bios_new, 188 .bus = nv04_bus_new, 189 .clk = nv04_clk_new, 190 .devinit = nv10_devinit_new, 191 .fb = nv10_fb_new, 192 .gpio = nv10_gpio_new, 193 .i2c = nv04_i2c_new, 194 .imem = nv04_instmem_new, 195 .mc = nv04_mc_new, 196 .mmu = nv04_mmu_new, 197 .pci = nv04_pci_new, 198 .timer = nv04_timer_new, 199 .disp = nv04_disp_new, 200 .dma = nv04_dma_new, 201 .fifo = nv10_fifo_new, 202 .gr = nv15_gr_new, 203 .sw = nv10_sw_new, 204}; 205 206static const struct nvkm_device_chip 207nv17_chipset = { 208 .name = "NV17", 209 .bios = nvkm_bios_new, 210 .bus = nv04_bus_new, 211 .clk = nv04_clk_new, 212 .devinit = nv10_devinit_new, 213 .fb = nv10_fb_new, 214 .gpio = nv10_gpio_new, 215 .i2c = nv04_i2c_new, 216 .imem = nv04_instmem_new, 217 .mc = nv04_mc_new, 218 .mmu = nv04_mmu_new, 219 .pci = nv04_pci_new, 220 .timer = nv04_timer_new, 221 .disp = nv04_disp_new, 222 .dma = nv04_dma_new, 223 .fifo = nv17_fifo_new, 224 .gr = nv17_gr_new, 225 .sw = nv10_sw_new, 226}; 227 228static const struct nvkm_device_chip 229nv18_chipset = { 230 .name = "NV18", 231 .bios = nvkm_bios_new, 232 .bus = nv04_bus_new, 233 .clk = nv04_clk_new, 234 .devinit = nv10_devinit_new, 235 .fb = nv10_fb_new, 236 .gpio = nv10_gpio_new, 237 .i2c = nv04_i2c_new, 238 .imem = nv04_instmem_new, 239 .mc = nv04_mc_new, 240 .mmu = nv04_mmu_new, 241 .pci = nv04_pci_new, 242 .timer = nv04_timer_new, 243 .disp = nv04_disp_new, 244 .dma = nv04_dma_new, 245 .fifo = nv17_fifo_new, 246 .gr = nv17_gr_new, 247 .sw = nv10_sw_new, 248}; 249 250static const struct nvkm_device_chip 251nv1a_chipset = { 252 .name = "nForce", 253 .bios = nvkm_bios_new, 254 .bus = nv04_bus_new, 255 .clk = nv04_clk_new, 256 .devinit = nv1a_devinit_new, 257 .fb = nv1a_fb_new, 258 .gpio = nv10_gpio_new, 259 .i2c = nv04_i2c_new, 260 .imem = nv04_instmem_new, 261 .mc = nv04_mc_new, 262 .mmu = nv04_mmu_new, 263 .pci = nv04_pci_new, 264 .timer = nv04_timer_new, 265 .disp = nv04_disp_new, 266 .dma = nv04_dma_new, 267 .fifo = nv10_fifo_new, 268 .gr = nv15_gr_new, 269 .sw = nv10_sw_new, 270}; 271 272static const struct nvkm_device_chip 273nv1f_chipset = { 274 .name = "nForce2", 275 .bios = nvkm_bios_new, 276 .bus = nv04_bus_new, 277 .clk = nv04_clk_new, 278 .devinit = nv1a_devinit_new, 279 .fb = nv1a_fb_new, 280 .gpio = nv10_gpio_new, 281 .i2c = nv04_i2c_new, 282 .imem = nv04_instmem_new, 283 .mc = nv04_mc_new, 284 .mmu = nv04_mmu_new, 285 .pci = nv04_pci_new, 286 .timer = nv04_timer_new, 287 .disp = nv04_disp_new, 288 .dma = nv04_dma_new, 289 .fifo = nv17_fifo_new, 290 .gr = nv17_gr_new, 291 .sw = nv10_sw_new, 292}; 293 294static const struct nvkm_device_chip 295nv20_chipset = { 296 .name = "NV20", 297 .bios = nvkm_bios_new, 298 .bus = nv04_bus_new, 299 .clk = nv04_clk_new, 300 .devinit = nv20_devinit_new, 301 .fb = nv20_fb_new, 302 .gpio = nv10_gpio_new, 303 .i2c = nv04_i2c_new, 304 .imem = nv04_instmem_new, 305 .mc = nv04_mc_new, 306 .mmu = nv04_mmu_new, 307 .pci = nv04_pci_new, 308 .timer = nv04_timer_new, 309 .disp = nv04_disp_new, 310 .dma = nv04_dma_new, 311 .fifo = nv17_fifo_new, 312 .gr = nv20_gr_new, 313 .sw = nv10_sw_new, 314}; 315 316static const struct nvkm_device_chip 317nv25_chipset = { 318 .name = "NV25", 319 .bios = nvkm_bios_new, 320 .bus = nv04_bus_new, 321 .clk = nv04_clk_new, 322 .devinit = nv20_devinit_new, 323 .fb = nv25_fb_new, 324 .gpio = nv10_gpio_new, 325 .i2c = nv04_i2c_new, 326 .imem = nv04_instmem_new, 327 .mc = nv04_mc_new, 328 .mmu = nv04_mmu_new, 329 .pci = nv04_pci_new, 330 .timer = nv04_timer_new, 331 .disp = nv04_disp_new, 332 .dma = nv04_dma_new, 333 .fifo = nv17_fifo_new, 334 .gr = nv25_gr_new, 335 .sw = nv10_sw_new, 336}; 337 338static const struct nvkm_device_chip 339nv28_chipset = { 340 .name = "NV28", 341 .bios = nvkm_bios_new, 342 .bus = nv04_bus_new, 343 .clk = nv04_clk_new, 344 .devinit = nv20_devinit_new, 345 .fb = nv25_fb_new, 346 .gpio = nv10_gpio_new, 347 .i2c = nv04_i2c_new, 348 .imem = nv04_instmem_new, 349 .mc = nv04_mc_new, 350 .mmu = nv04_mmu_new, 351 .pci = nv04_pci_new, 352 .timer = nv04_timer_new, 353 .disp = nv04_disp_new, 354 .dma = nv04_dma_new, 355 .fifo = nv17_fifo_new, 356 .gr = nv25_gr_new, 357 .sw = nv10_sw_new, 358}; 359 360static const struct nvkm_device_chip 361nv2a_chipset = { 362 .name = "NV2A", 363 .bios = nvkm_bios_new, 364 .bus = nv04_bus_new, 365 .clk = nv04_clk_new, 366 .devinit = nv20_devinit_new, 367 .fb = nv25_fb_new, 368 .gpio = nv10_gpio_new, 369 .i2c = nv04_i2c_new, 370 .imem = nv04_instmem_new, 371 .mc = nv04_mc_new, 372 .mmu = nv04_mmu_new, 373 .pci = nv04_pci_new, 374 .timer = nv04_timer_new, 375 .disp = nv04_disp_new, 376 .dma = nv04_dma_new, 377 .fifo = nv17_fifo_new, 378 .gr = nv2a_gr_new, 379 .sw = nv10_sw_new, 380}; 381 382static const struct nvkm_device_chip 383nv30_chipset = { 384 .name = "NV30", 385 .bios = nvkm_bios_new, 386 .bus = nv04_bus_new, 387 .clk = nv04_clk_new, 388 .devinit = nv20_devinit_new, 389 .fb = nv30_fb_new, 390 .gpio = nv10_gpio_new, 391 .i2c = nv04_i2c_new, 392 .imem = nv04_instmem_new, 393 .mc = nv04_mc_new, 394 .mmu = nv04_mmu_new, 395 .pci = nv04_pci_new, 396 .timer = nv04_timer_new, 397 .disp = nv04_disp_new, 398 .dma = nv04_dma_new, 399 .fifo = nv17_fifo_new, 400 .gr = nv30_gr_new, 401 .sw = nv10_sw_new, 402}; 403 404static const struct nvkm_device_chip 405nv31_chipset = { 406 .name = "NV31", 407 .bios = nvkm_bios_new, 408 .bus = nv31_bus_new, 409 .clk = nv04_clk_new, 410 .devinit = nv20_devinit_new, 411 .fb = nv30_fb_new, 412 .gpio = nv10_gpio_new, 413 .i2c = nv04_i2c_new, 414 .imem = nv04_instmem_new, 415 .mc = nv04_mc_new, 416 .mmu = nv04_mmu_new, 417 .pci = nv04_pci_new, 418 .timer = nv04_timer_new, 419 .disp = nv04_disp_new, 420 .dma = nv04_dma_new, 421 .fifo = nv17_fifo_new, 422 .gr = nv30_gr_new, 423 .mpeg = nv31_mpeg_new, 424 .sw = nv10_sw_new, 425}; 426 427static const struct nvkm_device_chip 428nv34_chipset = { 429 .name = "NV34", 430 .bios = nvkm_bios_new, 431 .bus = nv31_bus_new, 432 .clk = nv04_clk_new, 433 .devinit = nv10_devinit_new, 434 .fb = nv10_fb_new, 435 .gpio = nv10_gpio_new, 436 .i2c = nv04_i2c_new, 437 .imem = nv04_instmem_new, 438 .mc = nv04_mc_new, 439 .mmu = nv04_mmu_new, 440 .pci = nv04_pci_new, 441 .timer = nv04_timer_new, 442 .disp = nv04_disp_new, 443 .dma = nv04_dma_new, 444 .fifo = nv17_fifo_new, 445 .gr = nv34_gr_new, 446 .mpeg = nv31_mpeg_new, 447 .sw = nv10_sw_new, 448}; 449 450static const struct nvkm_device_chip 451nv35_chipset = { 452 .name = "NV35", 453 .bios = nvkm_bios_new, 454 .bus = nv04_bus_new, 455 .clk = nv04_clk_new, 456 .devinit = nv20_devinit_new, 457 .fb = nv35_fb_new, 458 .gpio = nv10_gpio_new, 459 .i2c = nv04_i2c_new, 460 .imem = nv04_instmem_new, 461 .mc = nv04_mc_new, 462 .mmu = nv04_mmu_new, 463 .pci = nv04_pci_new, 464 .timer = nv04_timer_new, 465 .disp = nv04_disp_new, 466 .dma = nv04_dma_new, 467 .fifo = nv17_fifo_new, 468 .gr = nv35_gr_new, 469 .sw = nv10_sw_new, 470}; 471 472static const struct nvkm_device_chip 473nv36_chipset = { 474 .name = "NV36", 475 .bios = nvkm_bios_new, 476 .bus = nv31_bus_new, 477 .clk = nv04_clk_new, 478 .devinit = nv20_devinit_new, 479 .fb = nv36_fb_new, 480 .gpio = nv10_gpio_new, 481 .i2c = nv04_i2c_new, 482 .imem = nv04_instmem_new, 483 .mc = nv04_mc_new, 484 .mmu = nv04_mmu_new, 485 .pci = nv04_pci_new, 486 .timer = nv04_timer_new, 487 .disp = nv04_disp_new, 488 .dma = nv04_dma_new, 489 .fifo = nv17_fifo_new, 490 .gr = nv35_gr_new, 491 .mpeg = nv31_mpeg_new, 492 .sw = nv10_sw_new, 493}; 494 495static const struct nvkm_device_chip 496nv40_chipset = { 497 .name = "NV40", 498 .bios = nvkm_bios_new, 499 .bus = nv31_bus_new, 500 .clk = nv40_clk_new, 501 .devinit = nv1a_devinit_new, 502 .fb = nv40_fb_new, 503 .gpio = nv10_gpio_new, 504 .i2c = nv04_i2c_new, 505 .imem = nv40_instmem_new, 506 .mc = nv04_mc_new, 507 .mmu = nv04_mmu_new, 508 .pci = nv40_pci_new, 509 .therm = nv40_therm_new, 510 .timer = nv40_timer_new, 511 .volt = nv40_volt_new, 512 .disp = nv04_disp_new, 513 .dma = nv04_dma_new, 514 .fifo = nv40_fifo_new, 515 .gr = nv40_gr_new, 516 .mpeg = nv40_mpeg_new, 517 .pm = nv40_pm_new, 518 .sw = nv10_sw_new, 519}; 520 521static const struct nvkm_device_chip 522nv41_chipset = { 523 .name = "NV41", 524 .bios = nvkm_bios_new, 525 .bus = nv31_bus_new, 526 .clk = nv40_clk_new, 527 .devinit = nv1a_devinit_new, 528 .fb = nv41_fb_new, 529 .gpio = nv10_gpio_new, 530 .i2c = nv04_i2c_new, 531 .imem = nv40_instmem_new, 532 .mc = nv04_mc_new, 533 .mmu = nv41_mmu_new, 534 .pci = nv40_pci_new, 535 .therm = nv40_therm_new, 536 .timer = nv41_timer_new, 537 .volt = nv40_volt_new, 538 .disp = nv04_disp_new, 539 .dma = nv04_dma_new, 540 .fifo = nv40_fifo_new, 541 .gr = nv40_gr_new, 542 .mpeg = nv40_mpeg_new, 543 .pm = nv40_pm_new, 544 .sw = nv10_sw_new, 545}; 546 547static const struct nvkm_device_chip 548nv42_chipset = { 549 .name = "NV42", 550 .bios = nvkm_bios_new, 551 .bus = nv31_bus_new, 552 .clk = nv40_clk_new, 553 .devinit = nv1a_devinit_new, 554 .fb = nv41_fb_new, 555 .gpio = nv10_gpio_new, 556 .i2c = nv04_i2c_new, 557 .imem = nv40_instmem_new, 558 .mc = nv04_mc_new, 559 .mmu = nv41_mmu_new, 560 .pci = nv40_pci_new, 561 .therm = nv40_therm_new, 562 .timer = nv41_timer_new, 563 .volt = nv40_volt_new, 564 .disp = nv04_disp_new, 565 .dma = nv04_dma_new, 566 .fifo = nv40_fifo_new, 567 .gr = nv40_gr_new, 568 .mpeg = nv40_mpeg_new, 569 .pm = nv40_pm_new, 570 .sw = nv10_sw_new, 571}; 572 573static const struct nvkm_device_chip 574nv43_chipset = { 575 .name = "NV43", 576 .bios = nvkm_bios_new, 577 .bus = nv31_bus_new, 578 .clk = nv40_clk_new, 579 .devinit = nv1a_devinit_new, 580 .fb = nv41_fb_new, 581 .gpio = nv10_gpio_new, 582 .i2c = nv04_i2c_new, 583 .imem = nv40_instmem_new, 584 .mc = nv04_mc_new, 585 .mmu = nv41_mmu_new, 586 .pci = nv40_pci_new, 587 .therm = nv40_therm_new, 588 .timer = nv41_timer_new, 589 .volt = nv40_volt_new, 590 .disp = nv04_disp_new, 591 .dma = nv04_dma_new, 592 .fifo = nv40_fifo_new, 593 .gr = nv40_gr_new, 594 .mpeg = nv40_mpeg_new, 595 .pm = nv40_pm_new, 596 .sw = nv10_sw_new, 597}; 598 599static const struct nvkm_device_chip 600nv44_chipset = { 601 .name = "NV44", 602 .bios = nvkm_bios_new, 603 .bus = nv31_bus_new, 604 .clk = nv40_clk_new, 605 .devinit = nv1a_devinit_new, 606 .fb = nv44_fb_new, 607 .gpio = nv10_gpio_new, 608 .i2c = nv04_i2c_new, 609 .imem = nv40_instmem_new, 610 .mc = nv44_mc_new, 611 .mmu = nv44_mmu_new, 612 .pci = nv40_pci_new, 613 .therm = nv40_therm_new, 614 .timer = nv41_timer_new, 615 .volt = nv40_volt_new, 616 .disp = nv04_disp_new, 617 .dma = nv04_dma_new, 618 .fifo = nv40_fifo_new, 619 .gr = nv44_gr_new, 620 .mpeg = nv44_mpeg_new, 621 .pm = nv40_pm_new, 622 .sw = nv10_sw_new, 623}; 624 625static const struct nvkm_device_chip 626nv45_chipset = { 627 .name = "NV45", 628 .bios = nvkm_bios_new, 629 .bus = nv31_bus_new, 630 .clk = nv40_clk_new, 631 .devinit = nv1a_devinit_new, 632 .fb = nv40_fb_new, 633 .gpio = nv10_gpio_new, 634 .i2c = nv04_i2c_new, 635 .imem = nv40_instmem_new, 636 .mc = nv04_mc_new, 637 .mmu = nv04_mmu_new, 638 .pci = nv40_pci_new, 639 .therm = nv40_therm_new, 640 .timer = nv41_timer_new, 641 .volt = nv40_volt_new, 642 .disp = nv04_disp_new, 643 .dma = nv04_dma_new, 644 .fifo = nv40_fifo_new, 645 .gr = nv40_gr_new, 646 .mpeg = nv44_mpeg_new, 647 .pm = nv40_pm_new, 648 .sw = nv10_sw_new, 649}; 650 651static const struct nvkm_device_chip 652nv46_chipset = { 653 .name = "G72", 654 .bios = nvkm_bios_new, 655 .bus = nv31_bus_new, 656 .clk = nv40_clk_new, 657 .devinit = nv1a_devinit_new, 658 .fb = nv46_fb_new, 659 .gpio = nv10_gpio_new, 660 .i2c = nv04_i2c_new, 661 .imem = nv40_instmem_new, 662 .mc = nv44_mc_new, 663 .mmu = nv44_mmu_new, 664 .pci = nv46_pci_new, 665 .therm = nv40_therm_new, 666 .timer = nv41_timer_new, 667 .volt = nv40_volt_new, 668 .disp = nv04_disp_new, 669 .dma = nv04_dma_new, 670 .fifo = nv40_fifo_new, 671 .gr = nv44_gr_new, 672 .mpeg = nv44_mpeg_new, 673 .pm = nv40_pm_new, 674 .sw = nv10_sw_new, 675}; 676 677static const struct nvkm_device_chip 678nv47_chipset = { 679 .name = "G70", 680 .bios = nvkm_bios_new, 681 .bus = nv31_bus_new, 682 .clk = nv40_clk_new, 683 .devinit = nv1a_devinit_new, 684 .fb = nv47_fb_new, 685 .gpio = nv10_gpio_new, 686 .i2c = nv04_i2c_new, 687 .imem = nv40_instmem_new, 688 .mc = nv04_mc_new, 689 .mmu = nv41_mmu_new, 690 .pci = nv40_pci_new, 691 .therm = nv40_therm_new, 692 .timer = nv41_timer_new, 693 .volt = nv40_volt_new, 694 .disp = nv04_disp_new, 695 .dma = nv04_dma_new, 696 .fifo = nv40_fifo_new, 697 .gr = nv40_gr_new, 698 .mpeg = nv44_mpeg_new, 699 .pm = nv40_pm_new, 700 .sw = nv10_sw_new, 701}; 702 703static const struct nvkm_device_chip 704nv49_chipset = { 705 .name = "G71", 706 .bios = nvkm_bios_new, 707 .bus = nv31_bus_new, 708 .clk = nv40_clk_new, 709 .devinit = nv1a_devinit_new, 710 .fb = nv49_fb_new, 711 .gpio = nv10_gpio_new, 712 .i2c = nv04_i2c_new, 713 .imem = nv40_instmem_new, 714 .mc = nv04_mc_new, 715 .mmu = nv41_mmu_new, 716 .pci = nv40_pci_new, 717 .therm = nv40_therm_new, 718 .timer = nv41_timer_new, 719 .volt = nv40_volt_new, 720 .disp = nv04_disp_new, 721 .dma = nv04_dma_new, 722 .fifo = nv40_fifo_new, 723 .gr = nv40_gr_new, 724 .mpeg = nv44_mpeg_new, 725 .pm = nv40_pm_new, 726 .sw = nv10_sw_new, 727}; 728 729static const struct nvkm_device_chip 730nv4a_chipset = { 731 .name = "NV44A", 732 .bios = nvkm_bios_new, 733 .bus = nv31_bus_new, 734 .clk = nv40_clk_new, 735 .devinit = nv1a_devinit_new, 736 .fb = nv44_fb_new, 737 .gpio = nv10_gpio_new, 738 .i2c = nv04_i2c_new, 739 .imem = nv40_instmem_new, 740 .mc = nv44_mc_new, 741 .mmu = nv04_mmu_new, 742 .pci = nv40_pci_new, 743 .therm = nv40_therm_new, 744 .timer = nv41_timer_new, 745 .volt = nv40_volt_new, 746 .disp = nv04_disp_new, 747 .dma = nv04_dma_new, 748 .fifo = nv40_fifo_new, 749 .gr = nv44_gr_new, 750 .mpeg = nv44_mpeg_new, 751 .pm = nv40_pm_new, 752 .sw = nv10_sw_new, 753}; 754 755static const struct nvkm_device_chip 756nv4b_chipset = { 757 .name = "G73", 758 .bios = nvkm_bios_new, 759 .bus = nv31_bus_new, 760 .clk = nv40_clk_new, 761 .devinit = nv1a_devinit_new, 762 .fb = nv49_fb_new, 763 .gpio = nv10_gpio_new, 764 .i2c = nv04_i2c_new, 765 .imem = nv40_instmem_new, 766 .mc = nv04_mc_new, 767 .mmu = nv41_mmu_new, 768 .pci = nv40_pci_new, 769 .therm = nv40_therm_new, 770 .timer = nv41_timer_new, 771 .volt = nv40_volt_new, 772 .disp = nv04_disp_new, 773 .dma = nv04_dma_new, 774 .fifo = nv40_fifo_new, 775 .gr = nv40_gr_new, 776 .mpeg = nv44_mpeg_new, 777 .pm = nv40_pm_new, 778 .sw = nv10_sw_new, 779}; 780 781static const struct nvkm_device_chip 782nv4c_chipset = { 783 .name = "C61", 784 .bios = nvkm_bios_new, 785 .bus = nv31_bus_new, 786 .clk = nv40_clk_new, 787 .devinit = nv1a_devinit_new, 788 .fb = nv46_fb_new, 789 .gpio = nv10_gpio_new, 790 .i2c = nv04_i2c_new, 791 .imem = nv40_instmem_new, 792 .mc = nv44_mc_new, 793 .mmu = nv44_mmu_new, 794 .pci = nv4c_pci_new, 795 .therm = nv40_therm_new, 796 .timer = nv41_timer_new, 797 .volt = nv40_volt_new, 798 .disp = nv04_disp_new, 799 .dma = nv04_dma_new, 800 .fifo = nv40_fifo_new, 801 .gr = nv44_gr_new, 802 .mpeg = nv44_mpeg_new, 803 .pm = nv40_pm_new, 804 .sw = nv10_sw_new, 805}; 806 807static const struct nvkm_device_chip 808nv4e_chipset = { 809 .name = "C51", 810 .bios = nvkm_bios_new, 811 .bus = nv31_bus_new, 812 .clk = nv40_clk_new, 813 .devinit = nv1a_devinit_new, 814 .fb = nv4e_fb_new, 815 .gpio = nv10_gpio_new, 816 .i2c = nv4e_i2c_new, 817 .imem = nv40_instmem_new, 818 .mc = nv44_mc_new, 819 .mmu = nv44_mmu_new, 820 .pci = nv4c_pci_new, 821 .therm = nv40_therm_new, 822 .timer = nv41_timer_new, 823 .volt = nv40_volt_new, 824 .disp = nv04_disp_new, 825 .dma = nv04_dma_new, 826 .fifo = nv40_fifo_new, 827 .gr = nv44_gr_new, 828 .mpeg = nv44_mpeg_new, 829 .pm = nv40_pm_new, 830 .sw = nv10_sw_new, 831}; 832 833static const struct nvkm_device_chip 834nv50_chipset = { 835 .name = "G80", 836 .bar = nv50_bar_new, 837 .bios = nvkm_bios_new, 838 .bus = nv50_bus_new, 839 .clk = nv50_clk_new, 840 .devinit = nv50_devinit_new, 841 .fb = nv50_fb_new, 842 .fuse = nv50_fuse_new, 843 .gpio = nv50_gpio_new, 844 .i2c = nv50_i2c_new, 845 .imem = nv50_instmem_new, 846 .mc = nv50_mc_new, 847 .mmu = nv50_mmu_new, 848 .mxm = nv50_mxm_new, 849 .pci = nv46_pci_new, 850 .therm = nv50_therm_new, 851 .timer = nv41_timer_new, 852 .volt = nv40_volt_new, 853 .disp = nv50_disp_new, 854 .dma = nv50_dma_new, 855 .fifo = nv50_fifo_new, 856 .gr = nv50_gr_new, 857 .mpeg = nv50_mpeg_new, 858 .pm = nv50_pm_new, 859 .sw = nv50_sw_new, 860}; 861 862static const struct nvkm_device_chip 863nv63_chipset = { 864 .name = "C73", 865 .bios = nvkm_bios_new, 866 .bus = nv31_bus_new, 867 .clk = nv40_clk_new, 868 .devinit = nv1a_devinit_new, 869 .fb = nv46_fb_new, 870 .gpio = nv10_gpio_new, 871 .i2c = nv04_i2c_new, 872 .imem = nv40_instmem_new, 873 .mc = nv44_mc_new, 874 .mmu = nv44_mmu_new, 875 .pci = nv4c_pci_new, 876 .therm = nv40_therm_new, 877 .timer = nv41_timer_new, 878 .volt = nv40_volt_new, 879 .disp = nv04_disp_new, 880 .dma = nv04_dma_new, 881 .fifo = nv40_fifo_new, 882 .gr = nv44_gr_new, 883 .mpeg = nv44_mpeg_new, 884 .pm = nv40_pm_new, 885 .sw = nv10_sw_new, 886}; 887 888static const struct nvkm_device_chip 889nv67_chipset = { 890 .name = "C67", 891 .bios = nvkm_bios_new, 892 .bus = nv31_bus_new, 893 .clk = nv40_clk_new, 894 .devinit = nv1a_devinit_new, 895 .fb = nv46_fb_new, 896 .gpio = nv10_gpio_new, 897 .i2c = nv04_i2c_new, 898 .imem = nv40_instmem_new, 899 .mc = nv44_mc_new, 900 .mmu = nv44_mmu_new, 901 .pci = nv4c_pci_new, 902 .therm = nv40_therm_new, 903 .timer = nv41_timer_new, 904 .volt = nv40_volt_new, 905 .disp = nv04_disp_new, 906 .dma = nv04_dma_new, 907 .fifo = nv40_fifo_new, 908 .gr = nv44_gr_new, 909 .mpeg = nv44_mpeg_new, 910 .pm = nv40_pm_new, 911 .sw = nv10_sw_new, 912}; 913 914static const struct nvkm_device_chip 915nv68_chipset = { 916 .name = "C68", 917 .bios = nvkm_bios_new, 918 .bus = nv31_bus_new, 919 .clk = nv40_clk_new, 920 .devinit = nv1a_devinit_new, 921 .fb = nv46_fb_new, 922 .gpio = nv10_gpio_new, 923 .i2c = nv04_i2c_new, 924 .imem = nv40_instmem_new, 925 .mc = nv44_mc_new, 926 .mmu = nv44_mmu_new, 927 .pci = nv4c_pci_new, 928 .therm = nv40_therm_new, 929 .timer = nv41_timer_new, 930 .volt = nv40_volt_new, 931 .disp = nv04_disp_new, 932 .dma = nv04_dma_new, 933 .fifo = nv40_fifo_new, 934 .gr = nv44_gr_new, 935 .mpeg = nv44_mpeg_new, 936 .pm = nv40_pm_new, 937 .sw = nv10_sw_new, 938}; 939 940static const struct nvkm_device_chip 941nv84_chipset = { 942 .name = "G84", 943 .bar = g84_bar_new, 944 .bios = nvkm_bios_new, 945 .bus = nv50_bus_new, 946 .clk = g84_clk_new, 947 .devinit = g84_devinit_new, 948 .fb = g84_fb_new, 949 .fuse = nv50_fuse_new, 950 .gpio = nv50_gpio_new, 951 .i2c = nv50_i2c_new, 952 .imem = nv50_instmem_new, 953 .mc = nv50_mc_new, 954 .mmu = nv50_mmu_new, 955 .mxm = nv50_mxm_new, 956 .pci = g84_pci_new, 957 .therm = g84_therm_new, 958 .timer = nv41_timer_new, 959 .volt = nv40_volt_new, 960 .bsp = g84_bsp_new, 961 .cipher = g84_cipher_new, 962 .disp = g84_disp_new, 963 .dma = nv50_dma_new, 964 .fifo = g84_fifo_new, 965 .gr = g84_gr_new, 966 .mpeg = g84_mpeg_new, 967 .pm = g84_pm_new, 968 .sw = nv50_sw_new, 969 .vp = g84_vp_new, 970}; 971 972static const struct nvkm_device_chip 973nv86_chipset = { 974 .name = "G86", 975 .bar = g84_bar_new, 976 .bios = nvkm_bios_new, 977 .bus = nv50_bus_new, 978 .clk = g84_clk_new, 979 .devinit = g84_devinit_new, 980 .fb = g84_fb_new, 981 .fuse = nv50_fuse_new, 982 .gpio = nv50_gpio_new, 983 .i2c = nv50_i2c_new, 984 .imem = nv50_instmem_new, 985 .mc = nv50_mc_new, 986 .mmu = nv50_mmu_new, 987 .mxm = nv50_mxm_new, 988 .pci = g84_pci_new, 989 .therm = g84_therm_new, 990 .timer = nv41_timer_new, 991 .volt = nv40_volt_new, 992 .bsp = g84_bsp_new, 993 .cipher = g84_cipher_new, 994 .disp = g84_disp_new, 995 .dma = nv50_dma_new, 996 .fifo = g84_fifo_new, 997 .gr = g84_gr_new, 998 .mpeg = g84_mpeg_new, 999 .pm = g84_pm_new, 1000 .sw = nv50_sw_new, 1001 .vp = g84_vp_new, 1002}; 1003 1004static const struct nvkm_device_chip 1005nv92_chipset = { 1006 .name = "G92", 1007 .bar = g84_bar_new, 1008 .bios = nvkm_bios_new, 1009 .bus = nv50_bus_new, 1010 .clk = g84_clk_new, 1011 .devinit = g84_devinit_new, 1012 .fb = g84_fb_new, 1013 .fuse = nv50_fuse_new, 1014 .gpio = nv50_gpio_new, 1015 .i2c = nv50_i2c_new, 1016 .imem = nv50_instmem_new, 1017 .mc = nv50_mc_new, 1018 .mmu = nv50_mmu_new, 1019 .mxm = nv50_mxm_new, 1020 .pci = g84_pci_new, 1021 .therm = g84_therm_new, 1022 .timer = nv41_timer_new, 1023 .volt = nv40_volt_new, 1024 .bsp = g84_bsp_new, 1025 .cipher = g84_cipher_new, 1026 .disp = g84_disp_new, 1027 .dma = nv50_dma_new, 1028 .fifo = g84_fifo_new, 1029 .gr = g84_gr_new, 1030 .mpeg = g84_mpeg_new, 1031 .pm = g84_pm_new, 1032 .sw = nv50_sw_new, 1033 .vp = g84_vp_new, 1034}; 1035 1036static const struct nvkm_device_chip 1037nv94_chipset = { 1038 .name = "G94", 1039 .bar = g84_bar_new, 1040 .bios = nvkm_bios_new, 1041 .bus = g94_bus_new, 1042 .clk = g84_clk_new, 1043 .devinit = g84_devinit_new, 1044 .fb = g84_fb_new, 1045 .fuse = nv50_fuse_new, 1046 .gpio = g94_gpio_new, 1047 .i2c = g94_i2c_new, 1048 .imem = nv50_instmem_new, 1049 .mc = nv50_mc_new, 1050 .mmu = nv50_mmu_new, 1051 .mxm = nv50_mxm_new, 1052 .pci = g94_pci_new, 1053 .therm = g84_therm_new, 1054 .timer = nv41_timer_new, 1055 .volt = nv40_volt_new, 1056 .bsp = g84_bsp_new, 1057 .cipher = g84_cipher_new, 1058 .disp = g94_disp_new, 1059 .dma = nv50_dma_new, 1060 .fifo = g84_fifo_new, 1061 .gr = g84_gr_new, 1062 .mpeg = g84_mpeg_new, 1063 .pm = g84_pm_new, 1064 .sw = nv50_sw_new, 1065 .vp = g84_vp_new, 1066}; 1067 1068static const struct nvkm_device_chip 1069nv96_chipset = { 1070 .name = "G96", 1071 .bar = g84_bar_new, 1072 .bios = nvkm_bios_new, 1073 .bus = g94_bus_new, 1074 .clk = g84_clk_new, 1075 .devinit = g84_devinit_new, 1076 .fb = g84_fb_new, 1077 .fuse = nv50_fuse_new, 1078 .gpio = g94_gpio_new, 1079 .i2c = g94_i2c_new, 1080 .imem = nv50_instmem_new, 1081 .mc = nv50_mc_new, 1082 .mmu = nv50_mmu_new, 1083 .mxm = nv50_mxm_new, 1084 .pci = g94_pci_new, 1085 .therm = g84_therm_new, 1086 .timer = nv41_timer_new, 1087 .volt = nv40_volt_new, 1088 .bsp = g84_bsp_new, 1089 .cipher = g84_cipher_new, 1090 .disp = g94_disp_new, 1091 .dma = nv50_dma_new, 1092 .fifo = g84_fifo_new, 1093 .gr = g84_gr_new, 1094 .mpeg = g84_mpeg_new, 1095 .pm = g84_pm_new, 1096 .sw = nv50_sw_new, 1097 .vp = g84_vp_new, 1098}; 1099 1100static const struct nvkm_device_chip 1101nv98_chipset = { 1102 .name = "G98", 1103 .bar = g84_bar_new, 1104 .bios = nvkm_bios_new, 1105 .bus = g94_bus_new, 1106 .clk = g84_clk_new, 1107 .devinit = g98_devinit_new, 1108 .fb = g84_fb_new, 1109 .fuse = nv50_fuse_new, 1110 .gpio = g94_gpio_new, 1111 .i2c = g94_i2c_new, 1112 .imem = nv50_instmem_new, 1113 .mc = g98_mc_new, 1114 .mmu = nv50_mmu_new, 1115 .mxm = nv50_mxm_new, 1116 .pci = g94_pci_new, 1117 .therm = g84_therm_new, 1118 .timer = nv41_timer_new, 1119 .volt = nv40_volt_new, 1120 .disp = g94_disp_new, 1121 .dma = nv50_dma_new, 1122 .fifo = g84_fifo_new, 1123 .gr = g84_gr_new, 1124 .mspdec = g98_mspdec_new, 1125 .msppp = g98_msppp_new, 1126 .msvld = g98_msvld_new, 1127 .pm = g84_pm_new, 1128 .sec = g98_sec_new, 1129 .sw = nv50_sw_new, 1130}; 1131 1132static const struct nvkm_device_chip 1133nva0_chipset = { 1134 .name = "GT200", 1135 .bar = g84_bar_new, 1136 .bios = nvkm_bios_new, 1137 .bus = g94_bus_new, 1138 .clk = g84_clk_new, 1139 .devinit = g84_devinit_new, 1140 .fb = g84_fb_new, 1141 .fuse = nv50_fuse_new, 1142 .gpio = g94_gpio_new, 1143 .i2c = nv50_i2c_new, 1144 .imem = nv50_instmem_new, 1145 .mc = g98_mc_new, 1146 .mmu = nv50_mmu_new, 1147 .mxm = nv50_mxm_new, 1148 .pci = g94_pci_new, 1149 .therm = g84_therm_new, 1150 .timer = nv41_timer_new, 1151 .volt = nv40_volt_new, 1152 .bsp = g84_bsp_new, 1153 .cipher = g84_cipher_new, 1154 .disp = gt200_disp_new, 1155 .dma = nv50_dma_new, 1156 .fifo = g84_fifo_new, 1157 .gr = gt200_gr_new, 1158 .mpeg = g84_mpeg_new, 1159 .pm = gt200_pm_new, 1160 .sw = nv50_sw_new, 1161 .vp = g84_vp_new, 1162}; 1163 1164static const struct nvkm_device_chip 1165nva3_chipset = { 1166 .name = "GT215", 1167 .bar = g84_bar_new, 1168 .bios = nvkm_bios_new, 1169 .bus = g94_bus_new, 1170 .clk = gt215_clk_new, 1171 .devinit = gt215_devinit_new, 1172 .fb = gt215_fb_new, 1173 .fuse = nv50_fuse_new, 1174 .gpio = g94_gpio_new, 1175 .i2c = g94_i2c_new, 1176 .imem = nv50_instmem_new, 1177 .mc = g98_mc_new, 1178 .mmu = nv50_mmu_new, 1179 .mxm = nv50_mxm_new, 1180 .pci = g94_pci_new, 1181 .pmu = gt215_pmu_new, 1182 .therm = gt215_therm_new, 1183 .timer = nv41_timer_new, 1184 .volt = nv40_volt_new, 1185 .ce[0] = gt215_ce_new, 1186 .disp = gt215_disp_new, 1187 .dma = nv50_dma_new, 1188 .fifo = g84_fifo_new, 1189 .gr = gt215_gr_new, 1190 .mpeg = g84_mpeg_new, 1191 .mspdec = gt215_mspdec_new, 1192 .msppp = gt215_msppp_new, 1193 .msvld = gt215_msvld_new, 1194 .pm = gt215_pm_new, 1195 .sw = nv50_sw_new, 1196}; 1197 1198static const struct nvkm_device_chip 1199nva5_chipset = { 1200 .name = "GT216", 1201 .bar = g84_bar_new, 1202 .bios = nvkm_bios_new, 1203 .bus = g94_bus_new, 1204 .clk = gt215_clk_new, 1205 .devinit = gt215_devinit_new, 1206 .fb = gt215_fb_new, 1207 .fuse = nv50_fuse_new, 1208 .gpio = g94_gpio_new, 1209 .i2c = g94_i2c_new, 1210 .imem = nv50_instmem_new, 1211 .mc = g98_mc_new, 1212 .mmu = nv50_mmu_new, 1213 .mxm = nv50_mxm_new, 1214 .pci = g94_pci_new, 1215 .pmu = gt215_pmu_new, 1216 .therm = gt215_therm_new, 1217 .timer = nv41_timer_new, 1218 .volt = nv40_volt_new, 1219 .ce[0] = gt215_ce_new, 1220 .disp = gt215_disp_new, 1221 .dma = nv50_dma_new, 1222 .fifo = g84_fifo_new, 1223 .gr = gt215_gr_new, 1224 .mspdec = gt215_mspdec_new, 1225 .msppp = gt215_msppp_new, 1226 .msvld = gt215_msvld_new, 1227 .pm = gt215_pm_new, 1228 .sw = nv50_sw_new, 1229}; 1230 1231static const struct nvkm_device_chip 1232nva8_chipset = { 1233 .name = "GT218", 1234 .bar = g84_bar_new, 1235 .bios = nvkm_bios_new, 1236 .bus = g94_bus_new, 1237 .clk = gt215_clk_new, 1238 .devinit = gt215_devinit_new, 1239 .fb = gt215_fb_new, 1240 .fuse = nv50_fuse_new, 1241 .gpio = g94_gpio_new, 1242 .i2c = g94_i2c_new, 1243 .imem = nv50_instmem_new, 1244 .mc = g98_mc_new, 1245 .mmu = nv50_mmu_new, 1246 .mxm = nv50_mxm_new, 1247 .pci = g94_pci_new, 1248 .pmu = gt215_pmu_new, 1249 .therm = gt215_therm_new, 1250 .timer = nv41_timer_new, 1251 .volt = nv40_volt_new, 1252 .ce[0] = gt215_ce_new, 1253 .disp = gt215_disp_new, 1254 .dma = nv50_dma_new, 1255 .fifo = g84_fifo_new, 1256 .gr = gt215_gr_new, 1257 .mspdec = gt215_mspdec_new, 1258 .msppp = gt215_msppp_new, 1259 .msvld = gt215_msvld_new, 1260 .pm = gt215_pm_new, 1261 .sw = nv50_sw_new, 1262}; 1263 1264static const struct nvkm_device_chip 1265nvaa_chipset = { 1266 .name = "MCP77/MCP78", 1267 .bar = g84_bar_new, 1268 .bios = nvkm_bios_new, 1269 .bus = g94_bus_new, 1270 .clk = mcp77_clk_new, 1271 .devinit = g98_devinit_new, 1272 .fb = mcp77_fb_new, 1273 .fuse = nv50_fuse_new, 1274 .gpio = g94_gpio_new, 1275 .i2c = g94_i2c_new, 1276 .imem = nv50_instmem_new, 1277 .mc = g98_mc_new, 1278 .mmu = nv50_mmu_new, 1279 .mxm = nv50_mxm_new, 1280 .pci = g94_pci_new, 1281 .therm = g84_therm_new, 1282 .timer = nv41_timer_new, 1283 .volt = nv40_volt_new, 1284 .disp = g94_disp_new, 1285 .dma = nv50_dma_new, 1286 .fifo = g84_fifo_new, 1287 .gr = gt200_gr_new, 1288 .mspdec = g98_mspdec_new, 1289 .msppp = g98_msppp_new, 1290 .msvld = g98_msvld_new, 1291 .pm = g84_pm_new, 1292 .sec = g98_sec_new, 1293 .sw = nv50_sw_new, 1294}; 1295 1296static const struct nvkm_device_chip 1297nvac_chipset = { 1298 .name = "MCP79/MCP7A", 1299 .bar = g84_bar_new, 1300 .bios = nvkm_bios_new, 1301 .bus = g94_bus_new, 1302 .clk = mcp77_clk_new, 1303 .devinit = g98_devinit_new, 1304 .fb = mcp77_fb_new, 1305 .fuse = nv50_fuse_new, 1306 .gpio = g94_gpio_new, 1307 .i2c = g94_i2c_new, 1308 .imem = nv50_instmem_new, 1309 .mc = g98_mc_new, 1310 .mmu = nv50_mmu_new, 1311 .mxm = nv50_mxm_new, 1312 .pci = g94_pci_new, 1313 .therm = g84_therm_new, 1314 .timer = nv41_timer_new, 1315 .volt = nv40_volt_new, 1316 .disp = g94_disp_new, 1317 .dma = nv50_dma_new, 1318 .fifo = g84_fifo_new, 1319 .gr = mcp79_gr_new, 1320 .mspdec = g98_mspdec_new, 1321 .msppp = g98_msppp_new, 1322 .msvld = g98_msvld_new, 1323 .pm = g84_pm_new, 1324 .sec = g98_sec_new, 1325 .sw = nv50_sw_new, 1326}; 1327 1328static const struct nvkm_device_chip 1329nvaf_chipset = { 1330 .name = "MCP89", 1331 .bar = g84_bar_new, 1332 .bios = nvkm_bios_new, 1333 .bus = g94_bus_new, 1334 .clk = gt215_clk_new, 1335 .devinit = mcp89_devinit_new, 1336 .fb = mcp89_fb_new, 1337 .fuse = nv50_fuse_new, 1338 .gpio = g94_gpio_new, 1339 .i2c = g94_i2c_new, 1340 .imem = nv50_instmem_new, 1341 .mc = g98_mc_new, 1342 .mmu = nv50_mmu_new, 1343 .mxm = nv50_mxm_new, 1344 .pci = g94_pci_new, 1345 .pmu = gt215_pmu_new, 1346 .therm = gt215_therm_new, 1347 .timer = nv41_timer_new, 1348 .volt = nv40_volt_new, 1349 .ce[0] = gt215_ce_new, 1350 .disp = gt215_disp_new, 1351 .dma = nv50_dma_new, 1352 .fifo = g84_fifo_new, 1353 .gr = mcp89_gr_new, 1354 .mspdec = gt215_mspdec_new, 1355 .msppp = gt215_msppp_new, 1356 .msvld = mcp89_msvld_new, 1357 .pm = gt215_pm_new, 1358 .sw = nv50_sw_new, 1359}; 1360 1361static const struct nvkm_device_chip 1362nvc0_chipset = { 1363 .name = "GF100", 1364 .bar = gf100_bar_new, 1365 .bios = nvkm_bios_new, 1366 .bus = gf100_bus_new, 1367 .clk = gf100_clk_new, 1368 .devinit = gf100_devinit_new, 1369 .fb = gf100_fb_new, 1370 .fuse = gf100_fuse_new, 1371 .gpio = g94_gpio_new, 1372 .i2c = g94_i2c_new, 1373 .ibus = gf100_ibus_new, 1374 .imem = nv50_instmem_new, 1375 .ltc = gf100_ltc_new, 1376 .mc = gf100_mc_new, 1377 .mmu = gf100_mmu_new, 1378 .mxm = nv50_mxm_new, 1379 .pci = gf100_pci_new, 1380 .pmu = gf100_pmu_new, 1381 .therm = gt215_therm_new, 1382 .timer = nv41_timer_new, 1383 .volt = nv40_volt_new, 1384 .ce[0] = gf100_ce_new, 1385 .ce[1] = gf100_ce_new, 1386 .disp = gt215_disp_new, 1387 .dma = gf100_dma_new, 1388 .fifo = gf100_fifo_new, 1389 .gr = gf100_gr_new, 1390 .mspdec = gf100_mspdec_new, 1391 .msppp = gf100_msppp_new, 1392 .msvld = gf100_msvld_new, 1393 .pm = gf100_pm_new, 1394 .sw = gf100_sw_new, 1395}; 1396 1397static const struct nvkm_device_chip 1398nvc1_chipset = { 1399 .name = "GF108", 1400 .bar = gf100_bar_new, 1401 .bios = nvkm_bios_new, 1402 .bus = gf100_bus_new, 1403 .clk = gf100_clk_new, 1404 .devinit = gf100_devinit_new, 1405 .fb = gf100_fb_new, 1406 .fuse = gf100_fuse_new, 1407 .gpio = g94_gpio_new, 1408 .i2c = g94_i2c_new, 1409 .ibus = gf100_ibus_new, 1410 .imem = nv50_instmem_new, 1411 .ltc = gf100_ltc_new, 1412 .mc = gf100_mc_new, 1413 .mmu = gf100_mmu_new, 1414 .mxm = nv50_mxm_new, 1415 .pci = g94_pci_new, 1416 .pmu = gf100_pmu_new, 1417 .therm = gt215_therm_new, 1418 .timer = nv41_timer_new, 1419 .volt = nv40_volt_new, 1420 .ce[0] = gf100_ce_new, 1421 .disp = gt215_disp_new, 1422 .dma = gf100_dma_new, 1423 .fifo = gf100_fifo_new, 1424 .gr = gf108_gr_new, 1425 .mspdec = gf100_mspdec_new, 1426 .msppp = gf100_msppp_new, 1427 .msvld = gf100_msvld_new, 1428 .pm = gf108_pm_new, 1429 .sw = gf100_sw_new, 1430}; 1431 1432static const struct nvkm_device_chip 1433nvc3_chipset = { 1434 .name = "GF106", 1435 .bar = gf100_bar_new, 1436 .bios = nvkm_bios_new, 1437 .bus = gf100_bus_new, 1438 .clk = gf100_clk_new, 1439 .devinit = gf100_devinit_new, 1440 .fb = gf100_fb_new, 1441 .fuse = gf100_fuse_new, 1442 .gpio = g94_gpio_new, 1443 .i2c = g94_i2c_new, 1444 .ibus = gf100_ibus_new, 1445 .imem = nv50_instmem_new, 1446 .ltc = gf100_ltc_new, 1447 .mc = gf100_mc_new, 1448 .mmu = gf100_mmu_new, 1449 .mxm = nv50_mxm_new, 1450 .pci = g94_pci_new, 1451 .pmu = gf100_pmu_new, 1452 .therm = gt215_therm_new, 1453 .timer = nv41_timer_new, 1454 .volt = nv40_volt_new, 1455 .ce[0] = gf100_ce_new, 1456 .disp = gt215_disp_new, 1457 .dma = gf100_dma_new, 1458 .fifo = gf100_fifo_new, 1459 .gr = gf104_gr_new, 1460 .mspdec = gf100_mspdec_new, 1461 .msppp = gf100_msppp_new, 1462 .msvld = gf100_msvld_new, 1463 .pm = gf100_pm_new, 1464 .sw = gf100_sw_new, 1465}; 1466 1467static const struct nvkm_device_chip 1468nvc4_chipset = { 1469 .name = "GF104", 1470 .bar = gf100_bar_new, 1471 .bios = nvkm_bios_new, 1472 .bus = gf100_bus_new, 1473 .clk = gf100_clk_new, 1474 .devinit = gf100_devinit_new, 1475 .fb = gf100_fb_new, 1476 .fuse = gf100_fuse_new, 1477 .gpio = g94_gpio_new, 1478 .i2c = g94_i2c_new, 1479 .ibus = gf100_ibus_new, 1480 .imem = nv50_instmem_new, 1481 .ltc = gf100_ltc_new, 1482 .mc = gf100_mc_new, 1483 .mmu = gf100_mmu_new, 1484 .mxm = nv50_mxm_new, 1485 .pci = gf100_pci_new, 1486 .pmu = gf100_pmu_new, 1487 .therm = gt215_therm_new, 1488 .timer = nv41_timer_new, 1489 .volt = nv40_volt_new, 1490 .ce[0] = gf100_ce_new, 1491 .ce[1] = gf100_ce_new, 1492 .disp = gt215_disp_new, 1493 .dma = gf100_dma_new, 1494 .fifo = gf100_fifo_new, 1495 .gr = gf104_gr_new, 1496 .mspdec = gf100_mspdec_new, 1497 .msppp = gf100_msppp_new, 1498 .msvld = gf100_msvld_new, 1499 .pm = gf100_pm_new, 1500 .sw = gf100_sw_new, 1501}; 1502 1503static const struct nvkm_device_chip 1504nvc8_chipset = { 1505 .name = "GF110", 1506 .bar = gf100_bar_new, 1507 .bios = nvkm_bios_new, 1508 .bus = gf100_bus_new, 1509 .clk = gf100_clk_new, 1510 .devinit = gf100_devinit_new, 1511 .fb = gf100_fb_new, 1512 .fuse = gf100_fuse_new, 1513 .gpio = g94_gpio_new, 1514 .i2c = g94_i2c_new, 1515 .ibus = gf100_ibus_new, 1516 .imem = nv50_instmem_new, 1517 .ltc = gf100_ltc_new, 1518 .mc = gf100_mc_new, 1519 .mmu = gf100_mmu_new, 1520 .mxm = nv50_mxm_new, 1521 .pci = gf100_pci_new, 1522 .pmu = gf100_pmu_new, 1523 .therm = gt215_therm_new, 1524 .timer = nv41_timer_new, 1525 .volt = nv40_volt_new, 1526 .ce[0] = gf100_ce_new, 1527 .ce[1] = gf100_ce_new, 1528 .disp = gt215_disp_new, 1529 .dma = gf100_dma_new, 1530 .fifo = gf100_fifo_new, 1531 .gr = gf110_gr_new, 1532 .mspdec = gf100_mspdec_new, 1533 .msppp = gf100_msppp_new, 1534 .msvld = gf100_msvld_new, 1535 .pm = gf100_pm_new, 1536 .sw = gf100_sw_new, 1537}; 1538 1539static const struct nvkm_device_chip 1540nvce_chipset = { 1541 .name = "GF114", 1542 .bar = gf100_bar_new, 1543 .bios = nvkm_bios_new, 1544 .bus = gf100_bus_new, 1545 .clk = gf100_clk_new, 1546 .devinit = gf100_devinit_new, 1547 .fb = gf100_fb_new, 1548 .fuse = gf100_fuse_new, 1549 .gpio = g94_gpio_new, 1550 .i2c = g94_i2c_new, 1551 .ibus = gf100_ibus_new, 1552 .imem = nv50_instmem_new, 1553 .ltc = gf100_ltc_new, 1554 .mc = gf100_mc_new, 1555 .mmu = gf100_mmu_new, 1556 .mxm = nv50_mxm_new, 1557 .pci = gf100_pci_new, 1558 .pmu = gf100_pmu_new, 1559 .therm = gt215_therm_new, 1560 .timer = nv41_timer_new, 1561 .volt = nv40_volt_new, 1562 .ce[0] = gf100_ce_new, 1563 .ce[1] = gf100_ce_new, 1564 .disp = gt215_disp_new, 1565 .dma = gf100_dma_new, 1566 .fifo = gf100_fifo_new, 1567 .gr = gf104_gr_new, 1568 .mspdec = gf100_mspdec_new, 1569 .msppp = gf100_msppp_new, 1570 .msvld = gf100_msvld_new, 1571 .pm = gf100_pm_new, 1572 .sw = gf100_sw_new, 1573}; 1574 1575static const struct nvkm_device_chip 1576nvcf_chipset = { 1577 .name = "GF116", 1578 .bar = gf100_bar_new, 1579 .bios = nvkm_bios_new, 1580 .bus = gf100_bus_new, 1581 .clk = gf100_clk_new, 1582 .devinit = gf100_devinit_new, 1583 .fb = gf100_fb_new, 1584 .fuse = gf100_fuse_new, 1585 .gpio = g94_gpio_new, 1586 .i2c = g94_i2c_new, 1587 .ibus = gf100_ibus_new, 1588 .imem = nv50_instmem_new, 1589 .ltc = gf100_ltc_new, 1590 .mc = gf100_mc_new, 1591 .mmu = gf100_mmu_new, 1592 .mxm = nv50_mxm_new, 1593 .pci = g94_pci_new, 1594 .pmu = gf100_pmu_new, 1595 .therm = gt215_therm_new, 1596 .timer = nv41_timer_new, 1597 .volt = nv40_volt_new, 1598 .ce[0] = gf100_ce_new, 1599 .disp = gt215_disp_new, 1600 .dma = gf100_dma_new, 1601 .fifo = gf100_fifo_new, 1602 .gr = gf104_gr_new, 1603 .mspdec = gf100_mspdec_new, 1604 .msppp = gf100_msppp_new, 1605 .msvld = gf100_msvld_new, 1606 .pm = gf100_pm_new, 1607 .sw = gf100_sw_new, 1608}; 1609 1610static const struct nvkm_device_chip 1611nvd7_chipset = { 1612 .name = "GF117", 1613 .bar = gf100_bar_new, 1614 .bios = nvkm_bios_new, 1615 .bus = gf100_bus_new, 1616 .clk = gf100_clk_new, 1617 .devinit = gf100_devinit_new, 1618 .fb = gf100_fb_new, 1619 .fuse = gf100_fuse_new, 1620 .gpio = gf119_gpio_new, 1621 .i2c = gf117_i2c_new, 1622 .ibus = gf117_ibus_new, 1623 .imem = nv50_instmem_new, 1624 .ltc = gf100_ltc_new, 1625 .mc = gf100_mc_new, 1626 .mmu = gf100_mmu_new, 1627 .mxm = nv50_mxm_new, 1628 .pci = g94_pci_new, 1629 .therm = gf119_therm_new, 1630 .timer = nv41_timer_new, 1631 .ce[0] = gf100_ce_new, 1632 .disp = gf119_disp_new, 1633 .dma = gf119_dma_new, 1634 .fifo = gf100_fifo_new, 1635 .gr = gf117_gr_new, 1636 .mspdec = gf100_mspdec_new, 1637 .msppp = gf100_msppp_new, 1638 .msvld = gf100_msvld_new, 1639 .pm = gf117_pm_new, 1640 .sw = gf100_sw_new, 1641}; 1642 1643static const struct nvkm_device_chip 1644nvd9_chipset = { 1645 .name = "GF119", 1646 .bar = gf100_bar_new, 1647 .bios = nvkm_bios_new, 1648 .bus = gf100_bus_new, 1649 .clk = gf100_clk_new, 1650 .devinit = gf100_devinit_new, 1651 .fb = gf100_fb_new, 1652 .fuse = gf100_fuse_new, 1653 .gpio = gf119_gpio_new, 1654 .i2c = gf119_i2c_new, 1655 .ibus = gf117_ibus_new, 1656 .imem = nv50_instmem_new, 1657 .ltc = gf100_ltc_new, 1658 .mc = gf100_mc_new, 1659 .mmu = gf100_mmu_new, 1660 .mxm = nv50_mxm_new, 1661 .pci = g94_pci_new, 1662 .pmu = gf119_pmu_new, 1663 .therm = gf119_therm_new, 1664 .timer = nv41_timer_new, 1665 .volt = nv40_volt_new, 1666 .ce[0] = gf100_ce_new, 1667 .disp = gf119_disp_new, 1668 .dma = gf119_dma_new, 1669 .fifo = gf100_fifo_new, 1670 .gr = gf119_gr_new, 1671 .mspdec = gf100_mspdec_new, 1672 .msppp = gf100_msppp_new, 1673 .msvld = gf100_msvld_new, 1674 .pm = gf117_pm_new, 1675 .sw = gf100_sw_new, 1676}; 1677 1678static const struct nvkm_device_chip 1679nve4_chipset = { 1680 .name = "GK104", 1681 .bar = gf100_bar_new, 1682 .bios = nvkm_bios_new, 1683 .bus = gf100_bus_new, 1684 .clk = gk104_clk_new, 1685 .devinit = gf100_devinit_new, 1686 .fb = gk104_fb_new, 1687 .fuse = gf100_fuse_new, 1688 .gpio = gk104_gpio_new, 1689 .i2c = gk104_i2c_new, 1690 .ibus = gk104_ibus_new, 1691 .imem = nv50_instmem_new, 1692 .ltc = gk104_ltc_new, 1693 .mc = gf100_mc_new, 1694 .mmu = gf100_mmu_new, 1695 .mxm = nv50_mxm_new, 1696 .pci = g94_pci_new, 1697 .pmu = gk104_pmu_new, 1698 .therm = gf119_therm_new, 1699 .timer = nv41_timer_new, 1700 .volt = gk104_volt_new, 1701 .ce[0] = gk104_ce_new, 1702 .ce[1] = gk104_ce_new, 1703 .ce[2] = gk104_ce_new, 1704 .disp = gk104_disp_new, 1705 .dma = gf119_dma_new, 1706 .fifo = gk104_fifo_new, 1707 .gr = gk104_gr_new, 1708 .mspdec = gk104_mspdec_new, 1709 .msppp = gf100_msppp_new, 1710 .msvld = gk104_msvld_new, 1711 .pm = gk104_pm_new, 1712 .sw = gf100_sw_new, 1713}; 1714 1715static const struct nvkm_device_chip 1716nve6_chipset = { 1717 .name = "GK106", 1718 .bar = gf100_bar_new, 1719 .bios = nvkm_bios_new, 1720 .bus = gf100_bus_new, 1721 .clk = gk104_clk_new, 1722 .devinit = gf100_devinit_new, 1723 .fb = gk104_fb_new, 1724 .fuse = gf100_fuse_new, 1725 .gpio = gk104_gpio_new, 1726 .i2c = gk104_i2c_new, 1727 .ibus = gk104_ibus_new, 1728 .imem = nv50_instmem_new, 1729 .ltc = gk104_ltc_new, 1730 .mc = gf100_mc_new, 1731 .mmu = gf100_mmu_new, 1732 .mxm = nv50_mxm_new, 1733 .pci = g94_pci_new, 1734 .pmu = gk104_pmu_new, 1735 .therm = gf119_therm_new, 1736 .timer = nv41_timer_new, 1737 .volt = gk104_volt_new, 1738 .ce[0] = gk104_ce_new, 1739 .ce[1] = gk104_ce_new, 1740 .ce[2] = gk104_ce_new, 1741 .disp = gk104_disp_new, 1742 .dma = gf119_dma_new, 1743 .fifo = gk104_fifo_new, 1744 .gr = gk104_gr_new, 1745 .mspdec = gk104_mspdec_new, 1746 .msppp = gf100_msppp_new, 1747 .msvld = gk104_msvld_new, 1748 .pm = gk104_pm_new, 1749 .sw = gf100_sw_new, 1750}; 1751 1752static const struct nvkm_device_chip 1753nve7_chipset = { 1754 .name = "GK107", 1755 .bar = gf100_bar_new, 1756 .bios = nvkm_bios_new, 1757 .bus = gf100_bus_new, 1758 .clk = gk104_clk_new, 1759 .devinit = gf100_devinit_new, 1760 .fb = gk104_fb_new, 1761 .fuse = gf100_fuse_new, 1762 .gpio = gk104_gpio_new, 1763 .i2c = gk104_i2c_new, 1764 .ibus = gk104_ibus_new, 1765 .imem = nv50_instmem_new, 1766 .ltc = gk104_ltc_new, 1767 .mc = gf100_mc_new, 1768 .mmu = gf100_mmu_new, 1769 .mxm = nv50_mxm_new, 1770 .pci = g94_pci_new, 1771 .pmu = gk104_pmu_new, 1772 .therm = gf119_therm_new, 1773 .timer = nv41_timer_new, 1774 .volt = gk104_volt_new, 1775 .ce[0] = gk104_ce_new, 1776 .ce[1] = gk104_ce_new, 1777 .ce[2] = gk104_ce_new, 1778 .disp = gk104_disp_new, 1779 .dma = gf119_dma_new, 1780 .fifo = gk104_fifo_new, 1781 .gr = gk104_gr_new, 1782 .mspdec = gk104_mspdec_new, 1783 .msppp = gf100_msppp_new, 1784 .msvld = gk104_msvld_new, 1785 .pm = gk104_pm_new, 1786 .sw = gf100_sw_new, 1787}; 1788 1789static const struct nvkm_device_chip 1790nvea_chipset = { 1791 .name = "GK20A", 1792 .bar = gk20a_bar_new, 1793 .bus = gf100_bus_new, 1794 .clk = gk20a_clk_new, 1795 .fb = gk20a_fb_new, 1796 .fuse = gf100_fuse_new, 1797 .ibus = gk20a_ibus_new, 1798 .imem = gk20a_instmem_new, 1799 .ltc = gk104_ltc_new, 1800 .mc = gk20a_mc_new, 1801 .mmu = gf100_mmu_new, 1802 .pmu = gk20a_pmu_new, 1803 .timer = gk20a_timer_new, 1804 .volt = gk20a_volt_new, 1805 .ce[2] = gk104_ce_new, 1806 .dma = gf119_dma_new, 1807 .fifo = gk20a_fifo_new, 1808 .gr = gk20a_gr_new, 1809 .pm = gk104_pm_new, 1810 .sw = gf100_sw_new, 1811}; 1812 1813static const struct nvkm_device_chip 1814nvf0_chipset = { 1815 .name = "GK110", 1816 .bar = gf100_bar_new, 1817 .bios = nvkm_bios_new, 1818 .bus = gf100_bus_new, 1819 .clk = gk104_clk_new, 1820 .devinit = gf100_devinit_new, 1821 .fb = gk104_fb_new, 1822 .fuse = gf100_fuse_new, 1823 .gpio = gk104_gpio_new, 1824 .i2c = gk104_i2c_new, 1825 .ibus = gk104_ibus_new, 1826 .imem = nv50_instmem_new, 1827 .ltc = gk104_ltc_new, 1828 .mc = gf100_mc_new, 1829 .mmu = gf100_mmu_new, 1830 .mxm = nv50_mxm_new, 1831 .pci = g94_pci_new, 1832 .pmu = gk110_pmu_new, 1833 .therm = gf119_therm_new, 1834 .timer = nv41_timer_new, 1835 .volt = gk104_volt_new, 1836 .ce[0] = gk104_ce_new, 1837 .ce[1] = gk104_ce_new, 1838 .ce[2] = gk104_ce_new, 1839 .disp = gk110_disp_new, 1840 .dma = gf119_dma_new, 1841 .fifo = gk104_fifo_new, 1842 .gr = gk110_gr_new, 1843 .mspdec = gk104_mspdec_new, 1844 .msppp = gf100_msppp_new, 1845 .msvld = gk104_msvld_new, 1846 .sw = gf100_sw_new, 1847}; 1848 1849static const struct nvkm_device_chip 1850nvf1_chipset = { 1851 .name = "GK110B", 1852 .bar = gf100_bar_new, 1853 .bios = nvkm_bios_new, 1854 .bus = gf100_bus_new, 1855 .clk = gk104_clk_new, 1856 .devinit = gf100_devinit_new, 1857 .fb = gk104_fb_new, 1858 .fuse = gf100_fuse_new, 1859 .gpio = gk104_gpio_new, 1860 .i2c = gk104_i2c_new, 1861 .ibus = gk104_ibus_new, 1862 .imem = nv50_instmem_new, 1863 .ltc = gk104_ltc_new, 1864 .mc = gf100_mc_new, 1865 .mmu = gf100_mmu_new, 1866 .mxm = nv50_mxm_new, 1867 .pci = g94_pci_new, 1868 .pmu = gk110_pmu_new, 1869 .therm = gf119_therm_new, 1870 .timer = nv41_timer_new, 1871 .volt = gk104_volt_new, 1872 .ce[0] = gk104_ce_new, 1873 .ce[1] = gk104_ce_new, 1874 .ce[2] = gk104_ce_new, 1875 .disp = gk110_disp_new, 1876 .dma = gf119_dma_new, 1877 .fifo = gk104_fifo_new, 1878 .gr = gk110b_gr_new, 1879 .mspdec = gk104_mspdec_new, 1880 .msppp = gf100_msppp_new, 1881 .msvld = gk104_msvld_new, 1882 .sw = gf100_sw_new, 1883}; 1884 1885static const struct nvkm_device_chip 1886nv106_chipset = { 1887 .name = "GK208B", 1888 .bar = gf100_bar_new, 1889 .bios = nvkm_bios_new, 1890 .bus = gf100_bus_new, 1891 .clk = gk104_clk_new, 1892 .devinit = gf100_devinit_new, 1893 .fb = gk104_fb_new, 1894 .fuse = gf100_fuse_new, 1895 .gpio = gk104_gpio_new, 1896 .i2c = gk104_i2c_new, 1897 .ibus = gk104_ibus_new, 1898 .imem = nv50_instmem_new, 1899 .ltc = gk104_ltc_new, 1900 .mc = gk20a_mc_new, 1901 .mmu = gf100_mmu_new, 1902 .mxm = nv50_mxm_new, 1903 .pci = g94_pci_new, 1904 .pmu = gk208_pmu_new, 1905 .therm = gf119_therm_new, 1906 .timer = nv41_timer_new, 1907 .volt = gk104_volt_new, 1908 .ce[0] = gk104_ce_new, 1909 .ce[1] = gk104_ce_new, 1910 .ce[2] = gk104_ce_new, 1911 .disp = gk110_disp_new, 1912 .dma = gf119_dma_new, 1913 .fifo = gk208_fifo_new, 1914 .gr = gk208_gr_new, 1915 .mspdec = gk104_mspdec_new, 1916 .msppp = gf100_msppp_new, 1917 .msvld = gk104_msvld_new, 1918 .sw = gf100_sw_new, 1919}; 1920 1921static const struct nvkm_device_chip 1922nv108_chipset = { 1923 .name = "GK208", 1924 .bar = gf100_bar_new, 1925 .bios = nvkm_bios_new, 1926 .bus = gf100_bus_new, 1927 .clk = gk104_clk_new, 1928 .devinit = gf100_devinit_new, 1929 .fb = gk104_fb_new, 1930 .fuse = gf100_fuse_new, 1931 .gpio = gk104_gpio_new, 1932 .i2c = gk104_i2c_new, 1933 .ibus = gk104_ibus_new, 1934 .imem = nv50_instmem_new, 1935 .ltc = gk104_ltc_new, 1936 .mc = gk20a_mc_new, 1937 .mmu = gf100_mmu_new, 1938 .mxm = nv50_mxm_new, 1939 .pci = g94_pci_new, 1940 .pmu = gk208_pmu_new, 1941 .therm = gf119_therm_new, 1942 .timer = nv41_timer_new, 1943 .volt = gk104_volt_new, 1944 .ce[0] = gk104_ce_new, 1945 .ce[1] = gk104_ce_new, 1946 .ce[2] = gk104_ce_new, 1947 .disp = gk110_disp_new, 1948 .dma = gf119_dma_new, 1949 .fifo = gk208_fifo_new, 1950 .gr = gk208_gr_new, 1951 .mspdec = gk104_mspdec_new, 1952 .msppp = gf100_msppp_new, 1953 .msvld = gk104_msvld_new, 1954 .sw = gf100_sw_new, 1955}; 1956 1957static const struct nvkm_device_chip 1958nv117_chipset = { 1959 .name = "GM107", 1960 .bar = gf100_bar_new, 1961 .bios = nvkm_bios_new, 1962 .bus = gf100_bus_new, 1963 .clk = gk104_clk_new, 1964 .devinit = gm107_devinit_new, 1965 .fb = gm107_fb_new, 1966 .fuse = gm107_fuse_new, 1967 .gpio = gk104_gpio_new, 1968 .i2c = gk104_i2c_new, 1969 .ibus = gk104_ibus_new, 1970 .imem = nv50_instmem_new, 1971 .ltc = gm107_ltc_new, 1972 .mc = gk20a_mc_new, 1973 .mmu = gf100_mmu_new, 1974 .mxm = nv50_mxm_new, 1975 .pci = g94_pci_new, 1976 .pmu = gm107_pmu_new, 1977 .therm = gm107_therm_new, 1978 .timer = gk20a_timer_new, 1979 .volt = gk104_volt_new, 1980 .ce[0] = gk104_ce_new, 1981 .ce[2] = gk104_ce_new, 1982 .disp = gm107_disp_new, 1983 .dma = gf119_dma_new, 1984 .fifo = gk208_fifo_new, 1985 .gr = gm107_gr_new, 1986 .sw = gf100_sw_new, 1987}; 1988 1989static const struct nvkm_device_chip 1990nv124_chipset = { 1991 .name = "GM204", 1992 .bar = gf100_bar_new, 1993 .bios = nvkm_bios_new, 1994 .bus = gf100_bus_new, 1995 .devinit = gm204_devinit_new, 1996 .fb = gm107_fb_new, 1997 .fuse = gm107_fuse_new, 1998 .gpio = gk104_gpio_new, 1999 .i2c = gm204_i2c_new, 2000 .ibus = gk104_ibus_new, 2001 .imem = nv50_instmem_new, 2002 .ltc = gm107_ltc_new, 2003 .mc = gk20a_mc_new, 2004 .mmu = gf100_mmu_new, 2005 .mxm = nv50_mxm_new, 2006 .pci = g94_pci_new, 2007 .pmu = gm107_pmu_new, 2008 .timer = gk20a_timer_new, 2009 .volt = gk104_volt_new, 2010 .ce[0] = gm204_ce_new, 2011 .ce[1] = gm204_ce_new, 2012 .ce[2] = gm204_ce_new, 2013 .disp = gm204_disp_new, 2014 .dma = gf119_dma_new, 2015 .fifo = gm204_fifo_new, 2016 .gr = gm204_gr_new, 2017 .sw = gf100_sw_new, 2018}; 2019 2020static const struct nvkm_device_chip 2021nv126_chipset = { 2022 .name = "GM206", 2023 .bar = gf100_bar_new, 2024 .bios = nvkm_bios_new, 2025 .bus = gf100_bus_new, 2026 .devinit = gm204_devinit_new, 2027 .fb = gm107_fb_new, 2028 .fuse = gm107_fuse_new, 2029 .gpio = gk104_gpio_new, 2030 .i2c = gm204_i2c_new, 2031 .ibus = gk104_ibus_new, 2032 .imem = nv50_instmem_new, 2033 .ltc = gm107_ltc_new, 2034 .mc = gk20a_mc_new, 2035 .mmu = gf100_mmu_new, 2036 .mxm = nv50_mxm_new, 2037 .pci = g94_pci_new, 2038 .pmu = gm107_pmu_new, 2039 .timer = gk20a_timer_new, 2040 .volt = gk104_volt_new, 2041 .ce[0] = gm204_ce_new, 2042 .ce[1] = gm204_ce_new, 2043 .ce[2] = gm204_ce_new, 2044 .disp = gm204_disp_new, 2045 .dma = gf119_dma_new, 2046 .fifo = gm204_fifo_new, 2047 .gr = gm206_gr_new, 2048 .sw = gf100_sw_new, 2049}; 2050 2051static const struct nvkm_device_chip 2052nv12b_chipset = { 2053 .name = "GM20B", 2054 .bar = gk20a_bar_new, 2055 .bus = gf100_bus_new, 2056 .fb = gk20a_fb_new, 2057 .fuse = gm107_fuse_new, 2058 .ibus = gk20a_ibus_new, 2059 .imem = gk20a_instmem_new, 2060 .ltc = gm107_ltc_new, 2061 .mc = gk20a_mc_new, 2062 .mmu = gf100_mmu_new, 2063 .timer = gk20a_timer_new, 2064 .ce[2] = gm204_ce_new, 2065 .dma = gf119_dma_new, 2066 .fifo = gm20b_fifo_new, 2067 .gr = gm20b_gr_new, 2068 .sw = gf100_sw_new, 2069}; 2070 2071static int 2072nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 2073 struct nvkm_notify *notify) 2074{ 2075 if (!WARN_ON(size != 0)) { 2076 notify->size = 0; 2077 notify->types = 1; 2078 notify->index = 0; 2079 return 0; 2080 } 2081 return -EINVAL; 2082} 2083 2084static const struct nvkm_event_func 2085nvkm_device_event_func = { 2086 .ctor = nvkm_device_event_ctor, 2087}; 2088 2089struct nvkm_subdev * 2090nvkm_device_subdev(struct nvkm_device *device, int index) 2091{ 2092 struct nvkm_engine *engine; 2093 2094 if (device->disable_mask & (1ULL << index)) 2095 return NULL; 2096 2097 switch (index) { 2098#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break 2099 _(BAR , device->bar , &device->bar->subdev); 2100 _(VBIOS , device->bios , &device->bios->subdev); 2101 _(BUS , device->bus , &device->bus->subdev); 2102 _(CLK , device->clk , &device->clk->subdev); 2103 _(DEVINIT, device->devinit, &device->devinit->subdev); 2104 _(FB , device->fb , &device->fb->subdev); 2105 _(FUSE , device->fuse , &device->fuse->subdev); 2106 _(GPIO , device->gpio , &device->gpio->subdev); 2107 _(I2C , device->i2c , &device->i2c->subdev); 2108 _(IBUS , device->ibus , device->ibus); 2109 _(INSTMEM, device->imem , &device->imem->subdev); 2110 _(LTC , device->ltc , &device->ltc->subdev); 2111 _(MC , device->mc , &device->mc->subdev); 2112 _(MMU , device->mmu , &device->mmu->subdev); 2113 _(MXM , device->mxm , device->mxm); 2114 _(PCI , device->pci , &device->pci->subdev); 2115 _(PMU , device->pmu , &device->pmu->subdev); 2116 _(THERM , device->therm , &device->therm->subdev); 2117 _(TIMER , device->timer , &device->timer->subdev); 2118 _(VOLT , device->volt , &device->volt->subdev); 2119#undef _ 2120 default: 2121 engine = nvkm_device_engine(device, index); 2122 if (engine) 2123 return &engine->subdev; 2124 break; 2125 } 2126 return NULL; 2127} 2128 2129struct nvkm_engine * 2130nvkm_device_engine(struct nvkm_device *device, int index) 2131{ 2132 if (device->disable_mask & (1ULL << index)) 2133 return NULL; 2134 2135 switch (index) { 2136#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break 2137 _(BSP , device->bsp , device->bsp); 2138 _(CE0 , device->ce[0] , device->ce[0]); 2139 _(CE1 , device->ce[1] , device->ce[1]); 2140 _(CE2 , device->ce[2] , device->ce[2]); 2141 _(CIPHER , device->cipher , device->cipher); 2142 _(DISP , device->disp , &device->disp->engine); 2143 _(DMAOBJ , device->dma , &device->dma->engine); 2144 _(FIFO , device->fifo , &device->fifo->engine); 2145 _(GR , device->gr , &device->gr->engine); 2146 _(IFB , device->ifb , device->ifb); 2147 _(ME , device->me , device->me); 2148 _(MPEG , device->mpeg , device->mpeg); 2149 _(MSENC , device->msenc , device->msenc); 2150 _(MSPDEC , device->mspdec , device->mspdec); 2151 _(MSPPP , device->msppp , device->msppp); 2152 _(MSVLD , device->msvld , device->msvld); 2153 _(PM , device->pm , &device->pm->engine); 2154 _(SEC , device->sec , device->sec); 2155 _(SW , device->sw , &device->sw->engine); 2156 _(VIC , device->vic , device->vic); 2157 _(VP , device->vp , device->vp); 2158#undef _ 2159 default: 2160 WARN_ON(1); 2161 break; 2162 } 2163 return NULL; 2164} 2165 2166int 2167nvkm_device_fini(struct nvkm_device *device, bool suspend) 2168{ 2169 const char *action = suspend ? "suspend" : "fini"; 2170 struct nvkm_subdev *subdev; 2171 int ret, i; 2172 s64 time; 2173 2174 nvdev_trace(device, "%s running...\n", action); 2175 time = ktime_to_us(ktime_get()); 2176 2177 nvkm_acpi_fini(device); 2178 2179 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2180 if ((subdev = nvkm_device_subdev(device, i))) { 2181 ret = nvkm_subdev_fini(subdev, suspend); 2182 if (ret && suspend) 2183 goto fail; 2184 } 2185 } 2186 2187 2188 if (device->func->fini) 2189 device->func->fini(device, suspend); 2190 2191 time = ktime_to_us(ktime_get()) - time; 2192 nvdev_trace(device, "%s completed in %"PRId64"us...\n", action, time); 2193 return 0; 2194 2195fail: 2196 do { 2197 if ((subdev = nvkm_device_subdev(device, i))) { 2198 int rret = nvkm_subdev_init(subdev); 2199 if (rret) 2200 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2201 } 2202 } while (++i < NVKM_SUBDEV_NR); 2203 2204 nvdev_trace(device, "%s failed with %d\n", action, ret); 2205 return ret; 2206} 2207 2208static int 2209nvkm_device_preinit(struct nvkm_device *device) 2210{ 2211 struct nvkm_subdev *subdev; 2212 int ret, i; 2213 s64 time; 2214 2215 nvdev_trace(device, "preinit running...\n"); 2216 time = ktime_to_us(ktime_get()); 2217 2218 if (device->func->preinit) { 2219 ret = device->func->preinit(device); 2220 if (ret) 2221 goto fail; 2222 } 2223 2224 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2225 if ((subdev = nvkm_device_subdev(device, i))) { 2226 ret = nvkm_subdev_preinit(subdev); 2227 if (ret) 2228 goto fail; 2229 } 2230 } 2231 2232 ret = nvkm_devinit_post(device->devinit, &device->disable_mask); 2233 if (ret) 2234 goto fail; 2235 2236 time = ktime_to_us(ktime_get()) - time; 2237 nvdev_trace(device, "preinit completed in %"PRId64"us\n", time); 2238 return 0; 2239 2240fail: 2241 nvdev_error(device, "preinit failed with %d\n", ret); 2242 return ret; 2243} 2244 2245int 2246nvkm_device_init(struct nvkm_device *device) 2247{ 2248 struct nvkm_subdev *subdev; 2249 int ret, i; 2250 s64 time; 2251 2252 ret = nvkm_device_preinit(device); 2253 if (ret) 2254 return ret; 2255 2256 nvkm_device_fini(device, false); 2257 2258 nvdev_trace(device, "init running...\n"); 2259 time = ktime_to_us(ktime_get()); 2260 2261 if (device->func->init) { 2262 ret = device->func->init(device); 2263 if (ret) 2264 goto fail; 2265 } 2266 2267 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2268 if ((subdev = nvkm_device_subdev(device, i))) { 2269 ret = nvkm_subdev_init(subdev); 2270 if (ret) 2271 goto fail_subdev; 2272 } 2273 } 2274 2275 nvkm_acpi_init(device); 2276 2277 time = ktime_to_us(ktime_get()) - time; 2278 nvdev_trace(device, "init completed in %"PRId64"us\n", time); 2279 return 0; 2280 2281fail_subdev: 2282 do { 2283 if ((subdev = nvkm_device_subdev(device, i))) 2284 nvkm_subdev_fini(subdev, false); 2285 } while (--i >= 0); 2286 2287fail: 2288 nvdev_error(device, "init failed with %d\n", ret); 2289 return ret; 2290} 2291 2292void 2293nvkm_device_del(struct nvkm_device **pdevice) 2294{ 2295 struct nvkm_device *device = *pdevice; 2296 int i; 2297 if (device) { 2298 mutex_lock(&nv_devices_mutex); 2299 device->disable_mask = 0; 2300 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2301 struct nvkm_subdev *subdev = 2302 nvkm_device_subdev(device, i); 2303 nvkm_subdev_del(&subdev); 2304 } 2305 2306#ifdef __NetBSD__ 2307 linux_mutex_destroy(&device->mutex); 2308#else 2309 mutex_destroy(&device->mutex); 2310#endif 2311 2312 nvkm_event_fini(&device->event); 2313 2314#ifdef __NetBSD__ 2315 if (device->mmiosz) 2316 bus_space_unmap(device->mmiot, device->mmioh, 2317 device->mmiosz); 2318#else 2319 if (device->pri) 2320 iounmap(device->pri); 2321#endif 2322 list_del(&device->head); 2323 2324 if (device->func->dtor) 2325 *pdevice = device->func->dtor(device); 2326 mutex_unlock(&nv_devices_mutex); 2327 2328 kfree(*pdevice); 2329 *pdevice = NULL; 2330 } 2331} 2332 2333int 2334nvkm_device_ctor(const struct nvkm_device_func *func, 2335 const struct nvkm_device_quirk *quirk, 2336 struct device *dev, enum nvkm_device_type type, u64 handle, 2337 const char *name, const char *cfg, const char *dbg, 2338 bool detect, bool mmio, u64 subdev_mask, 2339 struct nvkm_device *device) 2340{ 2341 struct nvkm_subdev *subdev; 2342 u64 mmio_base, mmio_size; 2343 u32 boot0, strap; 2344#ifdef __NetBSD__ 2345 bus_space_tag_t mmiot; 2346 bus_space_handle_t mmioh; 2347#else 2348 void __iomem *map; 2349#endif 2350 int ret = -EEXIST; 2351 int i; 2352 2353 mutex_lock(&nv_devices_mutex); 2354 if (nvkm_device_find_locked(handle)) 2355 goto done; 2356 2357 device->func = func; 2358 device->quirk = quirk; 2359 device->dev = dev; 2360 device->type = type; 2361 device->handle = handle; 2362 device->cfgopt = cfg; 2363 device->dbgopt = dbg; 2364 device->name = name; 2365 list_add_tail(&device->head, &nv_devices); 2366 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 2367 2368 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 2369 if (ret) 2370 goto done; 2371 2372#ifdef __NetBSD__ 2373 mmiot = device->func->resource_tag(device, 0); 2374#endif 2375 mmio_base = device->func->resource_addr(device, 0); 2376 mmio_size = device->func->resource_size(device, 0); 2377 2378 /* identify the chipset, and determine classes of subdev/engines */ 2379 if (detect) { 2380#ifdef __NetBSD__ 2381 if (mmio_size < 0x102000) { 2382 ret = -ENOMEM; 2383 goto done; 2384 } 2385 /* XXX errno NetBSD->Linux */ 2386 ret = -bus_space_map(mmiot, mmio_base, 0x102000, 0, &mmioh); 2387 if (ret) 2388 goto done; 2389#ifndef __BIG_ENDIAN /* XXX bus_space_read/write_4_stream? */ 2390 if (bus_space_read_4(mmiot, mmioh, 4) != 0) 2391#else 2392 if (bus_space_read_4(mmiot, mmioh, 4) != 1) 2393#endif 2394 { 2395 bus_space_write_4(mmiot, mmioh, 4, 0x01000001); 2396 bus_space_read_4(mmiot, mmioh, 0); 2397 } 2398 2399 /* read boot0 and strapping information */ 2400 boot0 = bus_space_read_4(mmiot, mmioh, 0x000000); 2401 strap = bus_space_read_4(mmiot, mmioh, 0x101000); 2402 bus_space_unmap(mmiot, mmioh, 0x102000); 2403#else 2404 map = ioremap(mmio_base, 0x102000); 2405 if (ret = -ENOMEM, map == NULL) 2406 goto done; 2407 2408 /* switch mmio to cpu's native endianness */ 2409#ifndef __BIG_ENDIAN 2410 if (ioread32_native(map + 0x000004) != 0x00000000) { 2411#else 2412 if (ioread32_native(map + 0x000004) == 0x00000000) { 2413#endif 2414 iowrite32_native(0x01000001, map + 0x000004); 2415 ioread32_native(map); 2416 } 2417 2418 /* read boot0 and strapping information */ 2419 boot0 = ioread32_native(map + 0x000000); 2420 strap = ioread32_native(map + 0x101000); 2421 iounmap(map); 2422#endif 2423 2424 /* determine chipset and derive architecture from it */ 2425 if ((boot0 & 0x1f000000) > 0) { 2426 device->chipset = (boot0 & 0x1ff00000) >> 20; 2427 device->chiprev = (boot0 & 0x000000ff); 2428 switch (device->chipset & 0x1f0) { 2429 case 0x010: { 2430 if (0x461 & (1 << (device->chipset & 0xf))) 2431 device->card_type = NV_10; 2432 else 2433 device->card_type = NV_11; 2434 device->chiprev = 0x00; 2435 break; 2436 } 2437 case 0x020: device->card_type = NV_20; break; 2438 case 0x030: device->card_type = NV_30; break; 2439 case 0x040: 2440 case 0x060: device->card_type = NV_40; break; 2441 case 0x050: 2442 case 0x080: 2443 case 0x090: 2444 case 0x0a0: device->card_type = NV_50; break; 2445 case 0x0c0: 2446 case 0x0d0: device->card_type = NV_C0; break; 2447 case 0x0e0: 2448 case 0x0f0: 2449 case 0x100: device->card_type = NV_E0; break; 2450 case 0x110: 2451 case 0x120: device->card_type = GM100; break; 2452 default: 2453 break; 2454 } 2455 } else 2456 if ((boot0 & 0xff00fff0) == 0x20004000) { 2457 if (boot0 & 0x00f00000) 2458 device->chipset = 0x05; 2459 else 2460 device->chipset = 0x04; 2461 device->card_type = NV_04; 2462 } 2463 2464 switch (device->chipset) { 2465 case 0x004: device->chip = &nv4_chipset; break; 2466 case 0x005: device->chip = &nv5_chipset; break; 2467 case 0x010: device->chip = &nv10_chipset; break; 2468 case 0x011: device->chip = &nv11_chipset; break; 2469 case 0x015: device->chip = &nv15_chipset; break; 2470 case 0x017: device->chip = &nv17_chipset; break; 2471 case 0x018: device->chip = &nv18_chipset; break; 2472 case 0x01a: device->chip = &nv1a_chipset; break; 2473 case 0x01f: device->chip = &nv1f_chipset; break; 2474 case 0x020: device->chip = &nv20_chipset; break; 2475 case 0x025: device->chip = &nv25_chipset; break; 2476 case 0x028: device->chip = &nv28_chipset; break; 2477 case 0x02a: device->chip = &nv2a_chipset; break; 2478 case 0x030: device->chip = &nv30_chipset; break; 2479 case 0x031: device->chip = &nv31_chipset; break; 2480 case 0x034: device->chip = &nv34_chipset; break; 2481 case 0x035: device->chip = &nv35_chipset; break; 2482 case 0x036: device->chip = &nv36_chipset; break; 2483 case 0x040: device->chip = &nv40_chipset; break; 2484 case 0x041: device->chip = &nv41_chipset; break; 2485 case 0x042: device->chip = &nv42_chipset; break; 2486 case 0x043: device->chip = &nv43_chipset; break; 2487 case 0x044: device->chip = &nv44_chipset; break; 2488 case 0x045: device->chip = &nv45_chipset; break; 2489 case 0x046: device->chip = &nv46_chipset; break; 2490 case 0x047: device->chip = &nv47_chipset; break; 2491 case 0x049: device->chip = &nv49_chipset; break; 2492 case 0x04a: device->chip = &nv4a_chipset; break; 2493 case 0x04b: device->chip = &nv4b_chipset; break; 2494 case 0x04c: device->chip = &nv4c_chipset; break; 2495 case 0x04e: device->chip = &nv4e_chipset; break; 2496 case 0x050: device->chip = &nv50_chipset; break; 2497 case 0x063: device->chip = &nv63_chipset; break; 2498 case 0x067: device->chip = &nv67_chipset; break; 2499 case 0x068: device->chip = &nv68_chipset; break; 2500 case 0x084: device->chip = &nv84_chipset; break; 2501 case 0x086: device->chip = &nv86_chipset; break; 2502 case 0x092: device->chip = &nv92_chipset; break; 2503 case 0x094: device->chip = &nv94_chipset; break; 2504 case 0x096: device->chip = &nv96_chipset; break; 2505 case 0x098: device->chip = &nv98_chipset; break; 2506 case 0x0a0: device->chip = &nva0_chipset; break; 2507 case 0x0a3: device->chip = &nva3_chipset; break; 2508 case 0x0a5: device->chip = &nva5_chipset; break; 2509 case 0x0a8: device->chip = &nva8_chipset; break; 2510 case 0x0aa: device->chip = &nvaa_chipset; break; 2511 case 0x0ac: device->chip = &nvac_chipset; break; 2512 case 0x0af: device->chip = &nvaf_chipset; break; 2513 case 0x0c0: device->chip = &nvc0_chipset; break; 2514 case 0x0c1: device->chip = &nvc1_chipset; break; 2515 case 0x0c3: device->chip = &nvc3_chipset; break; 2516 case 0x0c4: device->chip = &nvc4_chipset; break; 2517 case 0x0c8: device->chip = &nvc8_chipset; break; 2518 case 0x0ce: device->chip = &nvce_chipset; break; 2519 case 0x0cf: device->chip = &nvcf_chipset; break; 2520 case 0x0d7: device->chip = &nvd7_chipset; break; 2521 case 0x0d9: device->chip = &nvd9_chipset; break; 2522 case 0x0e4: device->chip = &nve4_chipset; break; 2523 case 0x0e6: device->chip = &nve6_chipset; break; 2524 case 0x0e7: device->chip = &nve7_chipset; break; 2525 case 0x0ea: device->chip = &nvea_chipset; break; 2526 case 0x0f0: device->chip = &nvf0_chipset; break; 2527 case 0x0f1: device->chip = &nvf1_chipset; break; 2528 case 0x106: device->chip = &nv106_chipset; break; 2529 case 0x108: device->chip = &nv108_chipset; break; 2530 case 0x117: device->chip = &nv117_chipset; break; 2531 case 0x124: device->chip = &nv124_chipset; break; 2532 case 0x126: device->chip = &nv126_chipset; break; 2533 case 0x12b: device->chip = &nv12b_chipset; break; 2534 default: 2535 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 2536 goto done; 2537 } 2538 2539 nvdev_info(device, "NVIDIA %s (%08x)\n", 2540 device->chip->name, boot0); 2541 2542 /* determine frequency of timing crystal */ 2543 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 2544 (device->chipset >= 0x20 && device->chipset < 0x25)) 2545 strap &= 0x00000040; 2546 else 2547 strap &= 0x00400040; 2548 2549 switch (strap) { 2550 case 0x00000000: device->crystal = 13500; break; 2551 case 0x00000040: device->crystal = 14318; break; 2552 case 0x00400000: device->crystal = 27000; break; 2553 case 0x00400040: device->crystal = 25000; break; 2554 } 2555 } else { 2556 device->chip = &null_chipset; 2557 } 2558 2559 if (!device->name) 2560 device->name = device->chip->name; 2561 2562 if (mmio) { 2563#ifdef __NetBSD__ 2564 /* XXX errno NetBSD->Linux */ 2565 ret = -bus_space_map(mmiot, mmio_base, mmio_size, 0, &mmioh); 2566 if (ret) { 2567 nvdev_error(device, "unable to map device registers\n"); 2568 goto done; /* XXX Linux leaks mutex */ 2569 } 2570 device->mmiot = mmiot; 2571 device->mmioh = mmioh; 2572 device->mmiosz = mmiosz; 2573#else 2574 device->pri = ioremap(mmio_base, mmio_size); 2575 if (!device->pri) { 2576 nvdev_error(device, "unable to map PRI\n"); 2577 return -ENOMEM; 2578 } 2579#endif 2580 } 2581 2582#ifdef __NetBSD__ 2583 linux_mutex_init(&device->mutex); 2584#else 2585 mutex_init(&device->mutex); 2586#endif 2587 2588 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2589#define _(s,m) case s: \ 2590 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ 2591 ret = device->chip->m(device, (s), &device->m); \ 2592 if (ret) { \ 2593 subdev = nvkm_device_subdev(device, (s)); \ 2594 nvkm_subdev_del(&subdev); \ 2595 device->m = NULL; \ 2596 if (ret != -ENODEV) { \ 2597 nvdev_error(device, "%s ctor failed, %d\n", \ 2598 nvkm_subdev_name[s], ret); \ 2599 goto done; \ 2600 } \ 2601 } \ 2602 } \ 2603 break 2604 switch (i) { 2605 _(NVKM_SUBDEV_BAR , bar); 2606 _(NVKM_SUBDEV_VBIOS , bios); 2607 _(NVKM_SUBDEV_BUS , bus); 2608 _(NVKM_SUBDEV_CLK , clk); 2609 _(NVKM_SUBDEV_DEVINIT, devinit); 2610 _(NVKM_SUBDEV_FB , fb); 2611 _(NVKM_SUBDEV_FUSE , fuse); 2612 _(NVKM_SUBDEV_GPIO , gpio); 2613 _(NVKM_SUBDEV_I2C , i2c); 2614 _(NVKM_SUBDEV_IBUS , ibus); 2615 _(NVKM_SUBDEV_INSTMEM, imem); 2616 _(NVKM_SUBDEV_LTC , ltc); 2617 _(NVKM_SUBDEV_MC , mc); 2618 _(NVKM_SUBDEV_MMU , mmu); 2619 _(NVKM_SUBDEV_MXM , mxm); 2620 _(NVKM_SUBDEV_PCI , pci); 2621 _(NVKM_SUBDEV_PMU , pmu); 2622 _(NVKM_SUBDEV_THERM , therm); 2623 _(NVKM_SUBDEV_TIMER , timer); 2624 _(NVKM_SUBDEV_VOLT , volt); 2625 _(NVKM_ENGINE_BSP , bsp); 2626 _(NVKM_ENGINE_CE0 , ce[0]); 2627 _(NVKM_ENGINE_CE1 , ce[1]); 2628 _(NVKM_ENGINE_CE2 , ce[2]); 2629 _(NVKM_ENGINE_CIPHER , cipher); 2630 _(NVKM_ENGINE_DISP , disp); 2631 _(NVKM_ENGINE_DMAOBJ , dma); 2632 _(NVKM_ENGINE_FIFO , fifo); 2633 _(NVKM_ENGINE_GR , gr); 2634 _(NVKM_ENGINE_IFB , ifb); 2635 _(NVKM_ENGINE_ME , me); 2636 _(NVKM_ENGINE_MPEG , mpeg); 2637 _(NVKM_ENGINE_MSENC , msenc); 2638 _(NVKM_ENGINE_MSPDEC , mspdec); 2639 _(NVKM_ENGINE_MSPPP , msppp); 2640 _(NVKM_ENGINE_MSVLD , msvld); 2641 _(NVKM_ENGINE_PM , pm); 2642 _(NVKM_ENGINE_SEC , sec); 2643 _(NVKM_ENGINE_SW , sw); 2644 _(NVKM_ENGINE_VIC , vic); 2645 _(NVKM_ENGINE_VP , vp); 2646 default: 2647 WARN_ON(1); 2648 continue; 2649 } 2650#undef _ 2651 } 2652 2653 ret = 0; 2654done: 2655 mutex_unlock(&nv_devices_mutex); 2656 return ret; 2657} 2658