nouveau_nvkm_engine_device_base.c revision 1.1
1/* $NetBSD: nouveau_nvkm_engine_device_base.c,v 1.1 2018/08/27 01:34:55 riastradh Exp $ */ 2 3/* 4 * Copyright 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Ben Skeggs 25 */ 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: nouveau_nvkm_engine_device_base.c,v 1.1 2018/08/27 01:34:55 riastradh Exp $"); 28 29#include "priv.h" 30#include "acpi.h" 31 32#include <core/notify.h> 33#include <core/option.h> 34 35#include <subdev/bios.h> 36 37static DEFINE_MUTEX(nv_devices_mutex); 38static LIST_HEAD(nv_devices); 39 40static struct nvkm_device * 41nvkm_device_find_locked(u64 handle) 42{ 43 struct nvkm_device *device; 44 list_for_each_entry(device, &nv_devices, head) { 45 if (device->handle == handle) 46 return device; 47 } 48 return NULL; 49} 50 51struct nvkm_device * 52nvkm_device_find(u64 handle) 53{ 54 struct nvkm_device *device; 55 mutex_lock(&nv_devices_mutex); 56 device = nvkm_device_find_locked(handle); 57 mutex_unlock(&nv_devices_mutex); 58 return device; 59} 60 61int 62nvkm_device_list(u64 *name, int size) 63{ 64 struct nvkm_device *device; 65 int nr = 0; 66 mutex_lock(&nv_devices_mutex); 67 list_for_each_entry(device, &nv_devices, head) { 68 if (nr++ < size) 69 name[nr - 1] = device->handle; 70 } 71 mutex_unlock(&nv_devices_mutex); 72 return nr; 73} 74 75static const struct nvkm_device_chip 76null_chipset = { 77 .name = "NULL", 78 .bios = nvkm_bios_new, 79}; 80 81static const struct nvkm_device_chip 82nv4_chipset = { 83 .name = "NV04", 84 .bios = nvkm_bios_new, 85 .bus = nv04_bus_new, 86 .clk = nv04_clk_new, 87 .devinit = nv04_devinit_new, 88 .fb = nv04_fb_new, 89 .i2c = nv04_i2c_new, 90 .imem = nv04_instmem_new, 91 .mc = nv04_mc_new, 92 .mmu = nv04_mmu_new, 93 .pci = nv04_pci_new, 94 .timer = nv04_timer_new, 95 .disp = nv04_disp_new, 96 .dma = nv04_dma_new, 97 .fifo = nv04_fifo_new, 98 .gr = nv04_gr_new, 99 .sw = nv04_sw_new, 100}; 101 102static const struct nvkm_device_chip 103nv5_chipset = { 104 .name = "NV05", 105 .bios = nvkm_bios_new, 106 .bus = nv04_bus_new, 107 .clk = nv04_clk_new, 108 .devinit = nv05_devinit_new, 109 .fb = nv04_fb_new, 110 .i2c = nv04_i2c_new, 111 .imem = nv04_instmem_new, 112 .mc = nv04_mc_new, 113 .mmu = nv04_mmu_new, 114 .pci = nv04_pci_new, 115 .timer = nv04_timer_new, 116 .disp = nv04_disp_new, 117 .dma = nv04_dma_new, 118 .fifo = nv04_fifo_new, 119 .gr = nv04_gr_new, 120 .sw = nv04_sw_new, 121}; 122 123static const struct nvkm_device_chip 124nv10_chipset = { 125 .name = "NV10", 126 .bios = nvkm_bios_new, 127 .bus = nv04_bus_new, 128 .clk = nv04_clk_new, 129 .devinit = nv10_devinit_new, 130 .fb = nv10_fb_new, 131 .gpio = nv10_gpio_new, 132 .i2c = nv04_i2c_new, 133 .imem = nv04_instmem_new, 134 .mc = nv04_mc_new, 135 .mmu = nv04_mmu_new, 136 .pci = nv04_pci_new, 137 .timer = nv04_timer_new, 138 .disp = nv04_disp_new, 139 .dma = nv04_dma_new, 140 .gr = nv10_gr_new, 141}; 142 143static const struct nvkm_device_chip 144nv11_chipset = { 145 .name = "NV11", 146 .bios = nvkm_bios_new, 147 .bus = nv04_bus_new, 148 .clk = nv04_clk_new, 149 .devinit = nv10_devinit_new, 150 .fb = nv10_fb_new, 151 .gpio = nv10_gpio_new, 152 .i2c = nv04_i2c_new, 153 .imem = nv04_instmem_new, 154 .mc = nv04_mc_new, 155 .mmu = nv04_mmu_new, 156 .pci = nv04_pci_new, 157 .timer = nv04_timer_new, 158 .disp = nv04_disp_new, 159 .dma = nv04_dma_new, 160 .fifo = nv10_fifo_new, 161 .gr = nv15_gr_new, 162 .sw = nv10_sw_new, 163}; 164 165static const struct nvkm_device_chip 166nv15_chipset = { 167 .name = "NV15", 168 .bios = nvkm_bios_new, 169 .bus = nv04_bus_new, 170 .clk = nv04_clk_new, 171 .devinit = nv10_devinit_new, 172 .fb = nv10_fb_new, 173 .gpio = nv10_gpio_new, 174 .i2c = nv04_i2c_new, 175 .imem = nv04_instmem_new, 176 .mc = nv04_mc_new, 177 .mmu = nv04_mmu_new, 178 .pci = nv04_pci_new, 179 .timer = nv04_timer_new, 180 .disp = nv04_disp_new, 181 .dma = nv04_dma_new, 182 .fifo = nv10_fifo_new, 183 .gr = nv15_gr_new, 184 .sw = nv10_sw_new, 185}; 186 187static const struct nvkm_device_chip 188nv17_chipset = { 189 .name = "NV17", 190 .bios = nvkm_bios_new, 191 .bus = nv04_bus_new, 192 .clk = nv04_clk_new, 193 .devinit = nv10_devinit_new, 194 .fb = nv10_fb_new, 195 .gpio = nv10_gpio_new, 196 .i2c = nv04_i2c_new, 197 .imem = nv04_instmem_new, 198 .mc = nv04_mc_new, 199 .mmu = nv04_mmu_new, 200 .pci = nv04_pci_new, 201 .timer = nv04_timer_new, 202 .disp = nv04_disp_new, 203 .dma = nv04_dma_new, 204 .fifo = nv17_fifo_new, 205 .gr = nv17_gr_new, 206 .sw = nv10_sw_new, 207}; 208 209static const struct nvkm_device_chip 210nv18_chipset = { 211 .name = "NV18", 212 .bios = nvkm_bios_new, 213 .bus = nv04_bus_new, 214 .clk = nv04_clk_new, 215 .devinit = nv10_devinit_new, 216 .fb = nv10_fb_new, 217 .gpio = nv10_gpio_new, 218 .i2c = nv04_i2c_new, 219 .imem = nv04_instmem_new, 220 .mc = nv04_mc_new, 221 .mmu = nv04_mmu_new, 222 .pci = nv04_pci_new, 223 .timer = nv04_timer_new, 224 .disp = nv04_disp_new, 225 .dma = nv04_dma_new, 226 .fifo = nv17_fifo_new, 227 .gr = nv17_gr_new, 228 .sw = nv10_sw_new, 229}; 230 231static const struct nvkm_device_chip 232nv1a_chipset = { 233 .name = "nForce", 234 .bios = nvkm_bios_new, 235 .bus = nv04_bus_new, 236 .clk = nv04_clk_new, 237 .devinit = nv1a_devinit_new, 238 .fb = nv1a_fb_new, 239 .gpio = nv10_gpio_new, 240 .i2c = nv04_i2c_new, 241 .imem = nv04_instmem_new, 242 .mc = nv04_mc_new, 243 .mmu = nv04_mmu_new, 244 .pci = nv04_pci_new, 245 .timer = nv04_timer_new, 246 .disp = nv04_disp_new, 247 .dma = nv04_dma_new, 248 .fifo = nv10_fifo_new, 249 .gr = nv15_gr_new, 250 .sw = nv10_sw_new, 251}; 252 253static const struct nvkm_device_chip 254nv1f_chipset = { 255 .name = "nForce2", 256 .bios = nvkm_bios_new, 257 .bus = nv04_bus_new, 258 .clk = nv04_clk_new, 259 .devinit = nv1a_devinit_new, 260 .fb = nv1a_fb_new, 261 .gpio = nv10_gpio_new, 262 .i2c = nv04_i2c_new, 263 .imem = nv04_instmem_new, 264 .mc = nv04_mc_new, 265 .mmu = nv04_mmu_new, 266 .pci = nv04_pci_new, 267 .timer = nv04_timer_new, 268 .disp = nv04_disp_new, 269 .dma = nv04_dma_new, 270 .fifo = nv17_fifo_new, 271 .gr = nv17_gr_new, 272 .sw = nv10_sw_new, 273}; 274 275static const struct nvkm_device_chip 276nv20_chipset = { 277 .name = "NV20", 278 .bios = nvkm_bios_new, 279 .bus = nv04_bus_new, 280 .clk = nv04_clk_new, 281 .devinit = nv20_devinit_new, 282 .fb = nv20_fb_new, 283 .gpio = nv10_gpio_new, 284 .i2c = nv04_i2c_new, 285 .imem = nv04_instmem_new, 286 .mc = nv04_mc_new, 287 .mmu = nv04_mmu_new, 288 .pci = nv04_pci_new, 289 .timer = nv04_timer_new, 290 .disp = nv04_disp_new, 291 .dma = nv04_dma_new, 292 .fifo = nv17_fifo_new, 293 .gr = nv20_gr_new, 294 .sw = nv10_sw_new, 295}; 296 297static const struct nvkm_device_chip 298nv25_chipset = { 299 .name = "NV25", 300 .bios = nvkm_bios_new, 301 .bus = nv04_bus_new, 302 .clk = nv04_clk_new, 303 .devinit = nv20_devinit_new, 304 .fb = nv25_fb_new, 305 .gpio = nv10_gpio_new, 306 .i2c = nv04_i2c_new, 307 .imem = nv04_instmem_new, 308 .mc = nv04_mc_new, 309 .mmu = nv04_mmu_new, 310 .pci = nv04_pci_new, 311 .timer = nv04_timer_new, 312 .disp = nv04_disp_new, 313 .dma = nv04_dma_new, 314 .fifo = nv17_fifo_new, 315 .gr = nv25_gr_new, 316 .sw = nv10_sw_new, 317}; 318 319static const struct nvkm_device_chip 320nv28_chipset = { 321 .name = "NV28", 322 .bios = nvkm_bios_new, 323 .bus = nv04_bus_new, 324 .clk = nv04_clk_new, 325 .devinit = nv20_devinit_new, 326 .fb = nv25_fb_new, 327 .gpio = nv10_gpio_new, 328 .i2c = nv04_i2c_new, 329 .imem = nv04_instmem_new, 330 .mc = nv04_mc_new, 331 .mmu = nv04_mmu_new, 332 .pci = nv04_pci_new, 333 .timer = nv04_timer_new, 334 .disp = nv04_disp_new, 335 .dma = nv04_dma_new, 336 .fifo = nv17_fifo_new, 337 .gr = nv25_gr_new, 338 .sw = nv10_sw_new, 339}; 340 341static const struct nvkm_device_chip 342nv2a_chipset = { 343 .name = "NV2A", 344 .bios = nvkm_bios_new, 345 .bus = nv04_bus_new, 346 .clk = nv04_clk_new, 347 .devinit = nv20_devinit_new, 348 .fb = nv25_fb_new, 349 .gpio = nv10_gpio_new, 350 .i2c = nv04_i2c_new, 351 .imem = nv04_instmem_new, 352 .mc = nv04_mc_new, 353 .mmu = nv04_mmu_new, 354 .pci = nv04_pci_new, 355 .timer = nv04_timer_new, 356 .disp = nv04_disp_new, 357 .dma = nv04_dma_new, 358 .fifo = nv17_fifo_new, 359 .gr = nv2a_gr_new, 360 .sw = nv10_sw_new, 361}; 362 363static const struct nvkm_device_chip 364nv30_chipset = { 365 .name = "NV30", 366 .bios = nvkm_bios_new, 367 .bus = nv04_bus_new, 368 .clk = nv04_clk_new, 369 .devinit = nv20_devinit_new, 370 .fb = nv30_fb_new, 371 .gpio = nv10_gpio_new, 372 .i2c = nv04_i2c_new, 373 .imem = nv04_instmem_new, 374 .mc = nv04_mc_new, 375 .mmu = nv04_mmu_new, 376 .pci = nv04_pci_new, 377 .timer = nv04_timer_new, 378 .disp = nv04_disp_new, 379 .dma = nv04_dma_new, 380 .fifo = nv17_fifo_new, 381 .gr = nv30_gr_new, 382 .sw = nv10_sw_new, 383}; 384 385static const struct nvkm_device_chip 386nv31_chipset = { 387 .name = "NV31", 388 .bios = nvkm_bios_new, 389 .bus = nv31_bus_new, 390 .clk = nv04_clk_new, 391 .devinit = nv20_devinit_new, 392 .fb = nv30_fb_new, 393 .gpio = nv10_gpio_new, 394 .i2c = nv04_i2c_new, 395 .imem = nv04_instmem_new, 396 .mc = nv04_mc_new, 397 .mmu = nv04_mmu_new, 398 .pci = nv04_pci_new, 399 .timer = nv04_timer_new, 400 .disp = nv04_disp_new, 401 .dma = nv04_dma_new, 402 .fifo = nv17_fifo_new, 403 .gr = nv30_gr_new, 404 .mpeg = nv31_mpeg_new, 405 .sw = nv10_sw_new, 406}; 407 408static const struct nvkm_device_chip 409nv34_chipset = { 410 .name = "NV34", 411 .bios = nvkm_bios_new, 412 .bus = nv31_bus_new, 413 .clk = nv04_clk_new, 414 .devinit = nv10_devinit_new, 415 .fb = nv10_fb_new, 416 .gpio = nv10_gpio_new, 417 .i2c = nv04_i2c_new, 418 .imem = nv04_instmem_new, 419 .mc = nv04_mc_new, 420 .mmu = nv04_mmu_new, 421 .pci = nv04_pci_new, 422 .timer = nv04_timer_new, 423 .disp = nv04_disp_new, 424 .dma = nv04_dma_new, 425 .fifo = nv17_fifo_new, 426 .gr = nv34_gr_new, 427 .mpeg = nv31_mpeg_new, 428 .sw = nv10_sw_new, 429}; 430 431static const struct nvkm_device_chip 432nv35_chipset = { 433 .name = "NV35", 434 .bios = nvkm_bios_new, 435 .bus = nv04_bus_new, 436 .clk = nv04_clk_new, 437 .devinit = nv20_devinit_new, 438 .fb = nv35_fb_new, 439 .gpio = nv10_gpio_new, 440 .i2c = nv04_i2c_new, 441 .imem = nv04_instmem_new, 442 .mc = nv04_mc_new, 443 .mmu = nv04_mmu_new, 444 .pci = nv04_pci_new, 445 .timer = nv04_timer_new, 446 .disp = nv04_disp_new, 447 .dma = nv04_dma_new, 448 .fifo = nv17_fifo_new, 449 .gr = nv35_gr_new, 450 .sw = nv10_sw_new, 451}; 452 453static const struct nvkm_device_chip 454nv36_chipset = { 455 .name = "NV36", 456 .bios = nvkm_bios_new, 457 .bus = nv31_bus_new, 458 .clk = nv04_clk_new, 459 .devinit = nv20_devinit_new, 460 .fb = nv36_fb_new, 461 .gpio = nv10_gpio_new, 462 .i2c = nv04_i2c_new, 463 .imem = nv04_instmem_new, 464 .mc = nv04_mc_new, 465 .mmu = nv04_mmu_new, 466 .pci = nv04_pci_new, 467 .timer = nv04_timer_new, 468 .disp = nv04_disp_new, 469 .dma = nv04_dma_new, 470 .fifo = nv17_fifo_new, 471 .gr = nv35_gr_new, 472 .mpeg = nv31_mpeg_new, 473 .sw = nv10_sw_new, 474}; 475 476static const struct nvkm_device_chip 477nv40_chipset = { 478 .name = "NV40", 479 .bios = nvkm_bios_new, 480 .bus = nv31_bus_new, 481 .clk = nv40_clk_new, 482 .devinit = nv1a_devinit_new, 483 .fb = nv40_fb_new, 484 .gpio = nv10_gpio_new, 485 .i2c = nv04_i2c_new, 486 .imem = nv40_instmem_new, 487 .mc = nv04_mc_new, 488 .mmu = nv04_mmu_new, 489 .pci = nv40_pci_new, 490 .therm = nv40_therm_new, 491 .timer = nv40_timer_new, 492 .volt = nv40_volt_new, 493 .disp = nv04_disp_new, 494 .dma = nv04_dma_new, 495 .fifo = nv40_fifo_new, 496 .gr = nv40_gr_new, 497 .mpeg = nv40_mpeg_new, 498 .pm = nv40_pm_new, 499 .sw = nv10_sw_new, 500}; 501 502static const struct nvkm_device_chip 503nv41_chipset = { 504 .name = "NV41", 505 .bios = nvkm_bios_new, 506 .bus = nv31_bus_new, 507 .clk = nv40_clk_new, 508 .devinit = nv1a_devinit_new, 509 .fb = nv41_fb_new, 510 .gpio = nv10_gpio_new, 511 .i2c = nv04_i2c_new, 512 .imem = nv40_instmem_new, 513 .mc = nv04_mc_new, 514 .mmu = nv41_mmu_new, 515 .pci = nv40_pci_new, 516 .therm = nv40_therm_new, 517 .timer = nv41_timer_new, 518 .volt = nv40_volt_new, 519 .disp = nv04_disp_new, 520 .dma = nv04_dma_new, 521 .fifo = nv40_fifo_new, 522 .gr = nv40_gr_new, 523 .mpeg = nv40_mpeg_new, 524 .pm = nv40_pm_new, 525 .sw = nv10_sw_new, 526}; 527 528static const struct nvkm_device_chip 529nv42_chipset = { 530 .name = "NV42", 531 .bios = nvkm_bios_new, 532 .bus = nv31_bus_new, 533 .clk = nv40_clk_new, 534 .devinit = nv1a_devinit_new, 535 .fb = nv41_fb_new, 536 .gpio = nv10_gpio_new, 537 .i2c = nv04_i2c_new, 538 .imem = nv40_instmem_new, 539 .mc = nv04_mc_new, 540 .mmu = nv41_mmu_new, 541 .pci = nv40_pci_new, 542 .therm = nv40_therm_new, 543 .timer = nv41_timer_new, 544 .volt = nv40_volt_new, 545 .disp = nv04_disp_new, 546 .dma = nv04_dma_new, 547 .fifo = nv40_fifo_new, 548 .gr = nv40_gr_new, 549 .mpeg = nv40_mpeg_new, 550 .pm = nv40_pm_new, 551 .sw = nv10_sw_new, 552}; 553 554static const struct nvkm_device_chip 555nv43_chipset = { 556 .name = "NV43", 557 .bios = nvkm_bios_new, 558 .bus = nv31_bus_new, 559 .clk = nv40_clk_new, 560 .devinit = nv1a_devinit_new, 561 .fb = nv41_fb_new, 562 .gpio = nv10_gpio_new, 563 .i2c = nv04_i2c_new, 564 .imem = nv40_instmem_new, 565 .mc = nv04_mc_new, 566 .mmu = nv41_mmu_new, 567 .pci = nv40_pci_new, 568 .therm = nv40_therm_new, 569 .timer = nv41_timer_new, 570 .volt = nv40_volt_new, 571 .disp = nv04_disp_new, 572 .dma = nv04_dma_new, 573 .fifo = nv40_fifo_new, 574 .gr = nv40_gr_new, 575 .mpeg = nv40_mpeg_new, 576 .pm = nv40_pm_new, 577 .sw = nv10_sw_new, 578}; 579 580static const struct nvkm_device_chip 581nv44_chipset = { 582 .name = "NV44", 583 .bios = nvkm_bios_new, 584 .bus = nv31_bus_new, 585 .clk = nv40_clk_new, 586 .devinit = nv1a_devinit_new, 587 .fb = nv44_fb_new, 588 .gpio = nv10_gpio_new, 589 .i2c = nv04_i2c_new, 590 .imem = nv40_instmem_new, 591 .mc = nv44_mc_new, 592 .mmu = nv44_mmu_new, 593 .pci = nv40_pci_new, 594 .therm = nv40_therm_new, 595 .timer = nv41_timer_new, 596 .volt = nv40_volt_new, 597 .disp = nv04_disp_new, 598 .dma = nv04_dma_new, 599 .fifo = nv40_fifo_new, 600 .gr = nv44_gr_new, 601 .mpeg = nv44_mpeg_new, 602 .pm = nv40_pm_new, 603 .sw = nv10_sw_new, 604}; 605 606static const struct nvkm_device_chip 607nv45_chipset = { 608 .name = "NV45", 609 .bios = nvkm_bios_new, 610 .bus = nv31_bus_new, 611 .clk = nv40_clk_new, 612 .devinit = nv1a_devinit_new, 613 .fb = nv40_fb_new, 614 .gpio = nv10_gpio_new, 615 .i2c = nv04_i2c_new, 616 .imem = nv40_instmem_new, 617 .mc = nv04_mc_new, 618 .mmu = nv04_mmu_new, 619 .pci = nv40_pci_new, 620 .therm = nv40_therm_new, 621 .timer = nv41_timer_new, 622 .volt = nv40_volt_new, 623 .disp = nv04_disp_new, 624 .dma = nv04_dma_new, 625 .fifo = nv40_fifo_new, 626 .gr = nv40_gr_new, 627 .mpeg = nv44_mpeg_new, 628 .pm = nv40_pm_new, 629 .sw = nv10_sw_new, 630}; 631 632static const struct nvkm_device_chip 633nv46_chipset = { 634 .name = "G72", 635 .bios = nvkm_bios_new, 636 .bus = nv31_bus_new, 637 .clk = nv40_clk_new, 638 .devinit = nv1a_devinit_new, 639 .fb = nv46_fb_new, 640 .gpio = nv10_gpio_new, 641 .i2c = nv04_i2c_new, 642 .imem = nv40_instmem_new, 643 .mc = nv44_mc_new, 644 .mmu = nv44_mmu_new, 645 .pci = nv46_pci_new, 646 .therm = nv40_therm_new, 647 .timer = nv41_timer_new, 648 .volt = nv40_volt_new, 649 .disp = nv04_disp_new, 650 .dma = nv04_dma_new, 651 .fifo = nv40_fifo_new, 652 .gr = nv44_gr_new, 653 .mpeg = nv44_mpeg_new, 654 .pm = nv40_pm_new, 655 .sw = nv10_sw_new, 656}; 657 658static const struct nvkm_device_chip 659nv47_chipset = { 660 .name = "G70", 661 .bios = nvkm_bios_new, 662 .bus = nv31_bus_new, 663 .clk = nv40_clk_new, 664 .devinit = nv1a_devinit_new, 665 .fb = nv47_fb_new, 666 .gpio = nv10_gpio_new, 667 .i2c = nv04_i2c_new, 668 .imem = nv40_instmem_new, 669 .mc = nv04_mc_new, 670 .mmu = nv41_mmu_new, 671 .pci = nv40_pci_new, 672 .therm = nv40_therm_new, 673 .timer = nv41_timer_new, 674 .volt = nv40_volt_new, 675 .disp = nv04_disp_new, 676 .dma = nv04_dma_new, 677 .fifo = nv40_fifo_new, 678 .gr = nv40_gr_new, 679 .mpeg = nv44_mpeg_new, 680 .pm = nv40_pm_new, 681 .sw = nv10_sw_new, 682}; 683 684static const struct nvkm_device_chip 685nv49_chipset = { 686 .name = "G71", 687 .bios = nvkm_bios_new, 688 .bus = nv31_bus_new, 689 .clk = nv40_clk_new, 690 .devinit = nv1a_devinit_new, 691 .fb = nv49_fb_new, 692 .gpio = nv10_gpio_new, 693 .i2c = nv04_i2c_new, 694 .imem = nv40_instmem_new, 695 .mc = nv04_mc_new, 696 .mmu = nv41_mmu_new, 697 .pci = nv40_pci_new, 698 .therm = nv40_therm_new, 699 .timer = nv41_timer_new, 700 .volt = nv40_volt_new, 701 .disp = nv04_disp_new, 702 .dma = nv04_dma_new, 703 .fifo = nv40_fifo_new, 704 .gr = nv40_gr_new, 705 .mpeg = nv44_mpeg_new, 706 .pm = nv40_pm_new, 707 .sw = nv10_sw_new, 708}; 709 710static const struct nvkm_device_chip 711nv4a_chipset = { 712 .name = "NV44A", 713 .bios = nvkm_bios_new, 714 .bus = nv31_bus_new, 715 .clk = nv40_clk_new, 716 .devinit = nv1a_devinit_new, 717 .fb = nv44_fb_new, 718 .gpio = nv10_gpio_new, 719 .i2c = nv04_i2c_new, 720 .imem = nv40_instmem_new, 721 .mc = nv44_mc_new, 722 .mmu = nv04_mmu_new, 723 .pci = nv40_pci_new, 724 .therm = nv40_therm_new, 725 .timer = nv41_timer_new, 726 .volt = nv40_volt_new, 727 .disp = nv04_disp_new, 728 .dma = nv04_dma_new, 729 .fifo = nv40_fifo_new, 730 .gr = nv44_gr_new, 731 .mpeg = nv44_mpeg_new, 732 .pm = nv40_pm_new, 733 .sw = nv10_sw_new, 734}; 735 736static const struct nvkm_device_chip 737nv4b_chipset = { 738 .name = "G73", 739 .bios = nvkm_bios_new, 740 .bus = nv31_bus_new, 741 .clk = nv40_clk_new, 742 .devinit = nv1a_devinit_new, 743 .fb = nv49_fb_new, 744 .gpio = nv10_gpio_new, 745 .i2c = nv04_i2c_new, 746 .imem = nv40_instmem_new, 747 .mc = nv04_mc_new, 748 .mmu = nv41_mmu_new, 749 .pci = nv40_pci_new, 750 .therm = nv40_therm_new, 751 .timer = nv41_timer_new, 752 .volt = nv40_volt_new, 753 .disp = nv04_disp_new, 754 .dma = nv04_dma_new, 755 .fifo = nv40_fifo_new, 756 .gr = nv40_gr_new, 757 .mpeg = nv44_mpeg_new, 758 .pm = nv40_pm_new, 759 .sw = nv10_sw_new, 760}; 761 762static const struct nvkm_device_chip 763nv4c_chipset = { 764 .name = "C61", 765 .bios = nvkm_bios_new, 766 .bus = nv31_bus_new, 767 .clk = nv40_clk_new, 768 .devinit = nv1a_devinit_new, 769 .fb = nv46_fb_new, 770 .gpio = nv10_gpio_new, 771 .i2c = nv04_i2c_new, 772 .imem = nv40_instmem_new, 773 .mc = nv44_mc_new, 774 .mmu = nv44_mmu_new, 775 .pci = nv4c_pci_new, 776 .therm = nv40_therm_new, 777 .timer = nv41_timer_new, 778 .volt = nv40_volt_new, 779 .disp = nv04_disp_new, 780 .dma = nv04_dma_new, 781 .fifo = nv40_fifo_new, 782 .gr = nv44_gr_new, 783 .mpeg = nv44_mpeg_new, 784 .pm = nv40_pm_new, 785 .sw = nv10_sw_new, 786}; 787 788static const struct nvkm_device_chip 789nv4e_chipset = { 790 .name = "C51", 791 .bios = nvkm_bios_new, 792 .bus = nv31_bus_new, 793 .clk = nv40_clk_new, 794 .devinit = nv1a_devinit_new, 795 .fb = nv4e_fb_new, 796 .gpio = nv10_gpio_new, 797 .i2c = nv4e_i2c_new, 798 .imem = nv40_instmem_new, 799 .mc = nv44_mc_new, 800 .mmu = nv44_mmu_new, 801 .pci = nv4c_pci_new, 802 .therm = nv40_therm_new, 803 .timer = nv41_timer_new, 804 .volt = nv40_volt_new, 805 .disp = nv04_disp_new, 806 .dma = nv04_dma_new, 807 .fifo = nv40_fifo_new, 808 .gr = nv44_gr_new, 809 .mpeg = nv44_mpeg_new, 810 .pm = nv40_pm_new, 811 .sw = nv10_sw_new, 812}; 813 814static const struct nvkm_device_chip 815nv50_chipset = { 816 .name = "G80", 817 .bar = nv50_bar_new, 818 .bios = nvkm_bios_new, 819 .bus = nv50_bus_new, 820 .clk = nv50_clk_new, 821 .devinit = nv50_devinit_new, 822 .fb = nv50_fb_new, 823 .fuse = nv50_fuse_new, 824 .gpio = nv50_gpio_new, 825 .i2c = nv50_i2c_new, 826 .imem = nv50_instmem_new, 827 .mc = nv50_mc_new, 828 .mmu = nv50_mmu_new, 829 .mxm = nv50_mxm_new, 830 .pci = nv46_pci_new, 831 .therm = nv50_therm_new, 832 .timer = nv41_timer_new, 833 .volt = nv40_volt_new, 834 .disp = nv50_disp_new, 835 .dma = nv50_dma_new, 836 .fifo = nv50_fifo_new, 837 .gr = nv50_gr_new, 838 .mpeg = nv50_mpeg_new, 839 .pm = nv50_pm_new, 840 .sw = nv50_sw_new, 841}; 842 843static const struct nvkm_device_chip 844nv63_chipset = { 845 .name = "C73", 846 .bios = nvkm_bios_new, 847 .bus = nv31_bus_new, 848 .clk = nv40_clk_new, 849 .devinit = nv1a_devinit_new, 850 .fb = nv46_fb_new, 851 .gpio = nv10_gpio_new, 852 .i2c = nv04_i2c_new, 853 .imem = nv40_instmem_new, 854 .mc = nv44_mc_new, 855 .mmu = nv44_mmu_new, 856 .pci = nv4c_pci_new, 857 .therm = nv40_therm_new, 858 .timer = nv41_timer_new, 859 .volt = nv40_volt_new, 860 .disp = nv04_disp_new, 861 .dma = nv04_dma_new, 862 .fifo = nv40_fifo_new, 863 .gr = nv44_gr_new, 864 .mpeg = nv44_mpeg_new, 865 .pm = nv40_pm_new, 866 .sw = nv10_sw_new, 867}; 868 869static const struct nvkm_device_chip 870nv67_chipset = { 871 .name = "C67", 872 .bios = nvkm_bios_new, 873 .bus = nv31_bus_new, 874 .clk = nv40_clk_new, 875 .devinit = nv1a_devinit_new, 876 .fb = nv46_fb_new, 877 .gpio = nv10_gpio_new, 878 .i2c = nv04_i2c_new, 879 .imem = nv40_instmem_new, 880 .mc = nv44_mc_new, 881 .mmu = nv44_mmu_new, 882 .pci = nv4c_pci_new, 883 .therm = nv40_therm_new, 884 .timer = nv41_timer_new, 885 .volt = nv40_volt_new, 886 .disp = nv04_disp_new, 887 .dma = nv04_dma_new, 888 .fifo = nv40_fifo_new, 889 .gr = nv44_gr_new, 890 .mpeg = nv44_mpeg_new, 891 .pm = nv40_pm_new, 892 .sw = nv10_sw_new, 893}; 894 895static const struct nvkm_device_chip 896nv68_chipset = { 897 .name = "C68", 898 .bios = nvkm_bios_new, 899 .bus = nv31_bus_new, 900 .clk = nv40_clk_new, 901 .devinit = nv1a_devinit_new, 902 .fb = nv46_fb_new, 903 .gpio = nv10_gpio_new, 904 .i2c = nv04_i2c_new, 905 .imem = nv40_instmem_new, 906 .mc = nv44_mc_new, 907 .mmu = nv44_mmu_new, 908 .pci = nv4c_pci_new, 909 .therm = nv40_therm_new, 910 .timer = nv41_timer_new, 911 .volt = nv40_volt_new, 912 .disp = nv04_disp_new, 913 .dma = nv04_dma_new, 914 .fifo = nv40_fifo_new, 915 .gr = nv44_gr_new, 916 .mpeg = nv44_mpeg_new, 917 .pm = nv40_pm_new, 918 .sw = nv10_sw_new, 919}; 920 921static const struct nvkm_device_chip 922nv84_chipset = { 923 .name = "G84", 924 .bar = g84_bar_new, 925 .bios = nvkm_bios_new, 926 .bus = nv50_bus_new, 927 .clk = g84_clk_new, 928 .devinit = g84_devinit_new, 929 .fb = g84_fb_new, 930 .fuse = nv50_fuse_new, 931 .gpio = nv50_gpio_new, 932 .i2c = nv50_i2c_new, 933 .imem = nv50_instmem_new, 934 .mc = nv50_mc_new, 935 .mmu = nv50_mmu_new, 936 .mxm = nv50_mxm_new, 937 .pci = g84_pci_new, 938 .therm = g84_therm_new, 939 .timer = nv41_timer_new, 940 .volt = nv40_volt_new, 941 .bsp = g84_bsp_new, 942 .cipher = g84_cipher_new, 943 .disp = g84_disp_new, 944 .dma = nv50_dma_new, 945 .fifo = g84_fifo_new, 946 .gr = g84_gr_new, 947 .mpeg = g84_mpeg_new, 948 .pm = g84_pm_new, 949 .sw = nv50_sw_new, 950 .vp = g84_vp_new, 951}; 952 953static const struct nvkm_device_chip 954nv86_chipset = { 955 .name = "G86", 956 .bar = g84_bar_new, 957 .bios = nvkm_bios_new, 958 .bus = nv50_bus_new, 959 .clk = g84_clk_new, 960 .devinit = g84_devinit_new, 961 .fb = g84_fb_new, 962 .fuse = nv50_fuse_new, 963 .gpio = nv50_gpio_new, 964 .i2c = nv50_i2c_new, 965 .imem = nv50_instmem_new, 966 .mc = nv50_mc_new, 967 .mmu = nv50_mmu_new, 968 .mxm = nv50_mxm_new, 969 .pci = g84_pci_new, 970 .therm = g84_therm_new, 971 .timer = nv41_timer_new, 972 .volt = nv40_volt_new, 973 .bsp = g84_bsp_new, 974 .cipher = g84_cipher_new, 975 .disp = g84_disp_new, 976 .dma = nv50_dma_new, 977 .fifo = g84_fifo_new, 978 .gr = g84_gr_new, 979 .mpeg = g84_mpeg_new, 980 .pm = g84_pm_new, 981 .sw = nv50_sw_new, 982 .vp = g84_vp_new, 983}; 984 985static const struct nvkm_device_chip 986nv92_chipset = { 987 .name = "G92", 988 .bar = g84_bar_new, 989 .bios = nvkm_bios_new, 990 .bus = nv50_bus_new, 991 .clk = g84_clk_new, 992 .devinit = g84_devinit_new, 993 .fb = g84_fb_new, 994 .fuse = nv50_fuse_new, 995 .gpio = nv50_gpio_new, 996 .i2c = nv50_i2c_new, 997 .imem = nv50_instmem_new, 998 .mc = nv50_mc_new, 999 .mmu = nv50_mmu_new, 1000 .mxm = nv50_mxm_new, 1001 .pci = g84_pci_new, 1002 .therm = g84_therm_new, 1003 .timer = nv41_timer_new, 1004 .volt = nv40_volt_new, 1005 .bsp = g84_bsp_new, 1006 .cipher = g84_cipher_new, 1007 .disp = g84_disp_new, 1008 .dma = nv50_dma_new, 1009 .fifo = g84_fifo_new, 1010 .gr = g84_gr_new, 1011 .mpeg = g84_mpeg_new, 1012 .pm = g84_pm_new, 1013 .sw = nv50_sw_new, 1014 .vp = g84_vp_new, 1015}; 1016 1017static const struct nvkm_device_chip 1018nv94_chipset = { 1019 .name = "G94", 1020 .bar = g84_bar_new, 1021 .bios = nvkm_bios_new, 1022 .bus = g94_bus_new, 1023 .clk = g84_clk_new, 1024 .devinit = g84_devinit_new, 1025 .fb = g84_fb_new, 1026 .fuse = nv50_fuse_new, 1027 .gpio = g94_gpio_new, 1028 .i2c = g94_i2c_new, 1029 .imem = nv50_instmem_new, 1030 .mc = nv50_mc_new, 1031 .mmu = nv50_mmu_new, 1032 .mxm = nv50_mxm_new, 1033 .pci = g94_pci_new, 1034 .therm = g84_therm_new, 1035 .timer = nv41_timer_new, 1036 .volt = nv40_volt_new, 1037 .bsp = g84_bsp_new, 1038 .cipher = g84_cipher_new, 1039 .disp = g94_disp_new, 1040 .dma = nv50_dma_new, 1041 .fifo = g84_fifo_new, 1042 .gr = g84_gr_new, 1043 .mpeg = g84_mpeg_new, 1044 .pm = g84_pm_new, 1045 .sw = nv50_sw_new, 1046 .vp = g84_vp_new, 1047}; 1048 1049static const struct nvkm_device_chip 1050nv96_chipset = { 1051 .name = "G96", 1052 .bar = g84_bar_new, 1053 .bios = nvkm_bios_new, 1054 .bus = g94_bus_new, 1055 .clk = g84_clk_new, 1056 .devinit = g84_devinit_new, 1057 .fb = g84_fb_new, 1058 .fuse = nv50_fuse_new, 1059 .gpio = g94_gpio_new, 1060 .i2c = g94_i2c_new, 1061 .imem = nv50_instmem_new, 1062 .mc = nv50_mc_new, 1063 .mmu = nv50_mmu_new, 1064 .mxm = nv50_mxm_new, 1065 .pci = g94_pci_new, 1066 .therm = g84_therm_new, 1067 .timer = nv41_timer_new, 1068 .volt = nv40_volt_new, 1069 .bsp = g84_bsp_new, 1070 .cipher = g84_cipher_new, 1071 .disp = g94_disp_new, 1072 .dma = nv50_dma_new, 1073 .fifo = g84_fifo_new, 1074 .gr = g84_gr_new, 1075 .mpeg = g84_mpeg_new, 1076 .pm = g84_pm_new, 1077 .sw = nv50_sw_new, 1078 .vp = g84_vp_new, 1079}; 1080 1081static const struct nvkm_device_chip 1082nv98_chipset = { 1083 .name = "G98", 1084 .bar = g84_bar_new, 1085 .bios = nvkm_bios_new, 1086 .bus = g94_bus_new, 1087 .clk = g84_clk_new, 1088 .devinit = g98_devinit_new, 1089 .fb = g84_fb_new, 1090 .fuse = nv50_fuse_new, 1091 .gpio = g94_gpio_new, 1092 .i2c = g94_i2c_new, 1093 .imem = nv50_instmem_new, 1094 .mc = g98_mc_new, 1095 .mmu = nv50_mmu_new, 1096 .mxm = nv50_mxm_new, 1097 .pci = g94_pci_new, 1098 .therm = g84_therm_new, 1099 .timer = nv41_timer_new, 1100 .volt = nv40_volt_new, 1101 .disp = g94_disp_new, 1102 .dma = nv50_dma_new, 1103 .fifo = g84_fifo_new, 1104 .gr = g84_gr_new, 1105 .mspdec = g98_mspdec_new, 1106 .msppp = g98_msppp_new, 1107 .msvld = g98_msvld_new, 1108 .pm = g84_pm_new, 1109 .sec = g98_sec_new, 1110 .sw = nv50_sw_new, 1111}; 1112 1113static const struct nvkm_device_chip 1114nva0_chipset = { 1115 .name = "GT200", 1116 .bar = g84_bar_new, 1117 .bios = nvkm_bios_new, 1118 .bus = g94_bus_new, 1119 .clk = g84_clk_new, 1120 .devinit = g84_devinit_new, 1121 .fb = g84_fb_new, 1122 .fuse = nv50_fuse_new, 1123 .gpio = g94_gpio_new, 1124 .i2c = nv50_i2c_new, 1125 .imem = nv50_instmem_new, 1126 .mc = g98_mc_new, 1127 .mmu = nv50_mmu_new, 1128 .mxm = nv50_mxm_new, 1129 .pci = g94_pci_new, 1130 .therm = g84_therm_new, 1131 .timer = nv41_timer_new, 1132 .volt = nv40_volt_new, 1133 .bsp = g84_bsp_new, 1134 .cipher = g84_cipher_new, 1135 .disp = gt200_disp_new, 1136 .dma = nv50_dma_new, 1137 .fifo = g84_fifo_new, 1138 .gr = gt200_gr_new, 1139 .mpeg = g84_mpeg_new, 1140 .pm = gt200_pm_new, 1141 .sw = nv50_sw_new, 1142 .vp = g84_vp_new, 1143}; 1144 1145static const struct nvkm_device_chip 1146nva3_chipset = { 1147 .name = "GT215", 1148 .bar = g84_bar_new, 1149 .bios = nvkm_bios_new, 1150 .bus = g94_bus_new, 1151 .clk = gt215_clk_new, 1152 .devinit = gt215_devinit_new, 1153 .fb = gt215_fb_new, 1154 .fuse = nv50_fuse_new, 1155 .gpio = g94_gpio_new, 1156 .i2c = g94_i2c_new, 1157 .imem = nv50_instmem_new, 1158 .mc = g98_mc_new, 1159 .mmu = nv50_mmu_new, 1160 .mxm = nv50_mxm_new, 1161 .pci = g94_pci_new, 1162 .pmu = gt215_pmu_new, 1163 .therm = gt215_therm_new, 1164 .timer = nv41_timer_new, 1165 .volt = nv40_volt_new, 1166 .ce[0] = gt215_ce_new, 1167 .disp = gt215_disp_new, 1168 .dma = nv50_dma_new, 1169 .fifo = g84_fifo_new, 1170 .gr = gt215_gr_new, 1171 .mpeg = g84_mpeg_new, 1172 .mspdec = gt215_mspdec_new, 1173 .msppp = gt215_msppp_new, 1174 .msvld = gt215_msvld_new, 1175 .pm = gt215_pm_new, 1176 .sw = nv50_sw_new, 1177}; 1178 1179static const struct nvkm_device_chip 1180nva5_chipset = { 1181 .name = "GT216", 1182 .bar = g84_bar_new, 1183 .bios = nvkm_bios_new, 1184 .bus = g94_bus_new, 1185 .clk = gt215_clk_new, 1186 .devinit = gt215_devinit_new, 1187 .fb = gt215_fb_new, 1188 .fuse = nv50_fuse_new, 1189 .gpio = g94_gpio_new, 1190 .i2c = g94_i2c_new, 1191 .imem = nv50_instmem_new, 1192 .mc = g98_mc_new, 1193 .mmu = nv50_mmu_new, 1194 .mxm = nv50_mxm_new, 1195 .pci = g94_pci_new, 1196 .pmu = gt215_pmu_new, 1197 .therm = gt215_therm_new, 1198 .timer = nv41_timer_new, 1199 .volt = nv40_volt_new, 1200 .ce[0] = gt215_ce_new, 1201 .disp = gt215_disp_new, 1202 .dma = nv50_dma_new, 1203 .fifo = g84_fifo_new, 1204 .gr = gt215_gr_new, 1205 .mspdec = gt215_mspdec_new, 1206 .msppp = gt215_msppp_new, 1207 .msvld = gt215_msvld_new, 1208 .pm = gt215_pm_new, 1209 .sw = nv50_sw_new, 1210}; 1211 1212static const struct nvkm_device_chip 1213nva8_chipset = { 1214 .name = "GT218", 1215 .bar = g84_bar_new, 1216 .bios = nvkm_bios_new, 1217 .bus = g94_bus_new, 1218 .clk = gt215_clk_new, 1219 .devinit = gt215_devinit_new, 1220 .fb = gt215_fb_new, 1221 .fuse = nv50_fuse_new, 1222 .gpio = g94_gpio_new, 1223 .i2c = g94_i2c_new, 1224 .imem = nv50_instmem_new, 1225 .mc = g98_mc_new, 1226 .mmu = nv50_mmu_new, 1227 .mxm = nv50_mxm_new, 1228 .pci = g94_pci_new, 1229 .pmu = gt215_pmu_new, 1230 .therm = gt215_therm_new, 1231 .timer = nv41_timer_new, 1232 .volt = nv40_volt_new, 1233 .ce[0] = gt215_ce_new, 1234 .disp = gt215_disp_new, 1235 .dma = nv50_dma_new, 1236 .fifo = g84_fifo_new, 1237 .gr = gt215_gr_new, 1238 .mspdec = gt215_mspdec_new, 1239 .msppp = gt215_msppp_new, 1240 .msvld = gt215_msvld_new, 1241 .pm = gt215_pm_new, 1242 .sw = nv50_sw_new, 1243}; 1244 1245static const struct nvkm_device_chip 1246nvaa_chipset = { 1247 .name = "MCP77/MCP78", 1248 .bar = g84_bar_new, 1249 .bios = nvkm_bios_new, 1250 .bus = g94_bus_new, 1251 .clk = mcp77_clk_new, 1252 .devinit = g98_devinit_new, 1253 .fb = mcp77_fb_new, 1254 .fuse = nv50_fuse_new, 1255 .gpio = g94_gpio_new, 1256 .i2c = g94_i2c_new, 1257 .imem = nv50_instmem_new, 1258 .mc = g98_mc_new, 1259 .mmu = nv50_mmu_new, 1260 .mxm = nv50_mxm_new, 1261 .pci = g94_pci_new, 1262 .therm = g84_therm_new, 1263 .timer = nv41_timer_new, 1264 .volt = nv40_volt_new, 1265 .disp = g94_disp_new, 1266 .dma = nv50_dma_new, 1267 .fifo = g84_fifo_new, 1268 .gr = gt200_gr_new, 1269 .mspdec = g98_mspdec_new, 1270 .msppp = g98_msppp_new, 1271 .msvld = g98_msvld_new, 1272 .pm = g84_pm_new, 1273 .sec = g98_sec_new, 1274 .sw = nv50_sw_new, 1275}; 1276 1277static const struct nvkm_device_chip 1278nvac_chipset = { 1279 .name = "MCP79/MCP7A", 1280 .bar = g84_bar_new, 1281 .bios = nvkm_bios_new, 1282 .bus = g94_bus_new, 1283 .clk = mcp77_clk_new, 1284 .devinit = g98_devinit_new, 1285 .fb = mcp77_fb_new, 1286 .fuse = nv50_fuse_new, 1287 .gpio = g94_gpio_new, 1288 .i2c = g94_i2c_new, 1289 .imem = nv50_instmem_new, 1290 .mc = g98_mc_new, 1291 .mmu = nv50_mmu_new, 1292 .mxm = nv50_mxm_new, 1293 .pci = g94_pci_new, 1294 .therm = g84_therm_new, 1295 .timer = nv41_timer_new, 1296 .volt = nv40_volt_new, 1297 .disp = g94_disp_new, 1298 .dma = nv50_dma_new, 1299 .fifo = g84_fifo_new, 1300 .gr = mcp79_gr_new, 1301 .mspdec = g98_mspdec_new, 1302 .msppp = g98_msppp_new, 1303 .msvld = g98_msvld_new, 1304 .pm = g84_pm_new, 1305 .sec = g98_sec_new, 1306 .sw = nv50_sw_new, 1307}; 1308 1309static const struct nvkm_device_chip 1310nvaf_chipset = { 1311 .name = "MCP89", 1312 .bar = g84_bar_new, 1313 .bios = nvkm_bios_new, 1314 .bus = g94_bus_new, 1315 .clk = gt215_clk_new, 1316 .devinit = mcp89_devinit_new, 1317 .fb = mcp89_fb_new, 1318 .fuse = nv50_fuse_new, 1319 .gpio = g94_gpio_new, 1320 .i2c = g94_i2c_new, 1321 .imem = nv50_instmem_new, 1322 .mc = g98_mc_new, 1323 .mmu = nv50_mmu_new, 1324 .mxm = nv50_mxm_new, 1325 .pci = g94_pci_new, 1326 .pmu = gt215_pmu_new, 1327 .therm = gt215_therm_new, 1328 .timer = nv41_timer_new, 1329 .volt = nv40_volt_new, 1330 .ce[0] = gt215_ce_new, 1331 .disp = gt215_disp_new, 1332 .dma = nv50_dma_new, 1333 .fifo = g84_fifo_new, 1334 .gr = mcp89_gr_new, 1335 .mspdec = gt215_mspdec_new, 1336 .msppp = gt215_msppp_new, 1337 .msvld = mcp89_msvld_new, 1338 .pm = gt215_pm_new, 1339 .sw = nv50_sw_new, 1340}; 1341 1342static const struct nvkm_device_chip 1343nvc0_chipset = { 1344 .name = "GF100", 1345 .bar = gf100_bar_new, 1346 .bios = nvkm_bios_new, 1347 .bus = gf100_bus_new, 1348 .clk = gf100_clk_new, 1349 .devinit = gf100_devinit_new, 1350 .fb = gf100_fb_new, 1351 .fuse = gf100_fuse_new, 1352 .gpio = g94_gpio_new, 1353 .i2c = g94_i2c_new, 1354 .ibus = gf100_ibus_new, 1355 .imem = nv50_instmem_new, 1356 .ltc = gf100_ltc_new, 1357 .mc = gf100_mc_new, 1358 .mmu = gf100_mmu_new, 1359 .mxm = nv50_mxm_new, 1360 .pci = gf100_pci_new, 1361 .pmu = gf100_pmu_new, 1362 .therm = gt215_therm_new, 1363 .timer = nv41_timer_new, 1364 .volt = nv40_volt_new, 1365 .ce[0] = gf100_ce_new, 1366 .ce[1] = gf100_ce_new, 1367 .disp = gt215_disp_new, 1368 .dma = gf100_dma_new, 1369 .fifo = gf100_fifo_new, 1370 .gr = gf100_gr_new, 1371 .mspdec = gf100_mspdec_new, 1372 .msppp = gf100_msppp_new, 1373 .msvld = gf100_msvld_new, 1374 .pm = gf100_pm_new, 1375 .sw = gf100_sw_new, 1376}; 1377 1378static const struct nvkm_device_chip 1379nvc1_chipset = { 1380 .name = "GF108", 1381 .bar = gf100_bar_new, 1382 .bios = nvkm_bios_new, 1383 .bus = gf100_bus_new, 1384 .clk = gf100_clk_new, 1385 .devinit = gf100_devinit_new, 1386 .fb = gf100_fb_new, 1387 .fuse = gf100_fuse_new, 1388 .gpio = g94_gpio_new, 1389 .i2c = g94_i2c_new, 1390 .ibus = gf100_ibus_new, 1391 .imem = nv50_instmem_new, 1392 .ltc = gf100_ltc_new, 1393 .mc = gf100_mc_new, 1394 .mmu = gf100_mmu_new, 1395 .mxm = nv50_mxm_new, 1396 .pci = g94_pci_new, 1397 .pmu = gf100_pmu_new, 1398 .therm = gt215_therm_new, 1399 .timer = nv41_timer_new, 1400 .volt = nv40_volt_new, 1401 .ce[0] = gf100_ce_new, 1402 .disp = gt215_disp_new, 1403 .dma = gf100_dma_new, 1404 .fifo = gf100_fifo_new, 1405 .gr = gf108_gr_new, 1406 .mspdec = gf100_mspdec_new, 1407 .msppp = gf100_msppp_new, 1408 .msvld = gf100_msvld_new, 1409 .pm = gf108_pm_new, 1410 .sw = gf100_sw_new, 1411}; 1412 1413static const struct nvkm_device_chip 1414nvc3_chipset = { 1415 .name = "GF106", 1416 .bar = gf100_bar_new, 1417 .bios = nvkm_bios_new, 1418 .bus = gf100_bus_new, 1419 .clk = gf100_clk_new, 1420 .devinit = gf100_devinit_new, 1421 .fb = gf100_fb_new, 1422 .fuse = gf100_fuse_new, 1423 .gpio = g94_gpio_new, 1424 .i2c = g94_i2c_new, 1425 .ibus = gf100_ibus_new, 1426 .imem = nv50_instmem_new, 1427 .ltc = gf100_ltc_new, 1428 .mc = gf100_mc_new, 1429 .mmu = gf100_mmu_new, 1430 .mxm = nv50_mxm_new, 1431 .pci = g94_pci_new, 1432 .pmu = gf100_pmu_new, 1433 .therm = gt215_therm_new, 1434 .timer = nv41_timer_new, 1435 .volt = nv40_volt_new, 1436 .ce[0] = gf100_ce_new, 1437 .disp = gt215_disp_new, 1438 .dma = gf100_dma_new, 1439 .fifo = gf100_fifo_new, 1440 .gr = gf104_gr_new, 1441 .mspdec = gf100_mspdec_new, 1442 .msppp = gf100_msppp_new, 1443 .msvld = gf100_msvld_new, 1444 .pm = gf100_pm_new, 1445 .sw = gf100_sw_new, 1446}; 1447 1448static const struct nvkm_device_chip 1449nvc4_chipset = { 1450 .name = "GF104", 1451 .bar = gf100_bar_new, 1452 .bios = nvkm_bios_new, 1453 .bus = gf100_bus_new, 1454 .clk = gf100_clk_new, 1455 .devinit = gf100_devinit_new, 1456 .fb = gf100_fb_new, 1457 .fuse = gf100_fuse_new, 1458 .gpio = g94_gpio_new, 1459 .i2c = g94_i2c_new, 1460 .ibus = gf100_ibus_new, 1461 .imem = nv50_instmem_new, 1462 .ltc = gf100_ltc_new, 1463 .mc = gf100_mc_new, 1464 .mmu = gf100_mmu_new, 1465 .mxm = nv50_mxm_new, 1466 .pci = gf100_pci_new, 1467 .pmu = gf100_pmu_new, 1468 .therm = gt215_therm_new, 1469 .timer = nv41_timer_new, 1470 .volt = nv40_volt_new, 1471 .ce[0] = gf100_ce_new, 1472 .ce[1] = gf100_ce_new, 1473 .disp = gt215_disp_new, 1474 .dma = gf100_dma_new, 1475 .fifo = gf100_fifo_new, 1476 .gr = gf104_gr_new, 1477 .mspdec = gf100_mspdec_new, 1478 .msppp = gf100_msppp_new, 1479 .msvld = gf100_msvld_new, 1480 .pm = gf100_pm_new, 1481 .sw = gf100_sw_new, 1482}; 1483 1484static const struct nvkm_device_chip 1485nvc8_chipset = { 1486 .name = "GF110", 1487 .bar = gf100_bar_new, 1488 .bios = nvkm_bios_new, 1489 .bus = gf100_bus_new, 1490 .clk = gf100_clk_new, 1491 .devinit = gf100_devinit_new, 1492 .fb = gf100_fb_new, 1493 .fuse = gf100_fuse_new, 1494 .gpio = g94_gpio_new, 1495 .i2c = g94_i2c_new, 1496 .ibus = gf100_ibus_new, 1497 .imem = nv50_instmem_new, 1498 .ltc = gf100_ltc_new, 1499 .mc = gf100_mc_new, 1500 .mmu = gf100_mmu_new, 1501 .mxm = nv50_mxm_new, 1502 .pci = gf100_pci_new, 1503 .pmu = gf100_pmu_new, 1504 .therm = gt215_therm_new, 1505 .timer = nv41_timer_new, 1506 .volt = nv40_volt_new, 1507 .ce[0] = gf100_ce_new, 1508 .ce[1] = gf100_ce_new, 1509 .disp = gt215_disp_new, 1510 .dma = gf100_dma_new, 1511 .fifo = gf100_fifo_new, 1512 .gr = gf110_gr_new, 1513 .mspdec = gf100_mspdec_new, 1514 .msppp = gf100_msppp_new, 1515 .msvld = gf100_msvld_new, 1516 .pm = gf100_pm_new, 1517 .sw = gf100_sw_new, 1518}; 1519 1520static const struct nvkm_device_chip 1521nvce_chipset = { 1522 .name = "GF114", 1523 .bar = gf100_bar_new, 1524 .bios = nvkm_bios_new, 1525 .bus = gf100_bus_new, 1526 .clk = gf100_clk_new, 1527 .devinit = gf100_devinit_new, 1528 .fb = gf100_fb_new, 1529 .fuse = gf100_fuse_new, 1530 .gpio = g94_gpio_new, 1531 .i2c = g94_i2c_new, 1532 .ibus = gf100_ibus_new, 1533 .imem = nv50_instmem_new, 1534 .ltc = gf100_ltc_new, 1535 .mc = gf100_mc_new, 1536 .mmu = gf100_mmu_new, 1537 .mxm = nv50_mxm_new, 1538 .pci = gf100_pci_new, 1539 .pmu = gf100_pmu_new, 1540 .therm = gt215_therm_new, 1541 .timer = nv41_timer_new, 1542 .volt = nv40_volt_new, 1543 .ce[0] = gf100_ce_new, 1544 .ce[1] = gf100_ce_new, 1545 .disp = gt215_disp_new, 1546 .dma = gf100_dma_new, 1547 .fifo = gf100_fifo_new, 1548 .gr = gf104_gr_new, 1549 .mspdec = gf100_mspdec_new, 1550 .msppp = gf100_msppp_new, 1551 .msvld = gf100_msvld_new, 1552 .pm = gf100_pm_new, 1553 .sw = gf100_sw_new, 1554}; 1555 1556static const struct nvkm_device_chip 1557nvcf_chipset = { 1558 .name = "GF116", 1559 .bar = gf100_bar_new, 1560 .bios = nvkm_bios_new, 1561 .bus = gf100_bus_new, 1562 .clk = gf100_clk_new, 1563 .devinit = gf100_devinit_new, 1564 .fb = gf100_fb_new, 1565 .fuse = gf100_fuse_new, 1566 .gpio = g94_gpio_new, 1567 .i2c = g94_i2c_new, 1568 .ibus = gf100_ibus_new, 1569 .imem = nv50_instmem_new, 1570 .ltc = gf100_ltc_new, 1571 .mc = gf100_mc_new, 1572 .mmu = gf100_mmu_new, 1573 .mxm = nv50_mxm_new, 1574 .pci = g94_pci_new, 1575 .pmu = gf100_pmu_new, 1576 .therm = gt215_therm_new, 1577 .timer = nv41_timer_new, 1578 .volt = nv40_volt_new, 1579 .ce[0] = gf100_ce_new, 1580 .disp = gt215_disp_new, 1581 .dma = gf100_dma_new, 1582 .fifo = gf100_fifo_new, 1583 .gr = gf104_gr_new, 1584 .mspdec = gf100_mspdec_new, 1585 .msppp = gf100_msppp_new, 1586 .msvld = gf100_msvld_new, 1587 .pm = gf100_pm_new, 1588 .sw = gf100_sw_new, 1589}; 1590 1591static const struct nvkm_device_chip 1592nvd7_chipset = { 1593 .name = "GF117", 1594 .bar = gf100_bar_new, 1595 .bios = nvkm_bios_new, 1596 .bus = gf100_bus_new, 1597 .clk = gf100_clk_new, 1598 .devinit = gf100_devinit_new, 1599 .fb = gf100_fb_new, 1600 .fuse = gf100_fuse_new, 1601 .gpio = gf119_gpio_new, 1602 .i2c = gf117_i2c_new, 1603 .ibus = gf117_ibus_new, 1604 .imem = nv50_instmem_new, 1605 .ltc = gf100_ltc_new, 1606 .mc = gf100_mc_new, 1607 .mmu = gf100_mmu_new, 1608 .mxm = nv50_mxm_new, 1609 .pci = g94_pci_new, 1610 .therm = gf119_therm_new, 1611 .timer = nv41_timer_new, 1612 .ce[0] = gf100_ce_new, 1613 .disp = gf119_disp_new, 1614 .dma = gf119_dma_new, 1615 .fifo = gf100_fifo_new, 1616 .gr = gf117_gr_new, 1617 .mspdec = gf100_mspdec_new, 1618 .msppp = gf100_msppp_new, 1619 .msvld = gf100_msvld_new, 1620 .pm = gf117_pm_new, 1621 .sw = gf100_sw_new, 1622}; 1623 1624static const struct nvkm_device_chip 1625nvd9_chipset = { 1626 .name = "GF119", 1627 .bar = gf100_bar_new, 1628 .bios = nvkm_bios_new, 1629 .bus = gf100_bus_new, 1630 .clk = gf100_clk_new, 1631 .devinit = gf100_devinit_new, 1632 .fb = gf100_fb_new, 1633 .fuse = gf100_fuse_new, 1634 .gpio = gf119_gpio_new, 1635 .i2c = gf119_i2c_new, 1636 .ibus = gf117_ibus_new, 1637 .imem = nv50_instmem_new, 1638 .ltc = gf100_ltc_new, 1639 .mc = gf100_mc_new, 1640 .mmu = gf100_mmu_new, 1641 .mxm = nv50_mxm_new, 1642 .pci = g94_pci_new, 1643 .pmu = gf119_pmu_new, 1644 .therm = gf119_therm_new, 1645 .timer = nv41_timer_new, 1646 .volt = nv40_volt_new, 1647 .ce[0] = gf100_ce_new, 1648 .disp = gf119_disp_new, 1649 .dma = gf119_dma_new, 1650 .fifo = gf100_fifo_new, 1651 .gr = gf119_gr_new, 1652 .mspdec = gf100_mspdec_new, 1653 .msppp = gf100_msppp_new, 1654 .msvld = gf100_msvld_new, 1655 .pm = gf117_pm_new, 1656 .sw = gf100_sw_new, 1657}; 1658 1659static const struct nvkm_device_chip 1660nve4_chipset = { 1661 .name = "GK104", 1662 .bar = gf100_bar_new, 1663 .bios = nvkm_bios_new, 1664 .bus = gf100_bus_new, 1665 .clk = gk104_clk_new, 1666 .devinit = gf100_devinit_new, 1667 .fb = gk104_fb_new, 1668 .fuse = gf100_fuse_new, 1669 .gpio = gk104_gpio_new, 1670 .i2c = gk104_i2c_new, 1671 .ibus = gk104_ibus_new, 1672 .imem = nv50_instmem_new, 1673 .ltc = gk104_ltc_new, 1674 .mc = gf100_mc_new, 1675 .mmu = gf100_mmu_new, 1676 .mxm = nv50_mxm_new, 1677 .pci = g94_pci_new, 1678 .pmu = gk104_pmu_new, 1679 .therm = gf119_therm_new, 1680 .timer = nv41_timer_new, 1681 .volt = gk104_volt_new, 1682 .ce[0] = gk104_ce_new, 1683 .ce[1] = gk104_ce_new, 1684 .ce[2] = gk104_ce_new, 1685 .disp = gk104_disp_new, 1686 .dma = gf119_dma_new, 1687 .fifo = gk104_fifo_new, 1688 .gr = gk104_gr_new, 1689 .mspdec = gk104_mspdec_new, 1690 .msppp = gf100_msppp_new, 1691 .msvld = gk104_msvld_new, 1692 .pm = gk104_pm_new, 1693 .sw = gf100_sw_new, 1694}; 1695 1696static const struct nvkm_device_chip 1697nve6_chipset = { 1698 .name = "GK106", 1699 .bar = gf100_bar_new, 1700 .bios = nvkm_bios_new, 1701 .bus = gf100_bus_new, 1702 .clk = gk104_clk_new, 1703 .devinit = gf100_devinit_new, 1704 .fb = gk104_fb_new, 1705 .fuse = gf100_fuse_new, 1706 .gpio = gk104_gpio_new, 1707 .i2c = gk104_i2c_new, 1708 .ibus = gk104_ibus_new, 1709 .imem = nv50_instmem_new, 1710 .ltc = gk104_ltc_new, 1711 .mc = gf100_mc_new, 1712 .mmu = gf100_mmu_new, 1713 .mxm = nv50_mxm_new, 1714 .pci = g94_pci_new, 1715 .pmu = gk104_pmu_new, 1716 .therm = gf119_therm_new, 1717 .timer = nv41_timer_new, 1718 .volt = gk104_volt_new, 1719 .ce[0] = gk104_ce_new, 1720 .ce[1] = gk104_ce_new, 1721 .ce[2] = gk104_ce_new, 1722 .disp = gk104_disp_new, 1723 .dma = gf119_dma_new, 1724 .fifo = gk104_fifo_new, 1725 .gr = gk104_gr_new, 1726 .mspdec = gk104_mspdec_new, 1727 .msppp = gf100_msppp_new, 1728 .msvld = gk104_msvld_new, 1729 .pm = gk104_pm_new, 1730 .sw = gf100_sw_new, 1731}; 1732 1733static const struct nvkm_device_chip 1734nve7_chipset = { 1735 .name = "GK107", 1736 .bar = gf100_bar_new, 1737 .bios = nvkm_bios_new, 1738 .bus = gf100_bus_new, 1739 .clk = gk104_clk_new, 1740 .devinit = gf100_devinit_new, 1741 .fb = gk104_fb_new, 1742 .fuse = gf100_fuse_new, 1743 .gpio = gk104_gpio_new, 1744 .i2c = gk104_i2c_new, 1745 .ibus = gk104_ibus_new, 1746 .imem = nv50_instmem_new, 1747 .ltc = gk104_ltc_new, 1748 .mc = gf100_mc_new, 1749 .mmu = gf100_mmu_new, 1750 .mxm = nv50_mxm_new, 1751 .pci = g94_pci_new, 1752 .pmu = gk104_pmu_new, 1753 .therm = gf119_therm_new, 1754 .timer = nv41_timer_new, 1755 .volt = gk104_volt_new, 1756 .ce[0] = gk104_ce_new, 1757 .ce[1] = gk104_ce_new, 1758 .ce[2] = gk104_ce_new, 1759 .disp = gk104_disp_new, 1760 .dma = gf119_dma_new, 1761 .fifo = gk104_fifo_new, 1762 .gr = gk104_gr_new, 1763 .mspdec = gk104_mspdec_new, 1764 .msppp = gf100_msppp_new, 1765 .msvld = gk104_msvld_new, 1766 .pm = gk104_pm_new, 1767 .sw = gf100_sw_new, 1768}; 1769 1770static const struct nvkm_device_chip 1771nvea_chipset = { 1772 .name = "GK20A", 1773 .bar = gk20a_bar_new, 1774 .bus = gf100_bus_new, 1775 .clk = gk20a_clk_new, 1776 .fb = gk20a_fb_new, 1777 .fuse = gf100_fuse_new, 1778 .ibus = gk20a_ibus_new, 1779 .imem = gk20a_instmem_new, 1780 .ltc = gk104_ltc_new, 1781 .mc = gk20a_mc_new, 1782 .mmu = gf100_mmu_new, 1783 .pmu = gk20a_pmu_new, 1784 .timer = gk20a_timer_new, 1785 .volt = gk20a_volt_new, 1786 .ce[2] = gk104_ce_new, 1787 .dma = gf119_dma_new, 1788 .fifo = gk20a_fifo_new, 1789 .gr = gk20a_gr_new, 1790 .pm = gk104_pm_new, 1791 .sw = gf100_sw_new, 1792}; 1793 1794static const struct nvkm_device_chip 1795nvf0_chipset = { 1796 .name = "GK110", 1797 .bar = gf100_bar_new, 1798 .bios = nvkm_bios_new, 1799 .bus = gf100_bus_new, 1800 .clk = gk104_clk_new, 1801 .devinit = gf100_devinit_new, 1802 .fb = gk104_fb_new, 1803 .fuse = gf100_fuse_new, 1804 .gpio = gk104_gpio_new, 1805 .i2c = gk104_i2c_new, 1806 .ibus = gk104_ibus_new, 1807 .imem = nv50_instmem_new, 1808 .ltc = gk104_ltc_new, 1809 .mc = gf100_mc_new, 1810 .mmu = gf100_mmu_new, 1811 .mxm = nv50_mxm_new, 1812 .pci = g94_pci_new, 1813 .pmu = gk110_pmu_new, 1814 .therm = gf119_therm_new, 1815 .timer = nv41_timer_new, 1816 .volt = gk104_volt_new, 1817 .ce[0] = gk104_ce_new, 1818 .ce[1] = gk104_ce_new, 1819 .ce[2] = gk104_ce_new, 1820 .disp = gk110_disp_new, 1821 .dma = gf119_dma_new, 1822 .fifo = gk104_fifo_new, 1823 .gr = gk110_gr_new, 1824 .mspdec = gk104_mspdec_new, 1825 .msppp = gf100_msppp_new, 1826 .msvld = gk104_msvld_new, 1827 .sw = gf100_sw_new, 1828}; 1829 1830static const struct nvkm_device_chip 1831nvf1_chipset = { 1832 .name = "GK110B", 1833 .bar = gf100_bar_new, 1834 .bios = nvkm_bios_new, 1835 .bus = gf100_bus_new, 1836 .clk = gk104_clk_new, 1837 .devinit = gf100_devinit_new, 1838 .fb = gk104_fb_new, 1839 .fuse = gf100_fuse_new, 1840 .gpio = gk104_gpio_new, 1841 .i2c = gk104_i2c_new, 1842 .ibus = gk104_ibus_new, 1843 .imem = nv50_instmem_new, 1844 .ltc = gk104_ltc_new, 1845 .mc = gf100_mc_new, 1846 .mmu = gf100_mmu_new, 1847 .mxm = nv50_mxm_new, 1848 .pci = g94_pci_new, 1849 .pmu = gk110_pmu_new, 1850 .therm = gf119_therm_new, 1851 .timer = nv41_timer_new, 1852 .volt = gk104_volt_new, 1853 .ce[0] = gk104_ce_new, 1854 .ce[1] = gk104_ce_new, 1855 .ce[2] = gk104_ce_new, 1856 .disp = gk110_disp_new, 1857 .dma = gf119_dma_new, 1858 .fifo = gk104_fifo_new, 1859 .gr = gk110b_gr_new, 1860 .mspdec = gk104_mspdec_new, 1861 .msppp = gf100_msppp_new, 1862 .msvld = gk104_msvld_new, 1863 .sw = gf100_sw_new, 1864}; 1865 1866static const struct nvkm_device_chip 1867nv106_chipset = { 1868 .name = "GK208B", 1869 .bar = gf100_bar_new, 1870 .bios = nvkm_bios_new, 1871 .bus = gf100_bus_new, 1872 .clk = gk104_clk_new, 1873 .devinit = gf100_devinit_new, 1874 .fb = gk104_fb_new, 1875 .fuse = gf100_fuse_new, 1876 .gpio = gk104_gpio_new, 1877 .i2c = gk104_i2c_new, 1878 .ibus = gk104_ibus_new, 1879 .imem = nv50_instmem_new, 1880 .ltc = gk104_ltc_new, 1881 .mc = gk20a_mc_new, 1882 .mmu = gf100_mmu_new, 1883 .mxm = nv50_mxm_new, 1884 .pci = g94_pci_new, 1885 .pmu = gk208_pmu_new, 1886 .therm = gf119_therm_new, 1887 .timer = nv41_timer_new, 1888 .volt = gk104_volt_new, 1889 .ce[0] = gk104_ce_new, 1890 .ce[1] = gk104_ce_new, 1891 .ce[2] = gk104_ce_new, 1892 .disp = gk110_disp_new, 1893 .dma = gf119_dma_new, 1894 .fifo = gk208_fifo_new, 1895 .gr = gk208_gr_new, 1896 .mspdec = gk104_mspdec_new, 1897 .msppp = gf100_msppp_new, 1898 .msvld = gk104_msvld_new, 1899 .sw = gf100_sw_new, 1900}; 1901 1902static const struct nvkm_device_chip 1903nv108_chipset = { 1904 .name = "GK208", 1905 .bar = gf100_bar_new, 1906 .bios = nvkm_bios_new, 1907 .bus = gf100_bus_new, 1908 .clk = gk104_clk_new, 1909 .devinit = gf100_devinit_new, 1910 .fb = gk104_fb_new, 1911 .fuse = gf100_fuse_new, 1912 .gpio = gk104_gpio_new, 1913 .i2c = gk104_i2c_new, 1914 .ibus = gk104_ibus_new, 1915 .imem = nv50_instmem_new, 1916 .ltc = gk104_ltc_new, 1917 .mc = gk20a_mc_new, 1918 .mmu = gf100_mmu_new, 1919 .mxm = nv50_mxm_new, 1920 .pci = g94_pci_new, 1921 .pmu = gk208_pmu_new, 1922 .therm = gf119_therm_new, 1923 .timer = nv41_timer_new, 1924 .volt = gk104_volt_new, 1925 .ce[0] = gk104_ce_new, 1926 .ce[1] = gk104_ce_new, 1927 .ce[2] = gk104_ce_new, 1928 .disp = gk110_disp_new, 1929 .dma = gf119_dma_new, 1930 .fifo = gk208_fifo_new, 1931 .gr = gk208_gr_new, 1932 .mspdec = gk104_mspdec_new, 1933 .msppp = gf100_msppp_new, 1934 .msvld = gk104_msvld_new, 1935 .sw = gf100_sw_new, 1936}; 1937 1938static const struct nvkm_device_chip 1939nv117_chipset = { 1940 .name = "GM107", 1941 .bar = gf100_bar_new, 1942 .bios = nvkm_bios_new, 1943 .bus = gf100_bus_new, 1944 .clk = gk104_clk_new, 1945 .devinit = gm107_devinit_new, 1946 .fb = gm107_fb_new, 1947 .fuse = gm107_fuse_new, 1948 .gpio = gk104_gpio_new, 1949 .i2c = gk104_i2c_new, 1950 .ibus = gk104_ibus_new, 1951 .imem = nv50_instmem_new, 1952 .ltc = gm107_ltc_new, 1953 .mc = gk20a_mc_new, 1954 .mmu = gf100_mmu_new, 1955 .mxm = nv50_mxm_new, 1956 .pci = g94_pci_new, 1957 .pmu = gm107_pmu_new, 1958 .therm = gm107_therm_new, 1959 .timer = gk20a_timer_new, 1960 .volt = gk104_volt_new, 1961 .ce[0] = gk104_ce_new, 1962 .ce[2] = gk104_ce_new, 1963 .disp = gm107_disp_new, 1964 .dma = gf119_dma_new, 1965 .fifo = gk208_fifo_new, 1966 .gr = gm107_gr_new, 1967 .sw = gf100_sw_new, 1968}; 1969 1970static const struct nvkm_device_chip 1971nv124_chipset = { 1972 .name = "GM204", 1973 .bar = gf100_bar_new, 1974 .bios = nvkm_bios_new, 1975 .bus = gf100_bus_new, 1976 .devinit = gm204_devinit_new, 1977 .fb = gm107_fb_new, 1978 .fuse = gm107_fuse_new, 1979 .gpio = gk104_gpio_new, 1980 .i2c = gm204_i2c_new, 1981 .ibus = gk104_ibus_new, 1982 .imem = nv50_instmem_new, 1983 .ltc = gm107_ltc_new, 1984 .mc = gk20a_mc_new, 1985 .mmu = gf100_mmu_new, 1986 .mxm = nv50_mxm_new, 1987 .pci = g94_pci_new, 1988 .pmu = gm107_pmu_new, 1989 .timer = gk20a_timer_new, 1990 .volt = gk104_volt_new, 1991 .ce[0] = gm204_ce_new, 1992 .ce[1] = gm204_ce_new, 1993 .ce[2] = gm204_ce_new, 1994 .disp = gm204_disp_new, 1995 .dma = gf119_dma_new, 1996 .fifo = gm204_fifo_new, 1997 .gr = gm204_gr_new, 1998 .sw = gf100_sw_new, 1999}; 2000 2001static const struct nvkm_device_chip 2002nv126_chipset = { 2003 .name = "GM206", 2004 .bar = gf100_bar_new, 2005 .bios = nvkm_bios_new, 2006 .bus = gf100_bus_new, 2007 .devinit = gm204_devinit_new, 2008 .fb = gm107_fb_new, 2009 .fuse = gm107_fuse_new, 2010 .gpio = gk104_gpio_new, 2011 .i2c = gm204_i2c_new, 2012 .ibus = gk104_ibus_new, 2013 .imem = nv50_instmem_new, 2014 .ltc = gm107_ltc_new, 2015 .mc = gk20a_mc_new, 2016 .mmu = gf100_mmu_new, 2017 .mxm = nv50_mxm_new, 2018 .pci = g94_pci_new, 2019 .pmu = gm107_pmu_new, 2020 .timer = gk20a_timer_new, 2021 .volt = gk104_volt_new, 2022 .ce[0] = gm204_ce_new, 2023 .ce[1] = gm204_ce_new, 2024 .ce[2] = gm204_ce_new, 2025 .disp = gm204_disp_new, 2026 .dma = gf119_dma_new, 2027 .fifo = gm204_fifo_new, 2028 .gr = gm206_gr_new, 2029 .sw = gf100_sw_new, 2030}; 2031 2032static const struct nvkm_device_chip 2033nv12b_chipset = { 2034 .name = "GM20B", 2035 .bar = gk20a_bar_new, 2036 .bus = gf100_bus_new, 2037 .fb = gk20a_fb_new, 2038 .fuse = gm107_fuse_new, 2039 .ibus = gk20a_ibus_new, 2040 .imem = gk20a_instmem_new, 2041 .ltc = gm107_ltc_new, 2042 .mc = gk20a_mc_new, 2043 .mmu = gf100_mmu_new, 2044 .timer = gk20a_timer_new, 2045 .ce[2] = gm204_ce_new, 2046 .dma = gf119_dma_new, 2047 .fifo = gm20b_fifo_new, 2048 .gr = gm20b_gr_new, 2049 .sw = gf100_sw_new, 2050}; 2051 2052static int 2053nvkm_device_event_ctor(struct nvkm_object *object, void *data, u32 size, 2054 struct nvkm_notify *notify) 2055{ 2056 if (!WARN_ON(size != 0)) { 2057 notify->size = 0; 2058 notify->types = 1; 2059 notify->index = 0; 2060 return 0; 2061 } 2062 return -EINVAL; 2063} 2064 2065static const struct nvkm_event_func 2066nvkm_device_event_func = { 2067 .ctor = nvkm_device_event_ctor, 2068}; 2069 2070struct nvkm_subdev * 2071nvkm_device_subdev(struct nvkm_device *device, int index) 2072{ 2073 struct nvkm_engine *engine; 2074 2075 if (device->disable_mask & (1ULL << index)) 2076 return NULL; 2077 2078 switch (index) { 2079#define _(n,p,m) case NVKM_SUBDEV_##n: if (p) return (m); break 2080 _(BAR , device->bar , &device->bar->subdev); 2081 _(VBIOS , device->bios , &device->bios->subdev); 2082 _(BUS , device->bus , &device->bus->subdev); 2083 _(CLK , device->clk , &device->clk->subdev); 2084 _(DEVINIT, device->devinit, &device->devinit->subdev); 2085 _(FB , device->fb , &device->fb->subdev); 2086 _(FUSE , device->fuse , &device->fuse->subdev); 2087 _(GPIO , device->gpio , &device->gpio->subdev); 2088 _(I2C , device->i2c , &device->i2c->subdev); 2089 _(IBUS , device->ibus , device->ibus); 2090 _(INSTMEM, device->imem , &device->imem->subdev); 2091 _(LTC , device->ltc , &device->ltc->subdev); 2092 _(MC , device->mc , &device->mc->subdev); 2093 _(MMU , device->mmu , &device->mmu->subdev); 2094 _(MXM , device->mxm , device->mxm); 2095 _(PCI , device->pci , &device->pci->subdev); 2096 _(PMU , device->pmu , &device->pmu->subdev); 2097 _(THERM , device->therm , &device->therm->subdev); 2098 _(TIMER , device->timer , &device->timer->subdev); 2099 _(VOLT , device->volt , &device->volt->subdev); 2100#undef _ 2101 default: 2102 engine = nvkm_device_engine(device, index); 2103 if (engine) 2104 return &engine->subdev; 2105 break; 2106 } 2107 return NULL; 2108} 2109 2110struct nvkm_engine * 2111nvkm_device_engine(struct nvkm_device *device, int index) 2112{ 2113 if (device->disable_mask & (1ULL << index)) 2114 return NULL; 2115 2116 switch (index) { 2117#define _(n,p,m) case NVKM_ENGINE_##n: if (p) return (m); break 2118 _(BSP , device->bsp , device->bsp); 2119 _(CE0 , device->ce[0] , device->ce[0]); 2120 _(CE1 , device->ce[1] , device->ce[1]); 2121 _(CE2 , device->ce[2] , device->ce[2]); 2122 _(CIPHER , device->cipher , device->cipher); 2123 _(DISP , device->disp , &device->disp->engine); 2124 _(DMAOBJ , device->dma , &device->dma->engine); 2125 _(FIFO , device->fifo , &device->fifo->engine); 2126 _(GR , device->gr , &device->gr->engine); 2127 _(IFB , device->ifb , device->ifb); 2128 _(ME , device->me , device->me); 2129 _(MPEG , device->mpeg , device->mpeg); 2130 _(MSENC , device->msenc , device->msenc); 2131 _(MSPDEC , device->mspdec , device->mspdec); 2132 _(MSPPP , device->msppp , device->msppp); 2133 _(MSVLD , device->msvld , device->msvld); 2134 _(PM , device->pm , &device->pm->engine); 2135 _(SEC , device->sec , device->sec); 2136 _(SW , device->sw , &device->sw->engine); 2137 _(VIC , device->vic , device->vic); 2138 _(VP , device->vp , device->vp); 2139#undef _ 2140 default: 2141 WARN_ON(1); 2142 break; 2143 } 2144 return NULL; 2145} 2146 2147int 2148nvkm_device_fini(struct nvkm_device *device, bool suspend) 2149{ 2150 const char *action = suspend ? "suspend" : "fini"; 2151 struct nvkm_subdev *subdev; 2152 int ret, i; 2153 s64 time; 2154 2155 nvdev_trace(device, "%s running...\n", action); 2156 time = ktime_to_us(ktime_get()); 2157 2158 nvkm_acpi_fini(device); 2159 2160 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2161 if ((subdev = nvkm_device_subdev(device, i))) { 2162 ret = nvkm_subdev_fini(subdev, suspend); 2163 if (ret && suspend) 2164 goto fail; 2165 } 2166 } 2167 2168 2169 if (device->func->fini) 2170 device->func->fini(device, suspend); 2171 2172 time = ktime_to_us(ktime_get()) - time; 2173 nvdev_trace(device, "%s completed in %lldus...\n", action, time); 2174 return 0; 2175 2176fail: 2177 do { 2178 if ((subdev = nvkm_device_subdev(device, i))) { 2179 int rret = nvkm_subdev_init(subdev); 2180 if (rret) 2181 nvkm_fatal(subdev, "failed restart, %d\n", ret); 2182 } 2183 } while (++i < NVKM_SUBDEV_NR); 2184 2185 nvdev_trace(device, "%s failed with %d\n", action, ret); 2186 return ret; 2187} 2188 2189static int 2190nvkm_device_preinit(struct nvkm_device *device) 2191{ 2192 struct nvkm_subdev *subdev; 2193 int ret, i; 2194 s64 time; 2195 2196 nvdev_trace(device, "preinit running...\n"); 2197 time = ktime_to_us(ktime_get()); 2198 2199 if (device->func->preinit) { 2200 ret = device->func->preinit(device); 2201 if (ret) 2202 goto fail; 2203 } 2204 2205 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2206 if ((subdev = nvkm_device_subdev(device, i))) { 2207 ret = nvkm_subdev_preinit(subdev); 2208 if (ret) 2209 goto fail; 2210 } 2211 } 2212 2213 ret = nvkm_devinit_post(device->devinit, &device->disable_mask); 2214 if (ret) 2215 goto fail; 2216 2217 time = ktime_to_us(ktime_get()) - time; 2218 nvdev_trace(device, "preinit completed in %lldus\n", time); 2219 return 0; 2220 2221fail: 2222 nvdev_error(device, "preinit failed with %d\n", ret); 2223 return ret; 2224} 2225 2226int 2227nvkm_device_init(struct nvkm_device *device) 2228{ 2229 struct nvkm_subdev *subdev; 2230 int ret, i; 2231 s64 time; 2232 2233 ret = nvkm_device_preinit(device); 2234 if (ret) 2235 return ret; 2236 2237 nvkm_device_fini(device, false); 2238 2239 nvdev_trace(device, "init running...\n"); 2240 time = ktime_to_us(ktime_get()); 2241 2242 if (device->func->init) { 2243 ret = device->func->init(device); 2244 if (ret) 2245 goto fail; 2246 } 2247 2248 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2249 if ((subdev = nvkm_device_subdev(device, i))) { 2250 ret = nvkm_subdev_init(subdev); 2251 if (ret) 2252 goto fail_subdev; 2253 } 2254 } 2255 2256 nvkm_acpi_init(device); 2257 2258 time = ktime_to_us(ktime_get()) - time; 2259 nvdev_trace(device, "init completed in %lldus\n", time); 2260 return 0; 2261 2262fail_subdev: 2263 do { 2264 if ((subdev = nvkm_device_subdev(device, i))) 2265 nvkm_subdev_fini(subdev, false); 2266 } while (--i >= 0); 2267 2268fail: 2269 nvdev_error(device, "init failed with %d\n", ret); 2270 return ret; 2271} 2272 2273void 2274nvkm_device_del(struct nvkm_device **pdevice) 2275{ 2276 struct nvkm_device *device = *pdevice; 2277 int i; 2278 if (device) { 2279 mutex_lock(&nv_devices_mutex); 2280 device->disable_mask = 0; 2281 for (i = NVKM_SUBDEV_NR - 1; i >= 0; i--) { 2282 struct nvkm_subdev *subdev = 2283 nvkm_device_subdev(device, i); 2284 nvkm_subdev_del(&subdev); 2285 } 2286 2287 nvkm_event_fini(&device->event); 2288 2289 if (device->pri) 2290 iounmap(device->pri); 2291 list_del(&device->head); 2292 2293 if (device->func->dtor) 2294 *pdevice = device->func->dtor(device); 2295 mutex_unlock(&nv_devices_mutex); 2296 2297 kfree(*pdevice); 2298 *pdevice = NULL; 2299 } 2300} 2301 2302int 2303nvkm_device_ctor(const struct nvkm_device_func *func, 2304 const struct nvkm_device_quirk *quirk, 2305 struct device *dev, enum nvkm_device_type type, u64 handle, 2306 const char *name, const char *cfg, const char *dbg, 2307 bool detect, bool mmio, u64 subdev_mask, 2308 struct nvkm_device *device) 2309{ 2310 struct nvkm_subdev *subdev; 2311 u64 mmio_base, mmio_size; 2312 u32 boot0, strap; 2313 void __iomem *map; 2314 int ret = -EEXIST; 2315 int i; 2316 2317 mutex_lock(&nv_devices_mutex); 2318 if (nvkm_device_find_locked(handle)) 2319 goto done; 2320 2321 device->func = func; 2322 device->quirk = quirk; 2323 device->dev = dev; 2324 device->type = type; 2325 device->handle = handle; 2326 device->cfgopt = cfg; 2327 device->dbgopt = dbg; 2328 device->name = name; 2329 list_add_tail(&device->head, &nv_devices); 2330 device->debug = nvkm_dbgopt(device->dbgopt, "device"); 2331 2332 ret = nvkm_event_init(&nvkm_device_event_func, 1, 1, &device->event); 2333 if (ret) 2334 goto done; 2335 2336 mmio_base = device->func->resource_addr(device, 0); 2337 mmio_size = device->func->resource_size(device, 0); 2338 2339 /* identify the chipset, and determine classes of subdev/engines */ 2340 if (detect) { 2341 map = ioremap(mmio_base, 0x102000); 2342 if (ret = -ENOMEM, map == NULL) 2343 goto done; 2344 2345 /* switch mmio to cpu's native endianness */ 2346#ifndef __BIG_ENDIAN 2347 if (ioread32_native(map + 0x000004) != 0x00000000) { 2348#else 2349 if (ioread32_native(map + 0x000004) == 0x00000000) { 2350#endif 2351 iowrite32_native(0x01000001, map + 0x000004); 2352 ioread32_native(map); 2353 } 2354 2355 /* read boot0 and strapping information */ 2356 boot0 = ioread32_native(map + 0x000000); 2357 strap = ioread32_native(map + 0x101000); 2358 iounmap(map); 2359 2360 /* determine chipset and derive architecture from it */ 2361 if ((boot0 & 0x1f000000) > 0) { 2362 device->chipset = (boot0 & 0x1ff00000) >> 20; 2363 device->chiprev = (boot0 & 0x000000ff); 2364 switch (device->chipset & 0x1f0) { 2365 case 0x010: { 2366 if (0x461 & (1 << (device->chipset & 0xf))) 2367 device->card_type = NV_10; 2368 else 2369 device->card_type = NV_11; 2370 device->chiprev = 0x00; 2371 break; 2372 } 2373 case 0x020: device->card_type = NV_20; break; 2374 case 0x030: device->card_type = NV_30; break; 2375 case 0x040: 2376 case 0x060: device->card_type = NV_40; break; 2377 case 0x050: 2378 case 0x080: 2379 case 0x090: 2380 case 0x0a0: device->card_type = NV_50; break; 2381 case 0x0c0: 2382 case 0x0d0: device->card_type = NV_C0; break; 2383 case 0x0e0: 2384 case 0x0f0: 2385 case 0x100: device->card_type = NV_E0; break; 2386 case 0x110: 2387 case 0x120: device->card_type = GM100; break; 2388 default: 2389 break; 2390 } 2391 } else 2392 if ((boot0 & 0xff00fff0) == 0x20004000) { 2393 if (boot0 & 0x00f00000) 2394 device->chipset = 0x05; 2395 else 2396 device->chipset = 0x04; 2397 device->card_type = NV_04; 2398 } 2399 2400 switch (device->chipset) { 2401 case 0x004: device->chip = &nv4_chipset; break; 2402 case 0x005: device->chip = &nv5_chipset; break; 2403 case 0x010: device->chip = &nv10_chipset; break; 2404 case 0x011: device->chip = &nv11_chipset; break; 2405 case 0x015: device->chip = &nv15_chipset; break; 2406 case 0x017: device->chip = &nv17_chipset; break; 2407 case 0x018: device->chip = &nv18_chipset; break; 2408 case 0x01a: device->chip = &nv1a_chipset; break; 2409 case 0x01f: device->chip = &nv1f_chipset; break; 2410 case 0x020: device->chip = &nv20_chipset; break; 2411 case 0x025: device->chip = &nv25_chipset; break; 2412 case 0x028: device->chip = &nv28_chipset; break; 2413 case 0x02a: device->chip = &nv2a_chipset; break; 2414 case 0x030: device->chip = &nv30_chipset; break; 2415 case 0x031: device->chip = &nv31_chipset; break; 2416 case 0x034: device->chip = &nv34_chipset; break; 2417 case 0x035: device->chip = &nv35_chipset; break; 2418 case 0x036: device->chip = &nv36_chipset; break; 2419 case 0x040: device->chip = &nv40_chipset; break; 2420 case 0x041: device->chip = &nv41_chipset; break; 2421 case 0x042: device->chip = &nv42_chipset; break; 2422 case 0x043: device->chip = &nv43_chipset; break; 2423 case 0x044: device->chip = &nv44_chipset; break; 2424 case 0x045: device->chip = &nv45_chipset; break; 2425 case 0x046: device->chip = &nv46_chipset; break; 2426 case 0x047: device->chip = &nv47_chipset; break; 2427 case 0x049: device->chip = &nv49_chipset; break; 2428 case 0x04a: device->chip = &nv4a_chipset; break; 2429 case 0x04b: device->chip = &nv4b_chipset; break; 2430 case 0x04c: device->chip = &nv4c_chipset; break; 2431 case 0x04e: device->chip = &nv4e_chipset; break; 2432 case 0x050: device->chip = &nv50_chipset; break; 2433 case 0x063: device->chip = &nv63_chipset; break; 2434 case 0x067: device->chip = &nv67_chipset; break; 2435 case 0x068: device->chip = &nv68_chipset; break; 2436 case 0x084: device->chip = &nv84_chipset; break; 2437 case 0x086: device->chip = &nv86_chipset; break; 2438 case 0x092: device->chip = &nv92_chipset; break; 2439 case 0x094: device->chip = &nv94_chipset; break; 2440 case 0x096: device->chip = &nv96_chipset; break; 2441 case 0x098: device->chip = &nv98_chipset; break; 2442 case 0x0a0: device->chip = &nva0_chipset; break; 2443 case 0x0a3: device->chip = &nva3_chipset; break; 2444 case 0x0a5: device->chip = &nva5_chipset; break; 2445 case 0x0a8: device->chip = &nva8_chipset; break; 2446 case 0x0aa: device->chip = &nvaa_chipset; break; 2447 case 0x0ac: device->chip = &nvac_chipset; break; 2448 case 0x0af: device->chip = &nvaf_chipset; break; 2449 case 0x0c0: device->chip = &nvc0_chipset; break; 2450 case 0x0c1: device->chip = &nvc1_chipset; break; 2451 case 0x0c3: device->chip = &nvc3_chipset; break; 2452 case 0x0c4: device->chip = &nvc4_chipset; break; 2453 case 0x0c8: device->chip = &nvc8_chipset; break; 2454 case 0x0ce: device->chip = &nvce_chipset; break; 2455 case 0x0cf: device->chip = &nvcf_chipset; break; 2456 case 0x0d7: device->chip = &nvd7_chipset; break; 2457 case 0x0d9: device->chip = &nvd9_chipset; break; 2458 case 0x0e4: device->chip = &nve4_chipset; break; 2459 case 0x0e6: device->chip = &nve6_chipset; break; 2460 case 0x0e7: device->chip = &nve7_chipset; break; 2461 case 0x0ea: device->chip = &nvea_chipset; break; 2462 case 0x0f0: device->chip = &nvf0_chipset; break; 2463 case 0x0f1: device->chip = &nvf1_chipset; break; 2464 case 0x106: device->chip = &nv106_chipset; break; 2465 case 0x108: device->chip = &nv108_chipset; break; 2466 case 0x117: device->chip = &nv117_chipset; break; 2467 case 0x124: device->chip = &nv124_chipset; break; 2468 case 0x126: device->chip = &nv126_chipset; break; 2469 case 0x12b: device->chip = &nv12b_chipset; break; 2470 default: 2471 nvdev_error(device, "unknown chipset (%08x)\n", boot0); 2472 goto done; 2473 } 2474 2475 nvdev_info(device, "NVIDIA %s (%08x)\n", 2476 device->chip->name, boot0); 2477 2478 /* determine frequency of timing crystal */ 2479 if ( device->card_type <= NV_10 || device->chipset < 0x17 || 2480 (device->chipset >= 0x20 && device->chipset < 0x25)) 2481 strap &= 0x00000040; 2482 else 2483 strap &= 0x00400040; 2484 2485 switch (strap) { 2486 case 0x00000000: device->crystal = 13500; break; 2487 case 0x00000040: device->crystal = 14318; break; 2488 case 0x00400000: device->crystal = 27000; break; 2489 case 0x00400040: device->crystal = 25000; break; 2490 } 2491 } else { 2492 device->chip = &null_chipset; 2493 } 2494 2495 if (!device->name) 2496 device->name = device->chip->name; 2497 2498 if (mmio) { 2499 device->pri = ioremap(mmio_base, mmio_size); 2500 if (!device->pri) { 2501 nvdev_error(device, "unable to map PRI\n"); 2502 return -ENOMEM; 2503 } 2504 } 2505 2506 mutex_init(&device->mutex); 2507 2508 for (i = 0; i < NVKM_SUBDEV_NR; i++) { 2509#define _(s,m) case s: \ 2510 if (device->chip->m && (subdev_mask & (1ULL << (s)))) { \ 2511 ret = device->chip->m(device, (s), &device->m); \ 2512 if (ret) { \ 2513 subdev = nvkm_device_subdev(device, (s)); \ 2514 nvkm_subdev_del(&subdev); \ 2515 device->m = NULL; \ 2516 if (ret != -ENODEV) { \ 2517 nvdev_error(device, "%s ctor failed, %d\n", \ 2518 nvkm_subdev_name[s], ret); \ 2519 goto done; \ 2520 } \ 2521 } \ 2522 } \ 2523 break 2524 switch (i) { 2525 _(NVKM_SUBDEV_BAR , bar); 2526 _(NVKM_SUBDEV_VBIOS , bios); 2527 _(NVKM_SUBDEV_BUS , bus); 2528 _(NVKM_SUBDEV_CLK , clk); 2529 _(NVKM_SUBDEV_DEVINIT, devinit); 2530 _(NVKM_SUBDEV_FB , fb); 2531 _(NVKM_SUBDEV_FUSE , fuse); 2532 _(NVKM_SUBDEV_GPIO , gpio); 2533 _(NVKM_SUBDEV_I2C , i2c); 2534 _(NVKM_SUBDEV_IBUS , ibus); 2535 _(NVKM_SUBDEV_INSTMEM, imem); 2536 _(NVKM_SUBDEV_LTC , ltc); 2537 _(NVKM_SUBDEV_MC , mc); 2538 _(NVKM_SUBDEV_MMU , mmu); 2539 _(NVKM_SUBDEV_MXM , mxm); 2540 _(NVKM_SUBDEV_PCI , pci); 2541 _(NVKM_SUBDEV_PMU , pmu); 2542 _(NVKM_SUBDEV_THERM , therm); 2543 _(NVKM_SUBDEV_TIMER , timer); 2544 _(NVKM_SUBDEV_VOLT , volt); 2545 _(NVKM_ENGINE_BSP , bsp); 2546 _(NVKM_ENGINE_CE0 , ce[0]); 2547 _(NVKM_ENGINE_CE1 , ce[1]); 2548 _(NVKM_ENGINE_CE2 , ce[2]); 2549 _(NVKM_ENGINE_CIPHER , cipher); 2550 _(NVKM_ENGINE_DISP , disp); 2551 _(NVKM_ENGINE_DMAOBJ , dma); 2552 _(NVKM_ENGINE_FIFO , fifo); 2553 _(NVKM_ENGINE_GR , gr); 2554 _(NVKM_ENGINE_IFB , ifb); 2555 _(NVKM_ENGINE_ME , me); 2556 _(NVKM_ENGINE_MPEG , mpeg); 2557 _(NVKM_ENGINE_MSENC , msenc); 2558 _(NVKM_ENGINE_MSPDEC , mspdec); 2559 _(NVKM_ENGINE_MSPPP , msppp); 2560 _(NVKM_ENGINE_MSVLD , msvld); 2561 _(NVKM_ENGINE_PM , pm); 2562 _(NVKM_ENGINE_SEC , sec); 2563 _(NVKM_ENGINE_SW , sw); 2564 _(NVKM_ENGINE_VIC , vic); 2565 _(NVKM_ENGINE_VP , vp); 2566 default: 2567 WARN_ON(1); 2568 continue; 2569 } 2570#undef _ 2571 } 2572 2573 ret = 0; 2574done: 2575 mutex_unlock(&nv_devices_mutex); 2576 return ret; 2577} 2578