1/* $NetBSD: clk.h,v 1.4 2021/12/18 23:45:33 riastradh Exp $ */ 2 3/* SPDX-License-Identifier: MIT */ 4#ifndef __NVKM_CLK_H__ 5#define __NVKM_CLK_H__ 6#include <core/subdev.h> 7#include <core/notify.h> 8#include <subdev/pci.h> 9struct nvbios_pll; 10struct nvkm_pll_vals; 11 12#define NVKM_CLK_CSTATE_DEFAULT -1 /* POSTed default */ 13#define NVKM_CLK_CSTATE_BASE -2 /* pstate base */ 14#define NVKM_CLK_CSTATE_HIGHEST -3 /* highest possible */ 15 16enum nv_clk_src { 17 nv_clk_src_crystal, 18 nv_clk_src_href, 19 20 nv_clk_src_hclk, 21 nv_clk_src_hclkm3, 22 nv_clk_src_hclkm3d2, 23 nv_clk_src_hclkm2d3, /* NVAA */ 24 nv_clk_src_hclkm4, /* NVAA */ 25 nv_clk_src_cclk, /* NVAA */ 26 27 nv_clk_src_host, 28 29 nv_clk_src_sppll0, 30 nv_clk_src_sppll1, 31 32 nv_clk_src_mpllsrcref, 33 nv_clk_src_mpllsrc, 34 nv_clk_src_mpll, 35 nv_clk_src_mdiv, 36 37 nv_clk_src_core, 38 nv_clk_src_core_intm, 39 nv_clk_src_shader, 40 41 nv_clk_src_mem, 42 43 nv_clk_src_gpc, 44 nv_clk_src_rop, 45 nv_clk_src_hubk01, 46 nv_clk_src_hubk06, 47 nv_clk_src_hubk07, 48 nv_clk_src_copy, 49 nv_clk_src_pmu, 50 nv_clk_src_disp, 51 nv_clk_src_vdec, 52 53 nv_clk_src_dom6, 54 55 nv_clk_src_max, 56}; 57 58struct nvkm_cstate { 59 struct list_head head; 60 u8 voltage; 61 u32 domain[nv_clk_src_max]; 62 u8 id; 63}; 64 65struct nvkm_pstate { 66 struct list_head head; 67 struct list_head list; /* c-states */ 68 struct nvkm_cstate base; 69 u8 pstate; 70 u8 fanspeed; 71 enum nvkm_pcie_speed pcie_speed; 72 u8 pcie_width; 73}; 74 75struct nvkm_domain { 76 enum nv_clk_src name; 77 u8 bios; /* 0xff for none */ 78#define NVKM_CLK_DOM_FLAG_CORE 0x01 79#define NVKM_CLK_DOM_FLAG_VPSTATE 0x02 80 u8 flags; 81 const char *mname; 82 int mdiv; 83}; 84 85struct nvkm_clk { 86 const struct nvkm_clk_func *func; 87 struct nvkm_subdev subdev; 88 89 const struct nvkm_domain *domains; 90 struct nvkm_pstate bstate; 91 92 struct list_head states; 93 int state_nr; 94 95 struct work_struct work; 96#ifdef __NetBSD__ 97 drm_waitqueue_t wait; 98 spinlock_t lock; 99#else 100 wait_queue_head_t wait; 101#endif 102 atomic_t waiting; 103 104 struct nvkm_notify pwrsrc_ntfy; 105 int pwrsrc; 106 int pstate; /* current */ 107 int ustate_ac; /* user-requested (-1 disabled, -2 perfmon) */ 108 int ustate_dc; /* user-requested (-1 disabled, -2 perfmon) */ 109 int astate; /* perfmon adjustment (base) */ 110 int dstate; /* display adjustment (min+) */ 111 u8 temp; 112 113 bool allow_reclock; 114#define NVKM_CLK_BOOST_NONE 0x0 115#define NVKM_CLK_BOOST_BIOS 0x1 116#define NVKM_CLK_BOOST_FULL 0x2 117 u8 boost_mode; 118 u32 base_khz; 119 u32 boost_khz; 120 121 /*XXX: die, these are here *only* to support the completely 122 * bat-shit insane what-was-nouveau_hw.c code 123 */ 124 int (*pll_calc)(struct nvkm_clk *, struct nvbios_pll *, int clk, 125 struct nvkm_pll_vals *pv); 126 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv); 127}; 128 129int nvkm_clk_read(struct nvkm_clk *, enum nv_clk_src); 130int nvkm_clk_ustate(struct nvkm_clk *, int req, int pwr); 131int nvkm_clk_astate(struct nvkm_clk *, int req, int rel, bool wait); 132int nvkm_clk_dstate(struct nvkm_clk *, int req, int rel); 133int nvkm_clk_tstate(struct nvkm_clk *, u8 temperature); 134 135int nv04_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 136int nv40_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 137int nv50_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 138int g84_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 139int mcp77_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 140int gt215_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 141int gf100_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 142int gk104_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 143int gk20a_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 144int gm20b_clk_new(struct nvkm_device *, int, struct nvkm_clk **); 145#endif 146