11590Srgrimes/* $NetBSD: atom.h,v 1.3 2021/12/19 10:49:47 riastradh Exp $ */ 21590Srgrimes 31590Srgrimes#ifndef __NV50_KMS_ATOM_H__ 41590Srgrimes#define __NV50_KMS_ATOM_H__ 51590Srgrimes#define nv50_atom(p) container_of((p), struct nv50_atom, state) 61590Srgrimes#include <drm/drm_atomic.h> 71590Srgrimes 81590Srgrimesstruct nv50_atom { 91590Srgrimes struct drm_atomic_state state; 101590Srgrimes 111590Srgrimes struct list_head outp; 121590Srgrimes bool lock_core; 131590Srgrimes bool flush_disable; 141590Srgrimes}; 151590Srgrimes 161590Srgrimes#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state) 171590Srgrimes 181590Srgrimes#ifdef __NetBSD__ 191590Srgrimes# define __lut_iomem volatile 201590Srgrimes# define __iomem __lut_iomem 211590Srgrimes#endif 221590Srgrimes 231590Srgrimesstruct nv50_head_atom { 241590Srgrimes struct drm_crtc_state state; 251590Srgrimes 261590Srgrimes struct { 271590Srgrimes u32 mask; 281590Srgrimes u32 olut; 291590Srgrimes } wndw; 301590Srgrimes 311590Srgrimes struct { 321590Srgrimes u16 iW; 331590Srgrimes u16 iH; 341590Srgrimes u16 oW; 351590Srgrimes u16 oH; 361590Srgrimes } view; 3787712Smarkm 3887712Smarkm struct nv50_head_mode { 3987712Smarkm bool interlace; 4087712Smarkm u32 clock; 411590Srgrimes struct { 4287712Smarkm u16 active; 4369528Sasmodai u16 synce; 441590Srgrimes u16 blanke; 451590Srgrimes u16 blanks; 461590Srgrimes } h; 4774876Sdwmalone struct { 4887712Smarkm u32 active; 4987712Smarkm u16 synce; 501590Srgrimes u16 blanke; 511590Srgrimes u16 blanks; 521590Srgrimes u16 blank2s; 531590Srgrimes u16 blank2e; 5487712Smarkm u16 blankus; 5587712Smarkm } v; 561590Srgrimes } mode; 571590Srgrimes 581590Srgrimes struct { 59193488Sbrian bool visible; 601590Srgrimes u32 handle; 6117833Sadam u64 offset:40; 6217833Sadam u8 buffer:1; 631590Srgrimes u8 mode:4; 641590Srgrimes u16 size:11; 651590Srgrimes u8 range:2; 66201382Sed u8 output_mode:2; 671590Srgrimes void (*load)(struct drm_color_lut *, int size, void __iomem *); 6817825Speter } olut; 691590Srgrimes 7074876Sdwmalone struct { 7174876Sdwmalone bool visible; 7274876Sdwmalone u32 handle; 7374876Sdwmalone u64 offset:40; 7474876Sdwmalone u8 format; 7574876Sdwmalone u8 kind:7; 76137157Spaul u8 layout:1; 7774876Sdwmalone u8 blockh:4; 7874876Sdwmalone u16 blocks:12; 7974876Sdwmalone u32 pitch:20; 8074876Sdwmalone u16 x; 8174876Sdwmalone u16 y; 82139994Sdwmalone u16 w; 8374876Sdwmalone u16 h; 8474876Sdwmalone } core; 8574876Sdwmalone 8674876Sdwmalone struct { 8774876Sdwmalone bool visible; 8874876Sdwmalone u32 handle; 8974876Sdwmalone u64 offset:40; 9074876Sdwmalone u8 layout:2; 9174876Sdwmalone u8 format:8; 9274876Sdwmalone } curs; 9374876Sdwmalone 9474876Sdwmalone struct { 9574876Sdwmalone u8 depth; 9674876Sdwmalone u8 cpp; 9774876Sdwmalone u16 x; 9874876Sdwmalone u16 y; 9974876Sdwmalone u16 w; 10074876Sdwmalone u16 h; 10174876Sdwmalone } base; 102137157Spaul 10374876Sdwmalone struct { 10474876Sdwmalone u8 cpp; 10574876Sdwmalone } ovly; 10674876Sdwmalone 10774876Sdwmalone struct { 10874876Sdwmalone bool enable:1; 10974876Sdwmalone u8 bits:2; 110139994Sdwmalone u8 mode:4; 11174876Sdwmalone } dither; 11274876Sdwmalone 11374876Sdwmalone struct { 11474876Sdwmalone struct { 11574876Sdwmalone u16 cos:12; 11674876Sdwmalone u16 sin:12; 11774876Sdwmalone } sat; 11874876Sdwmalone } procamp; 11974876Sdwmalone 120 struct { 121 u8 nhsync:1; 122 u8 nvsync:1; 123 u8 depth:4; 124 u8 bpc; 125 } or; 126 127 /* Currently only used for MST */ 128 struct { 129 int pbn; 130 u8 tu:6; 131 } dp; 132 133 union nv50_head_atom_mask { 134 struct { 135 bool olut:1; 136 bool core:1; 137 bool curs:1; 138 bool view:1; 139 bool mode:1; 140 bool base:1; 141 bool ovly:1; 142 bool dither:1; 143 bool procamp:1; 144 bool or:1; 145 }; 146 u16 mask; 147 } set, clr; 148}; 149 150static inline struct nv50_head_atom * 151nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc) 152{ 153 struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc); 154 if (IS_ERR(statec)) 155 return (void *)statec; 156 return nv50_head_atom(statec); 157} 158 159#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state) 160 161struct nv50_wndw_atom { 162 struct drm_plane_state state; 163 164 struct drm_property_blob *ilut; 165 bool visible; 166 167 struct { 168 u32 handle; 169 u16 offset:12; 170 bool awaken:1; 171 } ntfy; 172 173 struct { 174 u32 handle; 175 u16 offset:12; 176 u32 acquire; 177 u32 release; 178 } sema; 179 180 struct { 181 u32 handle; 182 struct { 183 u64 offset:40; 184 u8 buffer:1; 185 u8 enable:2; 186 u8 mode:4; 187 u16 size:11; 188 u8 range:2; 189 u8 output_mode:2; 190 void (*load)(struct drm_color_lut *, int size, 191 void __iomem *); 192 } i; 193 } xlut; 194 195 struct { 196 u32 matrix[12]; 197 bool valid; 198 } csc; 199 200 struct { 201 u8 mode:2; 202 u8 interval:4; 203 204 u8 colorspace:2; 205 u8 format; 206 u8 kind:7; 207 u8 layout:1; 208 u8 blockh:4; 209 u16 blocks[3]; 210 u32 pitch[3]; 211 u16 w; 212 u16 h; 213 214 u32 handle[6]; 215 u64 offset[6]; 216 } image; 217 218 struct { 219 u16 sx; 220 u16 sy; 221 u16 sw; 222 u16 sh; 223 u16 dw; 224 u16 dh; 225 } scale; 226 227 struct { 228 u16 x; 229 u16 y; 230 } point; 231 232 struct { 233 u8 depth; 234 u8 k1; 235 u8 src_color:4; 236 u8 dst_color:4; 237 } blend; 238 239 union nv50_wndw_atom_mask { 240 struct { 241 bool ntfy:1; 242 bool sema:1; 243 bool xlut:1; 244 bool csc:1; 245 bool image:1; 246 bool scale:1; 247 bool point:1; 248 bool blend:1; 249 }; 250 u8 mask; 251 } set, clr; 252}; 253 254#ifdef __NetBSD__ 255# undef __iomem 256#endif 257 258#endif 259