1/* $NetBSD: nouveau_dispnv04_cursor.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $ */ 2 3// SPDX-License-Identifier: MIT 4#include <sys/cdefs.h> 5__KERNEL_RCSID(0, "$NetBSD: nouveau_dispnv04_cursor.c,v 1.3 2021/12/18 23:45:32 riastradh Exp $"); 6 7#include <drm/drm_mode.h> 8#include "nouveau_drv.h" 9#include "nouveau_reg.h" 10#include "nouveau_crtc.h" 11#include "hw.h" 12 13static void 14nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) 15{ 16 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); 17} 18 19static void 20nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) 21{ 22 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); 23} 24 25static void 26nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) 27{ 28 nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; 29 NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, 30 NV_PRAMDAC_CU_START_POS, 31 XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | 32 XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); 33} 34 35static void 36crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) 37{ 38 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, 39 crtcstate->CRTC[index]); 40} 41 42static void 43nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) 44{ 45 struct drm_device *dev = nv_crtc->base.dev; 46 struct nouveau_drm *drm = nouveau_drm(dev); 47 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; 48 struct drm_crtc *crtc = &nv_crtc->base; 49 50 regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = 51 MASK(NV_CIO_CRE_HCUR_ASI) | 52 XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); 53 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = 54 XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); 55 if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) 56 regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= 57 MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); 58 regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; 59 60 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); 61 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); 62 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); 63 if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) 64 nv_fix_nv40_hw_cursor(dev, nv_crtc->index); 65} 66 67int 68nv04_cursor_init(struct nouveau_crtc *crtc) 69{ 70 crtc->cursor.set_offset = nv04_cursor_set_offset; 71 crtc->cursor.set_pos = nv04_cursor_set_pos; 72 crtc->cursor.hide = nv04_cursor_hide; 73 crtc->cursor.show = nv04_cursor_show; 74 return 0; 75} 76