i915_gpu_error.c revision 1.8
1/* $NetBSD: i915_gpu_error.c,v 1.8 2018/08/27 07:09:28 riastradh Exp $ */ 2 3/* 4 * Copyright (c) 2008 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Keith Packard <keithp@keithp.com> 28 * Mika Kuoppala <mika.kuoppala@intel.com> 29 * 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: i915_gpu_error.c,v 1.8 2018/08/27 07:09:28 riastradh Exp $"); 34 35#include <sys/param.h> 36 37#include <asm/io.h> 38#include <linux/irqflags.h> 39#include "i915_drv.h" 40 41static const char *ring_str(int ring) 42{ 43 switch (ring) { 44 case RCS: return "render"; 45 case VCS: return "bsd"; 46 case BCS: return "blt"; 47 case VECS: return "vebox"; 48 case VCS2: return "bsd2"; 49 default: return ""; 50 } 51} 52 53static const char *pin_flag(int pinned) 54{ 55 if (pinned > 0) 56 return " P"; 57 else if (pinned < 0) 58 return " p"; 59 else 60 return ""; 61} 62 63static const char *tiling_flag(int tiling) 64{ 65 switch (tiling) { 66 default: 67 case I915_TILING_NONE: return ""; 68 case I915_TILING_X: return " X"; 69 case I915_TILING_Y: return " Y"; 70 } 71} 72 73static const char *dirty_flag(int dirty) 74{ 75 return dirty ? " dirty" : ""; 76} 77 78static const char *purgeable_flag(int purgeable) 79{ 80 return purgeable ? " purgeable" : ""; 81} 82 83static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 84{ 85 86 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 87 e->err = -ENOSPC; 88 return false; 89 } 90 91 if (e->bytes == e->size - 1 || e->err) 92 return false; 93 94 return true; 95} 96 97static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 98 unsigned len) 99{ 100 if (e->pos + len <= e->start) { 101 e->pos += len; 102 return false; 103 } 104 105 /* First vsnprintf needs to fit in its entirety for memmove */ 106 if (len >= e->size) { 107 e->err = -EIO; 108 return false; 109 } 110 111 return true; 112} 113 114static void __i915_error_advance(struct drm_i915_error_state_buf *e, 115 unsigned len) 116{ 117 /* If this is first printf in this window, adjust it so that 118 * start position matches start of the buffer 119 */ 120 121 if (e->pos < e->start) { 122 const size_t off = e->start - e->pos; 123 124 /* Should not happen but be paranoid */ 125 if (off > len || e->bytes) { 126 e->err = -EIO; 127 return; 128 } 129 130 memmove(e->buf, e->buf + off, len - off); 131 e->bytes = len - off; 132 e->pos = e->start; 133 return; 134 } 135 136 e->bytes += len; 137 e->pos += len; 138} 139 140static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 141 const char *f, va_list args) 142{ 143 unsigned len; 144 145 if (!__i915_error_ok(e)) 146 return; 147 148 /* Seek the first printf which is hits start position */ 149 if (e->pos < e->start) { 150 va_list tmp; 151 152 va_copy(tmp, args); 153 len = vsnprintf(NULL, 0, f, tmp); 154 va_end(tmp); 155 156 if (!__i915_error_seek(e, len)) 157 return; 158 } 159 160 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 161 if (len >= e->size - e->bytes) 162 len = e->size - e->bytes - 1; 163 164 __i915_error_advance(e, len); 165} 166 167static void i915_error_puts(struct drm_i915_error_state_buf *e, 168 const char *str) 169{ 170 unsigned len; 171 172 if (!__i915_error_ok(e)) 173 return; 174 175 len = strlen(str); 176 177 /* Seek the first printf which is hits start position */ 178 if (e->pos < e->start) { 179 if (!__i915_error_seek(e, len)) 180 return; 181 } 182 183 if (len >= e->size - e->bytes) 184 len = e->size - e->bytes - 1; 185 memcpy(e->buf + e->bytes, str, len); 186 187 __i915_error_advance(e, len); 188} 189 190#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 191#define err_puts(e, s) i915_error_puts(e, s) 192 193static void print_error_buffers(struct drm_i915_error_state_buf *m, 194 const char *name, 195 struct drm_i915_error_buffer *err, 196 int count) 197{ 198 int i; 199 200 err_printf(m, " %s [%d]:\n", name, count); 201 202 while (count--) { 203 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 204 upper_32_bits(err->gtt_offset), 205 lower_32_bits(err->gtt_offset), 206 err->size, 207 err->read_domains, 208 err->write_domain); 209 for (i = 0; i < I915_NUM_RINGS; i++) 210 err_printf(m, "%02x ", err->rseqno[i]); 211 212 err_printf(m, "] %02x", err->wseqno); 213 err_puts(m, pin_flag(err->pinned)); 214 err_puts(m, tiling_flag(err->tiling)); 215 err_puts(m, dirty_flag(err->dirty)); 216 err_puts(m, purgeable_flag(err->purgeable)); 217 err_puts(m, err->userptr ? " userptr" : ""); 218 err_puts(m, err->ring != -1 ? " " : ""); 219 err_puts(m, ring_str(err->ring)); 220 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 221 222 if (err->name) 223 err_printf(m, " (name: %d)", err->name); 224 if (err->fence_reg != I915_FENCE_REG_NONE) 225 err_printf(m, " (fence: %d)", err->fence_reg); 226 227 err_puts(m, "\n"); 228 err++; 229 } 230} 231 232static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 233{ 234 switch (a) { 235 case HANGCHECK_IDLE: 236 return "idle"; 237 case HANGCHECK_WAIT: 238 return "wait"; 239 case HANGCHECK_ACTIVE: 240 return "active"; 241 case HANGCHECK_ACTIVE_LOOP: 242 return "active (loop)"; 243 case HANGCHECK_KICK: 244 return "kick"; 245 case HANGCHECK_HUNG: 246 return "hung"; 247 } 248 249 return "unknown"; 250} 251 252static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 253 struct drm_device *dev, 254 struct drm_i915_error_state *error, 255 int ring_idx) 256{ 257 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 258 259 if (!ring->valid) 260 return; 261 262 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 263 err_printf(m, " START: 0x%08x\n", ring->start); 264 err_printf(m, " HEAD: 0x%08x\n", ring->head); 265 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 266 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 267 err_printf(m, " HWS: 0x%08x\n", ring->hws); 268 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 269 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 270 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 271 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 272 if (INTEL_INFO(dev)->gen >= 4) { 273 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 274 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 275 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 276 } 277 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 278 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 279 lower_32_bits(ring->faddr)); 280 if (INTEL_INFO(dev)->gen >= 6) { 281 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 282 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 283 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 284 ring->semaphore_mboxes[0], 285 ring->semaphore_seqno[0]); 286 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 287 ring->semaphore_mboxes[1], 288 ring->semaphore_seqno[1]); 289 if (HAS_VEBOX(dev)) { 290 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 291 ring->semaphore_mboxes[2], 292 ring->semaphore_seqno[2]); 293 } 294 } 295 if (USES_PPGTT(dev)) { 296 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 297 298 if (INTEL_INFO(dev)->gen >= 8) { 299 int i; 300 for (i = 0; i < 4; i++) 301 err_printf(m, " PDP%d: 0x%016"PRIx64"\n", 302 i, ring->vm_info.pdp[i]); 303 } else { 304 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 305 ring->vm_info.pp_dir_base); 306 } 307 } 308 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 309 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 310 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 311 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 312 err_printf(m, " hangcheck: %s [%d]\n", 313 hangcheck_action_to_str(ring->hangcheck_action), 314 ring->hangcheck_score); 315} 316 317void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 318{ 319 va_list args; 320 321 va_start(args, f); 322 i915_error_vprintf(e, f, args); 323 va_end(args); 324} 325 326static void print_error_obj(struct drm_i915_error_state_buf *m, 327 struct drm_i915_error_object *obj) 328{ 329 int page, offset, elt; 330 331 for (page = offset = 0; page < obj->page_count; page++) { 332 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 333 err_printf(m, "%08x : %08x\n", offset, 334 obj->pages[page][elt]); 335 offset += 4; 336 } 337 } 338} 339 340int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 341 const struct i915_error_state_file_priv *error_priv) 342{ 343 struct drm_device *dev = error_priv->dev; 344 struct drm_i915_private *dev_priv = dev->dev_private; 345 struct drm_i915_error_state *error = error_priv->error; 346 struct drm_i915_error_object *obj; 347 int i, j, offset, elt; 348 int max_hangcheck_score; 349 350 if (!error) { 351 err_printf(m, "no error state collected\n"); 352 goto out; 353 } 354 355 err_printf(m, "%s\n", error->error_msg); 356 err_printf(m, "Time: %"PRIdMAX" s %ld us\n", (intmax_t)error->time.tv_sec, 357 (long)error->time.tv_usec); 358 err_printf(m, "Kernel: %d\n", __NetBSD_Version__); 359 err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, 360 (long)error->time.tv_usec); 361 max_hangcheck_score = 0; 362 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 363 if (error->ring[i].hangcheck_score > max_hangcheck_score) 364 max_hangcheck_score = error->ring[i].hangcheck_score; 365 } 366 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 367 if (error->ring[i].hangcheck_score == max_hangcheck_score && 368 error->ring[i].pid != -1) { 369 err_printf(m, "Active process (on ring %s): %s [%d]\n", 370 ring_str(i), 371 error->ring[i].comm, 372 error->ring[i].pid); 373 } 374 } 375 err_printf(m, "Reset count: %u\n", error->reset_count); 376 err_printf(m, "Suspend count: %u\n", error->suspend_count); 377 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 378 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 379 err_printf(m, "EIR: 0x%08x\n", error->eir); 380 err_printf(m, "IER: 0x%08x\n", error->ier); 381 if (INTEL_INFO(dev)->gen >= 8) { 382 for (i = 0; i < 4; i++) 383 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 384 error->gtier[i]); 385 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 386 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 387 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 388 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 389 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 390 err_printf(m, "CCID: 0x%08x\n", error->ccid); 391 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 392 393 for (i = 0; i < dev_priv->num_fence_regs; i++) 394 err_printf(m, " fence[%d] = %08"PRIx64"\n", i, error->fence[i]); 395 396 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 397 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 398 error->extra_instdone[i]); 399 400 if (INTEL_INFO(dev)->gen >= 6) { 401 err_printf(m, "ERROR: 0x%08x\n", error->error); 402 403 if (INTEL_INFO(dev)->gen >= 8) 404 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 405 error->fault_data1, error->fault_data0); 406 407 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 408 } 409 410 if (INTEL_INFO(dev)->gen == 7) 411 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 412 413 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 414 i915_ring_error_state(m, dev, error, i); 415 416 for (i = 0; i < error->vm_count; i++) { 417 err_printf(m, "vm[%d]\n", i); 418 419 print_error_buffers(m, "Active", 420 error->active_bo[i], 421 error->active_bo_count[i]); 422 423 print_error_buffers(m, "Pinned", 424 error->pinned_bo[i], 425 error->pinned_bo_count[i]); 426 } 427 428 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 429 obj = error->ring[i].batchbuffer; 430 if (obj) { 431 err_puts(m, dev_priv->ring[i].name); 432 if (error->ring[i].pid != -1) 433 err_printf(m, " (submitted by %s [%d])", 434 error->ring[i].comm, 435 error->ring[i].pid); 436 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 437 upper_32_bits(obj->gtt_offset), 438 lower_32_bits(obj->gtt_offset)); 439 print_error_obj(m, obj); 440 } 441 442 obj = error->ring[i].wa_batchbuffer; 443 if (obj) { 444 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 445 dev_priv->ring[i].name, 446 lower_32_bits(obj->gtt_offset)); 447 print_error_obj(m, obj); 448 } 449 450 if (error->ring[i].num_requests) { 451 err_printf(m, "%s --- %d requests\n", 452 dev_priv->ring[i].name, 453 error->ring[i].num_requests); 454 for (j = 0; j < error->ring[i].num_requests; j++) { 455 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 456 error->ring[i].requests[j].seqno, 457 error->ring[i].requests[j].jiffies, 458 error->ring[i].requests[j].tail); 459 } 460 } 461 462 if ((obj = error->ring[i].ringbuffer)) { 463 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 464 dev_priv->ring[i].name, 465 lower_32_bits(obj->gtt_offset)); 466 print_error_obj(m, obj); 467 } 468 469 if ((obj = error->ring[i].hws_page)) { 470 u64 hws_offset = obj->gtt_offset; 471 u32 *hws_page = &obj->pages[0][0]; 472 473 if (i915.enable_execlists) { 474 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 475 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 476 } 477 err_printf(m, "%s --- HW Status = 0x%08"PRIx64"\n", 478 dev_priv->ring[i].name, hws_offset); 479 offset = 0; 480 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 481 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 482 offset, 483 hws_page[elt], 484 hws_page[elt+1], 485 hws_page[elt+2], 486 hws_page[elt+3]); 487 offset += 16; 488 } 489 } 490 491 if ((obj = error->ring[i].ctx)) { 492 err_printf(m, "%s --- HW Context = 0x%08x\n", 493 dev_priv->ring[i].name, 494 lower_32_bits(obj->gtt_offset)); 495 print_error_obj(m, obj); 496 } 497 } 498 499 if ((obj = error->semaphore_obj)) { 500 err_printf(m, "Semaphore page = 0x%08x\n", 501 lower_32_bits(obj->gtt_offset)); 502 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 503 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 504 elt * 4, 505 obj->pages[0][elt], 506 obj->pages[0][elt+1], 507 obj->pages[0][elt+2], 508 obj->pages[0][elt+3]); 509 } 510 } 511 512 if (error->overlay) 513 intel_overlay_print_error_state(m, error->overlay); 514 515 if (error->display) 516 intel_display_print_error_state(m, dev, error->display); 517 518out: 519 if (m->bytes == 0 && m->err) 520 return m->err; 521 522 return 0; 523} 524 525int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 526 struct drm_i915_private *i915, 527 size_t count, loff_t pos) 528{ 529 memset(ebuf, 0, sizeof(*ebuf)); 530 ebuf->i915 = i915; 531 532 /* We need to have enough room to store any i915_error_state printf 533 * so that we can move it to start position. 534 */ 535 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 536 ebuf->buf = kmalloc(ebuf->size, 537 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 538 539 if (ebuf->buf == NULL) { 540 ebuf->size = PAGE_SIZE; 541 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 542 } 543 544 if (ebuf->buf == NULL) { 545 ebuf->size = 128; 546 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 547 } 548 549 if (ebuf->buf == NULL) 550 return -ENOMEM; 551 552 ebuf->start = pos; 553 554 return 0; 555} 556 557static void i915_error_object_free(struct drm_i915_error_object *obj) 558{ 559 int page; 560 561 if (obj == NULL) 562 return; 563 564 for (page = 0; page < obj->page_count; page++) 565 kfree(obj->pages[page]); 566 567 kfree(obj); 568} 569 570static void i915_error_state_free(struct kref *error_ref) 571{ 572 struct drm_i915_error_state *error = container_of(error_ref, 573 typeof(*error), ref); 574 int i; 575 576 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 577 i915_error_object_free(error->ring[i].batchbuffer); 578 i915_error_object_free(error->ring[i].wa_batchbuffer); 579 i915_error_object_free(error->ring[i].ringbuffer); 580 i915_error_object_free(error->ring[i].hws_page); 581 i915_error_object_free(error->ring[i].ctx); 582 kfree(error->ring[i].requests); 583 } 584 585 i915_error_object_free(error->semaphore_obj); 586 587 for (i = 0; i < error->vm_count; i++) 588 kfree(error->active_bo[i]); 589 590 kfree(error->active_bo); 591 kfree(error->active_bo_count); 592 kfree(error->pinned_bo); 593 kfree(error->pinned_bo_count); 594 kfree(error->overlay); 595 kfree(error->display); 596 kfree(error); 597} 598 599#ifdef __NetBSD__ 600# define __aperture_iomem 601# define __iomem __aperture_iomem 602#endif 603 604static struct drm_i915_error_object * 605i915_error_object_create(struct drm_i915_private *dev_priv, 606 struct drm_i915_gem_object *src, 607 struct i915_address_space *vm) 608{ 609 struct drm_i915_error_object *dst; 610 struct i915_vma *vma = NULL; 611 int num_pages; 612 bool use_ggtt; 613 int i = 0; 614 u64 reloc_offset; 615 616 if (src == NULL || src->pages == NULL) 617 return NULL; 618 619 num_pages = src->base.size >> PAGE_SHIFT; 620 621 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 622 if (dst == NULL) 623 return NULL; 624 625 if (i915_gem_obj_bound(src, vm)) 626 dst->gtt_offset = i915_gem_obj_offset(src, vm); 627 else 628 dst->gtt_offset = -1; 629 630 reloc_offset = dst->gtt_offset; 631 if (i915_is_ggtt(vm)) 632 vma = i915_gem_obj_to_ggtt(src); 633 use_ggtt = (src->cache_level == I915_CACHE_NONE && 634 vma && (vma->bound & GLOBAL_BIND) && 635 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); 636 637 /* Cannot access stolen address directly, try to use the aperture */ 638 if (src->stolen) { 639 use_ggtt = true; 640 641 if (!(vma && vma->bound & GLOBAL_BIND)) 642 goto unwind; 643 644 reloc_offset = i915_gem_obj_ggtt_offset(src); 645 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) 646 goto unwind; 647 } 648 649 /* Cannot access snooped pages through the aperture */ 650 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) 651 goto unwind; 652 653 dst->page_count = num_pages; 654 while (num_pages--) { 655 unsigned long flags; 656 void *d; 657 658 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 659 if (d == NULL) 660 goto unwind; 661 662 local_irq_save(flags); 663 if (use_ggtt) { 664 void __iomem *s; 665 666 /* Simply ignore tiling or any overlapping fence. 667 * It's part of the error state, and this hopefully 668 * captures what the GPU read. 669 */ 670 671 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 672 reloc_offset); 673 memcpy_fromio(d, s, PAGE_SIZE); 674#ifdef __NetBSD__ 675 io_mapping_unmap_atomic(dev_priv->gtt.mappable, s); 676#else 677 io_mapping_unmap_atomic(s); 678#endif 679 } else { 680 681 if (cpu_intr_p() || cpu_softintr_p() || 682 (curlwp->l_pflag & LP_INTR) != 0) { 683 /* 684 * We can't take locks during interrupts 685 * and finding the page from uvm requires 686 * taking a lock. Checking for an interrupt 687 * context is bogus, but this is the least 688 * intrusive change. Zero the result, doesn't 689 * matter much, because this is only used 690 * for diagnostics. 691 */ 692 memset(d, 0, PAGE_SIZE); 693 } else { 694 struct page *page; 695 void *s; 696 697 page = i915_gem_object_get_page(src, i); 698 699 drm_clflush_pages(&page, 1); 700 701 s = kmap_atomic(page); 702 memcpy(d, s, PAGE_SIZE); 703 kunmap_atomic(s); 704 705 drm_clflush_pages(&page, 1); 706 } 707 } 708 local_irq_restore(flags); 709 710 dst->pages[i++] = d; 711 reloc_offset += PAGE_SIZE; 712 } 713 714 return dst; 715 716unwind: 717 while (i--) 718 kfree(dst->pages[i]); 719 kfree(dst); 720 return NULL; 721} 722#define i915_error_ggtt_object_create(dev_priv, src) \ 723 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) 724 725#ifdef __NetBSD__ 726# undef __iomem 727# undef __aperture_iomem 728#endif 729 730static void capture_bo(struct drm_i915_error_buffer *err, 731 struct i915_vma *vma) 732{ 733 struct drm_i915_gem_object *obj = vma->obj; 734 int i; 735 736 err->size = obj->base.size; 737 err->name = obj->base.name; 738 for (i = 0; i < I915_NUM_RINGS; i++) 739 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 740 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 741 err->gtt_offset = vma->node.start; 742 err->read_domains = obj->base.read_domains; 743 err->write_domain = obj->base.write_domain; 744 err->fence_reg = obj->fence_reg; 745 err->pinned = 0; 746 if (i915_gem_obj_is_pinned(obj)) 747 err->pinned = 1; 748 err->tiling = obj->tiling_mode; 749 err->dirty = obj->dirty; 750 err->purgeable = obj->madv != I915_MADV_WILLNEED; 751 err->userptr = obj->userptr.mm != NULL; 752 err->ring = obj->last_write_req ? 753 i915_gem_request_get_ring(obj->last_write_req)->id : -1; 754 err->cache_level = obj->cache_level; 755} 756 757static u32 capture_active_bo(struct drm_i915_error_buffer *err, 758 int count, struct list_head *head) 759{ 760 struct i915_vma *vma; 761 int i = 0; 762 763 list_for_each_entry(vma, head, mm_list) { 764 capture_bo(err++, vma); 765 if (++i == count) 766 break; 767 } 768 769 return i; 770} 771 772static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 773 int count, struct list_head *head, 774 struct i915_address_space *vm) 775{ 776 struct drm_i915_gem_object *obj; 777 struct drm_i915_error_buffer * const first = err; 778 struct drm_i915_error_buffer * const last = err + count; 779 780 list_for_each_entry(obj, head, global_list) { 781 struct i915_vma *vma; 782 783 if (err == last) 784 break; 785 786 list_for_each_entry(vma, &obj->vma_list, vma_link) 787 if (vma->vm == vm && vma->pin_count > 0) 788 capture_bo(err++, vma); 789 } 790 791 return err - first; 792} 793 794/* Generate a semi-unique error code. The code is not meant to have meaning, The 795 * code's only purpose is to try to prevent false duplicated bug reports by 796 * grossly estimating a GPU error state. 797 * 798 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 799 * the hang if we could strip the GTT offset information from it. 800 * 801 * It's only a small step better than a random number in its current form. 802 */ 803static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 804 struct drm_i915_error_state *error, 805 int *ring_id) 806{ 807 uint32_t error_code = 0; 808 int i; 809 810 /* IPEHR would be an ideal way to detect errors, as it's the gross 811 * measure of "the command that hung." However, has some very common 812 * synchronization commands which almost always appear in the case 813 * strictly a client bug. Use instdone to differentiate those some. 814 */ 815 for (i = 0; i < I915_NUM_RINGS; i++) { 816 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 817 if (ring_id) 818 *ring_id = i; 819 820 return error->ring[i].ipehr ^ error->ring[i].instdone; 821 } 822 } 823 824 return error_code; 825} 826 827static void i915_gem_record_fences(struct drm_device *dev, 828 struct drm_i915_error_state *error) 829{ 830 struct drm_i915_private *dev_priv = dev->dev_private; 831 int i; 832 833 if (IS_GEN3(dev) || IS_GEN2(dev)) { 834 for (i = 0; i < dev_priv->num_fence_regs; i++) 835 error->fence[i] = I915_READ(FENCE_REG(i)); 836 } else if (IS_GEN5(dev) || IS_GEN4(dev)) { 837 for (i = 0; i < dev_priv->num_fence_regs; i++) 838 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 839 } else if (INTEL_INFO(dev)->gen >= 6) { 840 for (i = 0; i < dev_priv->num_fence_regs; i++) 841 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 842 } 843} 844 845 846static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 847 struct drm_i915_error_state *error, 848 struct intel_engine_cs *ring, 849 struct drm_i915_error_ring *ering) 850{ 851 struct intel_engine_cs *to; 852 int i; 853 854 if (!i915_semaphore_is_enabled(dev_priv->dev)) 855 return; 856 857 if (!error->semaphore_obj) 858 error->semaphore_obj = 859 i915_error_ggtt_object_create(dev_priv, 860 dev_priv->semaphore_obj); 861 862 for_each_ring(to, dev_priv, i) { 863 int idx; 864 u16 signal_offset; 865 u32 *tmp; 866 867 if (ring == to) 868 continue; 869 870 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 871 / 4; 872 tmp = error->semaphore_obj->pages[0]; 873 idx = intel_ring_sync_index(ring, to); 874 875 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 876 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 877 } 878} 879 880static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 881 struct intel_engine_cs *ring, 882 struct drm_i915_error_ring *ering) 883{ 884 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 885 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 886 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 887 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 888 889 if (HAS_VEBOX(dev_priv->dev)) { 890 ering->semaphore_mboxes[2] = 891 I915_READ(RING_SYNC_2(ring->mmio_base)); 892 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 893 } 894} 895 896static void i915_record_ring_state(struct drm_device *dev, 897 struct drm_i915_error_state *error, 898 struct intel_engine_cs *ring, 899 struct drm_i915_error_ring *ering) 900{ 901 struct drm_i915_private *dev_priv = dev->dev_private; 902 903 if (INTEL_INFO(dev)->gen >= 6) { 904 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 905 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 906 if (INTEL_INFO(dev)->gen >= 8) 907 gen8_record_semaphore_state(dev_priv, error, ring, ering); 908 else 909 gen6_record_semaphore_state(dev_priv, ring, ering); 910 } 911 912 if (INTEL_INFO(dev)->gen >= 4) { 913 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 914 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 915 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 916 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 917 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 918 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 919 if (INTEL_INFO(dev)->gen >= 8) { 920 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 921 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 922 } 923 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 924 } else { 925 ering->faddr = I915_READ(DMA_FADD_I8XX); 926 ering->ipeir = I915_READ(IPEIR); 927 ering->ipehr = I915_READ(IPEHR); 928 ering->instdone = I915_READ(GEN2_INSTDONE); 929 } 930 931#ifdef __NetBSD__ 932 ering->waiting = DRM_SPIN_WAITERS_P(&ring->irq_queue, 933 &dev_priv->irq_lock); 934#else 935 ering->waiting = waitqueue_active(&ring->irq_queue); 936#endif 937 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 938 ering->seqno = ring->get_seqno(ring, false); 939 ering->acthd = intel_ring_get_active_head(ring); 940 ering->start = I915_READ_START(ring); 941 ering->head = I915_READ_HEAD(ring); 942 ering->tail = I915_READ_TAIL(ring); 943 ering->ctl = I915_READ_CTL(ring); 944 945 if (I915_NEED_GFX_HWS(dev)) { 946 int mmio; 947 948 if (IS_GEN7(dev)) { 949 switch (ring->id) { 950 default: 951 case RCS: 952 mmio = RENDER_HWS_PGA_GEN7; 953 break; 954 case BCS: 955 mmio = BLT_HWS_PGA_GEN7; 956 break; 957 case VCS: 958 mmio = BSD_HWS_PGA_GEN7; 959 break; 960 case VECS: 961 mmio = VEBOX_HWS_PGA_GEN7; 962 break; 963 } 964 } else if (IS_GEN6(ring->dev)) { 965 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 966 } else { 967 /* XXX: gen8 returns to sanity */ 968 mmio = RING_HWS_PGA(ring->mmio_base); 969 } 970 971 ering->hws = I915_READ(mmio); 972 } 973 974 ering->hangcheck_score = ring->hangcheck.score; 975 ering->hangcheck_action = ring->hangcheck.action; 976 977 if (USES_PPGTT(dev)) { 978 int i; 979 980 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 981 982 if (IS_GEN6(dev)) 983 ering->vm_info.pp_dir_base = 984 I915_READ(RING_PP_DIR_BASE_READ(ring)); 985 else if (IS_GEN7(dev)) 986 ering->vm_info.pp_dir_base = 987 I915_READ(RING_PP_DIR_BASE(ring)); 988 else if (INTEL_INFO(dev)->gen >= 8) 989 for (i = 0; i < 4; i++) { 990 ering->vm_info.pdp[i] = 991 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 992 ering->vm_info.pdp[i] <<= 32; 993 ering->vm_info.pdp[i] |= 994 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 995 } 996 } 997} 998 999 1000static void i915_gem_record_active_context(struct intel_engine_cs *ring, 1001 struct drm_i915_error_state *error, 1002 struct drm_i915_error_ring *ering) 1003{ 1004 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1005 struct drm_i915_gem_object *obj; 1006 1007 /* Currently render ring is the only HW context user */ 1008 if (ring->id != RCS || !error->ccid) 1009 return; 1010 1011 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1012 if (!i915_gem_obj_ggtt_bound(obj)) 1013 continue; 1014 1015 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 1016 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 1017 break; 1018 } 1019 } 1020} 1021 1022static void i915_gem_record_rings(struct drm_device *dev, 1023 struct drm_i915_error_state *error) 1024{ 1025 struct drm_i915_private *dev_priv = dev->dev_private; 1026 struct drm_i915_gem_request *request; 1027 int i, count; 1028 1029 for (i = 0; i < I915_NUM_RINGS; i++) { 1030 struct intel_engine_cs *ring = &dev_priv->ring[i]; 1031 struct intel_ringbuffer *rbuf; 1032 1033 error->ring[i].pid = -1; 1034 1035 if (ring->dev == NULL) 1036 continue; 1037 1038 error->ring[i].valid = true; 1039 1040 i915_record_ring_state(dev, error, ring, &error->ring[i]); 1041 1042 request = i915_gem_find_active_request(ring); 1043 if (request) { 1044 struct i915_address_space *vm; 1045 1046 vm = request->ctx && request->ctx->ppgtt ? 1047 &request->ctx->ppgtt->base : 1048 &dev_priv->gtt.base; 1049 1050 /* We need to copy these to an anonymous buffer 1051 * as the simplest method to avoid being overwritten 1052 * by userspace. 1053 */ 1054 error->ring[i].batchbuffer = 1055 i915_error_object_create(dev_priv, 1056 request->batch_obj, 1057 vm); 1058 1059 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) 1060 error->ring[i].wa_batchbuffer = 1061 i915_error_ggtt_object_create(dev_priv, 1062 ring->scratch.obj); 1063 1064#ifndef __NetBSD__ /* XXX not a clue */ 1065 if (request->pid) { 1066 struct task_struct *task; 1067 1068 rcu_read_lock(); 1069 task = pid_task(request->pid, PIDTYPE_PID); 1070 if (task) { 1071 strcpy(error->ring[i].comm, task->comm); 1072 error->ring[i].pid = task->pid; 1073 } 1074 rcu_read_unlock(); 1075 } 1076#endif 1077 } 1078 1079 if (i915.enable_execlists) { 1080 /* TODO: This is only a small fix to keep basic error 1081 * capture working, but we need to add more information 1082 * for it to be useful (e.g. dump the context being 1083 * executed). 1084 */ 1085 if (request) 1086 rbuf = request->ctx->engine[ring->id].ringbuf; 1087 else 1088 rbuf = ring->default_context->engine[ring->id].ringbuf; 1089 } else 1090 rbuf = ring->buffer; 1091 1092 error->ring[i].cpu_ring_head = rbuf->head; 1093 error->ring[i].cpu_ring_tail = rbuf->tail; 1094 1095 error->ring[i].ringbuffer = 1096 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1097 1098 error->ring[i].hws_page = 1099 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1100 1101 i915_gem_record_active_context(ring, error, &error->ring[i]); 1102 1103 count = 0; 1104 list_for_each_entry(request, &ring->request_list, list) 1105 count++; 1106 1107 error->ring[i].num_requests = count; 1108 error->ring[i].requests = 1109 kcalloc(count, sizeof(*error->ring[i].requests), 1110 GFP_ATOMIC); 1111 if (error->ring[i].requests == NULL) { 1112 error->ring[i].num_requests = 0; 1113 continue; 1114 } 1115 1116 count = 0; 1117 list_for_each_entry(request, &ring->request_list, list) { 1118 struct drm_i915_error_request *erq; 1119 1120 erq = &error->ring[i].requests[count++]; 1121 erq->seqno = request->seqno; 1122 erq->jiffies = request->emitted_jiffies; 1123 erq->tail = request->postfix; 1124 } 1125 } 1126} 1127 1128/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1129 * VM. 1130 */ 1131static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1132 struct drm_i915_error_state *error, 1133 struct i915_address_space *vm, 1134 const int ndx) 1135{ 1136 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1137 struct drm_i915_gem_object *obj; 1138 struct i915_vma *vma; 1139 int i; 1140 1141 i = 0; 1142 list_for_each_entry(vma, &vm->active_list, mm_list) 1143 i++; 1144 error->active_bo_count[ndx] = i; 1145 1146 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1147 list_for_each_entry(vma, &obj->vma_list, vma_link) 1148 if (vma->vm == vm && vma->pin_count > 0) 1149 i++; 1150 } 1151 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1152 1153 if (i) { 1154 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1155 if (active_bo) 1156 pinned_bo = active_bo + error->active_bo_count[ndx]; 1157 } 1158 1159 if (active_bo) 1160 error->active_bo_count[ndx] = 1161 capture_active_bo(active_bo, 1162 error->active_bo_count[ndx], 1163 &vm->active_list); 1164 1165 if (pinned_bo) 1166 error->pinned_bo_count[ndx] = 1167 capture_pinned_bo(pinned_bo, 1168 error->pinned_bo_count[ndx], 1169 &dev_priv->mm.bound_list, vm); 1170 error->active_bo[ndx] = active_bo; 1171 error->pinned_bo[ndx] = pinned_bo; 1172} 1173 1174static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1175 struct drm_i915_error_state *error) 1176{ 1177 struct i915_address_space *vm; 1178 int cnt = 0, i = 0; 1179 1180 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1181 cnt++; 1182 1183 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1184 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1185 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1186 GFP_ATOMIC); 1187 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1188 GFP_ATOMIC); 1189 1190 if (error->active_bo == NULL || 1191 error->pinned_bo == NULL || 1192 error->active_bo_count == NULL || 1193 error->pinned_bo_count == NULL) { 1194 kfree(error->active_bo); 1195 kfree(error->active_bo_count); 1196 kfree(error->pinned_bo); 1197 kfree(error->pinned_bo_count); 1198 1199 error->active_bo = NULL; 1200 error->active_bo_count = NULL; 1201 error->pinned_bo = NULL; 1202 error->pinned_bo_count = NULL; 1203 } else { 1204 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1205 i915_gem_capture_vm(dev_priv, error, vm, i++); 1206 1207 error->vm_count = cnt; 1208 } 1209} 1210 1211/* Capture all registers which don't fit into another category. */ 1212static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1213 struct drm_i915_error_state *error) 1214{ 1215 struct drm_device *dev = dev_priv->dev; 1216 int i; 1217 1218 /* General organization 1219 * 1. Registers specific to a single generation 1220 * 2. Registers which belong to multiple generations 1221 * 3. Feature specific registers. 1222 * 4. Everything else 1223 * Please try to follow the order. 1224 */ 1225 1226 /* 1: Registers specific to a single generation */ 1227 if (IS_VALLEYVIEW(dev)) { 1228 error->gtier[0] = I915_READ(GTIER); 1229 error->ier = I915_READ(VLV_IER); 1230 error->forcewake = I915_READ(FORCEWAKE_VLV); 1231 } 1232 1233 if (IS_GEN7(dev)) 1234 error->err_int = I915_READ(GEN7_ERR_INT); 1235 1236 if (INTEL_INFO(dev)->gen >= 8) { 1237 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1238 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1239 } 1240 1241 if (IS_GEN6(dev)) { 1242 error->forcewake = I915_READ(FORCEWAKE); 1243 error->gab_ctl = I915_READ(GAB_CTL); 1244 error->gfx_mode = I915_READ(GFX_MODE); 1245 } 1246 1247 /* 2: Registers which belong to multiple generations */ 1248 if (INTEL_INFO(dev)->gen >= 7) 1249 error->forcewake = I915_READ(FORCEWAKE_MT); 1250 1251 if (INTEL_INFO(dev)->gen >= 6) { 1252 error->derrmr = I915_READ(DERRMR); 1253 error->error = I915_READ(ERROR_GEN6); 1254 error->done_reg = I915_READ(DONE_REG); 1255 } 1256 1257 /* 3: Feature specific registers */ 1258 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1259 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1260 error->gac_eco = I915_READ(GAC_ECO_BITS); 1261 } 1262 1263 /* 4: Everything else */ 1264 if (HAS_HW_CONTEXTS(dev)) 1265 error->ccid = I915_READ(CCID); 1266 1267 if (INTEL_INFO(dev)->gen >= 8) { 1268 error->ier = I915_READ(GEN8_DE_MISC_IER); 1269 for (i = 0; i < 4; i++) 1270 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1271 } else if (HAS_PCH_SPLIT(dev)) { 1272 error->ier = I915_READ(DEIER); 1273 error->gtier[0] = I915_READ(GTIER); 1274 } else if (IS_GEN2(dev)) { 1275 error->ier = I915_READ16(IER); 1276 } else if (!IS_VALLEYVIEW(dev)) { 1277 error->ier = I915_READ(IER); 1278 } 1279 error->eir = I915_READ(EIR); 1280 error->pgtbl_er = I915_READ(PGTBL_ER); 1281 1282 i915_get_extra_instdone(dev, error->extra_instdone); 1283} 1284 1285static void i915_error_capture_msg(struct drm_device *dev, 1286 struct drm_i915_error_state *error, 1287 bool wedged, 1288 const char *error_msg) 1289{ 1290 struct drm_i915_private *dev_priv = dev->dev_private; 1291 u32 ecode; 1292 int ring_id = -1, len; 1293 1294 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1295 1296 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1297 "GPU HANG: ecode %d:%d:0x%08x", 1298 INTEL_INFO(dev)->gen, ring_id, ecode); 1299 1300 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1301 len += scnprintf(error->error_msg + len, 1302 sizeof(error->error_msg) - len, 1303 ", in %s [%d]", 1304 error->ring[ring_id].comm, 1305 error->ring[ring_id].pid); 1306 1307 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1308 ", reason: %s, action: %s", 1309 error_msg, 1310 wedged ? "reset" : "continue"); 1311} 1312 1313static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1314 struct drm_i915_error_state *error) 1315{ 1316 error->iommu = -1; 1317#ifdef CONFIG_INTEL_IOMMU 1318 error->iommu = intel_iommu_gfx_mapped; 1319#endif 1320 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1321 error->suspend_count = dev_priv->suspend_count; 1322} 1323 1324/** 1325 * i915_capture_error_state - capture an error record for later analysis 1326 * @dev: drm device 1327 * 1328 * Should be called when an error is detected (either a hang or an error 1329 * interrupt) to capture error state from the time of the error. Fills 1330 * out a structure which becomes available in debugfs for user level tools 1331 * to pick up. 1332 */ 1333void i915_capture_error_state(struct drm_device *dev, bool wedged, 1334 const char *error_msg) 1335{ 1336 static bool warned; 1337 struct drm_i915_private *dev_priv = dev->dev_private; 1338 struct drm_i915_error_state *error; 1339 unsigned long flags; 1340 1341 /* Account for pipe specific data like PIPE*STAT */ 1342 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1343 if (!error) { 1344 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1345 return; 1346 } 1347 1348 kref_init(&error->ref); 1349 1350 i915_capture_gen_state(dev_priv, error); 1351 i915_capture_reg_state(dev_priv, error); 1352 i915_gem_capture_buffers(dev_priv, error); 1353 i915_gem_record_fences(dev, error); 1354 i915_gem_record_rings(dev, error); 1355 1356 do_gettimeofday(&error->time); 1357 1358 error->overlay = intel_overlay_capture_error_state(dev); 1359 error->display = intel_display_capture_error_state(dev); 1360 1361 i915_error_capture_msg(dev, error, wedged, error_msg); 1362 DRM_INFO("%s\n", error->error_msg); 1363 1364 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1365 if (dev_priv->gpu_error.first_error == NULL) { 1366 dev_priv->gpu_error.first_error = error; 1367 error = NULL; 1368 } 1369 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1370 1371 if (error) { 1372 i915_error_state_free(&error->ref); 1373 return; 1374 } 1375 1376 if (!warned) { 1377 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1378 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1379 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1380 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1381 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1382 warned = true; 1383 } 1384} 1385 1386void i915_error_state_get(struct drm_device *dev, 1387 struct i915_error_state_file_priv *error_priv) 1388{ 1389 struct drm_i915_private *dev_priv = dev->dev_private; 1390 1391 spin_lock_irq(&dev_priv->gpu_error.lock); 1392 error_priv->error = dev_priv->gpu_error.first_error; 1393 if (error_priv->error) 1394 kref_get(&error_priv->error->ref); 1395 spin_unlock_irq(&dev_priv->gpu_error.lock); 1396 1397} 1398 1399void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1400{ 1401 if (error_priv->error) 1402 kref_put(&error_priv->error->ref, i915_error_state_free); 1403} 1404 1405void i915_destroy_error_state(struct drm_device *dev) 1406{ 1407 struct drm_i915_private *dev_priv = dev->dev_private; 1408 struct drm_i915_error_state *error; 1409 1410 spin_lock_irq(&dev_priv->gpu_error.lock); 1411 error = dev_priv->gpu_error.first_error; 1412 dev_priv->gpu_error.first_error = NULL; 1413 spin_unlock_irq(&dev_priv->gpu_error.lock); 1414 1415 if (error) 1416 kref_put(&error->ref, i915_error_state_free); 1417} 1418 1419const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1420{ 1421 switch (type) { 1422 case I915_CACHE_NONE: return " uncached"; 1423 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1424 case I915_CACHE_L3_LLC: return " L3+LLC"; 1425 case I915_CACHE_WT: return " WT"; 1426 default: return ""; 1427 } 1428} 1429 1430/* NB: please notice the memset */ 1431void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1432{ 1433 struct drm_i915_private *dev_priv = dev->dev_private; 1434 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1435 1436 if (IS_GEN2(dev) || IS_GEN3(dev)) 1437 instdone[0] = I915_READ(GEN2_INSTDONE); 1438 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1439 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1440 instdone[1] = I915_READ(GEN4_INSTDONE1); 1441 } else if (INTEL_INFO(dev)->gen >= 7) { 1442 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1443 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1444 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1445 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1446 } 1447} 1448