i915_gpu_error.c revision 1.5
1/* $NetBSD: i915_gpu_error.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $ */ 2 3/* 4 * Copyright (c) 2008 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Keith Packard <keithp@keithp.com> 28 * Mika Kuoppala <mika.kuoppala@intel.com> 29 * 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: i915_gpu_error.c,v 1.5 2018/08/27 04:58:23 riastradh Exp $"); 34 35#include <generated/utsrelease.h> 36#include <asm/io.h> 37#include <linux/irqflags.h> 38#include "i915_drv.h" 39 40static const char *ring_str(int ring) 41{ 42 switch (ring) { 43 case RCS: return "render"; 44 case VCS: return "bsd"; 45 case BCS: return "blt"; 46 case VECS: return "vebox"; 47 case VCS2: return "bsd2"; 48 default: return ""; 49 } 50} 51 52static const char *pin_flag(int pinned) 53{ 54 if (pinned > 0) 55 return " P"; 56 else if (pinned < 0) 57 return " p"; 58 else 59 return ""; 60} 61 62static const char *tiling_flag(int tiling) 63{ 64 switch (tiling) { 65 default: 66 case I915_TILING_NONE: return ""; 67 case I915_TILING_X: return " X"; 68 case I915_TILING_Y: return " Y"; 69 } 70} 71 72static const char *dirty_flag(int dirty) 73{ 74 return dirty ? " dirty" : ""; 75} 76 77static const char *purgeable_flag(int purgeable) 78{ 79 return purgeable ? " purgeable" : ""; 80} 81 82static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 83{ 84 85 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 86 e->err = -ENOSPC; 87 return false; 88 } 89 90 if (e->bytes == e->size - 1 || e->err) 91 return false; 92 93 return true; 94} 95 96static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 97 unsigned len) 98{ 99 if (e->pos + len <= e->start) { 100 e->pos += len; 101 return false; 102 } 103 104 /* First vsnprintf needs to fit in its entirety for memmove */ 105 if (len >= e->size) { 106 e->err = -EIO; 107 return false; 108 } 109 110 return true; 111} 112 113static void __i915_error_advance(struct drm_i915_error_state_buf *e, 114 unsigned len) 115{ 116 /* If this is first printf in this window, adjust it so that 117 * start position matches start of the buffer 118 */ 119 120 if (e->pos < e->start) { 121 const size_t off = e->start - e->pos; 122 123 /* Should not happen but be paranoid */ 124 if (off > len || e->bytes) { 125 e->err = -EIO; 126 return; 127 } 128 129 memmove(e->buf, e->buf + off, len - off); 130 e->bytes = len - off; 131 e->pos = e->start; 132 return; 133 } 134 135 e->bytes += len; 136 e->pos += len; 137} 138 139static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 140 const char *f, va_list args) 141{ 142 unsigned len; 143 144 if (!__i915_error_ok(e)) 145 return; 146 147 /* Seek the first printf which is hits start position */ 148 if (e->pos < e->start) { 149 va_list tmp; 150 151 va_copy(tmp, args); 152 len = vsnprintf(NULL, 0, f, tmp); 153 va_end(tmp); 154 155 if (!__i915_error_seek(e, len)) 156 return; 157 } 158 159 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 160 if (len >= e->size - e->bytes) 161 len = e->size - e->bytes - 1; 162 163 __i915_error_advance(e, len); 164} 165 166static void i915_error_puts(struct drm_i915_error_state_buf *e, 167 const char *str) 168{ 169 unsigned len; 170 171 if (!__i915_error_ok(e)) 172 return; 173 174 len = strlen(str); 175 176 /* Seek the first printf which is hits start position */ 177 if (e->pos < e->start) { 178 if (!__i915_error_seek(e, len)) 179 return; 180 } 181 182 if (len >= e->size - e->bytes) 183 len = e->size - e->bytes - 1; 184 memcpy(e->buf + e->bytes, str, len); 185 186 __i915_error_advance(e, len); 187} 188 189#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 190#define err_puts(e, s) i915_error_puts(e, s) 191 192static void print_error_buffers(struct drm_i915_error_state_buf *m, 193 const char *name, 194 struct drm_i915_error_buffer *err, 195 int count) 196{ 197 int i; 198 199 err_printf(m, " %s [%d]:\n", name, count); 200 201 while (count--) { 202 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 203 upper_32_bits(err->gtt_offset), 204 lower_32_bits(err->gtt_offset), 205 err->size, 206 err->read_domains, 207 err->write_domain); 208 for (i = 0; i < I915_NUM_RINGS; i++) 209 err_printf(m, "%02x ", err->rseqno[i]); 210 211 err_printf(m, "] %02x", err->wseqno); 212 err_puts(m, pin_flag(err->pinned)); 213 err_puts(m, tiling_flag(err->tiling)); 214 err_puts(m, dirty_flag(err->dirty)); 215 err_puts(m, purgeable_flag(err->purgeable)); 216 err_puts(m, err->userptr ? " userptr" : ""); 217 err_puts(m, err->ring != -1 ? " " : ""); 218 err_puts(m, ring_str(err->ring)); 219 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 220 221 if (err->name) 222 err_printf(m, " (name: %d)", err->name); 223 if (err->fence_reg != I915_FENCE_REG_NONE) 224 err_printf(m, " (fence: %d)", err->fence_reg); 225 226 err_puts(m, "\n"); 227 err++; 228 } 229} 230 231static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 232{ 233 switch (a) { 234 case HANGCHECK_IDLE: 235 return "idle"; 236 case HANGCHECK_WAIT: 237 return "wait"; 238 case HANGCHECK_ACTIVE: 239 return "active"; 240 case HANGCHECK_ACTIVE_LOOP: 241 return "active (loop)"; 242 case HANGCHECK_KICK: 243 return "kick"; 244 case HANGCHECK_HUNG: 245 return "hung"; 246 } 247 248 return "unknown"; 249} 250 251static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 252 struct drm_device *dev, 253 struct drm_i915_error_state *error, 254 int ring_idx) 255{ 256 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 257 258 if (!ring->valid) 259 return; 260 261 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 262 err_printf(m, " START: 0x%08x\n", ring->start); 263 err_printf(m, " HEAD: 0x%08x\n", ring->head); 264 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 265 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 266 err_printf(m, " HWS: 0x%08x\n", ring->hws); 267 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 268 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 269 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 270 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 271 if (INTEL_INFO(dev)->gen >= 4) { 272 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 273 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 274 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 275 } 276 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 277 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 278 lower_32_bits(ring->faddr)); 279 if (INTEL_INFO(dev)->gen >= 6) { 280 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 281 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 282 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 283 ring->semaphore_mboxes[0], 284 ring->semaphore_seqno[0]); 285 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 286 ring->semaphore_mboxes[1], 287 ring->semaphore_seqno[1]); 288 if (HAS_VEBOX(dev)) { 289 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 290 ring->semaphore_mboxes[2], 291 ring->semaphore_seqno[2]); 292 } 293 } 294 if (USES_PPGTT(dev)) { 295 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 296 297 if (INTEL_INFO(dev)->gen >= 8) { 298 int i; 299 for (i = 0; i < 4; i++) 300 err_printf(m, " PDP%d: 0x%016"PRIx64"\n", 301 i, ring->vm_info.pdp[i]); 302 } else { 303 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 304 ring->vm_info.pp_dir_base); 305 } 306 } 307 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 308 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 309 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 310 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 311 err_printf(m, " hangcheck: %s [%d]\n", 312 hangcheck_action_to_str(ring->hangcheck_action), 313 ring->hangcheck_score); 314} 315 316void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 317{ 318 va_list args; 319 320 va_start(args, f); 321 i915_error_vprintf(e, f, args); 322 va_end(args); 323} 324 325static void print_error_obj(struct drm_i915_error_state_buf *m, 326 struct drm_i915_error_object *obj) 327{ 328 int page, offset, elt; 329 330 for (page = offset = 0; page < obj->page_count; page++) { 331 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 332 err_printf(m, "%08x : %08x\n", offset, 333 obj->pages[page][elt]); 334 offset += 4; 335 } 336 } 337} 338 339int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 340 const struct i915_error_state_file_priv *error_priv) 341{ 342 struct drm_device *dev = error_priv->dev; 343 struct drm_i915_private *dev_priv = dev->dev_private; 344 struct drm_i915_error_state *error = error_priv->error; 345 struct drm_i915_error_object *obj; 346 int i, j, offset, elt; 347 int max_hangcheck_score; 348 349 if (!error) { 350 err_printf(m, "no error state collected\n"); 351 goto out; 352 } 353 354 err_printf(m, "%s\n", error->error_msg); 355 err_printf(m, "Time: %"PRIdMAX" s %ld us\n", (intmax_t)error->time.tv_sec, 356 (long)error->time.tv_usec); 357#ifndef __NetBSD__ /* XXX kernel version */ 358 err_printf(m, "Kernel: " UTS_RELEASE "\n"); 359#endif 360 max_hangcheck_score = 0; 361 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 362 if (error->ring[i].hangcheck_score > max_hangcheck_score) 363 max_hangcheck_score = error->ring[i].hangcheck_score; 364 } 365 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 366 if (error->ring[i].hangcheck_score == max_hangcheck_score && 367 error->ring[i].pid != -1) { 368 err_printf(m, "Active process (on ring %s): %s [%d]\n", 369 ring_str(i), 370 error->ring[i].comm, 371 error->ring[i].pid); 372 } 373 } 374 err_printf(m, "Reset count: %u\n", error->reset_count); 375 err_printf(m, "Suspend count: %u\n", error->suspend_count); 376 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 377 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 378 err_printf(m, "EIR: 0x%08x\n", error->eir); 379 err_printf(m, "IER: 0x%08x\n", error->ier); 380 if (INTEL_INFO(dev)->gen >= 8) { 381 for (i = 0; i < 4; i++) 382 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 383 error->gtier[i]); 384 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 385 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 386 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 387 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 388 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 389 err_printf(m, "CCID: 0x%08x\n", error->ccid); 390 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 391 392 for (i = 0; i < dev_priv->num_fence_regs; i++) 393 err_printf(m, " fence[%d] = %08"PRIx64"\n", i, error->fence[i]); 394 395 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 396 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 397 error->extra_instdone[i]); 398 399 if (INTEL_INFO(dev)->gen >= 6) { 400 err_printf(m, "ERROR: 0x%08x\n", error->error); 401 402 if (INTEL_INFO(dev)->gen >= 8) 403 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 404 error->fault_data1, error->fault_data0); 405 406 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 407 } 408 409 if (INTEL_INFO(dev)->gen == 7) 410 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 411 412 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 413 i915_ring_error_state(m, dev, error, i); 414 415 for (i = 0; i < error->vm_count; i++) { 416 err_printf(m, "vm[%d]\n", i); 417 418 print_error_buffers(m, "Active", 419 error->active_bo[i], 420 error->active_bo_count[i]); 421 422 print_error_buffers(m, "Pinned", 423 error->pinned_bo[i], 424 error->pinned_bo_count[i]); 425 } 426 427 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 428 obj = error->ring[i].batchbuffer; 429 if (obj) { 430 err_puts(m, dev_priv->ring[i].name); 431 if (error->ring[i].pid != -1) 432 err_printf(m, " (submitted by %s [%d])", 433 error->ring[i].comm, 434 error->ring[i].pid); 435 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 436 upper_32_bits(obj->gtt_offset), 437 lower_32_bits(obj->gtt_offset)); 438 print_error_obj(m, obj); 439 } 440 441 obj = error->ring[i].wa_batchbuffer; 442 if (obj) { 443 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 444 dev_priv->ring[i].name, 445 lower_32_bits(obj->gtt_offset)); 446 print_error_obj(m, obj); 447 } 448 449 if (error->ring[i].num_requests) { 450 err_printf(m, "%s --- %d requests\n", 451 dev_priv->ring[i].name, 452 error->ring[i].num_requests); 453 for (j = 0; j < error->ring[i].num_requests; j++) { 454 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 455 error->ring[i].requests[j].seqno, 456 error->ring[i].requests[j].jiffies, 457 error->ring[i].requests[j].tail); 458 } 459 } 460 461 if ((obj = error->ring[i].ringbuffer)) { 462 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 463 dev_priv->ring[i].name, 464 lower_32_bits(obj->gtt_offset)); 465 print_error_obj(m, obj); 466 } 467 468 if ((obj = error->ring[i].hws_page)) { 469 u64 hws_offset = obj->gtt_offset; 470 u32 *hws_page = &obj->pages[0][0]; 471 472 if (i915.enable_execlists) { 473 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 474 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 475 } 476 err_printf(m, "%s --- HW Status = 0x%08llx\n", 477 dev_priv->ring[i].name, hws_offset); 478 offset = 0; 479 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 480 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 481 offset, 482 hws_page[elt], 483 hws_page[elt+1], 484 hws_page[elt+2], 485 hws_page[elt+3]); 486 offset += 16; 487 } 488 } 489 490 if ((obj = error->ring[i].ctx)) { 491 err_printf(m, "%s --- HW Context = 0x%08x\n", 492 dev_priv->ring[i].name, 493 lower_32_bits(obj->gtt_offset)); 494 print_error_obj(m, obj); 495 } 496 } 497 498 if ((obj = error->semaphore_obj)) { 499 err_printf(m, "Semaphore page = 0x%08x\n", 500 lower_32_bits(obj->gtt_offset)); 501 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 502 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 503 elt * 4, 504 obj->pages[0][elt], 505 obj->pages[0][elt+1], 506 obj->pages[0][elt+2], 507 obj->pages[0][elt+3]); 508 } 509 } 510 511 if (error->overlay) 512 intel_overlay_print_error_state(m, error->overlay); 513 514 if (error->display) 515 intel_display_print_error_state(m, dev, error->display); 516 517out: 518 if (m->bytes == 0 && m->err) 519 return m->err; 520 521 return 0; 522} 523 524int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 525 struct drm_i915_private *i915, 526 size_t count, loff_t pos) 527{ 528 memset(ebuf, 0, sizeof(*ebuf)); 529 ebuf->i915 = i915; 530 531 /* We need to have enough room to store any i915_error_state printf 532 * so that we can move it to start position. 533 */ 534 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 535 ebuf->buf = kmalloc(ebuf->size, 536 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 537 538 if (ebuf->buf == NULL) { 539 ebuf->size = PAGE_SIZE; 540 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 541 } 542 543 if (ebuf->buf == NULL) { 544 ebuf->size = 128; 545 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 546 } 547 548 if (ebuf->buf == NULL) 549 return -ENOMEM; 550 551 ebuf->start = pos; 552 553 return 0; 554} 555 556static void i915_error_object_free(struct drm_i915_error_object *obj) 557{ 558 int page; 559 560 if (obj == NULL) 561 return; 562 563 for (page = 0; page < obj->page_count; page++) 564 kfree(obj->pages[page]); 565 566 kfree(obj); 567} 568 569static void i915_error_state_free(struct kref *error_ref) 570{ 571 struct drm_i915_error_state *error = container_of(error_ref, 572 typeof(*error), ref); 573 int i; 574 575 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 576 i915_error_object_free(error->ring[i].batchbuffer); 577 i915_error_object_free(error->ring[i].wa_batchbuffer); 578 i915_error_object_free(error->ring[i].ringbuffer); 579 i915_error_object_free(error->ring[i].hws_page); 580 i915_error_object_free(error->ring[i].ctx); 581 kfree(error->ring[i].requests); 582 } 583 584 i915_error_object_free(error->semaphore_obj); 585 586 for (i = 0; i < error->vm_count; i++) 587 kfree(error->active_bo[i]); 588 589 kfree(error->active_bo); 590 kfree(error->active_bo_count); 591 kfree(error->pinned_bo); 592 kfree(error->pinned_bo_count); 593 kfree(error->overlay); 594 kfree(error->display); 595 kfree(error); 596} 597 598#ifdef __NetBSD__ 599# define __aperture_iomem 600# define __iomem __aperture_iomem 601#endif 602 603static struct drm_i915_error_object * 604i915_error_object_create(struct drm_i915_private *dev_priv, 605 struct drm_i915_gem_object *src, 606 struct i915_address_space *vm) 607{ 608 struct drm_i915_error_object *dst; 609 struct i915_vma *vma = NULL; 610 int num_pages; 611 bool use_ggtt; 612 int i = 0; 613 u64 reloc_offset; 614 615 if (src == NULL || src->pages == NULL) 616 return NULL; 617 618 num_pages = src->base.size >> PAGE_SHIFT; 619 620 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 621 if (dst == NULL) 622 return NULL; 623 624 if (i915_gem_obj_bound(src, vm)) 625 dst->gtt_offset = i915_gem_obj_offset(src, vm); 626 else 627 dst->gtt_offset = -1; 628 629 reloc_offset = dst->gtt_offset; 630 if (i915_is_ggtt(vm)) 631 vma = i915_gem_obj_to_ggtt(src); 632 use_ggtt = (src->cache_level == I915_CACHE_NONE && 633 vma && (vma->bound & GLOBAL_BIND) && 634 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); 635 636 /* Cannot access stolen address directly, try to use the aperture */ 637 if (src->stolen) { 638 use_ggtt = true; 639 640 if (!(vma && vma->bound & GLOBAL_BIND)) 641 goto unwind; 642 643 reloc_offset = i915_gem_obj_ggtt_offset(src); 644 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) 645 goto unwind; 646 } 647 648 /* Cannot access snooped pages through the aperture */ 649 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) 650 goto unwind; 651 652 dst->page_count = num_pages; 653 while (num_pages--) { 654 unsigned long flags; 655 void *d; 656 657 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 658 if (d == NULL) 659 goto unwind; 660 661 local_irq_save(flags); 662 if (use_ggtt) { 663 void __iomem *s; 664 665 /* Simply ignore tiling or any overlapping fence. 666 * It's part of the error state, and this hopefully 667 * captures what the GPU read. 668 */ 669 670 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 671 reloc_offset); 672 memcpy_fromio(d, s, PAGE_SIZE); 673#ifdef __NetBSD__ 674 io_mapping_unmap_atomic(dev_priv->gtt.mappable, s); 675#else 676 io_mapping_unmap_atomic(s); 677#endif 678 } else { 679 680 if (cpu_intr_p() || cpu_softintr_p() || 681 (curlwp->l_pflag & LP_INTR) != 0) { 682 /* 683 * We can't take locks during interrupts 684 * and finding the page from uvm requires 685 * taking a lock. Checking for an interrupt 686 * context is bogus, but this is the least 687 * intrusive change. Zero the result, doesn't 688 * matter much, because this is only used 689 * for diagnostics. 690 */ 691 memset(d, 0, PAGE_SIZE); 692 } else { 693 struct page *page; 694 void *s; 695 696 page = i915_gem_object_get_page(src, i); 697 698 drm_clflush_pages(&page, 1); 699 700 s = kmap_atomic(page); 701 memcpy(d, s, PAGE_SIZE); 702 kunmap_atomic(s); 703 704 drm_clflush_pages(&page, 1); 705 } 706 } 707 local_irq_restore(flags); 708 709 dst->pages[i++] = d; 710 reloc_offset += PAGE_SIZE; 711 } 712 713 return dst; 714 715unwind: 716 while (i--) 717 kfree(dst->pages[i]); 718 kfree(dst); 719 return NULL; 720} 721#define i915_error_ggtt_object_create(dev_priv, src) \ 722 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) 723 724#ifdef __NetBSD__ 725# undef __iomem 726# undef __aperture_iomem 727#endif 728 729static void capture_bo(struct drm_i915_error_buffer *err, 730 struct i915_vma *vma) 731{ 732 struct drm_i915_gem_object *obj = vma->obj; 733 int i; 734 735 err->size = obj->base.size; 736 err->name = obj->base.name; 737 for (i = 0; i < I915_NUM_RINGS; i++) 738 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 739 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 740 err->gtt_offset = vma->node.start; 741 err->read_domains = obj->base.read_domains; 742 err->write_domain = obj->base.write_domain; 743 err->fence_reg = obj->fence_reg; 744 err->pinned = 0; 745 if (i915_gem_obj_is_pinned(obj)) 746 err->pinned = 1; 747 err->tiling = obj->tiling_mode; 748 err->dirty = obj->dirty; 749 err->purgeable = obj->madv != I915_MADV_WILLNEED; 750 err->userptr = obj->userptr.mm != NULL; 751 err->ring = obj->last_write_req ? 752 i915_gem_request_get_ring(obj->last_write_req)->id : -1; 753 err->cache_level = obj->cache_level; 754} 755 756static u32 capture_active_bo(struct drm_i915_error_buffer *err, 757 int count, struct list_head *head) 758{ 759 struct i915_vma *vma; 760 int i = 0; 761 762 list_for_each_entry(vma, head, mm_list) { 763 capture_bo(err++, vma); 764 if (++i == count) 765 break; 766 } 767 768 return i; 769} 770 771static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 772 int count, struct list_head *head, 773 struct i915_address_space *vm) 774{ 775 struct drm_i915_gem_object *obj; 776 struct drm_i915_error_buffer * const first = err; 777 struct drm_i915_error_buffer * const last = err + count; 778 779 list_for_each_entry(obj, head, global_list) { 780 struct i915_vma *vma; 781 782 if (err == last) 783 break; 784 785 list_for_each_entry(vma, &obj->vma_list, vma_link) 786 if (vma->vm == vm && vma->pin_count > 0) 787 capture_bo(err++, vma); 788 } 789 790 return err - first; 791} 792 793/* Generate a semi-unique error code. The code is not meant to have meaning, The 794 * code's only purpose is to try to prevent false duplicated bug reports by 795 * grossly estimating a GPU error state. 796 * 797 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 798 * the hang if we could strip the GTT offset information from it. 799 * 800 * It's only a small step better than a random number in its current form. 801 */ 802static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 803 struct drm_i915_error_state *error, 804 int *ring_id) 805{ 806 uint32_t error_code = 0; 807 int i; 808 809 /* IPEHR would be an ideal way to detect errors, as it's the gross 810 * measure of "the command that hung." However, has some very common 811 * synchronization commands which almost always appear in the case 812 * strictly a client bug. Use instdone to differentiate those some. 813 */ 814 for (i = 0; i < I915_NUM_RINGS; i++) { 815 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 816 if (ring_id) 817 *ring_id = i; 818 819 return error->ring[i].ipehr ^ error->ring[i].instdone; 820 } 821 } 822 823 return error_code; 824} 825 826static void i915_gem_record_fences(struct drm_device *dev, 827 struct drm_i915_error_state *error) 828{ 829 struct drm_i915_private *dev_priv = dev->dev_private; 830 int i; 831 832 if (IS_GEN3(dev) || IS_GEN2(dev)) { 833 for (i = 0; i < dev_priv->num_fence_regs; i++) 834 error->fence[i] = I915_READ(FENCE_REG(i)); 835 } else if (IS_GEN5(dev) || IS_GEN4(dev)) { 836 for (i = 0; i < dev_priv->num_fence_regs; i++) 837 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 838 } else if (INTEL_INFO(dev)->gen >= 6) { 839 for (i = 0; i < dev_priv->num_fence_regs; i++) 840 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 841 } 842} 843 844 845static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 846 struct drm_i915_error_state *error, 847 struct intel_engine_cs *ring, 848 struct drm_i915_error_ring *ering) 849{ 850 struct intel_engine_cs *to; 851 int i; 852 853 if (!i915_semaphore_is_enabled(dev_priv->dev)) 854 return; 855 856 if (!error->semaphore_obj) 857 error->semaphore_obj = 858 i915_error_ggtt_object_create(dev_priv, 859 dev_priv->semaphore_obj); 860 861 for_each_ring(to, dev_priv, i) { 862 int idx; 863 u16 signal_offset; 864 u32 *tmp; 865 866 if (ring == to) 867 continue; 868 869 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 870 / 4; 871 tmp = error->semaphore_obj->pages[0]; 872 idx = intel_ring_sync_index(ring, to); 873 874 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 875 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 876 } 877} 878 879static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 880 struct intel_engine_cs *ring, 881 struct drm_i915_error_ring *ering) 882{ 883 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 884 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 885 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 886 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 887 888 if (HAS_VEBOX(dev_priv->dev)) { 889 ering->semaphore_mboxes[2] = 890 I915_READ(RING_SYNC_2(ring->mmio_base)); 891 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 892 } 893} 894 895static void i915_record_ring_state(struct drm_device *dev, 896 struct drm_i915_error_state *error, 897 struct intel_engine_cs *ring, 898 struct drm_i915_error_ring *ering) 899{ 900 struct drm_i915_private *dev_priv = dev->dev_private; 901 902 if (INTEL_INFO(dev)->gen >= 6) { 903 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 904 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 905 if (INTEL_INFO(dev)->gen >= 8) 906 gen8_record_semaphore_state(dev_priv, error, ring, ering); 907 else 908 gen6_record_semaphore_state(dev_priv, ring, ering); 909 } 910 911 if (INTEL_INFO(dev)->gen >= 4) { 912 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 913 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 914 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 915 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 916 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 917 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 918 if (INTEL_INFO(dev)->gen >= 8) { 919 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 920 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 921 } 922 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 923 } else { 924 ering->faddr = I915_READ(DMA_FADD_I8XX); 925 ering->ipeir = I915_READ(IPEIR); 926 ering->ipehr = I915_READ(IPEHR); 927 ering->instdone = I915_READ(GEN2_INSTDONE); 928 } 929 930#ifdef __NetBSD__ 931 ering->waiting = DRM_SPIN_WAITERS_P(&ring->irq_queue, 932 &dev_priv->irq_lock); 933#else 934 ering->waiting = waitqueue_active(&ring->irq_queue); 935#endif 936 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 937 ering->seqno = ring->get_seqno(ring, false); 938 ering->acthd = intel_ring_get_active_head(ring); 939 ering->start = I915_READ_START(ring); 940 ering->head = I915_READ_HEAD(ring); 941 ering->tail = I915_READ_TAIL(ring); 942 ering->ctl = I915_READ_CTL(ring); 943 944 if (I915_NEED_GFX_HWS(dev)) { 945 int mmio; 946 947 if (IS_GEN7(dev)) { 948 switch (ring->id) { 949 default: 950 case RCS: 951 mmio = RENDER_HWS_PGA_GEN7; 952 break; 953 case BCS: 954 mmio = BLT_HWS_PGA_GEN7; 955 break; 956 case VCS: 957 mmio = BSD_HWS_PGA_GEN7; 958 break; 959 case VECS: 960 mmio = VEBOX_HWS_PGA_GEN7; 961 break; 962 } 963 } else if (IS_GEN6(ring->dev)) { 964 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 965 } else { 966 /* XXX: gen8 returns to sanity */ 967 mmio = RING_HWS_PGA(ring->mmio_base); 968 } 969 970 ering->hws = I915_READ(mmio); 971 } 972 973 ering->hangcheck_score = ring->hangcheck.score; 974 ering->hangcheck_action = ring->hangcheck.action; 975 976 if (USES_PPGTT(dev)) { 977 int i; 978 979 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 980 981 if (IS_GEN6(dev)) 982 ering->vm_info.pp_dir_base = 983 I915_READ(RING_PP_DIR_BASE_READ(ring)); 984 else if (IS_GEN7(dev)) 985 ering->vm_info.pp_dir_base = 986 I915_READ(RING_PP_DIR_BASE(ring)); 987 else if (INTEL_INFO(dev)->gen >= 8) 988 for (i = 0; i < 4; i++) { 989 ering->vm_info.pdp[i] = 990 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 991 ering->vm_info.pdp[i] <<= 32; 992 ering->vm_info.pdp[i] |= 993 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 994 } 995 } 996} 997 998 999static void i915_gem_record_active_context(struct intel_engine_cs *ring, 1000 struct drm_i915_error_state *error, 1001 struct drm_i915_error_ring *ering) 1002{ 1003 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1004 struct drm_i915_gem_object *obj; 1005 1006 /* Currently render ring is the only HW context user */ 1007 if (ring->id != RCS || !error->ccid) 1008 return; 1009 1010 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1011 if (!i915_gem_obj_ggtt_bound(obj)) 1012 continue; 1013 1014 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 1015 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 1016 break; 1017 } 1018 } 1019} 1020 1021static void i915_gem_record_rings(struct drm_device *dev, 1022 struct drm_i915_error_state *error) 1023{ 1024 struct drm_i915_private *dev_priv = dev->dev_private; 1025 struct drm_i915_gem_request *request; 1026 int i, count; 1027 1028 for (i = 0; i < I915_NUM_RINGS; i++) { 1029 struct intel_engine_cs *ring = &dev_priv->ring[i]; 1030 struct intel_ringbuffer *rbuf; 1031 1032 error->ring[i].pid = -1; 1033 1034 if (ring->dev == NULL) 1035 continue; 1036 1037 error->ring[i].valid = true; 1038 1039 i915_record_ring_state(dev, error, ring, &error->ring[i]); 1040 1041 request = i915_gem_find_active_request(ring); 1042 if (request) { 1043 struct i915_address_space *vm; 1044 1045 vm = request->ctx && request->ctx->ppgtt ? 1046 &request->ctx->ppgtt->base : 1047 &dev_priv->gtt.base; 1048 1049 /* We need to copy these to an anonymous buffer 1050 * as the simplest method to avoid being overwritten 1051 * by userspace. 1052 */ 1053 error->ring[i].batchbuffer = 1054 i915_error_object_create(dev_priv, 1055 request->batch_obj, 1056 vm); 1057 1058 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) 1059 error->ring[i].wa_batchbuffer = 1060 i915_error_ggtt_object_create(dev_priv, 1061 ring->scratch.obj); 1062 1063#ifndef __NetBSD__ /* XXX not a clue */ 1064 if (request->pid) { 1065 struct task_struct *task; 1066 1067 rcu_read_lock(); 1068 task = pid_task(request->pid, PIDTYPE_PID); 1069 if (task) { 1070 strcpy(error->ring[i].comm, task->comm); 1071 error->ring[i].pid = task->pid; 1072 } 1073 rcu_read_unlock(); 1074 } 1075#endif 1076 } 1077 1078 if (i915.enable_execlists) { 1079 /* TODO: This is only a small fix to keep basic error 1080 * capture working, but we need to add more information 1081 * for it to be useful (e.g. dump the context being 1082 * executed). 1083 */ 1084 if (request) 1085 rbuf = request->ctx->engine[ring->id].ringbuf; 1086 else 1087 rbuf = ring->default_context->engine[ring->id].ringbuf; 1088 } else 1089 rbuf = ring->buffer; 1090 1091 error->ring[i].cpu_ring_head = rbuf->head; 1092 error->ring[i].cpu_ring_tail = rbuf->tail; 1093 1094 error->ring[i].ringbuffer = 1095 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1096 1097 error->ring[i].hws_page = 1098 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1099 1100 i915_gem_record_active_context(ring, error, &error->ring[i]); 1101 1102 count = 0; 1103 list_for_each_entry(request, &ring->request_list, list) 1104 count++; 1105 1106 error->ring[i].num_requests = count; 1107 error->ring[i].requests = 1108 kcalloc(count, sizeof(*error->ring[i].requests), 1109 GFP_ATOMIC); 1110 if (error->ring[i].requests == NULL) { 1111 error->ring[i].num_requests = 0; 1112 continue; 1113 } 1114 1115 count = 0; 1116 list_for_each_entry(request, &ring->request_list, list) { 1117 struct drm_i915_error_request *erq; 1118 1119 erq = &error->ring[i].requests[count++]; 1120 erq->seqno = request->seqno; 1121 erq->jiffies = request->emitted_jiffies; 1122 erq->tail = request->postfix; 1123 } 1124 } 1125} 1126 1127/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1128 * VM. 1129 */ 1130static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1131 struct drm_i915_error_state *error, 1132 struct i915_address_space *vm, 1133 const int ndx) 1134{ 1135 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1136 struct drm_i915_gem_object *obj; 1137 struct i915_vma *vma; 1138 int i; 1139 1140 i = 0; 1141 list_for_each_entry(vma, &vm->active_list, mm_list) 1142 i++; 1143 error->active_bo_count[ndx] = i; 1144 1145 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1146 list_for_each_entry(vma, &obj->vma_list, vma_link) 1147 if (vma->vm == vm && vma->pin_count > 0) 1148 i++; 1149 } 1150 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1151 1152 if (i) { 1153 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1154 if (active_bo) 1155 pinned_bo = active_bo + error->active_bo_count[ndx]; 1156 } 1157 1158 if (active_bo) 1159 error->active_bo_count[ndx] = 1160 capture_active_bo(active_bo, 1161 error->active_bo_count[ndx], 1162 &vm->active_list); 1163 1164 if (pinned_bo) 1165 error->pinned_bo_count[ndx] = 1166 capture_pinned_bo(pinned_bo, 1167 error->pinned_bo_count[ndx], 1168 &dev_priv->mm.bound_list, vm); 1169 error->active_bo[ndx] = active_bo; 1170 error->pinned_bo[ndx] = pinned_bo; 1171} 1172 1173static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1174 struct drm_i915_error_state *error) 1175{ 1176 struct i915_address_space *vm; 1177 int cnt = 0, i = 0; 1178 1179 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1180 cnt++; 1181 1182 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1183 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1184 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1185 GFP_ATOMIC); 1186 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1187 GFP_ATOMIC); 1188 1189 if (error->active_bo == NULL || 1190 error->pinned_bo == NULL || 1191 error->active_bo_count == NULL || 1192 error->pinned_bo_count == NULL) { 1193 kfree(error->active_bo); 1194 kfree(error->active_bo_count); 1195 kfree(error->pinned_bo); 1196 kfree(error->pinned_bo_count); 1197 1198 error->active_bo = NULL; 1199 error->active_bo_count = NULL; 1200 error->pinned_bo = NULL; 1201 error->pinned_bo_count = NULL; 1202 } else { 1203 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1204 i915_gem_capture_vm(dev_priv, error, vm, i++); 1205 1206 error->vm_count = cnt; 1207 } 1208} 1209 1210/* Capture all registers which don't fit into another category. */ 1211static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1212 struct drm_i915_error_state *error) 1213{ 1214 struct drm_device *dev = dev_priv->dev; 1215 int i; 1216 1217 /* General organization 1218 * 1. Registers specific to a single generation 1219 * 2. Registers which belong to multiple generations 1220 * 3. Feature specific registers. 1221 * 4. Everything else 1222 * Please try to follow the order. 1223 */ 1224 1225 /* 1: Registers specific to a single generation */ 1226 if (IS_VALLEYVIEW(dev)) { 1227 error->gtier[0] = I915_READ(GTIER); 1228 error->ier = I915_READ(VLV_IER); 1229 error->forcewake = I915_READ(FORCEWAKE_VLV); 1230 } 1231 1232 if (IS_GEN7(dev)) 1233 error->err_int = I915_READ(GEN7_ERR_INT); 1234 1235 if (INTEL_INFO(dev)->gen >= 8) { 1236 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1237 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1238 } 1239 1240 if (IS_GEN6(dev)) { 1241 error->forcewake = I915_READ(FORCEWAKE); 1242 error->gab_ctl = I915_READ(GAB_CTL); 1243 error->gfx_mode = I915_READ(GFX_MODE); 1244 } 1245 1246 /* 2: Registers which belong to multiple generations */ 1247 if (INTEL_INFO(dev)->gen >= 7) 1248 error->forcewake = I915_READ(FORCEWAKE_MT); 1249 1250 if (INTEL_INFO(dev)->gen >= 6) { 1251 error->derrmr = I915_READ(DERRMR); 1252 error->error = I915_READ(ERROR_GEN6); 1253 error->done_reg = I915_READ(DONE_REG); 1254 } 1255 1256 /* 3: Feature specific registers */ 1257 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1258 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1259 error->gac_eco = I915_READ(GAC_ECO_BITS); 1260 } 1261 1262 /* 4: Everything else */ 1263 if (HAS_HW_CONTEXTS(dev)) 1264 error->ccid = I915_READ(CCID); 1265 1266 if (INTEL_INFO(dev)->gen >= 8) { 1267 error->ier = I915_READ(GEN8_DE_MISC_IER); 1268 for (i = 0; i < 4; i++) 1269 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1270 } else if (HAS_PCH_SPLIT(dev)) { 1271 error->ier = I915_READ(DEIER); 1272 error->gtier[0] = I915_READ(GTIER); 1273 } else if (IS_GEN2(dev)) { 1274 error->ier = I915_READ16(IER); 1275 } else if (!IS_VALLEYVIEW(dev)) { 1276 error->ier = I915_READ(IER); 1277 } 1278 error->eir = I915_READ(EIR); 1279 error->pgtbl_er = I915_READ(PGTBL_ER); 1280 1281 i915_get_extra_instdone(dev, error->extra_instdone); 1282} 1283 1284static void i915_error_capture_msg(struct drm_device *dev, 1285 struct drm_i915_error_state *error, 1286 bool wedged, 1287 const char *error_msg) 1288{ 1289 struct drm_i915_private *dev_priv = dev->dev_private; 1290 u32 ecode; 1291 int ring_id = -1, len; 1292 1293 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1294 1295 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1296 "GPU HANG: ecode %d:%d:0x%08x", 1297 INTEL_INFO(dev)->gen, ring_id, ecode); 1298 1299 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1300 len += scnprintf(error->error_msg + len, 1301 sizeof(error->error_msg) - len, 1302 ", in %s [%d]", 1303 error->ring[ring_id].comm, 1304 error->ring[ring_id].pid); 1305 1306 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1307 ", reason: %s, action: %s", 1308 error_msg, 1309 wedged ? "reset" : "continue"); 1310} 1311 1312static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1313 struct drm_i915_error_state *error) 1314{ 1315 error->iommu = -1; 1316#ifdef CONFIG_INTEL_IOMMU 1317 error->iommu = intel_iommu_gfx_mapped; 1318#endif 1319 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1320 error->suspend_count = dev_priv->suspend_count; 1321} 1322 1323/** 1324 * i915_capture_error_state - capture an error record for later analysis 1325 * @dev: drm device 1326 * 1327 * Should be called when an error is detected (either a hang or an error 1328 * interrupt) to capture error state from the time of the error. Fills 1329 * out a structure which becomes available in debugfs for user level tools 1330 * to pick up. 1331 */ 1332void i915_capture_error_state(struct drm_device *dev, bool wedged, 1333 const char *error_msg) 1334{ 1335 static bool warned; 1336 struct drm_i915_private *dev_priv = dev->dev_private; 1337 struct drm_i915_error_state *error; 1338 unsigned long flags; 1339 1340 /* Account for pipe specific data like PIPE*STAT */ 1341 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1342 if (!error) { 1343 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1344 return; 1345 } 1346 1347 kref_init(&error->ref); 1348 1349 i915_capture_gen_state(dev_priv, error); 1350 i915_capture_reg_state(dev_priv, error); 1351 i915_gem_capture_buffers(dev_priv, error); 1352 i915_gem_record_fences(dev, error); 1353 i915_gem_record_rings(dev, error); 1354 1355 do_gettimeofday(&error->time); 1356 1357 error->overlay = intel_overlay_capture_error_state(dev); 1358 error->display = intel_display_capture_error_state(dev); 1359 1360 i915_error_capture_msg(dev, error, wedged, error_msg); 1361 DRM_INFO("%s\n", error->error_msg); 1362 1363 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1364 if (dev_priv->gpu_error.first_error == NULL) { 1365 dev_priv->gpu_error.first_error = error; 1366 error = NULL; 1367 } 1368 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1369 1370 if (error) { 1371 i915_error_state_free(&error->ref); 1372 return; 1373 } 1374 1375 if (!warned) { 1376 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1377 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1378 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1379 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1380 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1381 warned = true; 1382 } 1383} 1384 1385void i915_error_state_get(struct drm_device *dev, 1386 struct i915_error_state_file_priv *error_priv) 1387{ 1388 struct drm_i915_private *dev_priv = dev->dev_private; 1389 1390 spin_lock_irq(&dev_priv->gpu_error.lock); 1391 error_priv->error = dev_priv->gpu_error.first_error; 1392 if (error_priv->error) 1393 kref_get(&error_priv->error->ref); 1394 spin_unlock_irq(&dev_priv->gpu_error.lock); 1395 1396} 1397 1398void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1399{ 1400 if (error_priv->error) 1401 kref_put(&error_priv->error->ref, i915_error_state_free); 1402} 1403 1404void i915_destroy_error_state(struct drm_device *dev) 1405{ 1406 struct drm_i915_private *dev_priv = dev->dev_private; 1407 struct drm_i915_error_state *error; 1408 1409 spin_lock_irq(&dev_priv->gpu_error.lock); 1410 error = dev_priv->gpu_error.first_error; 1411 dev_priv->gpu_error.first_error = NULL; 1412 spin_unlock_irq(&dev_priv->gpu_error.lock); 1413 1414 if (error) 1415 kref_put(&error->ref, i915_error_state_free); 1416} 1417 1418const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1419{ 1420 switch (type) { 1421 case I915_CACHE_NONE: return " uncached"; 1422 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1423 case I915_CACHE_L3_LLC: return " L3+LLC"; 1424 case I915_CACHE_WT: return " WT"; 1425 default: return ""; 1426 } 1427} 1428 1429/* NB: please notice the memset */ 1430void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1431{ 1432 struct drm_i915_private *dev_priv = dev->dev_private; 1433 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1434 1435 if (IS_GEN2(dev) || IS_GEN3(dev)) 1436 instdone[0] = I915_READ(GEN2_INSTDONE); 1437 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1438 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1439 instdone[1] = I915_READ(GEN4_INSTDONE1); 1440 } else if (INTEL_INFO(dev)->gen >= 7) { 1441 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1442 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1443 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1444 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1445 } 1446} 1447