i915_gpu_error.c revision 1.11
1/* $NetBSD: i915_gpu_error.c,v 1.11 2020/02/14 14:34:58 maya Exp $ */ 2 3/* 4 * Copyright (c) 2008 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 23 * IN THE SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * Keith Packard <keithp@keithp.com> 28 * Mika Kuoppala <mika.kuoppala@intel.com> 29 * 30 */ 31 32#include <sys/cdefs.h> 33__KERNEL_RCSID(0, "$NetBSD: i915_gpu_error.c,v 1.11 2020/02/14 14:34:58 maya Exp $"); 34 35#include <sys/param.h> 36 37#include "i915_drv.h" 38 39static const char *ring_str(int ring) 40{ 41 switch (ring) { 42 case RCS: return "render"; 43 case VCS: return "bsd"; 44 case BCS: return "blt"; 45 case VECS: return "vebox"; 46 case VCS2: return "bsd2"; 47 default: return ""; 48 } 49} 50 51static const char *pin_flag(int pinned) 52{ 53 if (pinned > 0) 54 return " P"; 55 else if (pinned < 0) 56 return " p"; 57 else 58 return ""; 59} 60 61static const char *tiling_flag(int tiling) 62{ 63 switch (tiling) { 64 default: 65 case I915_TILING_NONE: return ""; 66 case I915_TILING_X: return " X"; 67 case I915_TILING_Y: return " Y"; 68 } 69} 70 71static const char *dirty_flag(int dirty) 72{ 73 return dirty ? " dirty" : ""; 74} 75 76static const char *purgeable_flag(int purgeable) 77{ 78 return purgeable ? " purgeable" : ""; 79} 80 81static bool __i915_error_ok(struct drm_i915_error_state_buf *e) 82{ 83 84 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) { 85 e->err = -ENOSPC; 86 return false; 87 } 88 89 if (e->bytes == e->size - 1 || e->err) 90 return false; 91 92 return true; 93} 94 95static bool __i915_error_seek(struct drm_i915_error_state_buf *e, 96 unsigned len) 97{ 98 if (e->pos + len <= e->start) { 99 e->pos += len; 100 return false; 101 } 102 103 /* First vsnprintf needs to fit in its entirety for memmove */ 104 if (len >= e->size) { 105 e->err = -EIO; 106 return false; 107 } 108 109 return true; 110} 111 112static void __i915_error_advance(struct drm_i915_error_state_buf *e, 113 unsigned len) 114{ 115 /* If this is first printf in this window, adjust it so that 116 * start position matches start of the buffer 117 */ 118 119 if (e->pos < e->start) { 120 const size_t off = e->start - e->pos; 121 122 /* Should not happen but be paranoid */ 123 if (off > len || e->bytes) { 124 e->err = -EIO; 125 return; 126 } 127 128 memmove(e->buf, e->buf + off, len - off); 129 e->bytes = len - off; 130 e->pos = e->start; 131 return; 132 } 133 134 e->bytes += len; 135 e->pos += len; 136} 137 138static void i915_error_vprintf(struct drm_i915_error_state_buf *e, 139 const char *f, va_list args) 140{ 141 unsigned len; 142 143 if (!__i915_error_ok(e)) 144 return; 145 146 /* Seek the first printf which is hits start position */ 147 if (e->pos < e->start) { 148 va_list tmp; 149 150 va_copy(tmp, args); 151 len = vsnprintf(NULL, 0, f, tmp); 152 va_end(tmp); 153 154 if (!__i915_error_seek(e, len)) 155 return; 156 } 157 158 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args); 159 if (len >= e->size - e->bytes) 160 len = e->size - e->bytes - 1; 161 162 __i915_error_advance(e, len); 163} 164 165static void i915_error_puts(struct drm_i915_error_state_buf *e, 166 const char *str) 167{ 168 unsigned len; 169 170 if (!__i915_error_ok(e)) 171 return; 172 173 len = strlen(str); 174 175 /* Seek the first printf which is hits start position */ 176 if (e->pos < e->start) { 177 if (!__i915_error_seek(e, len)) 178 return; 179 } 180 181 if (len >= e->size - e->bytes) 182 len = e->size - e->bytes - 1; 183 memcpy(e->buf + e->bytes, str, len); 184 185 __i915_error_advance(e, len); 186} 187 188#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) 189#define err_puts(e, s) i915_error_puts(e, s) 190 191static void print_error_buffers(struct drm_i915_error_state_buf *m, 192 const char *name, 193 struct drm_i915_error_buffer *err, 194 int count) 195{ 196 int i; 197 198 err_printf(m, " %s [%d]:\n", name, count); 199 200 while (count--) { 201 err_printf(m, " %08x_%08x %8u %02x %02x [ ", 202 upper_32_bits(err->gtt_offset), 203 lower_32_bits(err->gtt_offset), 204 err->size, 205 err->read_domains, 206 err->write_domain); 207 for (i = 0; i < I915_NUM_RINGS; i++) 208 err_printf(m, "%02x ", err->rseqno[i]); 209 210 err_printf(m, "] %02x", err->wseqno); 211 err_puts(m, pin_flag(err->pinned)); 212 err_puts(m, tiling_flag(err->tiling)); 213 err_puts(m, dirty_flag(err->dirty)); 214 err_puts(m, purgeable_flag(err->purgeable)); 215 err_puts(m, err->userptr ? " userptr" : ""); 216 err_puts(m, err->ring != -1 ? " " : ""); 217 err_puts(m, ring_str(err->ring)); 218 err_puts(m, i915_cache_level_str(m->i915, err->cache_level)); 219 220 if (err->name) 221 err_printf(m, " (name: %d)", err->name); 222 if (err->fence_reg != I915_FENCE_REG_NONE) 223 err_printf(m, " (fence: %d)", err->fence_reg); 224 225 err_puts(m, "\n"); 226 err++; 227 } 228} 229 230static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) 231{ 232 switch (a) { 233 case HANGCHECK_IDLE: 234 return "idle"; 235 case HANGCHECK_WAIT: 236 return "wait"; 237 case HANGCHECK_ACTIVE: 238 return "active"; 239 case HANGCHECK_ACTIVE_LOOP: 240 return "active (loop)"; 241 case HANGCHECK_KICK: 242 return "kick"; 243 case HANGCHECK_HUNG: 244 return "hung"; 245 } 246 247 return "unknown"; 248} 249 250static void i915_ring_error_state(struct drm_i915_error_state_buf *m, 251 struct drm_device *dev, 252 struct drm_i915_error_state *error, 253 int ring_idx) 254{ 255 struct drm_i915_error_ring *ring = &error->ring[ring_idx]; 256 257 if (!ring->valid) 258 return; 259 260 err_printf(m, "%s command stream:\n", ring_str(ring_idx)); 261 err_printf(m, " START: 0x%08x\n", ring->start); 262 err_printf(m, " HEAD: 0x%08x\n", ring->head); 263 err_printf(m, " TAIL: 0x%08x\n", ring->tail); 264 err_printf(m, " CTL: 0x%08x\n", ring->ctl); 265 err_printf(m, " HWS: 0x%08x\n", ring->hws); 266 err_printf(m, " ACTHD: 0x%08x %08x\n", (u32)(ring->acthd>>32), (u32)ring->acthd); 267 err_printf(m, " IPEIR: 0x%08x\n", ring->ipeir); 268 err_printf(m, " IPEHR: 0x%08x\n", ring->ipehr); 269 err_printf(m, " INSTDONE: 0x%08x\n", ring->instdone); 270 if (INTEL_INFO(dev)->gen >= 4) { 271 err_printf(m, " BBADDR: 0x%08x %08x\n", (u32)(ring->bbaddr>>32), (u32)ring->bbaddr); 272 err_printf(m, " BB_STATE: 0x%08x\n", ring->bbstate); 273 err_printf(m, " INSTPS: 0x%08x\n", ring->instps); 274 } 275 err_printf(m, " INSTPM: 0x%08x\n", ring->instpm); 276 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ring->faddr), 277 lower_32_bits(ring->faddr)); 278 if (INTEL_INFO(dev)->gen >= 6) { 279 err_printf(m, " RC PSMI: 0x%08x\n", ring->rc_psmi); 280 err_printf(m, " FAULT_REG: 0x%08x\n", ring->fault_reg); 281 err_printf(m, " SYNC_0: 0x%08x [last synced 0x%08x]\n", 282 ring->semaphore_mboxes[0], 283 ring->semaphore_seqno[0]); 284 err_printf(m, " SYNC_1: 0x%08x [last synced 0x%08x]\n", 285 ring->semaphore_mboxes[1], 286 ring->semaphore_seqno[1]); 287 if (HAS_VEBOX(dev)) { 288 err_printf(m, " SYNC_2: 0x%08x [last synced 0x%08x]\n", 289 ring->semaphore_mboxes[2], 290 ring->semaphore_seqno[2]); 291 } 292 } 293 if (USES_PPGTT(dev)) { 294 err_printf(m, " GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode); 295 296 if (INTEL_INFO(dev)->gen >= 8) { 297 int i; 298 for (i = 0; i < 4; i++) 299 err_printf(m, " PDP%d: 0x%016"PRIx64"\n", 300 i, ring->vm_info.pdp[i]); 301 } else { 302 err_printf(m, " PP_DIR_BASE: 0x%08x\n", 303 ring->vm_info.pp_dir_base); 304 } 305 } 306 err_printf(m, " seqno: 0x%08x\n", ring->seqno); 307 err_printf(m, " waiting: %s\n", yesno(ring->waiting)); 308 err_printf(m, " ring->head: 0x%08x\n", ring->cpu_ring_head); 309 err_printf(m, " ring->tail: 0x%08x\n", ring->cpu_ring_tail); 310 err_printf(m, " hangcheck: %s [%d]\n", 311 hangcheck_action_to_str(ring->hangcheck_action), 312 ring->hangcheck_score); 313} 314 315void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...) 316{ 317 va_list args; 318 319 va_start(args, f); 320 i915_error_vprintf(e, f, args); 321 va_end(args); 322} 323 324static void print_error_obj(struct drm_i915_error_state_buf *m, 325 struct drm_i915_error_object *obj) 326{ 327 int page, offset, elt; 328 329 for (page = offset = 0; page < obj->page_count; page++) { 330 for (elt = 0; elt < PAGE_SIZE/4; elt++) { 331 err_printf(m, "%08x : %08x\n", offset, 332 obj->pages[page][elt]); 333 offset += 4; 334 } 335 } 336} 337 338int i915_error_state_to_str(struct drm_i915_error_state_buf *m, 339 const struct i915_error_state_file_priv *error_priv) 340{ 341 struct drm_device *dev = error_priv->dev; 342 struct drm_i915_private *dev_priv = dev->dev_private; 343 struct drm_i915_error_state *error = error_priv->error; 344 struct drm_i915_error_object *obj; 345 int i, j, offset, elt; 346 int max_hangcheck_score; 347 348 if (!error) { 349 err_printf(m, "no error state collected\n"); 350 goto out; 351 } 352 353 err_printf(m, "%s\n", error->error_msg); 354 err_printf(m, "Time: %"PRIdMAX" s %ld us\n", (intmax_t)error->time.tv_sec, 355 (long)error->time.tv_usec); 356 err_printf(m, "Kernel: %d\n", __NetBSD_Version__); 357 max_hangcheck_score = 0; 358 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 359 if (error->ring[i].hangcheck_score > max_hangcheck_score) 360 max_hangcheck_score = error->ring[i].hangcheck_score; 361 } 362 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 363 if (error->ring[i].hangcheck_score == max_hangcheck_score && 364 error->ring[i].pid != -1) { 365 err_printf(m, "Active process (on ring %s): %s [%d]\n", 366 ring_str(i), 367 error->ring[i].comm, 368 error->ring[i].pid); 369 } 370 } 371 err_printf(m, "Reset count: %u\n", error->reset_count); 372 err_printf(m, "Suspend count: %u\n", error->suspend_count); 373 err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device); 374 err_printf(m, "IOMMU enabled?: %d\n", error->iommu); 375 err_printf(m, "EIR: 0x%08x\n", error->eir); 376 err_printf(m, "IER: 0x%08x\n", error->ier); 377 if (INTEL_INFO(dev)->gen >= 8) { 378 for (i = 0; i < 4; i++) 379 err_printf(m, "GTIER gt %d: 0x%08x\n", i, 380 error->gtier[i]); 381 } else if (HAS_PCH_SPLIT(dev) || IS_VALLEYVIEW(dev)) 382 err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]); 383 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 384 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake); 385 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr); 386 err_printf(m, "CCID: 0x%08x\n", error->ccid); 387 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings); 388 389 for (i = 0; i < dev_priv->num_fence_regs; i++) 390 err_printf(m, " fence[%d] = %08"PRIx64"\n", i, error->fence[i]); 391 392 for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++) 393 err_printf(m, " INSTDONE_%d: 0x%08x\n", i, 394 error->extra_instdone[i]); 395 396 if (INTEL_INFO(dev)->gen >= 6) { 397 err_printf(m, "ERROR: 0x%08x\n", error->error); 398 399 if (INTEL_INFO(dev)->gen >= 8) 400 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", 401 error->fault_data1, error->fault_data0); 402 403 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); 404 } 405 406 if (INTEL_INFO(dev)->gen == 7) 407 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); 408 409 for (i = 0; i < ARRAY_SIZE(error->ring); i++) 410 i915_ring_error_state(m, dev, error, i); 411 412 for (i = 0; i < error->vm_count; i++) { 413 err_printf(m, "vm[%d]\n", i); 414 415 print_error_buffers(m, "Active", 416 error->active_bo[i], 417 error->active_bo_count[i]); 418 419 print_error_buffers(m, "Pinned", 420 error->pinned_bo[i], 421 error->pinned_bo_count[i]); 422 } 423 424 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 425 obj = error->ring[i].batchbuffer; 426 if (obj) { 427 err_puts(m, dev_priv->ring[i].name); 428 if (error->ring[i].pid != -1) 429 err_printf(m, " (submitted by %s [%d])", 430 error->ring[i].comm, 431 error->ring[i].pid); 432 err_printf(m, " --- gtt_offset = 0x%08x %08x\n", 433 upper_32_bits(obj->gtt_offset), 434 lower_32_bits(obj->gtt_offset)); 435 print_error_obj(m, obj); 436 } 437 438 obj = error->ring[i].wa_batchbuffer; 439 if (obj) { 440 err_printf(m, "%s (w/a) --- gtt_offset = 0x%08x\n", 441 dev_priv->ring[i].name, 442 lower_32_bits(obj->gtt_offset)); 443 print_error_obj(m, obj); 444 } 445 446 if (error->ring[i].num_requests) { 447 err_printf(m, "%s --- %d requests\n", 448 dev_priv->ring[i].name, 449 error->ring[i].num_requests); 450 for (j = 0; j < error->ring[i].num_requests; j++) { 451 err_printf(m, " seqno 0x%08x, emitted %ld, tail 0x%08x\n", 452 error->ring[i].requests[j].seqno, 453 error->ring[i].requests[j].jiffies, 454 error->ring[i].requests[j].tail); 455 } 456 } 457 458 if ((obj = error->ring[i].ringbuffer)) { 459 err_printf(m, "%s --- ringbuffer = 0x%08x\n", 460 dev_priv->ring[i].name, 461 lower_32_bits(obj->gtt_offset)); 462 print_error_obj(m, obj); 463 } 464 465 if ((obj = error->ring[i].hws_page)) { 466 u64 hws_offset = obj->gtt_offset; 467 u32 *hws_page = &obj->pages[0][0]; 468 469 if (i915.enable_execlists) { 470 hws_offset += LRC_PPHWSP_PN * PAGE_SIZE; 471 hws_page = &obj->pages[LRC_PPHWSP_PN][0]; 472 } 473 err_printf(m, "%s --- HW Status = 0x%08"PRIx64"\n", 474 dev_priv->ring[i].name, hws_offset); 475 offset = 0; 476 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 477 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 478 offset, 479 hws_page[elt], 480 hws_page[elt+1], 481 hws_page[elt+2], 482 hws_page[elt+3]); 483 offset += 16; 484 } 485 } 486 487 if ((obj = error->ring[i].ctx)) { 488 err_printf(m, "%s --- HW Context = 0x%08x\n", 489 dev_priv->ring[i].name, 490 lower_32_bits(obj->gtt_offset)); 491 print_error_obj(m, obj); 492 } 493 } 494 495 if ((obj = error->semaphore_obj)) { 496 err_printf(m, "Semaphore page = 0x%08x\n", 497 lower_32_bits(obj->gtt_offset)); 498 for (elt = 0; elt < PAGE_SIZE/16; elt += 4) { 499 err_printf(m, "[%04x] %08x %08x %08x %08x\n", 500 elt * 4, 501 obj->pages[0][elt], 502 obj->pages[0][elt+1], 503 obj->pages[0][elt+2], 504 obj->pages[0][elt+3]); 505 } 506 } 507 508 if (error->overlay) 509 intel_overlay_print_error_state(m, error->overlay); 510 511 if (error->display) 512 intel_display_print_error_state(m, dev, error->display); 513 514out: 515 if (m->bytes == 0 && m->err) 516 return m->err; 517 518 return 0; 519} 520 521int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf, 522 struct drm_i915_private *i915, 523 size_t count, loff_t pos) 524{ 525 memset(ebuf, 0, sizeof(*ebuf)); 526 ebuf->i915 = i915; 527 528 /* We need to have enough room to store any i915_error_state printf 529 * so that we can move it to start position. 530 */ 531 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE; 532 ebuf->buf = kmalloc(ebuf->size, 533 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN); 534 535 if (ebuf->buf == NULL) { 536 ebuf->size = PAGE_SIZE; 537 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 538 } 539 540 if (ebuf->buf == NULL) { 541 ebuf->size = 128; 542 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY); 543 } 544 545 if (ebuf->buf == NULL) 546 return -ENOMEM; 547 548 ebuf->start = pos; 549 550 return 0; 551} 552 553static void i915_error_object_free(struct drm_i915_error_object *obj) 554{ 555 int page; 556 557 if (obj == NULL) 558 return; 559 560 for (page = 0; page < obj->page_count; page++) 561 kfree(obj->pages[page]); 562 563 kfree(obj); 564} 565 566static void i915_error_state_free(struct kref *error_ref) 567{ 568 struct drm_i915_error_state *error = container_of(error_ref, 569 typeof(*error), ref); 570 int i; 571 572 for (i = 0; i < ARRAY_SIZE(error->ring); i++) { 573 i915_error_object_free(error->ring[i].batchbuffer); 574 i915_error_object_free(error->ring[i].wa_batchbuffer); 575 i915_error_object_free(error->ring[i].ringbuffer); 576 i915_error_object_free(error->ring[i].hws_page); 577 i915_error_object_free(error->ring[i].ctx); 578 kfree(error->ring[i].requests); 579 } 580 581 i915_error_object_free(error->semaphore_obj); 582 583 for (i = 0; i < error->vm_count; i++) 584 kfree(error->active_bo[i]); 585 586 kfree(error->active_bo); 587 kfree(error->active_bo_count); 588 kfree(error->pinned_bo); 589 kfree(error->pinned_bo_count); 590 kfree(error->overlay); 591 kfree(error->display); 592 kfree(error); 593} 594 595#ifdef __NetBSD__ 596# define __aperture_iomem 597# define __iomem __aperture_iomem 598#endif 599 600static struct drm_i915_error_object * 601i915_error_object_create(struct drm_i915_private *dev_priv, 602 struct drm_i915_gem_object *src, 603 struct i915_address_space *vm) 604{ 605 struct drm_i915_error_object *dst; 606 struct i915_vma *vma = NULL; 607 int num_pages; 608 bool use_ggtt; 609 int i = 0; 610 u64 reloc_offset; 611 612 if (src == NULL || src->pages == NULL) 613 return NULL; 614 615 num_pages = src->base.size >> PAGE_SHIFT; 616 617 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC); 618 if (dst == NULL) 619 return NULL; 620 621 if (i915_gem_obj_bound(src, vm)) 622 dst->gtt_offset = i915_gem_obj_offset(src, vm); 623 else 624 dst->gtt_offset = -1; 625 626 reloc_offset = dst->gtt_offset; 627 if (i915_is_ggtt(vm)) 628 vma = i915_gem_obj_to_ggtt(src); 629 use_ggtt = (src->cache_level == I915_CACHE_NONE && 630 vma && (vma->bound & GLOBAL_BIND) && 631 reloc_offset + num_pages * PAGE_SIZE <= dev_priv->gtt.mappable_end); 632 633 /* Cannot access stolen address directly, try to use the aperture */ 634 if (src->stolen) { 635 use_ggtt = true; 636 637 if (!(vma && vma->bound & GLOBAL_BIND)) 638 goto unwind; 639 640 reloc_offset = i915_gem_obj_ggtt_offset(src); 641 if (reloc_offset + num_pages * PAGE_SIZE > dev_priv->gtt.mappable_end) 642 goto unwind; 643 } 644 645 /* Cannot access snooped pages through the aperture */ 646 if (use_ggtt && src->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv->dev)) 647 goto unwind; 648 649 dst->page_count = num_pages; 650 while (num_pages--) { 651 unsigned long flags; 652 void *d; 653 654 d = kmalloc(PAGE_SIZE, GFP_ATOMIC); 655 if (d == NULL) 656 goto unwind; 657 658 local_irq_save(flags); 659 if (use_ggtt) { 660 void __iomem *s; 661 662 /* Simply ignore tiling or any overlapping fence. 663 * It's part of the error state, and this hopefully 664 * captures what the GPU read. 665 */ 666 667 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, 668 reloc_offset); 669 memcpy_fromio(d, s, PAGE_SIZE); 670#ifdef __NetBSD__ 671 io_mapping_unmap_atomic(dev_priv->gtt.mappable, s); 672#else 673 io_mapping_unmap_atomic(s); 674#endif 675 } else { 676 677 if (cpu_intr_p() || cpu_softintr_p() || 678 (curlwp->l_pflag & LP_INTR) != 0) { 679 /* 680 * We can't take locks during interrupts 681 * and finding the page from uvm requires 682 * taking a lock. Checking for an interrupt 683 * context is bogus, but this is the least 684 * intrusive change. Zero the result, doesn't 685 * matter much, because this is only used 686 * for diagnostics. 687 */ 688 memset(d, 0, PAGE_SIZE); 689 } else { 690 struct page *page; 691 void *s; 692 693 page = i915_gem_object_get_page(src, i); 694 695 drm_clflush_pages(&page, 1); 696 697 s = kmap_atomic(page); 698 memcpy(d, s, PAGE_SIZE); 699 kunmap_atomic(s); 700 701 drm_clflush_pages(&page, 1); 702 } 703 } 704 local_irq_restore(flags); 705 706 dst->pages[i++] = d; 707 reloc_offset += PAGE_SIZE; 708 } 709 710 return dst; 711 712unwind: 713 while (i--) 714 kfree(dst->pages[i]); 715 kfree(dst); 716 return NULL; 717} 718#define i915_error_ggtt_object_create(dev_priv, src) \ 719 i915_error_object_create((dev_priv), (src), &(dev_priv)->gtt.base) 720 721#ifdef __NetBSD__ 722# undef __iomem 723# undef __aperture_iomem 724#endif 725 726static void capture_bo(struct drm_i915_error_buffer *err, 727 struct i915_vma *vma) 728{ 729 struct drm_i915_gem_object *obj = vma->obj; 730 int i; 731 732 err->size = obj->base.size; 733 err->name = obj->base.name; 734 for (i = 0; i < I915_NUM_RINGS; i++) 735 err->rseqno[i] = i915_gem_request_get_seqno(obj->last_read_req[i]); 736 err->wseqno = i915_gem_request_get_seqno(obj->last_write_req); 737 err->gtt_offset = vma->node.start; 738 err->read_domains = obj->base.read_domains; 739 err->write_domain = obj->base.write_domain; 740 err->fence_reg = obj->fence_reg; 741 err->pinned = 0; 742 if (i915_gem_obj_is_pinned(obj)) 743 err->pinned = 1; 744 err->tiling = obj->tiling_mode; 745 err->dirty = obj->dirty; 746 err->purgeable = obj->madv != I915_MADV_WILLNEED; 747 err->userptr = obj->userptr.mm != NULL; 748 err->ring = obj->last_write_req ? 749 i915_gem_request_get_ring(obj->last_write_req)->id : -1; 750 err->cache_level = obj->cache_level; 751} 752 753static u32 capture_active_bo(struct drm_i915_error_buffer *err, 754 int count, struct list_head *head) 755{ 756 struct i915_vma *vma; 757 int i = 0; 758 759 list_for_each_entry(vma, head, mm_list) { 760 capture_bo(err++, vma); 761 if (++i == count) 762 break; 763 } 764 765 return i; 766} 767 768static u32 capture_pinned_bo(struct drm_i915_error_buffer *err, 769 int count, struct list_head *head, 770 struct i915_address_space *vm) 771{ 772 struct drm_i915_gem_object *obj; 773 struct drm_i915_error_buffer * const first = err; 774 struct drm_i915_error_buffer * const last = err + count; 775 776 list_for_each_entry(obj, head, global_list) { 777 struct i915_vma *vma; 778 779 if (err == last) 780 break; 781 782 list_for_each_entry(vma, &obj->vma_list, vma_link) 783 if (vma->vm == vm && vma->pin_count > 0) 784 capture_bo(err++, vma); 785 } 786 787 return err - first; 788} 789 790/* Generate a semi-unique error code. The code is not meant to have meaning, The 791 * code's only purpose is to try to prevent false duplicated bug reports by 792 * grossly estimating a GPU error state. 793 * 794 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine 795 * the hang if we could strip the GTT offset information from it. 796 * 797 * It's only a small step better than a random number in its current form. 798 */ 799static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv, 800 struct drm_i915_error_state *error, 801 int *ring_id) 802{ 803 uint32_t error_code = 0; 804 int i; 805 806 /* IPEHR would be an ideal way to detect errors, as it's the gross 807 * measure of "the command that hung." However, has some very common 808 * synchronization commands which almost always appear in the case 809 * strictly a client bug. Use instdone to differentiate those some. 810 */ 811 for (i = 0; i < I915_NUM_RINGS; i++) { 812 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG) { 813 if (ring_id) 814 *ring_id = i; 815 816 return error->ring[i].ipehr ^ error->ring[i].instdone; 817 } 818 } 819 820 return error_code; 821} 822 823static void i915_gem_record_fences(struct drm_device *dev, 824 struct drm_i915_error_state *error) 825{ 826 struct drm_i915_private *dev_priv = dev->dev_private; 827 int i; 828 829 if (IS_GEN3(dev) || IS_GEN2(dev)) { 830 for (i = 0; i < dev_priv->num_fence_regs; i++) 831 error->fence[i] = I915_READ(FENCE_REG(i)); 832 } else if (IS_GEN5(dev) || IS_GEN4(dev)) { 833 for (i = 0; i < dev_priv->num_fence_regs; i++) 834 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); 835 } else if (INTEL_INFO(dev)->gen >= 6) { 836 for (i = 0; i < dev_priv->num_fence_regs; i++) 837 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); 838 } 839} 840 841 842static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, 843 struct drm_i915_error_state *error, 844 struct intel_engine_cs *ring, 845 struct drm_i915_error_ring *ering) 846{ 847 struct intel_engine_cs *to; 848 int i; 849 850 if (!i915_semaphore_is_enabled(dev_priv->dev)) 851 return; 852 853 if (!error->semaphore_obj) 854 error->semaphore_obj = 855 i915_error_ggtt_object_create(dev_priv, 856 dev_priv->semaphore_obj); 857 858 for_each_ring(to, dev_priv, i) { 859 int idx; 860 u16 signal_offset; 861 u32 *tmp; 862 863 if (ring == to) 864 continue; 865 866 signal_offset = (GEN8_SIGNAL_OFFSET(ring, i) & (PAGE_SIZE - 1)) 867 / 4; 868 tmp = error->semaphore_obj->pages[0]; 869 idx = intel_ring_sync_index(ring, to); 870 871 ering->semaphore_mboxes[idx] = tmp[signal_offset]; 872 ering->semaphore_seqno[idx] = ring->semaphore.sync_seqno[idx]; 873 } 874} 875 876static void gen6_record_semaphore_state(struct drm_i915_private *dev_priv, 877 struct intel_engine_cs *ring, 878 struct drm_i915_error_ring *ering) 879{ 880 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); 881 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); 882 ering->semaphore_seqno[0] = ring->semaphore.sync_seqno[0]; 883 ering->semaphore_seqno[1] = ring->semaphore.sync_seqno[1]; 884 885 if (HAS_VEBOX(dev_priv->dev)) { 886 ering->semaphore_mboxes[2] = 887 I915_READ(RING_SYNC_2(ring->mmio_base)); 888 ering->semaphore_seqno[2] = ring->semaphore.sync_seqno[2]; 889 } 890} 891 892static void i915_record_ring_state(struct drm_device *dev, 893 struct drm_i915_error_state *error, 894 struct intel_engine_cs *ring, 895 struct drm_i915_error_ring *ering) 896{ 897 struct drm_i915_private *dev_priv = dev->dev_private; 898 899 if (INTEL_INFO(dev)->gen >= 6) { 900 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); 901 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); 902 if (INTEL_INFO(dev)->gen >= 8) 903 gen8_record_semaphore_state(dev_priv, error, ring, ering); 904 else 905 gen6_record_semaphore_state(dev_priv, ring, ering); 906 } 907 908 if (INTEL_INFO(dev)->gen >= 4) { 909 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); 910 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); 911 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); 912 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base)); 913 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base)); 914 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base)); 915 if (INTEL_INFO(dev)->gen >= 8) { 916 ering->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(ring->mmio_base)) << 32; 917 ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32; 918 } 919 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base)); 920 } else { 921 ering->faddr = I915_READ(DMA_FADD_I8XX); 922 ering->ipeir = I915_READ(IPEIR); 923 ering->ipehr = I915_READ(IPEHR); 924 ering->instdone = I915_READ(GEN2_INSTDONE); 925 } 926 927#ifdef __NetBSD__ 928 spin_lock(&dev_priv->irq_lock); 929 ering->waiting = DRM_SPIN_WAITERS_P(&ring->irq_queue, 930 &dev_priv->irq_lock); 931 spin_unlock(&dev_priv->irq_lock); 932#else 933 ering->waiting = waitqueue_active(&ring->irq_queue); 934#endif 935 ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base)); 936 ering->seqno = ring->get_seqno(ring, false); 937 ering->acthd = intel_ring_get_active_head(ring); 938 ering->start = I915_READ_START(ring); 939 ering->head = I915_READ_HEAD(ring); 940 ering->tail = I915_READ_TAIL(ring); 941 ering->ctl = I915_READ_CTL(ring); 942 943 if (I915_NEED_GFX_HWS(dev)) { 944 int mmio; 945 946 if (IS_GEN7(dev)) { 947 switch (ring->id) { 948 default: 949 case RCS: 950 mmio = RENDER_HWS_PGA_GEN7; 951 break; 952 case BCS: 953 mmio = BLT_HWS_PGA_GEN7; 954 break; 955 case VCS: 956 mmio = BSD_HWS_PGA_GEN7; 957 break; 958 case VECS: 959 mmio = VEBOX_HWS_PGA_GEN7; 960 break; 961 } 962 } else if (IS_GEN6(ring->dev)) { 963 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 964 } else { 965 /* XXX: gen8 returns to sanity */ 966 mmio = RING_HWS_PGA(ring->mmio_base); 967 } 968 969 ering->hws = I915_READ(mmio); 970 } 971 972 ering->hangcheck_score = ring->hangcheck.score; 973 ering->hangcheck_action = ring->hangcheck.action; 974 975 if (USES_PPGTT(dev)) { 976 int i; 977 978 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring)); 979 980 if (IS_GEN6(dev)) 981 ering->vm_info.pp_dir_base = 982 I915_READ(RING_PP_DIR_BASE_READ(ring)); 983 else if (IS_GEN7(dev)) 984 ering->vm_info.pp_dir_base = 985 I915_READ(RING_PP_DIR_BASE(ring)); 986 else if (INTEL_INFO(dev)->gen >= 8) 987 for (i = 0; i < 4; i++) { 988 ering->vm_info.pdp[i] = 989 I915_READ(GEN8_RING_PDP_UDW(ring, i)); 990 ering->vm_info.pdp[i] <<= 32; 991 ering->vm_info.pdp[i] |= 992 I915_READ(GEN8_RING_PDP_LDW(ring, i)); 993 } 994 } 995} 996 997 998static void i915_gem_record_active_context(struct intel_engine_cs *ring, 999 struct drm_i915_error_state *error, 1000 struct drm_i915_error_ring *ering) 1001{ 1002 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1003 struct drm_i915_gem_object *obj; 1004 1005 /* Currently render ring is the only HW context user */ 1006 if (ring->id != RCS || !error->ccid) 1007 return; 1008 1009 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1010 if (!i915_gem_obj_ggtt_bound(obj)) 1011 continue; 1012 1013 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) { 1014 ering->ctx = i915_error_ggtt_object_create(dev_priv, obj); 1015 break; 1016 } 1017 } 1018} 1019 1020static void i915_gem_record_rings(struct drm_device *dev, 1021 struct drm_i915_error_state *error) 1022{ 1023 struct drm_i915_private *dev_priv = dev->dev_private; 1024 struct drm_i915_gem_request *request; 1025 int i, count; 1026 1027 for (i = 0; i < I915_NUM_RINGS; i++) { 1028 struct intel_engine_cs *ring = &dev_priv->ring[i]; 1029 struct intel_ringbuffer *rbuf; 1030 1031 error->ring[i].pid = -1; 1032 1033 if (ring->dev == NULL) 1034 continue; 1035 1036 error->ring[i].valid = true; 1037 1038 i915_record_ring_state(dev, error, ring, &error->ring[i]); 1039 1040 request = i915_gem_find_active_request(ring); 1041 if (request) { 1042 struct i915_address_space *vm; 1043 1044 vm = request->ctx && request->ctx->ppgtt ? 1045 &request->ctx->ppgtt->base : 1046 &dev_priv->gtt.base; 1047 1048 /* We need to copy these to an anonymous buffer 1049 * as the simplest method to avoid being overwritten 1050 * by userspace. 1051 */ 1052 error->ring[i].batchbuffer = 1053 i915_error_object_create(dev_priv, 1054 request->batch_obj, 1055 vm); 1056 1057 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) 1058 error->ring[i].wa_batchbuffer = 1059 i915_error_ggtt_object_create(dev_priv, 1060 ring->scratch.obj); 1061 1062#ifndef __NetBSD__ /* XXX not a clue */ 1063 if (request->pid) { 1064 struct task_struct *task; 1065 1066 rcu_read_lock(); 1067 task = pid_task(request->pid, PIDTYPE_PID); 1068 if (task) { 1069 strcpy(error->ring[i].comm, task->comm); 1070 error->ring[i].pid = task->pid; 1071 } 1072 rcu_read_unlock(); 1073 } 1074#endif 1075 } 1076 1077 if (i915.enable_execlists) { 1078 /* TODO: This is only a small fix to keep basic error 1079 * capture working, but we need to add more information 1080 * for it to be useful (e.g. dump the context being 1081 * executed). 1082 */ 1083 if (request) 1084 rbuf = request->ctx->engine[ring->id].ringbuf; 1085 else 1086 rbuf = ring->default_context->engine[ring->id].ringbuf; 1087 } else 1088 rbuf = ring->buffer; 1089 1090 error->ring[i].cpu_ring_head = rbuf->head; 1091 error->ring[i].cpu_ring_tail = rbuf->tail; 1092 1093 error->ring[i].ringbuffer = 1094 i915_error_ggtt_object_create(dev_priv, rbuf->obj); 1095 1096 error->ring[i].hws_page = 1097 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj); 1098 1099 i915_gem_record_active_context(ring, error, &error->ring[i]); 1100 1101 count = 0; 1102 list_for_each_entry(request, &ring->request_list, list) 1103 count++; 1104 1105 error->ring[i].num_requests = count; 1106 error->ring[i].requests = 1107 kcalloc(count, sizeof(*error->ring[i].requests), 1108 GFP_ATOMIC); 1109 if (error->ring[i].requests == NULL) { 1110 error->ring[i].num_requests = 0; 1111 continue; 1112 } 1113 1114 count = 0; 1115 list_for_each_entry(request, &ring->request_list, list) { 1116 struct drm_i915_error_request *erq; 1117 1118 erq = &error->ring[i].requests[count++]; 1119 erq->seqno = request->seqno; 1120 erq->jiffies = request->emitted_jiffies; 1121 erq->tail = request->postfix; 1122 } 1123 } 1124} 1125 1126/* FIXME: Since pin count/bound list is global, we duplicate what we capture per 1127 * VM. 1128 */ 1129static void i915_gem_capture_vm(struct drm_i915_private *dev_priv, 1130 struct drm_i915_error_state *error, 1131 struct i915_address_space *vm, 1132 const int ndx) 1133{ 1134 struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL; 1135 struct drm_i915_gem_object *obj; 1136 struct i915_vma *vma; 1137 int i; 1138 1139 i = 0; 1140 list_for_each_entry(vma, &vm->active_list, mm_list) 1141 i++; 1142 error->active_bo_count[ndx] = i; 1143 1144 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1145 list_for_each_entry(vma, &obj->vma_list, vma_link) 1146 if (vma->vm == vm && vma->pin_count > 0) 1147 i++; 1148 } 1149 error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx]; 1150 1151 if (i) { 1152 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC); 1153 if (active_bo) 1154 pinned_bo = active_bo + error->active_bo_count[ndx]; 1155 } 1156 1157 if (active_bo) 1158 error->active_bo_count[ndx] = 1159 capture_active_bo(active_bo, 1160 error->active_bo_count[ndx], 1161 &vm->active_list); 1162 1163 if (pinned_bo) 1164 error->pinned_bo_count[ndx] = 1165 capture_pinned_bo(pinned_bo, 1166 error->pinned_bo_count[ndx], 1167 &dev_priv->mm.bound_list, vm); 1168 error->active_bo[ndx] = active_bo; 1169 error->pinned_bo[ndx] = pinned_bo; 1170} 1171 1172static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv, 1173 struct drm_i915_error_state *error) 1174{ 1175 struct i915_address_space *vm; 1176 int cnt = 0, i = 0; 1177 1178 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1179 cnt++; 1180 1181 error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC); 1182 error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC); 1183 error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count), 1184 GFP_ATOMIC); 1185 error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count), 1186 GFP_ATOMIC); 1187 1188 if (error->active_bo == NULL || 1189 error->pinned_bo == NULL || 1190 error->active_bo_count == NULL || 1191 error->pinned_bo_count == NULL) { 1192 kfree(error->active_bo); 1193 kfree(error->active_bo_count); 1194 kfree(error->pinned_bo); 1195 kfree(error->pinned_bo_count); 1196 1197 error->active_bo = NULL; 1198 error->active_bo_count = NULL; 1199 error->pinned_bo = NULL; 1200 error->pinned_bo_count = NULL; 1201 } else { 1202 list_for_each_entry(vm, &dev_priv->vm_list, global_link) 1203 i915_gem_capture_vm(dev_priv, error, vm, i++); 1204 1205 error->vm_count = cnt; 1206 } 1207} 1208 1209/* Capture all registers which don't fit into another category. */ 1210static void i915_capture_reg_state(struct drm_i915_private *dev_priv, 1211 struct drm_i915_error_state *error) 1212{ 1213 struct drm_device *dev = dev_priv->dev; 1214 int i; 1215 1216 /* General organization 1217 * 1. Registers specific to a single generation 1218 * 2. Registers which belong to multiple generations 1219 * 3. Feature specific registers. 1220 * 4. Everything else 1221 * Please try to follow the order. 1222 */ 1223 1224 /* 1: Registers specific to a single generation */ 1225 if (IS_VALLEYVIEW(dev)) { 1226 error->gtier[0] = I915_READ(GTIER); 1227 error->ier = I915_READ(VLV_IER); 1228 error->forcewake = I915_READ(FORCEWAKE_VLV); 1229 } 1230 1231 if (IS_GEN7(dev)) 1232 error->err_int = I915_READ(GEN7_ERR_INT); 1233 1234 if (INTEL_INFO(dev)->gen >= 8) { 1235 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); 1236 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); 1237 } 1238 1239 if (IS_GEN6(dev)) { 1240 error->forcewake = I915_READ(FORCEWAKE); 1241 error->gab_ctl = I915_READ(GAB_CTL); 1242 error->gfx_mode = I915_READ(GFX_MODE); 1243 } 1244 1245 /* 2: Registers which belong to multiple generations */ 1246 if (INTEL_INFO(dev)->gen >= 7) 1247 error->forcewake = I915_READ(FORCEWAKE_MT); 1248 1249 if (INTEL_INFO(dev)->gen >= 6) { 1250 error->derrmr = I915_READ(DERRMR); 1251 error->error = I915_READ(ERROR_GEN6); 1252 error->done_reg = I915_READ(DONE_REG); 1253 } 1254 1255 /* 3: Feature specific registers */ 1256 if (IS_GEN6(dev) || IS_GEN7(dev)) { 1257 error->gam_ecochk = I915_READ(GAM_ECOCHK); 1258 error->gac_eco = I915_READ(GAC_ECO_BITS); 1259 } 1260 1261 /* 4: Everything else */ 1262 if (HAS_HW_CONTEXTS(dev)) 1263 error->ccid = I915_READ(CCID); 1264 1265 if (INTEL_INFO(dev)->gen >= 8) { 1266 error->ier = I915_READ(GEN8_DE_MISC_IER); 1267 for (i = 0; i < 4; i++) 1268 error->gtier[i] = I915_READ(GEN8_GT_IER(i)); 1269 } else if (HAS_PCH_SPLIT(dev)) { 1270 error->ier = I915_READ(DEIER); 1271 error->gtier[0] = I915_READ(GTIER); 1272 } else if (IS_GEN2(dev)) { 1273 error->ier = I915_READ16(IER); 1274 } else if (!IS_VALLEYVIEW(dev)) { 1275 error->ier = I915_READ(IER); 1276 } 1277 error->eir = I915_READ(EIR); 1278 error->pgtbl_er = I915_READ(PGTBL_ER); 1279 1280 i915_get_extra_instdone(dev, error->extra_instdone); 1281} 1282 1283static void i915_error_capture_msg(struct drm_device *dev, 1284 struct drm_i915_error_state *error, 1285 bool wedged, 1286 const char *error_msg) 1287{ 1288 struct drm_i915_private *dev_priv = dev->dev_private; 1289 u32 ecode; 1290 int ring_id = -1, len; 1291 1292 ecode = i915_error_generate_code(dev_priv, error, &ring_id); 1293 1294 len = scnprintf(error->error_msg, sizeof(error->error_msg), 1295 "GPU HANG: ecode %d:%d:0x%08x", 1296 INTEL_INFO(dev)->gen, ring_id, ecode); 1297 1298 if (ring_id != -1 && error->ring[ring_id].pid != -1) 1299 len += scnprintf(error->error_msg + len, 1300 sizeof(error->error_msg) - len, 1301 ", in %s [%d]", 1302 error->ring[ring_id].comm, 1303 error->ring[ring_id].pid); 1304 1305 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len, 1306 ", reason: %s, action: %s", 1307 error_msg, 1308 wedged ? "reset" : "continue"); 1309} 1310 1311static void i915_capture_gen_state(struct drm_i915_private *dev_priv, 1312 struct drm_i915_error_state *error) 1313{ 1314 error->iommu = -1; 1315#ifdef CONFIG_INTEL_IOMMU 1316 error->iommu = intel_iommu_gfx_mapped; 1317#endif 1318 error->reset_count = i915_reset_count(&dev_priv->gpu_error); 1319 error->suspend_count = dev_priv->suspend_count; 1320} 1321 1322/** 1323 * i915_capture_error_state - capture an error record for later analysis 1324 * @dev: drm device 1325 * 1326 * Should be called when an error is detected (either a hang or an error 1327 * interrupt) to capture error state from the time of the error. Fills 1328 * out a structure which becomes available in debugfs for user level tools 1329 * to pick up. 1330 */ 1331void i915_capture_error_state(struct drm_device *dev, bool wedged, 1332 const char *error_msg) 1333{ 1334 static bool warned; 1335 struct drm_i915_private *dev_priv = dev->dev_private; 1336 struct drm_i915_error_state *error; 1337 unsigned long flags; 1338 1339 /* Account for pipe specific data like PIPE*STAT */ 1340 error = kzalloc(sizeof(*error), GFP_ATOMIC); 1341 if (!error) { 1342 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); 1343 return; 1344 } 1345 1346 kref_init(&error->ref); 1347 1348 i915_capture_gen_state(dev_priv, error); 1349 i915_capture_reg_state(dev_priv, error); 1350 i915_gem_capture_buffers(dev_priv, error); 1351 i915_gem_record_fences(dev, error); 1352 i915_gem_record_rings(dev, error); 1353 1354 do_gettimeofday(&error->time); 1355 1356 error->overlay = intel_overlay_capture_error_state(dev); 1357 error->display = intel_display_capture_error_state(dev); 1358 1359 i915_error_capture_msg(dev, error, wedged, error_msg); 1360 DRM_INFO("%s\n", error->error_msg); 1361 1362 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags); 1363 if (dev_priv->gpu_error.first_error == NULL) { 1364 dev_priv->gpu_error.first_error = error; 1365 error = NULL; 1366 } 1367 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags); 1368 1369 if (error) { 1370 i915_error_state_free(&error->ref); 1371 return; 1372 } 1373 1374 if (!warned) { 1375 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n"); 1376 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n"); 1377 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n"); 1378 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n"); 1379 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n", dev->primary->index); 1380 warned = true; 1381 } 1382} 1383 1384void i915_error_state_get(struct drm_device *dev, 1385 struct i915_error_state_file_priv *error_priv) 1386{ 1387 struct drm_i915_private *dev_priv = dev->dev_private; 1388 1389 spin_lock_irq(&dev_priv->gpu_error.lock); 1390 error_priv->error = dev_priv->gpu_error.first_error; 1391 if (error_priv->error) 1392 kref_get(&error_priv->error->ref); 1393 spin_unlock_irq(&dev_priv->gpu_error.lock); 1394 1395} 1396 1397void i915_error_state_put(struct i915_error_state_file_priv *error_priv) 1398{ 1399 if (error_priv->error) 1400 kref_put(&error_priv->error->ref, i915_error_state_free); 1401} 1402 1403void i915_destroy_error_state(struct drm_device *dev) 1404{ 1405 struct drm_i915_private *dev_priv = dev->dev_private; 1406 struct drm_i915_error_state *error; 1407 1408 spin_lock_irq(&dev_priv->gpu_error.lock); 1409 error = dev_priv->gpu_error.first_error; 1410 dev_priv->gpu_error.first_error = NULL; 1411 spin_unlock_irq(&dev_priv->gpu_error.lock); 1412 1413 if (error) 1414 kref_put(&error->ref, i915_error_state_free); 1415} 1416 1417const char *i915_cache_level_str(struct drm_i915_private *i915, int type) 1418{ 1419 switch (type) { 1420 case I915_CACHE_NONE: return " uncached"; 1421 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped"; 1422 case I915_CACHE_L3_LLC: return " L3+LLC"; 1423 case I915_CACHE_WT: return " WT"; 1424 default: return ""; 1425 } 1426} 1427 1428/* NB: please notice the memset */ 1429void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone) 1430{ 1431 struct drm_i915_private *dev_priv = dev->dev_private; 1432 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); 1433 1434 if (IS_GEN2(dev) || IS_GEN3(dev)) 1435 instdone[0] = I915_READ(GEN2_INSTDONE); 1436 else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { 1437 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1438 instdone[1] = I915_READ(GEN4_INSTDONE1); 1439 } else if (INTEL_INFO(dev)->gen >= 7) { 1440 instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); 1441 instdone[1] = I915_READ(GEN7_SC_INSTDONE); 1442 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE); 1443 instdone[3] = I915_READ(GEN7_ROW_INSTDONE); 1444 } 1445} 1446