1/*	$NetBSD: mmio.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $	*/
2
3/*
4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 *    Ke Yu
27 *    Kevin Tian <kevin.tian@intel.com>
28 *    Dexuan Cui
29 *
30 * Contributors:
31 *    Tina Zhang <tina.zhang@intel.com>
32 *    Min He <min.he@intel.com>
33 *    Niu Bing <bing.niu@intel.com>
34 *    Zhi Wang <zhi.a.wang@intel.com>
35 *
36 */
37
38#ifndef _GVT_MMIO_H_
39#define _GVT_MMIO_H_
40
41#include <linux/types.h>
42
43struct intel_gvt;
44struct intel_vgpu;
45
46#define D_BDW   (1 << 0)
47#define D_SKL	(1 << 1)
48#define D_KBL	(1 << 2)
49#define D_BXT	(1 << 3)
50#define D_CFL	(1 << 4)
51
52#define D_GEN9PLUS	(D_SKL | D_KBL | D_BXT | D_CFL)
53#define D_GEN8PLUS	(D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)
54
55#define D_SKL_PLUS	(D_SKL | D_KBL | D_BXT | D_CFL)
56#define D_BDW_PLUS	(D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)
57
58#define D_PRE_SKL	(D_BDW)
59#define D_ALL		(D_BDW | D_SKL | D_KBL | D_BXT | D_CFL)
60
61typedef int (*gvt_mmio_func)(struct intel_vgpu *, unsigned int, void *,
62			     unsigned int);
63
64struct intel_gvt_mmio_info {
65	u32 offset;
66	u64 ro_mask;
67	u32 device;
68	gvt_mmio_func read;
69	gvt_mmio_func write;
70	u32 addr_range;
71	struct hlist_node node;
72};
73
74int intel_gvt_render_mmio_to_ring_id(struct intel_gvt *gvt,
75		unsigned int reg);
76unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt);
77bool intel_gvt_match_device(struct intel_gvt *gvt, unsigned long device);
78
79int intel_gvt_setup_mmio_info(struct intel_gvt *gvt);
80void intel_gvt_clean_mmio_info(struct intel_gvt *gvt);
81int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
82	int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
83	void *data);
84
85int intel_vgpu_init_mmio(struct intel_vgpu *vgpu);
86void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr);
87void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu);
88
89int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa);
90
91int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
92				void *p_data, unsigned int bytes);
93int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
94				void *p_data, unsigned int bytes);
95
96int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
97				 void *p_data, unsigned int bytes);
98int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
99				  void *p_data, unsigned int bytes);
100
101bool intel_gvt_in_force_nonpriv_whitelist(struct intel_gvt *gvt,
102					  unsigned int offset);
103
104int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
105			   void *pdata, unsigned int bytes, bool is_read);
106
107int intel_vgpu_mask_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
108				  void *p_data, unsigned int bytes);
109#endif
110