1/* $NetBSD: intel_vbt_defs.h,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3/* 4 * Copyright �� 2006-2016 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Eric Anholt <eric@anholt.net> 27 * 28 */ 29 30/* 31 * This information is private to VBT parsing in intel_bios.c. 32 * 33 * Please do NOT include anywhere else. 34 */ 35#ifndef _INTEL_BIOS_PRIVATE 36#error "intel_vbt_defs.h is private to intel_bios.c" 37#endif 38 39#ifndef _INTEL_VBT_DEFS_H_ 40#define _INTEL_VBT_DEFS_H_ 41 42#include "intel_bios.h" 43 44/** 45 * struct vbt_header - VBT Header structure 46 * @signature: VBT signature, always starts with "$VBT" 47 * @version: Version of this structure 48 * @header_size: Size of this structure 49 * @vbt_size: Size of VBT (VBT Header, BDB Header and data blocks) 50 * @vbt_checksum: Checksum 51 * @reserved0: Reserved 52 * @bdb_offset: Offset of &struct bdb_header from beginning of VBT 53 * @aim_offset: Offsets of add-in data blocks from beginning of VBT 54 */ 55struct vbt_header { 56 u8 signature[20]; 57 u16 version; 58 u16 header_size; 59 u16 vbt_size; 60 u8 vbt_checksum; 61 u8 reserved0; 62 u32 bdb_offset; 63 u32 aim_offset[4]; 64} __packed; 65 66/** 67 * struct bdb_header - BDB Header structure 68 * @signature: BDB signature "BIOS_DATA_BLOCK" 69 * @version: Version of the data block definitions 70 * @header_size: Size of this structure 71 * @bdb_size: Size of BDB (BDB Header and data blocks) 72 */ 73struct bdb_header { 74 u8 signature[16]; 75 u16 version; 76 u16 header_size; 77 u16 bdb_size; 78} __packed; 79 80/* 81 * There are several types of BIOS data blocks (BDBs), each block has 82 * an ID and size in the first 3 bytes (ID in first, size in next 2). 83 * Known types are listed below. 84 */ 85enum bdb_block_id { 86 BDB_GENERAL_FEATURES = 1, 87 BDB_GENERAL_DEFINITIONS = 2, 88 BDB_OLD_TOGGLE_LIST = 3, 89 BDB_MODE_SUPPORT_LIST = 4, 90 BDB_GENERIC_MODE_TABLE = 5, 91 BDB_EXT_MMIO_REGS = 6, 92 BDB_SWF_IO = 7, 93 BDB_SWF_MMIO = 8, 94 BDB_PSR = 9, 95 BDB_MODE_REMOVAL_TABLE = 10, 96 BDB_CHILD_DEVICE_TABLE = 11, 97 BDB_DRIVER_FEATURES = 12, 98 BDB_DRIVER_PERSISTENCE = 13, 99 BDB_EXT_TABLE_PTRS = 14, 100 BDB_DOT_CLOCK_OVERRIDE = 15, 101 BDB_DISPLAY_SELECT = 16, 102 BDB_DRIVER_ROTATION = 18, 103 BDB_DISPLAY_REMOVE = 19, 104 BDB_OEM_CUSTOM = 20, 105 BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ 106 BDB_SDVO_LVDS_OPTIONS = 22, 107 BDB_SDVO_PANEL_DTDS = 23, 108 BDB_SDVO_LVDS_PNP_IDS = 24, 109 BDB_SDVO_LVDS_POWER_SEQ = 25, 110 BDB_TV_OPTIONS = 26, 111 BDB_EDP = 27, 112 BDB_LVDS_OPTIONS = 40, 113 BDB_LVDS_LFP_DATA_PTRS = 41, 114 BDB_LVDS_LFP_DATA = 42, 115 BDB_LVDS_BACKLIGHT = 43, 116 BDB_LVDS_POWER = 44, 117 BDB_MIPI_CONFIG = 52, 118 BDB_MIPI_SEQUENCE = 53, 119 BDB_COMPRESSION_PARAMETERS = 56, 120 BDB_GENERIC_DTD = 58, 121 BDB_SKIP = 254, /* VBIOS private block, ignore */ 122}; 123 124/* 125 * Block 1 - General Bit Definitions 126 */ 127 128struct bdb_general_features { 129 /* bits 1 */ 130 u8 panel_fitting:2; 131 u8 flexaim:1; 132 u8 msg_enable:1; 133 u8 clear_screen:3; 134 u8 color_flip:1; 135 136 /* bits 2 */ 137 u8 download_ext_vbt:1; 138 u8 enable_ssc:1; 139 u8 ssc_freq:1; 140 u8 enable_lfp_on_override:1; 141 u8 disable_ssc_ddt:1; 142 u8 underscan_vga_timings:1; 143 u8 display_clock_mode:1; 144 u8 vbios_hotplug_support:1; 145 146 /* bits 3 */ 147 u8 disable_smooth_vision:1; 148 u8 single_dvi:1; 149 u8 rotate_180:1; /* 181 */ 150 u8 fdi_rx_polarity_inverted:1; 151 u8 vbios_extended_mode:1; /* 160 */ 152 u8 copy_ilfp_dtd_to_sdvo_lvds_dtd:1; /* 160 */ 153 u8 panel_best_fit_timing:1; /* 160 */ 154 u8 ignore_strap_state:1; /* 160 */ 155 156 /* bits 4 */ 157 u8 legacy_monitor_detect; 158 159 /* bits 5 */ 160 u8 int_crt_support:1; 161 u8 int_tv_support:1; 162 u8 int_efp_support:1; 163 u8 dp_ssc_enable:1; /* PCH attached eDP supports SSC */ 164 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 165 u8 dp_ssc_dongle_supported:1; 166 u8 rsvd11:2; /* finish byte */ 167} __packed; 168 169/* 170 * Block 2 - General Bytes Definition 171 */ 172 173/* pre-915 */ 174#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 175#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 176#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 177#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 178 179/* Pre 915 */ 180#define DEVICE_TYPE_NONE 0x00 181#define DEVICE_TYPE_CRT 0x01 182#define DEVICE_TYPE_TV 0x09 183#define DEVICE_TYPE_EFP 0x12 184#define DEVICE_TYPE_LFP 0x22 185/* On 915+ */ 186#define DEVICE_TYPE_CRT_DPMS 0x6001 187#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 188#define DEVICE_TYPE_TV_COMPOSITE 0x0209 189#define DEVICE_TYPE_TV_MACROVISION 0x0289 190#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 191#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 192#define DEVICE_TYPE_TV_SCART 0x0209 193#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 194#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 195#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 196#define DEVICE_TYPE_EFP_DVI_I 0x6053 197#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 198#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 199#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 200#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 201#define DEVICE_TYPE_LFP_PANELLINK 0x5012 202#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 203#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 204#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 205#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 206 207/* Add the device class for LFP, TV, HDMI */ 208#define DEVICE_TYPE_INT_LFP 0x1022 209#define DEVICE_TYPE_INT_TV 0x1009 210#define DEVICE_TYPE_HDMI 0x60D2 211#define DEVICE_TYPE_DP 0x68C6 212#define DEVICE_TYPE_DP_DUAL_MODE 0x60D6 213#define DEVICE_TYPE_eDP 0x78C6 214 215#define DEVICE_TYPE_CLASS_EXTENSION (1 << 15) 216#define DEVICE_TYPE_POWER_MANAGEMENT (1 << 14) 217#define DEVICE_TYPE_HOTPLUG_SIGNALING (1 << 13) 218#define DEVICE_TYPE_INTERNAL_CONNECTOR (1 << 12) 219#define DEVICE_TYPE_NOT_HDMI_OUTPUT (1 << 11) 220#define DEVICE_TYPE_MIPI_OUTPUT (1 << 10) 221#define DEVICE_TYPE_COMPOSITE_OUTPUT (1 << 9) 222#define DEVICE_TYPE_DUAL_CHANNEL (1 << 8) 223#define DEVICE_TYPE_HIGH_SPEED_LINK (1 << 6) 224#define DEVICE_TYPE_LVDS_SIGNALING (1 << 5) 225#define DEVICE_TYPE_TMDS_DVI_SIGNALING (1 << 4) 226#define DEVICE_TYPE_VIDEO_SIGNALING (1 << 3) 227#define DEVICE_TYPE_DISPLAYPORT_OUTPUT (1 << 2) 228#define DEVICE_TYPE_DIGITAL_OUTPUT (1 << 1) 229#define DEVICE_TYPE_ANALOG_OUTPUT (1 << 0) 230 231/* 232 * Bits we care about when checking for DEVICE_TYPE_eDP. Depending on the 233 * system, the other bits may or may not be set for eDP outputs. 234 */ 235#define DEVICE_TYPE_eDP_BITS \ 236 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 237 DEVICE_TYPE_MIPI_OUTPUT | \ 238 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 239 DEVICE_TYPE_DUAL_CHANNEL | \ 240 DEVICE_TYPE_LVDS_SIGNALING | \ 241 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 242 DEVICE_TYPE_VIDEO_SIGNALING | \ 243 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 244 DEVICE_TYPE_ANALOG_OUTPUT) 245 246#define DEVICE_TYPE_DP_DUAL_MODE_BITS \ 247 (DEVICE_TYPE_INTERNAL_CONNECTOR | \ 248 DEVICE_TYPE_MIPI_OUTPUT | \ 249 DEVICE_TYPE_COMPOSITE_OUTPUT | \ 250 DEVICE_TYPE_LVDS_SIGNALING | \ 251 DEVICE_TYPE_TMDS_DVI_SIGNALING | \ 252 DEVICE_TYPE_VIDEO_SIGNALING | \ 253 DEVICE_TYPE_DISPLAYPORT_OUTPUT | \ 254 DEVICE_TYPE_DIGITAL_OUTPUT | \ 255 DEVICE_TYPE_ANALOG_OUTPUT) 256 257#define DEVICE_CFG_NONE 0x00 258#define DEVICE_CFG_12BIT_DVOB 0x01 259#define DEVICE_CFG_12BIT_DVOC 0x02 260#define DEVICE_CFG_24BIT_DVOBC 0x09 261#define DEVICE_CFG_24BIT_DVOCB 0x0a 262#define DEVICE_CFG_DUAL_DVOB 0x11 263#define DEVICE_CFG_DUAL_DVOC 0x12 264#define DEVICE_CFG_DUAL_DVOBC 0x13 265#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 266#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 267 268#define DEVICE_WIRE_NONE 0x00 269#define DEVICE_WIRE_DVOB 0x01 270#define DEVICE_WIRE_DVOC 0x02 271#define DEVICE_WIRE_DVOBC 0x03 272#define DEVICE_WIRE_DVOBB 0x05 273#define DEVICE_WIRE_DVOCC 0x06 274#define DEVICE_WIRE_DVOB_MASTER 0x0d 275#define DEVICE_WIRE_DVOC_MASTER 0x0e 276 277/* dvo_port pre BDB 155 */ 278#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 279#define DEVICE_PORT_DVOB 0x01 280#define DEVICE_PORT_DVOC 0x02 281 282/* dvo_port BDB 155+ */ 283#define DVO_PORT_HDMIA 0 284#define DVO_PORT_HDMIB 1 285#define DVO_PORT_HDMIC 2 286#define DVO_PORT_HDMID 3 287#define DVO_PORT_LVDS 4 288#define DVO_PORT_TV 5 289#define DVO_PORT_CRT 6 290#define DVO_PORT_DPB 7 291#define DVO_PORT_DPC 8 292#define DVO_PORT_DPD 9 293#define DVO_PORT_DPA 10 294#define DVO_PORT_DPE 11 /* 193 */ 295#define DVO_PORT_HDMIE 12 /* 193 */ 296#define DVO_PORT_DPF 13 /* N/A */ 297#define DVO_PORT_HDMIF 14 /* N/A */ 298#define DVO_PORT_DPG 15 299#define DVO_PORT_HDMIG 16 300#define DVO_PORT_MIPIA 21 /* 171 */ 301#define DVO_PORT_MIPIB 22 /* 171 */ 302#define DVO_PORT_MIPIC 23 /* 171 */ 303#define DVO_PORT_MIPID 24 /* 171 */ 304 305#define HDMI_MAX_DATA_RATE_PLATFORM 0 /* 204 */ 306#define HDMI_MAX_DATA_RATE_297 1 /* 204 */ 307#define HDMI_MAX_DATA_RATE_165 2 /* 204 */ 308 309#define LEGACY_CHILD_DEVICE_CONFIG_SIZE 33 310 311/* DDC Bus DDI Type 155+ */ 312enum vbt_gmbus_ddi { 313 DDC_BUS_DDI_B = 0x1, 314 DDC_BUS_DDI_C, 315 DDC_BUS_DDI_D, 316 DDC_BUS_DDI_F, 317 ICL_DDC_BUS_DDI_A = 0x1, 318 ICL_DDC_BUS_DDI_B, 319 TGL_DDC_BUS_DDI_C, 320 ICL_DDC_BUS_PORT_1 = 0x4, 321 ICL_DDC_BUS_PORT_2, 322 ICL_DDC_BUS_PORT_3, 323 ICL_DDC_BUS_PORT_4, 324 TGL_DDC_BUS_PORT_5, 325 TGL_DDC_BUS_PORT_6, 326}; 327 328#define DP_AUX_A 0x40 329#define DP_AUX_B 0x10 330#define DP_AUX_C 0x20 331#define DP_AUX_D 0x30 332#define DP_AUX_E 0x50 333#define DP_AUX_F 0x60 334#define DP_AUX_G 0x70 335 336#define VBT_DP_MAX_LINK_RATE_HBR3 0 337#define VBT_DP_MAX_LINK_RATE_HBR2 1 338#define VBT_DP_MAX_LINK_RATE_HBR 2 339#define VBT_DP_MAX_LINK_RATE_LBR 3 340 341/* 342 * The child device config, aka the display device data structure, provides a 343 * description of a port and its configuration on the platform. 344 * 345 * The child device config size has been increased, and fields have been added 346 * and their meaning has changed over time. Care must be taken when accessing 347 * basically any of the fields to ensure the correct interpretation for the BDB 348 * version in question. 349 * 350 * When we copy the child device configs to dev_priv->vbt.child_dev, we reserve 351 * space for the full structure below, and initialize the tail not actually 352 * present in VBT to zeros. Accessing those fields is fine, as long as the 353 * default zero is taken into account, again according to the BDB version. 354 * 355 * BDB versions 155 and below are considered legacy, and version 155 seems to be 356 * a baseline for some of the VBT documentation. When adding new fields, please 357 * include the BDB version when the field was added, if it's above that. 358 */ 359struct child_device_config { 360 u16 handle; 361 u16 device_type; /* See DEVICE_TYPE_* above */ 362 363 union { 364 u8 device_id[10]; /* ascii string */ 365 struct { 366 u8 i2c_speed; 367 u8 dp_onboard_redriver; /* 158 */ 368 u8 dp_ondock_redriver; /* 158 */ 369 u8 hdmi_level_shifter_value:5; /* 169 */ 370 u8 hdmi_max_data_rate:3; /* 204 */ 371 u16 dtd_buf_ptr; /* 161 */ 372 u8 edidless_efp:1; /* 161 */ 373 u8 compression_enable:1; /* 198 */ 374 u8 compression_method_cps:1; /* 198 */ 375 u8 ganged_edp:1; /* 202 */ 376 u8 reserved0:4; 377 u8 compression_structure_index:4; /* 198 */ 378 u8 reserved1:4; 379 u8 slave_port; /* 202 */ 380 u8 reserved2; 381 } __packed; 382 } __packed; 383 384 u16 addin_offset; 385 u8 dvo_port; /* See DEVICE_PORT_* and DVO_PORT_* above */ 386 u8 i2c_pin; 387 u8 slave_addr; 388 u8 ddc_pin; 389 u16 edid_ptr; 390 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 391 392 union { 393 struct { 394 u8 dvo2_port; 395 u8 i2c2_pin; 396 u8 slave2_addr; 397 u8 ddc2_pin; 398 } __packed; 399 struct { 400 u8 efp_routed:1; /* 158 */ 401 u8 lane_reversal:1; /* 184 */ 402 u8 lspcon:1; /* 192 */ 403 u8 iboost:1; /* 196 */ 404 u8 hpd_invert:1; /* 196 */ 405 u8 use_vbt_vswing:1; /* 218 */ 406 u8 flag_reserved:2; 407 u8 hdmi_support:1; /* 158 */ 408 u8 dp_support:1; /* 158 */ 409 u8 tmds_support:1; /* 158 */ 410 u8 support_reserved:5; 411 u8 aux_channel; 412 u8 dongle_detect; 413 } __packed; 414 } __packed; 415 416 u8 pipe_cap:2; 417 u8 sdvo_stall:1; /* 158 */ 418 u8 hpd_status:2; 419 u8 integrated_encoder:1; 420 u8 capabilities_reserved:2; 421 u8 dvo_wiring; /* See DEVICE_WIRE_* above */ 422 423 union { 424 u8 dvo2_wiring; 425 u8 mipi_bridge_type; /* 171 */ 426 } __packed; 427 428 u16 extended_type; 429 u8 dvo_function; 430 u8 dp_usb_type_c:1; /* 195 */ 431 u8 tbt:1; /* 209 */ 432 u8 flags2_reserved:2; /* 195 */ 433 u8 dp_port_trace_length:4; /* 209 */ 434 u8 dp_gpio_index; /* 195 */ 435 u16 dp_gpio_pin_num; /* 195 */ 436 u8 dp_iboost_level:4; /* 196 */ 437 u8 hdmi_iboost_level:4; /* 196 */ 438 u8 dp_max_link_rate:2; /* 216 CNL+ */ 439 u8 dp_max_link_rate_reserved:6; /* 216 */ 440} __packed; 441 442struct bdb_general_definitions { 443 /* DDC GPIO */ 444 u8 crt_ddc_gmbus_pin; 445 446 /* DPMS bits */ 447 u8 dpms_acpi:1; 448 u8 skip_boot_crt_detect:1; 449 u8 dpms_aim:1; 450 u8 rsvd1:5; /* finish byte */ 451 452 /* boot device bits */ 453 u8 boot_display[2]; 454 u8 child_dev_size; 455 456 /* 457 * Device info: 458 * If TV is present, it'll be at devices[0]. 459 * LVDS will be next, either devices[0] or [1], if present. 460 * On some platforms the number of device is 6. But could be as few as 461 * 4 if both TV and LVDS are missing. 462 * And the device num is related with the size of general definition 463 * block. It is obtained by using the following formula: 464 * number = (block_size - sizeof(bdb_general_definitions))/ 465 * defs->child_dev_size; 466 */ 467 u8 devices[0]; 468} __packed; 469 470/* 471 * Block 9 - SRD Feature Block 472 */ 473 474struct psr_table { 475 /* Feature bits */ 476 u8 full_link:1; 477 u8 require_aux_to_wakeup:1; 478 u8 feature_bits_rsvd:6; 479 480 /* Wait times */ 481 u8 idle_frames:4; 482 u8 lines_to_wait:3; 483 u8 wait_times_rsvd:1; 484 485 /* TP wake up time in multiple of 100 */ 486 u16 tp1_wakeup_time; 487 u16 tp2_tp3_wakeup_time; 488} __packed; 489 490struct bdb_psr { 491 struct psr_table psr_table[16]; 492 493 /* PSR2 TP2/TP3 wakeup time for 16 panels */ 494 u32 psr2_tp2_tp3_wakeup_time; 495} __packed; 496 497/* 498 * Block 12 - Driver Features Data Block 499 */ 500 501#define BDB_DRIVER_FEATURE_NO_LVDS 0 502#define BDB_DRIVER_FEATURE_INT_LVDS 1 503#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 504#define BDB_DRIVER_FEATURE_INT_SDVO_LVDS 3 505 506struct bdb_driver_features { 507 u8 boot_dev_algorithm:1; 508 u8 block_display_switch:1; 509 u8 allow_display_switch:1; 510 u8 hotplug_dvo:1; 511 u8 dual_view_zoom:1; 512 u8 int15h_hook:1; 513 u8 sprite_in_clone:1; 514 u8 primary_lfp_id:1; 515 516 u16 boot_mode_x; 517 u16 boot_mode_y; 518 u8 boot_mode_bpp; 519 u8 boot_mode_refresh; 520 521 u16 enable_lfp_primary:1; 522 u16 selective_mode_pruning:1; 523 u16 dual_frequency:1; 524 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 525 u16 nt_clone_support:1; 526 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 527 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 528 u16 cui_aspect_scaling:1; 529 u16 preserve_aspect_ratio:1; 530 u16 sdvo_device_power_down:1; 531 u16 crt_hotplug:1; 532 u16 lvds_config:2; 533 u16 tv_hotplug:1; 534 u16 hdmi_config:2; 535 536 u8 static_display:1; 537 u8 reserved2:7; 538 u16 legacy_crt_max_x; 539 u16 legacy_crt_max_y; 540 u8 legacy_crt_max_refresh; 541 542 u8 hdmi_termination; 543 u8 custom_vbt_version; 544 /* Driver features data block */ 545 u16 rmpm_enabled:1; 546 u16 s2ddt_enabled:1; 547 u16 dpst_enabled:1; 548 u16 bltclt_enabled:1; 549 u16 adb_enabled:1; 550 u16 drrs_enabled:1; 551 u16 grs_enabled:1; 552 u16 gpmt_enabled:1; 553 u16 tbt_enabled:1; 554 u16 psr_enabled:1; 555 u16 ips_enabled:1; 556 u16 reserved3:4; 557 u16 pc_feature_valid:1; 558} __packed; 559 560/* 561 * Block 22 - SDVO LVDS General Options 562 */ 563 564struct bdb_sdvo_lvds_options { 565 u8 panel_backlight; 566 u8 h40_set_panel_type; 567 u8 panel_type; 568 u8 ssc_clk_freq; 569 u16 als_low_trip; 570 u16 als_high_trip; 571 u8 sclalarcoeff_tab_row_num; 572 u8 sclalarcoeff_tab_row_size; 573 u8 coefficient[8]; 574 u8 panel_misc_bits_1; 575 u8 panel_misc_bits_2; 576 u8 panel_misc_bits_3; 577 u8 panel_misc_bits_4; 578} __packed; 579 580/* 581 * Block 23 - SDVO LVDS Panel DTDs 582 */ 583 584struct lvds_dvo_timing { 585 u16 clock; /**< In 10khz */ 586 u8 hactive_lo; 587 u8 hblank_lo; 588 u8 hblank_hi:4; 589 u8 hactive_hi:4; 590 u8 vactive_lo; 591 u8 vblank_lo; 592 u8 vblank_hi:4; 593 u8 vactive_hi:4; 594 u8 hsync_off_lo; 595 u8 hsync_pulse_width_lo; 596 u8 vsync_pulse_width_lo:4; 597 u8 vsync_off_lo:4; 598 u8 vsync_pulse_width_hi:2; 599 u8 vsync_off_hi:2; 600 u8 hsync_pulse_width_hi:2; 601 u8 hsync_off_hi:2; 602 u8 himage_lo; 603 u8 vimage_lo; 604 u8 vimage_hi:4; 605 u8 himage_hi:4; 606 u8 h_border; 607 u8 v_border; 608 u8 rsvd1:3; 609 u8 digital:2; 610 u8 vsync_positive:1; 611 u8 hsync_positive:1; 612 u8 non_interlaced:1; 613} __packed; 614 615struct bdb_sdvo_panel_dtds { 616 struct lvds_dvo_timing dtds[4]; 617} __packed; 618 619/* 620 * Block 27 - eDP VBT Block 621 */ 622 623#define EDP_18BPP 0 624#define EDP_24BPP 1 625#define EDP_30BPP 2 626#define EDP_RATE_1_62 0 627#define EDP_RATE_2_7 1 628#define EDP_LANE_1 0 629#define EDP_LANE_2 1 630#define EDP_LANE_4 3 631#define EDP_PREEMPHASIS_NONE 0 632#define EDP_PREEMPHASIS_3_5dB 1 633#define EDP_PREEMPHASIS_6dB 2 634#define EDP_PREEMPHASIS_9_5dB 3 635#define EDP_VSWING_0_4V 0 636#define EDP_VSWING_0_6V 1 637#define EDP_VSWING_0_8V 2 638#define EDP_VSWING_1_2V 3 639 640 641struct edp_fast_link_params { 642 u8 rate:4; 643 u8 lanes:4; 644 u8 preemphasis:4; 645 u8 vswing:4; 646} __packed; 647 648struct edp_pwm_delays { 649 u16 pwm_on_to_backlight_enable; 650 u16 backlight_disable_to_pwm_off; 651} __packed; 652 653struct edp_full_link_params { 654 u8 preemphasis:4; 655 u8 vswing:4; 656} __packed; 657 658struct bdb_edp { 659 struct edp_power_seq power_seqs[16]; 660 u32 color_depth; 661 struct edp_fast_link_params fast_link_params[16]; 662 u32 sdrrs_msa_timing_delay; 663 664 /* ith bit indicates enabled/disabled for (i+1)th panel */ 665 u16 edp_s3d_feature; /* 162 */ 666 u16 edp_t3_optimization; /* 165 */ 667 u64 edp_vswing_preemph; /* 173 */ 668 u16 fast_link_training; /* 182 */ 669 u16 dpcd_600h_write_required; /* 185 */ 670 struct edp_pwm_delays pwm_delays[16]; /* 186 */ 671 u16 full_link_params_provided; /* 199 */ 672 struct edp_full_link_params full_link_params[16]; /* 199 */ 673} __packed; 674 675/* 676 * Block 40 - LFP Data Block 677 */ 678 679/* Mask for DRRS / Panel Channel / SSC / BLT control bits extraction */ 680#define MODE_MASK 0x3 681 682struct bdb_lvds_options { 683 u8 panel_type; 684 u8 panel_type2; /* 212 */ 685 /* LVDS capabilities, stored in a dword */ 686 u8 pfit_mode:2; 687 u8 pfit_text_mode_enhanced:1; 688 u8 pfit_gfx_mode_enhanced:1; 689 u8 pfit_ratio_auto:1; 690 u8 pixel_dither:1; 691 u8 lvds_edid:1; 692 u8 rsvd2:1; 693 u8 rsvd4; 694 /* LVDS Panel channel bits stored here */ 695 u32 lvds_panel_channel_bits; 696 /* LVDS SSC (Spread Spectrum Clock) bits stored here. */ 697 u16 ssc_bits; 698 u16 ssc_freq; 699 u16 ssc_ddt; 700 /* Panel color depth defined here */ 701 u16 panel_color_depth; 702 /* LVDS panel type bits stored here */ 703 u32 dps_panel_type_bits; 704 /* LVDS backlight control type bits stored here */ 705 u32 blt_control_type_bits; 706 707 u16 lcdvcc_s0_enable; /* 200 */ 708 u32 rotation; /* 228 */ 709} __packed; 710 711/* 712 * Block 41 - LFP Data Table Pointers 713 */ 714 715/* LFP pointer table contains entries to the struct below */ 716struct lvds_lfp_data_ptr { 717 u16 fp_timing_offset; /* offsets are from start of bdb */ 718 u8 fp_table_size; 719 u16 dvo_timing_offset; 720 u8 dvo_table_size; 721 u16 panel_pnp_id_offset; 722 u8 pnp_table_size; 723} __packed; 724 725struct bdb_lvds_lfp_data_ptrs { 726 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 727 struct lvds_lfp_data_ptr ptr[16]; 728} __packed; 729 730/* 731 * Block 42 - LFP Data Tables 732 */ 733 734/* LFP data has 3 blocks per entry */ 735struct lvds_fp_timing { 736 u16 x_res; 737 u16 y_res; 738 u32 lvds_reg; 739 u32 lvds_reg_val; 740 u32 pp_on_reg; 741 u32 pp_on_reg_val; 742 u32 pp_off_reg; 743 u32 pp_off_reg_val; 744 u32 pp_cycle_reg; 745 u32 pp_cycle_reg_val; 746 u32 pfit_reg; 747 u32 pfit_reg_val; 748 u16 terminator; 749} __packed; 750 751struct lvds_pnp_id { 752 u16 mfg_name; 753 u16 product_code; 754 u32 serial; 755 u8 mfg_week; 756 u8 mfg_year; 757} __packed; 758 759struct lvds_lfp_data_entry { 760 struct lvds_fp_timing fp_timing; 761 struct lvds_dvo_timing dvo_timing; 762 struct lvds_pnp_id pnp_id; 763} __packed; 764 765struct bdb_lvds_lfp_data { 766 struct lvds_lfp_data_entry data[16]; 767} __packed; 768 769/* 770 * Block 43 - LFP Backlight Control Data Block 771 */ 772 773#define BDB_BACKLIGHT_TYPE_NONE 0 774#define BDB_BACKLIGHT_TYPE_PWM 2 775 776struct lfp_backlight_data_entry { 777 u8 type:2; 778 u8 active_low_pwm:1; 779 u8 obsolete1:5; 780 u16 pwm_freq_hz; 781 u8 min_brightness; 782 u8 obsolete2; 783 u8 obsolete3; 784} __packed; 785 786struct lfp_backlight_control_method { 787 u8 type:4; 788 u8 controller:4; 789} __packed; 790 791struct bdb_lfp_backlight_data { 792 u8 entry_size; 793 struct lfp_backlight_data_entry data[16]; 794 u8 level[16]; 795 struct lfp_backlight_control_method backlight_control[16]; 796} __packed; 797 798/* 799 * Block 44 - LFP Power Conservation Features Block 800 */ 801 802struct als_data_entry { 803 u16 backlight_adjust; 804 u16 lux; 805} __packed; 806 807struct agressiveness_profile_entry { 808 u8 dpst_agressiveness : 4; 809 u8 lace_agressiveness : 4; 810} __packed; 811 812struct bdb_lfp_power { 813 u8 lfp_feature_bits; 814 struct als_data_entry als[5]; 815 u8 lace_aggressiveness_profile; 816 u16 dpst; 817 u16 psr; 818 u16 drrs; 819 u16 lace_support; 820 u16 adt; 821 u16 dmrrs; 822 u16 adb; 823 u16 lace_enabled_status; 824 struct agressiveness_profile_entry aggressivenes[16]; 825} __packed; 826 827/* 828 * Block 52 - MIPI Configuration Block 829 */ 830 831#define MAX_MIPI_CONFIGURATIONS 6 832 833struct bdb_mipi_config { 834 struct mipi_config config[MAX_MIPI_CONFIGURATIONS]; 835 struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; 836} __packed; 837 838/* 839 * Block 53 - MIPI Sequence Block 840 */ 841 842struct bdb_mipi_sequence { 843 u8 version; 844 u8 data[0]; /* up to 6 variable length blocks */ 845} __packed; 846 847/* 848 * Block 56 - Compression Parameters 849 */ 850 851#define VBT_RC_BUFFER_BLOCK_SIZE_1KB 0 852#define VBT_RC_BUFFER_BLOCK_SIZE_4KB 1 853#define VBT_RC_BUFFER_BLOCK_SIZE_16KB 2 854#define VBT_RC_BUFFER_BLOCK_SIZE_64KB 3 855 856#define VBT_DSC_LINE_BUFFER_DEPTH(vbt_value) ((vbt_value) + 8) /* bits */ 857#define VBT_DSC_MAX_BPP(vbt_value) (6 + (vbt_value) * 2) 858 859struct dsc_compression_parameters_entry { 860 u8 version_major:4; 861 u8 version_minor:4; 862 863 u8 rc_buffer_block_size:2; 864 u8 reserved1:6; 865 866 /* 867 * Buffer size in bytes: 868 * 869 * 4 ^ rc_buffer_block_size * 1024 * (rc_buffer_size + 1) bytes 870 */ 871 u8 rc_buffer_size; 872 u32 slices_per_line; 873 874 u8 line_buffer_depth:4; 875 u8 reserved2:4; 876 877 /* Flag Bits 1 */ 878 u8 block_prediction_enable:1; 879 u8 reserved3:7; 880 881 u8 max_bpp; /* mapping */ 882 883 /* Color depth capabilities */ 884 u8 reserved4:1; 885 u8 support_8bpc:1; 886 u8 support_10bpc:1; 887 u8 support_12bpc:1; 888 u8 reserved5:4; 889 890 u16 slice_height; 891} __packed; 892 893struct bdb_compression_parameters { 894 u16 entry_size; 895 struct dsc_compression_parameters_entry data[16]; 896} __packed; 897 898/* 899 * Block 58 - Generic DTD Block 900 */ 901 902struct generic_dtd_entry { 903 u32 pixel_clock; 904 u16 hactive; 905 u16 hblank; 906 u16 hfront_porch; 907 u16 hsync; 908 u16 vactive; 909 u16 vblank; 910 u16 vfront_porch; 911 u16 vsync; 912 u16 width_mm; 913 u16 height_mm; 914 915 /* Flags */ 916 u8 rsvd_flags:6; 917 u8 vsync_positive_polarity:1; 918 u8 hsync_positive_polarity:1; 919 920 u8 rsvd[3]; 921} __packed; 922 923struct bdb_generic_dtd { 924 u16 gdtd_size; 925 struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ 926} __packed; 927 928#endif /* _INTEL_VBT_DEFS_H_ */ 929