1/*	$NetBSD: smu10_driver_if.h,v 1.2 2021/12/18 23:45:26 riastradh Exp $	*/
2
3/*
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26#ifndef SMU10_DRIVER_IF_H
27#define SMU10_DRIVER_IF_H
28
29#define SMU10_DRIVER_IF_VERSION 0x6
30
31#define NUM_DSPCLK_LEVELS 8
32
33typedef struct {
34	int32_t value;
35	uint32_t numFractionalBits;
36} FloatInIntFormat_t;
37
38typedef enum {
39	DSPCLK_DCEFCLK = 0,
40	DSPCLK_DISPCLK,
41	DSPCLK_PIXCLK,
42	DSPCLK_PHYCLK,
43	DSPCLK_COUNT,
44} DSPCLK_e;
45
46typedef struct {
47	uint16_t Freq;
48	uint16_t Vid;
49} DisplayClockTable_t;
50
51
52typedef struct {
53	uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */
54	uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */
55	uint16_t MinMclk;
56	uint16_t MaxMclk;
57
58	uint8_t  WmSetting;
59	uint8_t  Padding[3];
60} WatermarkRowGeneric_t;
61
62#define NUM_WM_RANGES 4
63
64typedef enum {
65	WM_SOCCLK = 0,
66	WM_DCFCLK,
67	WM_COUNT,
68} WM_CLOCK_e;
69
70typedef struct {
71	WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
72	uint32_t              MmHubPadding[7];
73} Watermarks_t;
74
75typedef enum {
76	CUSTOM_DPM_SETTING_GFXCLK,
77	CUSTOM_DPM_SETTING_CCLK,
78	CUSTOM_DPM_SETTING_FCLK_CCX,
79	CUSTOM_DPM_SETTING_FCLK_GFX,
80	CUSTOM_DPM_SETTING_FCLK_STALLS,
81	CUSTOM_DPM_SETTING_LCLK,
82	CUSTOM_DPM_SETTING_COUNT,
83} CUSTOM_DPM_SETTING_e;
84
85typedef struct {
86	uint8_t             ActiveHystLimit;
87	uint8_t             IdleHystLimit;
88	uint8_t             FPS;
89	uint8_t             MinActiveFreqType;
90	FloatInIntFormat_t  MinActiveFreq;
91	FloatInIntFormat_t  PD_Data_limit;
92	FloatInIntFormat_t  PD_Data_time_constant;
93	FloatInIntFormat_t  PD_Data_error_coeff;
94	FloatInIntFormat_t  PD_Data_error_rate_coeff;
95} DpmActivityMonitorCoeffExt_t;
96
97typedef struct {
98	DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
99} CustomDpmSettings_t;
100
101#define NUM_SOCCLK_DPM_LEVELS  8
102#define NUM_DCEFCLK_DPM_LEVELS 4
103#define NUM_FCLK_DPM_LEVELS    4
104#define NUM_MEMCLK_DPM_LEVELS  4
105
106typedef struct {
107	uint32_t  Freq; /* In MHz */
108	uint32_t  Vol;  /* Millivolts with 2 fractional bits */
109} DpmClock_t;
110
111typedef struct {
112	DpmClock_t DcefClocks[NUM_DCEFCLK_DPM_LEVELS];
113	DpmClock_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
114	DpmClock_t FClocks[NUM_FCLK_DPM_LEVELS];
115	DpmClock_t MemClocks[NUM_MEMCLK_DPM_LEVELS];
116} DpmClocks_t;
117
118#endif
119