1/* $NetBSD: amdgpu_vega10_powertune.c,v 1.3 2021/12/19 12:21:30 riastradh Exp $ */ 2 3/* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26#include <sys/cdefs.h> 27__KERNEL_RCSID(0, "$NetBSD: amdgpu_vega10_powertune.c,v 1.3 2021/12/19 12:21:30 riastradh Exp $"); 28 29#include "hwmgr.h" 30#include "vega10_hwmgr.h" 31#include "vega10_smumgr.h" 32#include "vega10_powertune.h" 33#include "vega10_ppsmc.h" 34#include "vega10_inc.h" 35#include "pp_debug.h" 36#include "soc15_common.h" 37 38static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = 39{ 40/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 41 * Offset Mask Shift Value 42 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 43 */ 44 /* DIDT_SQ */ 45 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 }, 46 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 }, 47 48 /* DIDT_TD */ 49 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde }, 50 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde }, 51 52 /* DIDT_TCP */ 53 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, 54 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, 55 56 /* DIDT_DB */ 57 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde }, 58 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde }, 59 60 { 0xFFFFFFFF } /* End of list */ 61}; 62 63static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = 64{ 65/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 66 * Offset Mask Shift Value 67 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 68 */ 69 /*DIDT_SQ_CTRL3 */ 70 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 71 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 72 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 73 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 74 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 75 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 76 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 77 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 78 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 79 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 80 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 81 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 82 83 /*DIDT_TCP_CTRL3 */ 84 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 85 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 86 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 87 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 88 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 89 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 90 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 91 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 92 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 93 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 94 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 95 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 96 97 /*DIDT_TD_CTRL3 */ 98 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 99 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 100 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 101 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 102 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 103 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 104 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 105 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 106 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 107 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 108 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 109 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 110 111 /*DIDT_DB_CTRL3 */ 112 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 }, 113 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 114 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 }, 115 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 116 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 }, 117 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 }, 118 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 119 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 }, 120 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 }, 121 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 }, 122 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 }, 123 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 }, 124 125 { 0xFFFFFFFF } /* End of list */ 126}; 127 128static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = 129{ 130/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 131 * Offset Mask Shift Value 132 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 133 */ 134 /* DIDT_SQ */ 135 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 }, 136 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 137 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 }, 138 139 /* DIDT_TD */ 140 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff }, 141 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 142 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 143 144 /* DIDT_TCP */ 145 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, 146 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 147 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 148 149 /* DIDT_DB */ 150 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde }, 151 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 }, 152 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 }, 153 154 { 0xFFFFFFFF } /* End of list */ 155}; 156 157static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = 158{ 159/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 160 * Offset Mask Shift Value 161 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 162 */ 163 /* DIDT_SQ */ 164 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 165 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff }, 166 /* DIDT_TD */ 167 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 168 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff }, 169 /* DIDT_TCP */ 170 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 171 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff }, 172 /* DIDT_DB */ 173 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 }, 174 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff }, 175 176 { 0xFFFFFFFF } /* End of list */ 177}; 178 179 180static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = 181{ 182/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 183 * Offset Mask Shift Value 184 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 185 */ 186 /* DIDT_SQ */ 187 { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A }, 188 { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 }, 189 { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 }, 190 191 /* DIDT_TD */ 192 { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F }, 193 { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 }, 194 { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, 195 196 /* DIDT_TCP */ 197 { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D }, 198 { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 }, 199 { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 }, 200 201 /* DIDT_DB */ 202 { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F }, 203 { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 }, 204 { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 }, 205 206 { 0xFFFFFFFF } /* End of list */ 207}; 208 209static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = 210{ 211/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 212 * Offset Mask Shift Value 213 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 214 */ 215 /* DIDT_SQ */ 216 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 217 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 218 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 219 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 220 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 221 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 222 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 223 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 224 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 225 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 226 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 227 /* DIDT_TD */ 228 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 229 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 230 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 231 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 232 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 233 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 234 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 235 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 236 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 237 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 238 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 239 /* DIDT_TCP */ 240 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 241 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 242 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 243 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 244 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 245 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 246 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 247 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 248 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 249 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 250 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 251 /* DIDT_DB */ 252 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 253 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 254 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 }, 255 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 256 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 }, 257 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 }, 258 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 }, 259 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff }, 260 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 }, 261 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 }, 262 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 }, 263 264 { 0xFFFFFFFF } /* End of list */ 265}; 266 267 268static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = 269{ 270/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 271 * Offset Mask Shift Value 272 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 273 */ 274 /* DIDT_SQ */ 275 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, 276 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, 277 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 278 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 279 280 /* DIDT_TD */ 281 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, 282 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, 283 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 284 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 285 286 /* DIDT_TCP */ 287 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 }, 288 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 }, 289 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 290 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 291 292 /* DIDT_DB */ 293 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 }, 294 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 }, 295 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a }, 296 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a }, 297 298 { 0xFFFFFFFF } /* End of list */ 299}; 300 301static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = 302{ 303/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 304 * Offset Mask Shift Value 305 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 306 */ 307 /* DIDT_SQ_STALL_PATTERN_1_2 */ 308 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 309 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 310 311 /* DIDT_SQ_STALL_PATTERN_3_4 */ 312 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 313 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 314 315 /* DIDT_SQ_STALL_PATTERN_5_6 */ 316 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 317 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 318 319 /* DIDT_SQ_STALL_PATTERN_7 */ 320 { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 321 322 /* DIDT_TCP_STALL_PATTERN_1_2 */ 323 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 324 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 325 326 /* DIDT_TCP_STALL_PATTERN_3_4 */ 327 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 328 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 329 330 /* DIDT_TCP_STALL_PATTERN_5_6 */ 331 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 332 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 333 334 /* DIDT_TCP_STALL_PATTERN_7 */ 335 { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 336 337 /* DIDT_TD_STALL_PATTERN_1_2 */ 338 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 339 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 340 341 /* DIDT_TD_STALL_PATTERN_3_4 */ 342 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 343 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 344 345 /* DIDT_TD_STALL_PATTERN_5_6 */ 346 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 347 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 348 349 /* DIDT_TD_STALL_PATTERN_7 */ 350 { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 351 352 /* DIDT_DB_STALL_PATTERN_1_2 */ 353 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 }, 354 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 }, 355 356 /* DIDT_DB_STALL_PATTERN_3_4 */ 357 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 }, 358 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 }, 359 360 /* DIDT_DB_STALL_PATTERN_5_6 */ 361 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 }, 362 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 }, 363 364 /* DIDT_DB_STALL_PATTERN_7 */ 365 { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 }, 366 367 { 0xFFFFFFFF } /* End of list */ 368}; 369 370static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = 371{ 372/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 373 * Offset Mask Shift Value 374 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 375 */ 376 /* SQ */ 377 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 }, 378 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 }, 379 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 }, 380 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 }, 381 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 }, 382 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 }, 383 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 }, 384 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 }, 385 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 }, 386 /* TD */ 387 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 }, 388 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 }, 389 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 }, 390 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 }, 391 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 }, 392 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 }, 393 /* TCP */ 394 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 }, 395 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 }, 396 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 }, 397 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 }, 398 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 }, 399 /* DB */ 400 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 }, 401 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 }, 402 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 }, 403 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 }, 404 405 { 0xFFFFFFFF } /* End of list */ 406}; 407 408 409static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = 410{ 411/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 412 * Offset Mask Shift Value 413 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 414 */ 415 /* SQ */ 416 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 }, 417 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 }, 418 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F }, 419 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F }, 420 /* TD */ 421 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 422 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 423 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 424 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 425 /* TCP */ 426 { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 427 { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 428 { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 429 { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 430 /* DB */ 431 { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 }, 432 { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 433 { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 434 { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 435 436 { 0xFFFFFFFF } /* End of list */ 437}; 438 439static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = 440{ 441/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 442 * Offset Mask Shift Value 443 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 444 */ 445 /* SQ */ 446 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, 447 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 448 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 449 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 450 /* TD */ 451 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 }, 452 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 }, 453 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 }, 454 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 }, 455 456 { 0xFFFFFFFF } /* End of list */ 457}; 458 459static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = 460{ 461/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 462 * Offset Mask Shift Value 463 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 464 */ 465 /* SQ */ 466 { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 467 { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 468 { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 469 { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 470 /* TD */ 471 { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 472 { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 473 { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 474 { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 475 /* TCP */ 476 { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 477 { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 }, 478 { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 }, 479 { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 }, 480 /* DB */ 481 { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 }, 482 483 { 0xFFFFFFFF } /* End of list */ 484}; 485 486static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = 487{ 488/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 489 * Offset Mask Shift Value 490 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 491 */ 492 { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E }, 493 { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 494 { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 495 { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF }, 496 497 { 0xFFFFFFFF } /* End of list */ 498}; 499 500static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = 501{ 502/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 503 * Offset Mask Shift Value 504 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 505 */ 506 /* SQ */ 507 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 508 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 509 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 510 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 511 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 512 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, 513 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 514 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 515 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 516 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 517 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 518 519 { 0xFFFFFFFF } /* End of list */ 520}; 521 522static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = 523{ 524/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 525 * Offset Mask Shift Value 526 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 527 */ 528 /* SQ */ 529 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 530 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 531 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 532 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 533 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 }, 534 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 }, 535 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 536 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 537 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 538 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 539 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 540 541 { 0xFFFFFFFF } /* End of list */ 542}; 543 544static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = 545{ 546/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 547 * Offset Mask Shift Value 548 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 549 */ 550 /* SQ */ 551 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 552 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 553 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 554 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, 555 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, 556 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C }, 557 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 558 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 559 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 560 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 561 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 562 563 /* TD */ 564 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 565 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 566 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 567 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 }, 568 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 }, 569 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, 570 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 571 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 572 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 573 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 574 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 575 576 { 0xFFFFFFFF } /* End of list */ 577}; 578 579static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = 580{ 581/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 582 * Offset Mask Shift Value 583 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 584 */ 585 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 }, 586 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 }, 587 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 }, 588 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 }, 589 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 }, 590 591 { 0xFFFFFFFF } /* End of list */ 592}; 593 594static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = 595{ 596/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 597 * Offset Mask Shift Value 598 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 599 */ 600 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 }, 601 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 }, 602 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 }, 603 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 604 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 605 { 0xFFFFFFFF } /* End of list */ 606}; 607 608 609static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = 610{ 611/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 612 * Offset Mask Shift Value 613 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 614 */ 615 /* SQ EDC STALL PATTERNs */ 616 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 }, 617 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 }, 618 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 }, 619 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 }, 620 621 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 }, 622 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 }, 623 624 { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 }, 625 626 { 0xFFFFFFFF } /* End of list */ 627}; 628 629static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = 630{ 631/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 632 * Offset Mask Shift Value 633 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 634 */ 635 /* SQ EDC STALL DELAYs */ 636 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 }, 637 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 }, 638 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 }, 639 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 }, 640 641 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 }, 642 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 }, 643 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 }, 644 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 }, 645 646 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 }, 647 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 }, 648 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 }, 649 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 }, 650 651 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 }, 652 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 }, 653 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 }, 654 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 }, 655 656 { 0xFFFFFFFF } /* End of list */ 657}; 658 659static const struct vega10_didt_config_reg PSMSEEDCThresholdConfig_Vega10[] __unused = 660{ 661/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 662 * Offset Mask Shift Value 663 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 664 */ 665 /* SQ EDC THRESHOLD */ 666 { ixDIDT_SQ_EDC_THRESHOLD, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD_MASK, DIDT_SQ_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000 }, 667 668 { 0xFFFFFFFF } /* End of list */ 669}; 670 671static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = 672{ 673/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 674 * Offset Mask Shift Value 675 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 676 */ 677 /* SQ EDC CTRL */ 678 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 679 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 680 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 681 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 682 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 683 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 }, 684 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 685 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 }, 686 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 }, 687 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 688 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 689 690 { 0xFFFFFFFF } /* End of list */ 691}; 692 693static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = 694{ 695/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 696 * Offset Mask Shift Value 697 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 698 */ 699 /* SQ EDC CTRL */ 700 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 701 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 702 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 703 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 704 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 705 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E }, 706 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 707 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 }, 708 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 }, 709 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 }, 710 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 }, 711 712 { 0xFFFFFFFF } /* End of list */ 713}; 714 715static const struct vega10_didt_config_reg PSMGCEDCThresholdConfig_vega10[] __unused = 716{ 717/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 718 * Offset Mask Shift Value 719 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 720 */ 721 { mmGC_EDC_THRESHOLD, GC_EDC_THRESHOLD__EDC_THRESHOLD_MASK, GC_EDC_THRESHOLD__EDC_THRESHOLD__SHIFT, 0x0000000 }, 722 723 { 0xFFFFFFFF } /* End of list */ 724}; 725 726static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = 727{ 728/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 729 * Offset Mask Shift Value 730 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 731 */ 732 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 }, 733 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 }, 734 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 }, 735 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 }, 736 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 }, 737 738 { 0xFFFFFFFF } /* End of list */ 739}; 740 741static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = 742{ 743/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 744 * Offset Mask Shift Value 745 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 746 */ 747 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 }, 748 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 }, 749 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 750 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 751 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 752 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 753 754 { 0xFFFFFFFF } /* End of list */ 755}; 756 757static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = 758{ 759/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 760 * Offset Mask Shift Value 761 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 762 */ 763 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 }, 764 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 }, 765 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 }, 766 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 }, 767 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 }, 768 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 }, 769 770 { 0xFFFFFFFF } /* End of list */ 771}; 772 773static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[]= 774{ 775/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 776 * Offset Mask Shift Value 777 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 778 */ 779 { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F }, 780 { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 }, 781 { 0x16A06, 0x00000001, 0x0, 0x02000000 }, 782 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, 783 784 { 0xFFFFFFFF } /* End of list */ 785}; 786 787static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = 788{ 789/* --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 790 * Offset Mask Shift Value 791 * --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 792 */ 793 { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 }, 794 { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 }, 795 { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 }, 796 { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 }, 797 { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 }, 798 { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 }, 799 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 }, 800 801 { 0xFFFFFFFF } /* End of list */ 802}; 803 804static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type) 805{ 806 uint32_t data; 807 808 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL); 809 810 while (config_regs->offset != 0xFFFFFFFF) { 811 switch (reg_type) { 812 case VEGA10_CONFIGREG_DIDT: 813 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset); 814 data &= ~config_regs->mask; 815 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 816 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data); 817 break; 818 case VEGA10_CONFIGREG_GCCAC: 819 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset); 820 data &= ~config_regs->mask; 821 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 822 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data); 823 break; 824 case VEGA10_CONFIGREG_SECAC: 825 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset); 826 data &= ~config_regs->mask; 827 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 828 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data); 829 break; 830 default: 831 return -EINVAL; 832 } 833 834 config_regs++; 835 } 836 837 return 0; 838} 839 840static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs) 841{ 842 uint32_t data; 843 844 while (config_regs->offset != 0xFFFFFFFF) { 845 data = cgs_read_register(hwmgr->device, config_regs->offset); 846 data &= ~config_regs->mask; 847 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 848 cgs_write_register(hwmgr->device, config_regs->offset, data); 849 config_regs++; 850 } 851 852 return 0; 853} 854 855static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) 856{ 857 uint32_t data; 858 uint32_t en = (enable ? 1 : 0); 859 uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK; 860 861 if (PP_CAP(PHM_PlatformCaps_SQRamping)) { 862 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 863 DIDT_SQ_CTRL0, DIDT_CTRL_EN, en); 864 didt_block_info &= ~SQ_Enable_MASK; 865 didt_block_info |= en << SQ_Enable_SHIFT; 866 } 867 868 if (PP_CAP(PHM_PlatformCaps_DBRamping)) { 869 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 870 DIDT_DB_CTRL0, DIDT_CTRL_EN, en); 871 didt_block_info &= ~DB_Enable_MASK; 872 didt_block_info |= en << DB_Enable_SHIFT; 873 } 874 875 if (PP_CAP(PHM_PlatformCaps_TDRamping)) { 876 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 877 DIDT_TD_CTRL0, DIDT_CTRL_EN, en); 878 didt_block_info &= ~TD_Enable_MASK; 879 didt_block_info |= en << TD_Enable_SHIFT; 880 } 881 882 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { 883 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 884 DIDT_TCP_CTRL0, DIDT_CTRL_EN, en); 885 didt_block_info &= ~TCP_Enable_MASK; 886 didt_block_info |= en << TCP_Enable_SHIFT; 887 } 888 889 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { 890 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, 891 DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); 892 } 893 894 if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) { 895 if (PP_CAP(PHM_PlatformCaps_SQRamping)) { 896 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL); 897 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en); 898 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en); 899 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data); 900 } 901 902 if (PP_CAP(PHM_PlatformCaps_DBRamping)) { 903 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL); 904 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en); 905 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en); 906 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data); 907 } 908 909 if (PP_CAP(PHM_PlatformCaps_TDRamping)) { 910 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL); 911 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en); 912 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en); 913 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data); 914 } 915 916 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) { 917 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL); 918 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en); 919 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en); 920 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data); 921 } 922 923 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { 924 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL); 925 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en); 926 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en); 927 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data); 928 } 929 } 930 931 /* For Vega10, SMC does not support any mask yet. */ 932 if (enable) 933 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info); 934 935} 936 937static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 938{ 939 struct amdgpu_device *adev = hwmgr->adev; 940 int result; 941 uint32_t num_se = 0, count, data; 942 943 num_se = adev->gfx.config.max_shader_engines; 944 945 amdgpu_gfx_rlc_enter_safe_mode(adev); 946 947 mutex_lock(&adev->grbm_idx_mutex); 948 for (count = 0; count < num_se; count++) { 949 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 950 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 951 952 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 953 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); 954 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); 955 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT); 956 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT); 957 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); 958 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 959 result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC); 960 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); 961 962 if (0 != result) 963 break; 964 } 965 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 966 mutex_unlock(&adev->grbm_idx_mutex); 967 968 vega10_didt_set_mask(hwmgr, true); 969 970 amdgpu_gfx_rlc_exit_safe_mode(adev); 971 972 return 0; 973} 974 975static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr) 976{ 977 struct amdgpu_device *adev = hwmgr->adev; 978 979 amdgpu_gfx_rlc_enter_safe_mode(adev); 980 981 vega10_didt_set_mask(hwmgr, false); 982 983 amdgpu_gfx_rlc_exit_safe_mode(adev); 984 985 return 0; 986} 987 988static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 989{ 990 struct amdgpu_device *adev = hwmgr->adev; 991 int result; 992 uint32_t num_se = 0, count, data; 993 994 num_se = adev->gfx.config.max_shader_engines; 995 996 amdgpu_gfx_rlc_enter_safe_mode(adev); 997 998 mutex_lock(&adev->grbm_idx_mutex); 999 for (count = 0; count < num_se; count++) { 1000 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1001 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1002 1003 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT); 1004 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT); 1005 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT); 1006 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT); 1007 if (0 != result) 1008 break; 1009 } 1010 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1011 mutex_unlock(&adev->grbm_idx_mutex); 1012 1013 vega10_didt_set_mask(hwmgr, true); 1014 1015 amdgpu_gfx_rlc_exit_safe_mode(adev); 1016 1017 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10); 1018 if (PP_CAP(PHM_PlatformCaps_GCEDC)) 1019 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10); 1020 1021 if (PP_CAP(PHM_PlatformCaps_PSM)) 1022 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); 1023 1024 return 0; 1025} 1026 1027static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) 1028{ 1029 struct amdgpu_device *adev = hwmgr->adev; 1030 uint32_t data; 1031 1032 amdgpu_gfx_rlc_enter_safe_mode(adev); 1033 1034 vega10_didt_set_mask(hwmgr, false); 1035 1036 amdgpu_gfx_rlc_exit_safe_mode(adev); 1037 1038 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1039 data = 0x00000000; 1040 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data); 1041 } 1042 1043 if (PP_CAP(PHM_PlatformCaps_PSM)) 1044 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1045 1046 return 0; 1047} 1048 1049static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr) 1050{ 1051 struct amdgpu_device *adev = hwmgr->adev; 1052 int result; 1053 uint32_t num_se = 0, count, data; 1054 1055 num_se = adev->gfx.config.max_shader_engines; 1056 1057 amdgpu_gfx_rlc_enter_safe_mode(adev); 1058 1059 mutex_lock(&adev->grbm_idx_mutex); 1060 for (count = 0; count < num_se; count++) { 1061 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1062 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1063 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1064 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1065 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1066 result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1067 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1068 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1069 1070 if (0 != result) 1071 break; 1072 } 1073 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1074 mutex_unlock(&adev->grbm_idx_mutex); 1075 1076 vega10_didt_set_mask(hwmgr, true); 1077 1078 amdgpu_gfx_rlc_exit_safe_mode(adev); 1079 1080 return 0; 1081} 1082 1083static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr) 1084{ 1085 struct amdgpu_device *adev = hwmgr->adev; 1086 1087 amdgpu_gfx_rlc_enter_safe_mode(adev); 1088 1089 vega10_didt_set_mask(hwmgr, false); 1090 1091 amdgpu_gfx_rlc_exit_safe_mode(adev); 1092 1093 return 0; 1094} 1095 1096static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1097{ 1098 struct amdgpu_device *adev = hwmgr->adev; 1099 int result = 0; 1100 uint32_t num_se = 0; 1101 uint32_t count, data; 1102 1103 num_se = adev->gfx.config.max_shader_engines; 1104 1105 amdgpu_gfx_rlc_enter_safe_mode(adev); 1106 1107 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1108 1109 mutex_lock(&adev->grbm_idx_mutex); 1110 for (count = 0; count < num_se; count++) { 1111 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | ( count << GRBM_GFX_INDEX__SE_INDEX__SHIFT); 1112 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 1113 result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1114 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1115 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1116 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1117 1118 if (0 != result) 1119 break; 1120 } 1121 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1122 mutex_unlock(&adev->grbm_idx_mutex); 1123 1124 vega10_didt_set_mask(hwmgr, true); 1125 1126 amdgpu_gfx_rlc_exit_safe_mode(adev); 1127 1128 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10); 1129 1130 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1131 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10); 1132 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10); 1133 } 1134 1135 if (PP_CAP(PHM_PlatformCaps_PSM)) 1136 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10); 1137 1138 return 0; 1139} 1140 1141static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) 1142{ 1143 struct amdgpu_device *adev = hwmgr->adev; 1144 uint32_t data; 1145 1146 amdgpu_gfx_rlc_enter_safe_mode(adev); 1147 1148 vega10_didt_set_mask(hwmgr, false); 1149 1150 amdgpu_gfx_rlc_exit_safe_mode(adev); 1151 1152 if (PP_CAP(PHM_PlatformCaps_GCEDC)) { 1153 data = 0x00000000; 1154 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data); 1155 } 1156 1157 if (PP_CAP(PHM_PlatformCaps_PSM)) 1158 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10); 1159 1160 return 0; 1161} 1162 1163static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1164{ 1165 struct amdgpu_device *adev = hwmgr->adev; 1166 int result; 1167 1168 amdgpu_gfx_rlc_enter_safe_mode(adev); 1169 1170 mutex_lock(&adev->grbm_idx_mutex); 1171 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); 1172 mutex_unlock(&adev->grbm_idx_mutex); 1173 1174 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1175 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT); 1176 if (0 != result) 1177 return result; 1178 1179 vega10_didt_set_mask(hwmgr, false); 1180 1181 amdgpu_gfx_rlc_exit_safe_mode(adev); 1182 1183 return 0; 1184} 1185 1186static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr) 1187{ 1188 int result; 1189 1190 result = vega10_disable_se_edc_config(hwmgr); 1191 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result); 1192 1193 return 0; 1194} 1195 1196int vega10_enable_didt_config(struct pp_hwmgr *hwmgr) 1197{ 1198 int result = 0; 1199 struct vega10_hwmgr *data = hwmgr->backend; 1200 1201 if (data->smu_features[GNLD_DIDT].supported) { 1202 if (data->smu_features[GNLD_DIDT].enabled) 1203 PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n"); 1204 1205 switch (data->registry_data.didt_mode) { 1206 case 0: 1207 result = vega10_enable_cac_driving_se_didt_config(hwmgr); 1208 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result); 1209 break; 1210 case 2: 1211 result = vega10_enable_psm_gc_didt_config(hwmgr); 1212 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result); 1213 break; 1214 case 3: 1215 result = vega10_enable_se_edc_config(hwmgr); 1216 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result); 1217 break; 1218 case 1: 1219 case 4: 1220 case 5: 1221 result = vega10_enable_psm_gc_edc_config(hwmgr); 1222 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result); 1223 break; 1224 case 6: 1225 result = vega10_enable_se_edc_force_stall_config(hwmgr); 1226 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result); 1227 break; 1228 default: 1229 result = -EINVAL; 1230 break; 1231 } 1232 1233 if (0 == result) { 1234 result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap); 1235 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result); 1236 data->smu_features[GNLD_DIDT].enabled = true; 1237 } 1238 } 1239 1240 return result; 1241} 1242 1243int vega10_disable_didt_config(struct pp_hwmgr *hwmgr) 1244{ 1245 int result = 0; 1246 struct vega10_hwmgr *data = hwmgr->backend; 1247 1248 if (data->smu_features[GNLD_DIDT].supported) { 1249 if (!data->smu_features[GNLD_DIDT].enabled) 1250 PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n"); 1251 1252 switch (data->registry_data.didt_mode) { 1253 case 0: 1254 result = vega10_disable_cac_driving_se_didt_config(hwmgr); 1255 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result); 1256 break; 1257 case 2: 1258 result = vega10_disable_psm_gc_didt_config(hwmgr); 1259 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result); 1260 break; 1261 case 3: 1262 result = vega10_disable_se_edc_config(hwmgr); 1263 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result); 1264 break; 1265 case 1: 1266 case 4: 1267 case 5: 1268 result = vega10_disable_psm_gc_edc_config(hwmgr); 1269 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result); 1270 break; 1271 case 6: 1272 result = vega10_disable_se_edc_force_stall_config(hwmgr); 1273 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result); 1274 break; 1275 default: 1276 result = -EINVAL; 1277 break; 1278 } 1279 1280 if (0 == result) { 1281 result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap); 1282 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result); 1283 data->smu_features[GNLD_DIDT].enabled = false; 1284 } 1285 } 1286 1287 return result; 1288} 1289 1290void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) 1291{ 1292 struct vega10_hwmgr *data = hwmgr->backend; 1293 struct phm_ppt_v2_information *table_info = 1294 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1295 struct phm_tdp_table *tdp_table = table_info->tdp_table; 1296 PPTable_t *table = &(data->smc_state_table.pp_table); 1297 1298 table->SocketPowerLimit = cpu_to_le16( 1299 tdp_table->usMaximumPowerDeliveryLimit); 1300 table->TdcLimit = cpu_to_le16(tdp_table->usTDC); 1301 table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit); 1302 table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge); 1303 table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot); 1304 table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM); 1305 table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc); 1306 table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd); 1307 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1); 1308 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2); 1309 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx); 1310 table->LoadLineResistance = 1311 hwmgr->platform_descriptor.LoadLineSlope * 256; 1312 table->FitLimit = 0; /* Not used for Vega10 */ 1313 1314 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address; 1315 table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address; 1316 table->Vr_I2C_address = tdp_table->ucVr_I2C_address; 1317 table->Plx_I2C_address = tdp_table->ucPlx_I2C_address; 1318 1319 table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line; 1320 table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA; 1321 1322 table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line; 1323 table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA; 1324 1325 table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line; 1326 table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA; 1327} 1328 1329int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) 1330{ 1331 struct vega10_hwmgr *data = hwmgr->backend; 1332 1333 if (data->registry_data.enable_pkg_pwr_tracking_feature) 1334 smum_send_msg_to_smc_with_parameter(hwmgr, 1335 PPSMC_MSG_SetPptLimit, n); 1336 1337 return 0; 1338} 1339 1340int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) 1341{ 1342 struct vega10_hwmgr *data = hwmgr->backend; 1343 struct phm_ppt_v2_information *table_info = 1344 (struct phm_ppt_v2_information *)(hwmgr->pptable); 1345 struct phm_tdp_table *tdp_table = table_info->tdp_table; 1346 int result = 0; 1347 1348 hwmgr->default_power_limit = hwmgr->power_limit = 1349 (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit); 1350 1351 if (!hwmgr->not_vf) 1352 return 0; 1353 1354 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1355 if (data->smu_features[GNLD_PPT].supported) 1356 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1357 true, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1358 "Attempt to enable PPT feature Failed!", 1359 data->smu_features[GNLD_PPT].supported = false); 1360 1361 if (data->smu_features[GNLD_TDC].supported) 1362 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1363 true, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1364 "Attempt to enable PPT feature Failed!", 1365 data->smu_features[GNLD_TDC].supported = false); 1366 1367 result = vega10_set_power_limit(hwmgr, hwmgr->power_limit); 1368 PP_ASSERT_WITH_CODE(!result, 1369 "Failed to set Default Power Limit in SMC!", 1370 return result); 1371 } 1372 1373 return result; 1374} 1375 1376int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) 1377{ 1378 struct vega10_hwmgr *data = hwmgr->backend; 1379 1380 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1381 if (data->smu_features[GNLD_PPT].supported) 1382 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1383 false, data->smu_features[GNLD_PPT].smu_feature_bitmap), 1384 "Attempt to disable PPT feature Failed!", 1385 data->smu_features[GNLD_PPT].supported = false); 1386 1387 if (data->smu_features[GNLD_TDC].supported) 1388 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr, 1389 false, data->smu_features[GNLD_TDC].smu_feature_bitmap), 1390 "Attempt to disable PPT feature Failed!", 1391 data->smu_features[GNLD_TDC].supported = false); 1392 } 1393 1394 return 0; 1395} 1396 1397static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr, 1398 uint32_t adjust_percent) 1399{ 1400 smum_send_msg_to_smc_with_parameter(hwmgr, 1401 PPSMC_MSG_OverDriveSetPercentage, adjust_percent); 1402} 1403 1404int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) 1405{ 1406 int adjust_percent; 1407 1408 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) { 1409 adjust_percent = 1410 hwmgr->platform_descriptor.TDPAdjustmentPolarity ? 1411 hwmgr->platform_descriptor.TDPAdjustment : 1412 (-1 * hwmgr->platform_descriptor.TDPAdjustment); 1413 vega10_set_overdrive_target_percentage(hwmgr, 1414 (uint32_t)adjust_percent); 1415 } 1416 return 0; 1417} 1418