1/* $NetBSD: smuio_9_0_offset.h,v 1.2 2021/12/18 23:45:23 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _smuio_9_0_OFFSET_HEADER 24#define _smuio_9_0_OFFSET_HEADER 25 26 27 28// addressBlock: smuio_smuio_SmuSmuioDec 29// base address: 0x5a000 30#define mmROM_CNTL 0x0024 31#define mmROM_CNTL_BASE_IDX 0 32#define mmROM_STATUS 0x0026 33#define mmROM_STATUS_BASE_IDX 0 34#define mmCGTT_ROM_CLK_CTRL0 0x0027 35#define mmCGTT_ROM_CLK_CTRL0_BASE_IDX 0 36#define mmROM_INDEX 0x0028 37#define mmROM_INDEX_BASE_IDX 0 38#define mmROM_DATA 0x0029 39#define mmROM_DATA_BASE_IDX 0 40#define mmROM_START 0x002a 41#define mmROM_START_BASE_IDX 0 42#define mmROM_SW_CNTL 0x002b 43#define mmROM_SW_CNTL_BASE_IDX 0 44#define mmROM_SW_STATUS 0x002c 45#define mmROM_SW_STATUS_BASE_IDX 0 46#define mmROM_SW_COMMAND 0x002d 47#define mmROM_SW_COMMAND_BASE_IDX 0 48#define mmROM_SW_DATA_1 0x002e 49#define mmROM_SW_DATA_1_BASE_IDX 0 50#define mmROM_SW_DATA_2 0x002f 51#define mmROM_SW_DATA_2_BASE_IDX 0 52#define mmROM_SW_DATA_3 0x0030 53#define mmROM_SW_DATA_3_BASE_IDX 0 54#define mmROM_SW_DATA_4 0x0031 55#define mmROM_SW_DATA_4_BASE_IDX 0 56#define mmROM_SW_DATA_5 0x0032 57#define mmROM_SW_DATA_5_BASE_IDX 0 58#define mmROM_SW_DATA_6 0x0033 59#define mmROM_SW_DATA_6_BASE_IDX 0 60#define mmROM_SW_DATA_7 0x0034 61#define mmROM_SW_DATA_7_BASE_IDX 0 62#define mmROM_SW_DATA_8 0x0035 63#define mmROM_SW_DATA_8_BASE_IDX 0 64#define mmROM_SW_DATA_9 0x0036 65#define mmROM_SW_DATA_9_BASE_IDX 0 66#define mmROM_SW_DATA_10 0x0037 67#define mmROM_SW_DATA_10_BASE_IDX 0 68#define mmROM_SW_DATA_11 0x0038 69#define mmROM_SW_DATA_11_BASE_IDX 0 70#define mmROM_SW_DATA_12 0x0039 71#define mmROM_SW_DATA_12_BASE_IDX 0 72#define mmROM_SW_DATA_13 0x003a 73#define mmROM_SW_DATA_13_BASE_IDX 0 74#define mmROM_SW_DATA_14 0x003b 75#define mmROM_SW_DATA_14_BASE_IDX 0 76#define mmROM_SW_DATA_15 0x003c 77#define mmROM_SW_DATA_15_BASE_IDX 0 78#define mmROM_SW_DATA_16 0x003d 79#define mmROM_SW_DATA_16_BASE_IDX 0 80#define mmROM_SW_DATA_17 0x003e 81#define mmROM_SW_DATA_17_BASE_IDX 0 82#define mmROM_SW_DATA_18 0x003f 83#define mmROM_SW_DATA_18_BASE_IDX 0 84#define mmROM_SW_DATA_19 0x0040 85#define mmROM_SW_DATA_19_BASE_IDX 0 86#define mmROM_SW_DATA_20 0x0041 87#define mmROM_SW_DATA_20_BASE_IDX 0 88#define mmROM_SW_DATA_21 0x0042 89#define mmROM_SW_DATA_21_BASE_IDX 0 90#define mmROM_SW_DATA_22 0x0043 91#define mmROM_SW_DATA_22_BASE_IDX 0 92#define mmROM_SW_DATA_23 0x0044 93#define mmROM_SW_DATA_23_BASE_IDX 0 94#define mmROM_SW_DATA_24 0x0045 95#define mmROM_SW_DATA_24_BASE_IDX 0 96#define mmROM_SW_DATA_25 0x0046 97#define mmROM_SW_DATA_25_BASE_IDX 0 98#define mmROM_SW_DATA_26 0x0047 99#define mmROM_SW_DATA_26_BASE_IDX 0 100#define mmROM_SW_DATA_27 0x0048 101#define mmROM_SW_DATA_27_BASE_IDX 0 102#define mmROM_SW_DATA_28 0x0049 103#define mmROM_SW_DATA_28_BASE_IDX 0 104#define mmROM_SW_DATA_29 0x004a 105#define mmROM_SW_DATA_29_BASE_IDX 0 106#define mmROM_SW_DATA_30 0x004b 107#define mmROM_SW_DATA_30_BASE_IDX 0 108#define mmROM_SW_DATA_31 0x004c 109#define mmROM_SW_DATA_31_BASE_IDX 0 110#define mmROM_SW_DATA_32 0x004d 111#define mmROM_SW_DATA_32_BASE_IDX 0 112#define mmROM_SW_DATA_33 0x004e 113#define mmROM_SW_DATA_33_BASE_IDX 0 114#define mmROM_SW_DATA_34 0x004f 115#define mmROM_SW_DATA_34_BASE_IDX 0 116#define mmROM_SW_DATA_35 0x0050 117#define mmROM_SW_DATA_35_BASE_IDX 0 118#define mmROM_SW_DATA_36 0x0051 119#define mmROM_SW_DATA_36_BASE_IDX 0 120#define mmROM_SW_DATA_37 0x0052 121#define mmROM_SW_DATA_37_BASE_IDX 0 122#define mmROM_SW_DATA_38 0x0053 123#define mmROM_SW_DATA_38_BASE_IDX 0 124#define mmROM_SW_DATA_39 0x0054 125#define mmROM_SW_DATA_39_BASE_IDX 0 126#define mmROM_SW_DATA_40 0x0055 127#define mmROM_SW_DATA_40_BASE_IDX 0 128#define mmROM_SW_DATA_41 0x0056 129#define mmROM_SW_DATA_41_BASE_IDX 0 130#define mmROM_SW_DATA_42 0x0057 131#define mmROM_SW_DATA_42_BASE_IDX 0 132#define mmROM_SW_DATA_43 0x0058 133#define mmROM_SW_DATA_43_BASE_IDX 0 134#define mmROM_SW_DATA_44 0x0059 135#define mmROM_SW_DATA_44_BASE_IDX 0 136#define mmROM_SW_DATA_45 0x005a 137#define mmROM_SW_DATA_45_BASE_IDX 0 138#define mmROM_SW_DATA_46 0x005b 139#define mmROM_SW_DATA_46_BASE_IDX 0 140#define mmROM_SW_DATA_47 0x005c 141#define mmROM_SW_DATA_47_BASE_IDX 0 142#define mmROM_SW_DATA_48 0x005d 143#define mmROM_SW_DATA_48_BASE_IDX 0 144#define mmROM_SW_DATA_49 0x005e 145#define mmROM_SW_DATA_49_BASE_IDX 0 146#define mmROM_SW_DATA_50 0x005f 147#define mmROM_SW_DATA_50_BASE_IDX 0 148#define mmROM_SW_DATA_51 0x0060 149#define mmROM_SW_DATA_51_BASE_IDX 0 150#define mmROM_SW_DATA_52 0x0061 151#define mmROM_SW_DATA_52_BASE_IDX 0 152#define mmROM_SW_DATA_53 0x0062 153#define mmROM_SW_DATA_53_BASE_IDX 0 154#define mmROM_SW_DATA_54 0x0063 155#define mmROM_SW_DATA_54_BASE_IDX 0 156#define mmROM_SW_DATA_55 0x0064 157#define mmROM_SW_DATA_55_BASE_IDX 0 158#define mmROM_SW_DATA_56 0x0065 159#define mmROM_SW_DATA_56_BASE_IDX 0 160#define mmROM_SW_DATA_57 0x0066 161#define mmROM_SW_DATA_57_BASE_IDX 0 162#define mmROM_SW_DATA_58 0x0067 163#define mmROM_SW_DATA_58_BASE_IDX 0 164#define mmROM_SW_DATA_59 0x0068 165#define mmROM_SW_DATA_59_BASE_IDX 0 166#define mmROM_SW_DATA_60 0x0069 167#define mmROM_SW_DATA_60_BASE_IDX 0 168#define mmROM_SW_DATA_61 0x006a 169#define mmROM_SW_DATA_61_BASE_IDX 0 170#define mmROM_SW_DATA_62 0x006b 171#define mmROM_SW_DATA_62_BASE_IDX 0 172#define mmROM_SW_DATA_63 0x006c 173#define mmROM_SW_DATA_63_BASE_IDX 0 174#define mmROM_SW_DATA_64 0x006d 175#define mmROM_SW_DATA_64_BASE_IDX 0 176 177#define mmSMUSVI0_PLANE0_CURRENTVID_BASE_IDX 0 178#define mmSMUSVI0_PLANE0_CURRENTVID 0x0013 179 180#define mmSMUSVI0_TEL_PLANE0_BASE_IDX 0 181#define mmSMUSVI0_TEL_PLANE0 0x0004 182 183#endif 184