sdma3_4_2_2_offset.h revision 1.1
160484Sobrien/* $NetBSD: sdma3_4_2_2_offset.h,v 1.1 2021/12/18 20:15:07 riastradh Exp $ */ 277298Sobrien 360484Sobrien/* 460484Sobrien * Copyright (C) 2018 Advanced Micro Devices, Inc. 560484Sobrien * 660484Sobrien * Permission is hereby granted, free of charge, to any person obtaining a 760484Sobrien * copy of this software and associated documentation files (the "Software"), 860484Sobrien * to deal in the Software without restriction, including without limitation 960484Sobrien * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1060484Sobrien * and/or sell copies of the Software, and to permit persons to whom the 1160484Sobrien * Software is furnished to do so, subject to the following conditions: 1260484Sobrien * 1360484Sobrien * The above copyright notice and this permission notice shall be included 1460484Sobrien * in all copies or substantial portions of the Software. 1560484Sobrien * 1660484Sobrien * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 1760484Sobrien * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 1860484Sobrien * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 1960484Sobrien * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 2060484Sobrien * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 2160484Sobrien * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 2260484Sobrien */ 2360484Sobrien#ifndef _sdma3_4_2_2_OFFSET_HEADER 2460484Sobrien#define _sdma3_4_2_2_OFFSET_HEADER 2560484Sobrien 2660484Sobrien 2760484Sobrien 2860484Sobrien// addressBlock: sdma3_sdma3dec 2960484Sobrien// base address: 0x79000 3060484Sobrien#define mmSDMA3_UCODE_ADDR 0x0000 3160484Sobrien#define mmSDMA3_UCODE_ADDR_BASE_IDX 1 3260484Sobrien#define mmSDMA3_UCODE_DATA 0x0001 3360484Sobrien#define mmSDMA3_UCODE_DATA_BASE_IDX 1 3460484Sobrien#define mmSDMA3_VM_CNTL 0x0004 3560484Sobrien#define mmSDMA3_VM_CNTL_BASE_IDX 1 3660484Sobrien#define mmSDMA3_VM_CTX_LO 0x0005 3760484Sobrien#define mmSDMA3_VM_CTX_LO_BASE_IDX 1 3860484Sobrien#define mmSDMA3_VM_CTX_HI 0x0006 3960484Sobrien#define mmSDMA3_VM_CTX_HI_BASE_IDX 1 4060484Sobrien#define mmSDMA3_ACTIVE_FCN_ID 0x0007 4160484Sobrien#define mmSDMA3_ACTIVE_FCN_ID_BASE_IDX 1 4260484Sobrien#define mmSDMA3_VM_CTX_CNTL 0x0008 4360484Sobrien#define mmSDMA3_VM_CTX_CNTL_BASE_IDX 1 4460484Sobrien#define mmSDMA3_VIRT_RESET_REQ 0x0009 4560484Sobrien#define mmSDMA3_VIRT_RESET_REQ_BASE_IDX 1 4660484Sobrien#define mmSDMA3_VF_ENABLE 0x000a 4760484Sobrien#define mmSDMA3_VF_ENABLE_BASE_IDX 1 4860484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE0 0x000b 4960484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE0_BASE_IDX 1 5060484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE1 0x000c 5160484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE1_BASE_IDX 1 5260484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE2 0x000d 5360484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE2_BASE_IDX 1 5460484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE3 0x000e 5560484Sobrien#define mmSDMA3_CONTEXT_REG_TYPE3_BASE_IDX 1 5660484Sobrien#define mmSDMA3_PUB_REG_TYPE0 0x000f 5760484Sobrien#define mmSDMA3_PUB_REG_TYPE0_BASE_IDX 1 5860484Sobrien#define mmSDMA3_PUB_REG_TYPE1 0x0010 5960484Sobrien#define mmSDMA3_PUB_REG_TYPE1_BASE_IDX 1 6060484Sobrien#define mmSDMA3_PUB_REG_TYPE2 0x0011 6160484Sobrien#define mmSDMA3_PUB_REG_TYPE2_BASE_IDX 1 6260484Sobrien#define mmSDMA3_PUB_REG_TYPE3 0x0012 6360484Sobrien#define mmSDMA3_PUB_REG_TYPE3_BASE_IDX 1 6460484Sobrien#define mmSDMA3_MMHUB_CNTL 0x0013 6560484Sobrien#define mmSDMA3_MMHUB_CNTL_BASE_IDX 1 6660484Sobrien#define mmSDMA3_CONTEXT_GROUP_BOUNDARY 0x0019 6760484Sobrien#define mmSDMA3_CONTEXT_GROUP_BOUNDARY_BASE_IDX 1 6860484Sobrien#define mmSDMA3_POWER_CNTL 0x001a 6960484Sobrien#define mmSDMA3_POWER_CNTL_BASE_IDX 1 7060484Sobrien#define mmSDMA3_CLK_CTRL 0x001b 7160484Sobrien#define mmSDMA3_CLK_CTRL_BASE_IDX 1 7260484Sobrien#define mmSDMA3_CNTL 0x001c 7377298Sobrien#define mmSDMA3_CNTL_BASE_IDX 1 7477298Sobrien#define mmSDMA3_CHICKEN_BITS 0x001d 7577298Sobrien#define mmSDMA3_CHICKEN_BITS_BASE_IDX 1 7677298Sobrien#define mmSDMA3_GB_ADDR_CONFIG 0x001e 7760484Sobrien#define mmSDMA3_GB_ADDR_CONFIG_BASE_IDX 1 7860484Sobrien#define mmSDMA3_GB_ADDR_CONFIG_READ 0x001f 7960484Sobrien#define mmSDMA3_GB_ADDR_CONFIG_READ_BASE_IDX 1 8060484Sobrien#define mmSDMA3_RB_RPTR_FETCH_HI 0x0020 8160484Sobrien#define mmSDMA3_RB_RPTR_FETCH_HI_BASE_IDX 1 8260484Sobrien#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL 0x0021 8360484Sobrien#define mmSDMA3_SEM_WAIT_FAIL_TIMER_CNTL_BASE_IDX 1 8460484Sobrien#define mmSDMA3_RB_RPTR_FETCH 0x0022 8560484Sobrien#define mmSDMA3_RB_RPTR_FETCH_BASE_IDX 1 8660484Sobrien#define mmSDMA3_IB_OFFSET_FETCH 0x0023 8760484Sobrien#define mmSDMA3_IB_OFFSET_FETCH_BASE_IDX 1 8877298Sobrien#define mmSDMA3_PROGRAM 0x0024 8960484Sobrien#define mmSDMA3_PROGRAM_BASE_IDX 1 9060484Sobrien#define mmSDMA3_STATUS_REG 0x0025 9160484Sobrien#define mmSDMA3_STATUS_REG_BASE_IDX 1 9260484Sobrien#define mmSDMA3_STATUS1_REG 0x0026 9360484Sobrien#define mmSDMA3_STATUS1_REG_BASE_IDX 1 9460484Sobrien#define mmSDMA3_RD_BURST_CNTL 0x0027 9560484Sobrien#define mmSDMA3_RD_BURST_CNTL_BASE_IDX 1 9660484Sobrien#define mmSDMA3_HBM_PAGE_CONFIG 0x0028 9760484Sobrien#define mmSDMA3_HBM_PAGE_CONFIG_BASE_IDX 1 9860484Sobrien#define mmSDMA3_UCODE_CHECKSUM 0x0029 9960484Sobrien#define mmSDMA3_UCODE_CHECKSUM_BASE_IDX 1 10060484Sobrien#define mmSDMA3_F32_CNTL 0x002a 10160484Sobrien#define mmSDMA3_F32_CNTL_BASE_IDX 1 10260484Sobrien#define mmSDMA3_FREEZE 0x002b 10360484Sobrien#define mmSDMA3_FREEZE_BASE_IDX 1 10460484Sobrien#define mmSDMA3_PHASE0_QUANTUM 0x002c 10560484Sobrien#define mmSDMA3_PHASE0_QUANTUM_BASE_IDX 1 10660484Sobrien#define mmSDMA3_PHASE1_QUANTUM 0x002d 10760484Sobrien#define mmSDMA3_PHASE1_QUANTUM_BASE_IDX 1 10860484Sobrien#define mmSDMA3_EDC_CONFIG 0x0032 10960484Sobrien#define mmSDMA3_EDC_CONFIG_BASE_IDX 1 11060484Sobrien#define mmSDMA3_BA_THRESHOLD 0x0033 11160484Sobrien#define mmSDMA3_BA_THRESHOLD_BASE_IDX 1 11260484Sobrien#define mmSDMA3_ID 0x0034 11360484Sobrien#define mmSDMA3_ID_BASE_IDX 1 11460484Sobrien#define mmSDMA3_VERSION 0x0035 11560484Sobrien#define mmSDMA3_VERSION_BASE_IDX 1 11660484Sobrien#define mmSDMA3_EDC_COUNTER 0x0036 11760484Sobrien#define mmSDMA3_EDC_COUNTER_BASE_IDX 1 11877298Sobrien#define mmSDMA3_EDC_COUNTER_CLEAR 0x0037 11960484Sobrien#define mmSDMA3_EDC_COUNTER_CLEAR_BASE_IDX 1 12060484Sobrien#define mmSDMA3_STATUS2_REG 0x0038 12160484Sobrien#define mmSDMA3_STATUS2_REG_BASE_IDX 1 12260484Sobrien#define mmSDMA3_ATOMIC_CNTL 0x0039 12360484Sobrien#define mmSDMA3_ATOMIC_CNTL_BASE_IDX 1 12460484Sobrien#define mmSDMA3_ATOMIC_PREOP_LO 0x003a 12560484Sobrien#define mmSDMA3_ATOMIC_PREOP_LO_BASE_IDX 1 12660484Sobrien#define mmSDMA3_ATOMIC_PREOP_HI 0x003b 12760484Sobrien#define mmSDMA3_ATOMIC_PREOP_HI_BASE_IDX 1 12860484Sobrien#define mmSDMA3_UTCL1_CNTL 0x003c 12960484Sobrien#define mmSDMA3_UTCL1_CNTL_BASE_IDX 1 13060484Sobrien#define mmSDMA3_UTCL1_WATERMK 0x003d 13160484Sobrien#define mmSDMA3_UTCL1_WATERMK_BASE_IDX 1 13260484Sobrien#define mmSDMA3_UTCL1_RD_STATUS 0x003e 13360484Sobrien#define mmSDMA3_UTCL1_RD_STATUS_BASE_IDX 1 13460484Sobrien#define mmSDMA3_UTCL1_WR_STATUS 0x003f 13560484Sobrien#define mmSDMA3_UTCL1_WR_STATUS_BASE_IDX 1 13660484Sobrien#define mmSDMA3_UTCL1_INV0 0x0040 13760484Sobrien#define mmSDMA3_UTCL1_INV0_BASE_IDX 1 13860484Sobrien#define mmSDMA3_UTCL1_INV1 0x0041 13960484Sobrien#define mmSDMA3_UTCL1_INV1_BASE_IDX 1 14060484Sobrien#define mmSDMA3_UTCL1_INV2 0x0042 14160484Sobrien#define mmSDMA3_UTCL1_INV2_BASE_IDX 1 14260484Sobrien#define mmSDMA3_UTCL1_RD_XNACK0 0x0043 14360484Sobrien#define mmSDMA3_UTCL1_RD_XNACK0_BASE_IDX 1 14460484Sobrien#define mmSDMA3_UTCL1_RD_XNACK1 0x0044 14560484Sobrien#define mmSDMA3_UTCL1_RD_XNACK1_BASE_IDX 1 14660484Sobrien#define mmSDMA3_UTCL1_WR_XNACK0 0x0045 14760484Sobrien#define mmSDMA3_UTCL1_WR_XNACK0_BASE_IDX 1 14860484Sobrien#define mmSDMA3_UTCL1_WR_XNACK1 0x0046 14960484Sobrien#define mmSDMA3_UTCL1_WR_XNACK1_BASE_IDX 1 15060484Sobrien#define mmSDMA3_UTCL1_TIMEOUT 0x0047 15160484Sobrien#define mmSDMA3_UTCL1_TIMEOUT_BASE_IDX 1 15260484Sobrien#define mmSDMA3_UTCL1_PAGE 0x0048 15360484Sobrien#define mmSDMA3_UTCL1_PAGE_BASE_IDX 1 15460484Sobrien#define mmSDMA3_POWER_CNTL_IDLE 0x0049 15560484Sobrien#define mmSDMA3_POWER_CNTL_IDLE_BASE_IDX 1 15677298Sobrien#define mmSDMA3_RELAX_ORDERING_LUT 0x004a 15760484Sobrien#define mmSDMA3_RELAX_ORDERING_LUT_BASE_IDX 1 15860484Sobrien#define mmSDMA3_CHICKEN_BITS_2 0x004b 15960484Sobrien#define mmSDMA3_CHICKEN_BITS_2_BASE_IDX 1 16060484Sobrien#define mmSDMA3_STATUS3_REG 0x004c 16160484Sobrien#define mmSDMA3_STATUS3_REG_BASE_IDX 1 16260484Sobrien#define mmSDMA3_PHYSICAL_ADDR_LO 0x004d 16360484Sobrien#define mmSDMA3_PHYSICAL_ADDR_LO_BASE_IDX 1 16460484Sobrien#define mmSDMA3_PHYSICAL_ADDR_HI 0x004e 16560484Sobrien#define mmSDMA3_PHYSICAL_ADDR_HI_BASE_IDX 1 16660484Sobrien#define mmSDMA3_PHASE2_QUANTUM 0x004f 16760484Sobrien#define mmSDMA3_PHASE2_QUANTUM_BASE_IDX 1 16860484Sobrien#define mmSDMA3_ERROR_LOG 0x0050 16960484Sobrien#define mmSDMA3_ERROR_LOG_BASE_IDX 1 17060484Sobrien#define mmSDMA3_PUB_DUMMY_REG0 0x0051 17160484Sobrien#define mmSDMA3_PUB_DUMMY_REG0_BASE_IDX 1 17260484Sobrien#define mmSDMA3_PUB_DUMMY_REG1 0x0052 17360484Sobrien#define mmSDMA3_PUB_DUMMY_REG1_BASE_IDX 1 17460484Sobrien#define mmSDMA3_PUB_DUMMY_REG2 0x0053 17560484Sobrien#define mmSDMA3_PUB_DUMMY_REG2_BASE_IDX 1 17660484Sobrien#define mmSDMA3_PUB_DUMMY_REG3 0x0054 17760484Sobrien#define mmSDMA3_PUB_DUMMY_REG3_BASE_IDX 1 17860484Sobrien#define mmSDMA3_F32_COUNTER 0x0055 17960484Sobrien#define mmSDMA3_F32_COUNTER_BASE_IDX 1 18060484Sobrien#define mmSDMA3_UNBREAKABLE 0x0056 18160484Sobrien#define mmSDMA3_UNBREAKABLE_BASE_IDX 1 18260484Sobrien#define mmSDMA3_PERFMON_CNTL 0x0057 18360484Sobrien#define mmSDMA3_PERFMON_CNTL_BASE_IDX 1 18460484Sobrien#define mmSDMA3_PERFCOUNTER0_RESULT 0x0058 18560484Sobrien#define mmSDMA3_PERFCOUNTER0_RESULT_BASE_IDX 1 18660484Sobrien#define mmSDMA3_PERFCOUNTER1_RESULT 0x0059 18760484Sobrien#define mmSDMA3_PERFCOUNTER1_RESULT_BASE_IDX 1 18860484Sobrien#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE 0x005a 18960484Sobrien#define mmSDMA3_PERFCOUNTER_TAG_DELAY_RANGE_BASE_IDX 1 19060484Sobrien#define mmSDMA3_CRD_CNTL 0x005b 19160484Sobrien#define mmSDMA3_CRD_CNTL_BASE_IDX 1 19260484Sobrien#define mmSDMA3_GPU_IOV_VIOLATION_LOG 0x005d 19360484Sobrien#define mmSDMA3_GPU_IOV_VIOLATION_LOG_BASE_IDX 1 19460484Sobrien#define mmSDMA3_ULV_CNTL 0x005e 19560484Sobrien#define mmSDMA3_ULV_CNTL_BASE_IDX 1 19660484Sobrien#define mmSDMA3_EA_DBIT_ADDR_DATA 0x0060 19760484Sobrien#define mmSDMA3_EA_DBIT_ADDR_DATA_BASE_IDX 1 19860484Sobrien#define mmSDMA3_EA_DBIT_ADDR_INDEX 0x0061 19960484Sobrien#define mmSDMA3_EA_DBIT_ADDR_INDEX_BASE_IDX 1 20060484Sobrien#define mmSDMA3_GPU_IOV_VIOLATION_LOG2 0x0062 20160484Sobrien#define mmSDMA3_GPU_IOV_VIOLATION_LOG2_BASE_IDX 1 20260484Sobrien#define mmSDMA3_GFX_RB_CNTL 0x0080 20377298Sobrien#define mmSDMA3_GFX_RB_CNTL_BASE_IDX 1 20460484Sobrien#define mmSDMA3_GFX_RB_BASE 0x0081 20560484Sobrien#define mmSDMA3_GFX_RB_BASE_BASE_IDX 1 20660484Sobrien#define mmSDMA3_GFX_RB_BASE_HI 0x0082 20760484Sobrien#define mmSDMA3_GFX_RB_BASE_HI_BASE_IDX 1 20860484Sobrien#define mmSDMA3_GFX_RB_RPTR 0x0083 20960484Sobrien#define mmSDMA3_GFX_RB_RPTR_BASE_IDX 1 21060484Sobrien#define mmSDMA3_GFX_RB_RPTR_HI 0x0084 21160484Sobrien#define mmSDMA3_GFX_RB_RPTR_HI_BASE_IDX 1 21260484Sobrien#define mmSDMA3_GFX_RB_WPTR 0x0085 21360484Sobrien#define mmSDMA3_GFX_RB_WPTR_BASE_IDX 1 21477298Sobrien#define mmSDMA3_GFX_RB_WPTR_HI 0x0086 21560484Sobrien#define mmSDMA3_GFX_RB_WPTR_HI_BASE_IDX 1 21677298Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL 0x0087 21760484Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_CNTL_BASE_IDX 1 21860484Sobrien#define mmSDMA3_GFX_RB_RPTR_ADDR_HI 0x0088 21960484Sobrien#define mmSDMA3_GFX_RB_RPTR_ADDR_HI_BASE_IDX 1 22060484Sobrien#define mmSDMA3_GFX_RB_RPTR_ADDR_LO 0x0089 22160484Sobrien#define mmSDMA3_GFX_RB_RPTR_ADDR_LO_BASE_IDX 1 22260484Sobrien#define mmSDMA3_GFX_IB_CNTL 0x008a 22360484Sobrien#define mmSDMA3_GFX_IB_CNTL_BASE_IDX 1 22460484Sobrien#define mmSDMA3_GFX_IB_RPTR 0x008b 22560484Sobrien#define mmSDMA3_GFX_IB_RPTR_BASE_IDX 1 22660484Sobrien#define mmSDMA3_GFX_IB_OFFSET 0x008c 22760484Sobrien#define mmSDMA3_GFX_IB_OFFSET_BASE_IDX 1 22860484Sobrien#define mmSDMA3_GFX_IB_BASE_LO 0x008d 22960484Sobrien#define mmSDMA3_GFX_IB_BASE_LO_BASE_IDX 1 23060484Sobrien#define mmSDMA3_GFX_IB_BASE_HI 0x008e 23160484Sobrien#define mmSDMA3_GFX_IB_BASE_HI_BASE_IDX 1 23260484Sobrien#define mmSDMA3_GFX_IB_SIZE 0x008f 23360484Sobrien#define mmSDMA3_GFX_IB_SIZE_BASE_IDX 1 23460484Sobrien#define mmSDMA3_GFX_SKIP_CNTL 0x0090 23560484Sobrien#define mmSDMA3_GFX_SKIP_CNTL_BASE_IDX 1 23677298Sobrien#define mmSDMA3_GFX_CONTEXT_STATUS 0x0091 23777298Sobrien#define mmSDMA3_GFX_CONTEXT_STATUS_BASE_IDX 1 23877298Sobrien#define mmSDMA3_GFX_DOORBELL 0x0092 23960484Sobrien#define mmSDMA3_GFX_DOORBELL_BASE_IDX 1 24060484Sobrien#define mmSDMA3_GFX_CONTEXT_CNTL 0x0093 24160484Sobrien#define mmSDMA3_GFX_CONTEXT_CNTL_BASE_IDX 1 24260484Sobrien#define mmSDMA3_GFX_STATUS 0x00a8 24360484Sobrien#define mmSDMA3_GFX_STATUS_BASE_IDX 1 24460484Sobrien#define mmSDMA3_GFX_DOORBELL_LOG 0x00a9 24560484Sobrien#define mmSDMA3_GFX_DOORBELL_LOG_BASE_IDX 1 24660484Sobrien#define mmSDMA3_GFX_WATERMARK 0x00aa 24760484Sobrien#define mmSDMA3_GFX_WATERMARK_BASE_IDX 1 24860484Sobrien#define mmSDMA3_GFX_DOORBELL_OFFSET 0x00ab 24960484Sobrien#define mmSDMA3_GFX_DOORBELL_OFFSET_BASE_IDX 1 25060484Sobrien#define mmSDMA3_GFX_CSA_ADDR_LO 0x00ac 25160484Sobrien#define mmSDMA3_GFX_CSA_ADDR_LO_BASE_IDX 1 25260484Sobrien#define mmSDMA3_GFX_CSA_ADDR_HI 0x00ad 25360484Sobrien#define mmSDMA3_GFX_CSA_ADDR_HI_BASE_IDX 1 25460484Sobrien#define mmSDMA3_GFX_IB_SUB_REMAIN 0x00af 25560484Sobrien#define mmSDMA3_GFX_IB_SUB_REMAIN_BASE_IDX 1 25660484Sobrien#define mmSDMA3_GFX_PREEMPT 0x00b0 25760484Sobrien#define mmSDMA3_GFX_PREEMPT_BASE_IDX 1 25860484Sobrien#define mmSDMA3_GFX_DUMMY_REG 0x00b1 25960484Sobrien#define mmSDMA3_GFX_DUMMY_REG_BASE_IDX 1 26060484Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI 0x00b2 26160484Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 26260484Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO 0x00b3 26360484Sobrien#define mmSDMA3_GFX_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 26460484Sobrien#define mmSDMA3_GFX_RB_AQL_CNTL 0x00b4 26560484Sobrien#define mmSDMA3_GFX_RB_AQL_CNTL_BASE_IDX 1 26660484Sobrien#define mmSDMA3_GFX_MINOR_PTR_UPDATE 0x00b5 26760484Sobrien#define mmSDMA3_GFX_MINOR_PTR_UPDATE_BASE_IDX 1 26860484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA0 0x00c0 26960484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA0_BASE_IDX 1 27060484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA1 0x00c1 27160484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA1_BASE_IDX 1 27260484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA2 0x00c2 27360484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA2_BASE_IDX 1 27460484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA3 0x00c3 27560484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA3_BASE_IDX 1 27660484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA4 0x00c4 27760484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA4_BASE_IDX 1 27860484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA5 0x00c5 27960484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA5_BASE_IDX 1 28060484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA6 0x00c6 28160484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA6_BASE_IDX 1 28260484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA7 0x00c7 28360484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA7_BASE_IDX 1 28460484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA8 0x00c8 28560484Sobrien#define mmSDMA3_GFX_MIDCMD_DATA8_BASE_IDX 1 28660484Sobrien#define mmSDMA3_GFX_MIDCMD_CNTL 0x00c9 28760484Sobrien#define mmSDMA3_GFX_MIDCMD_CNTL_BASE_IDX 1 28860484Sobrien#define mmSDMA3_PAGE_RB_CNTL 0x00d8 28960484Sobrien#define mmSDMA3_PAGE_RB_CNTL_BASE_IDX 1 29060484Sobrien#define mmSDMA3_PAGE_RB_BASE 0x00d9 29160484Sobrien#define mmSDMA3_PAGE_RB_BASE_BASE_IDX 1 29260484Sobrien#define mmSDMA3_PAGE_RB_BASE_HI 0x00da 29360484Sobrien#define mmSDMA3_PAGE_RB_BASE_HI_BASE_IDX 1 29460484Sobrien#define mmSDMA3_PAGE_RB_RPTR 0x00db 29560484Sobrien#define mmSDMA3_PAGE_RB_RPTR_BASE_IDX 1 29660484Sobrien#define mmSDMA3_PAGE_RB_RPTR_HI 0x00dc 29760484Sobrien#define mmSDMA3_PAGE_RB_RPTR_HI_BASE_IDX 1 29860484Sobrien#define mmSDMA3_PAGE_RB_WPTR 0x00dd 29960484Sobrien#define mmSDMA3_PAGE_RB_WPTR_BASE_IDX 1 30060484Sobrien#define mmSDMA3_PAGE_RB_WPTR_HI 0x00de 30160484Sobrien#define mmSDMA3_PAGE_RB_WPTR_HI_BASE_IDX 1 30260484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL 0x00df 30360484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_CNTL_BASE_IDX 1 30460484Sobrien#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI 0x00e0 30560484Sobrien#define mmSDMA3_PAGE_RB_RPTR_ADDR_HI_BASE_IDX 1 30660484Sobrien#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO 0x00e1 30760484Sobrien#define mmSDMA3_PAGE_RB_RPTR_ADDR_LO_BASE_IDX 1 30860484Sobrien#define mmSDMA3_PAGE_IB_CNTL 0x00e2 30960484Sobrien#define mmSDMA3_PAGE_IB_CNTL_BASE_IDX 1 31060484Sobrien#define mmSDMA3_PAGE_IB_RPTR 0x00e3 31160484Sobrien#define mmSDMA3_PAGE_IB_RPTR_BASE_IDX 1 31260484Sobrien#define mmSDMA3_PAGE_IB_OFFSET 0x00e4 31360484Sobrien#define mmSDMA3_PAGE_IB_OFFSET_BASE_IDX 1 31460484Sobrien#define mmSDMA3_PAGE_IB_BASE_LO 0x00e5 31560484Sobrien#define mmSDMA3_PAGE_IB_BASE_LO_BASE_IDX 1 31660484Sobrien#define mmSDMA3_PAGE_IB_BASE_HI 0x00e6 31760484Sobrien#define mmSDMA3_PAGE_IB_BASE_HI_BASE_IDX 1 31860484Sobrien#define mmSDMA3_PAGE_IB_SIZE 0x00e7 31960484Sobrien#define mmSDMA3_PAGE_IB_SIZE_BASE_IDX 1 32060484Sobrien#define mmSDMA3_PAGE_SKIP_CNTL 0x00e8 32160484Sobrien#define mmSDMA3_PAGE_SKIP_CNTL_BASE_IDX 1 32260484Sobrien#define mmSDMA3_PAGE_CONTEXT_STATUS 0x00e9 32360484Sobrien#define mmSDMA3_PAGE_CONTEXT_STATUS_BASE_IDX 1 32460484Sobrien#define mmSDMA3_PAGE_DOORBELL 0x00ea 32560484Sobrien#define mmSDMA3_PAGE_DOORBELL_BASE_IDX 1 32660484Sobrien#define mmSDMA3_PAGE_STATUS 0x0100 32760484Sobrien#define mmSDMA3_PAGE_STATUS_BASE_IDX 1 32860484Sobrien#define mmSDMA3_PAGE_DOORBELL_LOG 0x0101 32960484Sobrien#define mmSDMA3_PAGE_DOORBELL_LOG_BASE_IDX 1 33060484Sobrien#define mmSDMA3_PAGE_WATERMARK 0x0102 33160484Sobrien#define mmSDMA3_PAGE_WATERMARK_BASE_IDX 1 33260484Sobrien#define mmSDMA3_PAGE_DOORBELL_OFFSET 0x0103 33360484Sobrien#define mmSDMA3_PAGE_DOORBELL_OFFSET_BASE_IDX 1 33460484Sobrien#define mmSDMA3_PAGE_CSA_ADDR_LO 0x0104 33560484Sobrien#define mmSDMA3_PAGE_CSA_ADDR_LO_BASE_IDX 1 33660484Sobrien#define mmSDMA3_PAGE_CSA_ADDR_HI 0x0105 33760484Sobrien#define mmSDMA3_PAGE_CSA_ADDR_HI_BASE_IDX 1 33860484Sobrien#define mmSDMA3_PAGE_IB_SUB_REMAIN 0x0107 33960484Sobrien#define mmSDMA3_PAGE_IB_SUB_REMAIN_BASE_IDX 1 34060484Sobrien#define mmSDMA3_PAGE_PREEMPT 0x0108 34160484Sobrien#define mmSDMA3_PAGE_PREEMPT_BASE_IDX 1 34260484Sobrien#define mmSDMA3_PAGE_DUMMY_REG 0x0109 34360484Sobrien#define mmSDMA3_PAGE_DUMMY_REG_BASE_IDX 1 34460484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI 0x010a 34560484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 34660484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO 0x010b 34760484Sobrien#define mmSDMA3_PAGE_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 34860484Sobrien#define mmSDMA3_PAGE_RB_AQL_CNTL 0x010c 34960484Sobrien#define mmSDMA3_PAGE_RB_AQL_CNTL_BASE_IDX 1 35060484Sobrien#define mmSDMA3_PAGE_MINOR_PTR_UPDATE 0x010d 35160484Sobrien#define mmSDMA3_PAGE_MINOR_PTR_UPDATE_BASE_IDX 1 35260484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA0 0x0118 35360484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA0_BASE_IDX 1 35460484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA1 0x0119 35560484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA1_BASE_IDX 1 35660484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA2 0x011a 35760484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA2_BASE_IDX 1 35860484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA3 0x011b 35960484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA3_BASE_IDX 1 36060484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA4 0x011c 36160484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA4_BASE_IDX 1 36260484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA5 0x011d 36360484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA5_BASE_IDX 1 36460484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA6 0x011e 36560484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA6_BASE_IDX 1 36660484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA7 0x011f 36760484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA7_BASE_IDX 1 36860484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA8 0x0120 36960484Sobrien#define mmSDMA3_PAGE_MIDCMD_DATA8_BASE_IDX 1 37060484Sobrien#define mmSDMA3_PAGE_MIDCMD_CNTL 0x0121 37160484Sobrien#define mmSDMA3_PAGE_MIDCMD_CNTL_BASE_IDX 1 37260484Sobrien#define mmSDMA3_RLC0_RB_CNTL 0x0130 37360484Sobrien#define mmSDMA3_RLC0_RB_CNTL_BASE_IDX 1 37460484Sobrien#define mmSDMA3_RLC0_RB_BASE 0x0131 37560484Sobrien#define mmSDMA3_RLC0_RB_BASE_BASE_IDX 1 37660484Sobrien#define mmSDMA3_RLC0_RB_BASE_HI 0x0132 37760484Sobrien#define mmSDMA3_RLC0_RB_BASE_HI_BASE_IDX 1 37860484Sobrien#define mmSDMA3_RLC0_RB_RPTR 0x0133 37960484Sobrien#define mmSDMA3_RLC0_RB_RPTR_BASE_IDX 1 38060484Sobrien#define mmSDMA3_RLC0_RB_RPTR_HI 0x0134 38160484Sobrien#define mmSDMA3_RLC0_RB_RPTR_HI_BASE_IDX 1 38260484Sobrien#define mmSDMA3_RLC0_RB_WPTR 0x0135 38360484Sobrien#define mmSDMA3_RLC0_RB_WPTR_BASE_IDX 1 38460484Sobrien#define mmSDMA3_RLC0_RB_WPTR_HI 0x0136 38560484Sobrien#define mmSDMA3_RLC0_RB_WPTR_HI_BASE_IDX 1 38660484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL 0x0137 38760484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_CNTL_BASE_IDX 1 38860484Sobrien#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI 0x0138 38960484Sobrien#define mmSDMA3_RLC0_RB_RPTR_ADDR_HI_BASE_IDX 1 39060484Sobrien#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO 0x0139 39160484Sobrien#define mmSDMA3_RLC0_RB_RPTR_ADDR_LO_BASE_IDX 1 39260484Sobrien#define mmSDMA3_RLC0_IB_CNTL 0x013a 39360484Sobrien#define mmSDMA3_RLC0_IB_CNTL_BASE_IDX 1 39460484Sobrien#define mmSDMA3_RLC0_IB_RPTR 0x013b 39560484Sobrien#define mmSDMA3_RLC0_IB_RPTR_BASE_IDX 1 39660484Sobrien#define mmSDMA3_RLC0_IB_OFFSET 0x013c 39760484Sobrien#define mmSDMA3_RLC0_IB_OFFSET_BASE_IDX 1 39860484Sobrien#define mmSDMA3_RLC0_IB_BASE_LO 0x013d 39960484Sobrien#define mmSDMA3_RLC0_IB_BASE_LO_BASE_IDX 1 40060484Sobrien#define mmSDMA3_RLC0_IB_BASE_HI 0x013e 40160484Sobrien#define mmSDMA3_RLC0_IB_BASE_HI_BASE_IDX 1 40260484Sobrien#define mmSDMA3_RLC0_IB_SIZE 0x013f 40360484Sobrien#define mmSDMA3_RLC0_IB_SIZE_BASE_IDX 1 40460484Sobrien#define mmSDMA3_RLC0_SKIP_CNTL 0x0140 40560484Sobrien#define mmSDMA3_RLC0_SKIP_CNTL_BASE_IDX 1 40660484Sobrien#define mmSDMA3_RLC0_CONTEXT_STATUS 0x0141 40760484Sobrien#define mmSDMA3_RLC0_CONTEXT_STATUS_BASE_IDX 1 40860484Sobrien#define mmSDMA3_RLC0_DOORBELL 0x0142 40960484Sobrien#define mmSDMA3_RLC0_DOORBELL_BASE_IDX 1 41060484Sobrien#define mmSDMA3_RLC0_STATUS 0x0158 41160484Sobrien#define mmSDMA3_RLC0_STATUS_BASE_IDX 1 41260484Sobrien#define mmSDMA3_RLC0_DOORBELL_LOG 0x0159 41360484Sobrien#define mmSDMA3_RLC0_DOORBELL_LOG_BASE_IDX 1 41460484Sobrien#define mmSDMA3_RLC0_WATERMARK 0x015a 41560484Sobrien#define mmSDMA3_RLC0_WATERMARK_BASE_IDX 1 41660484Sobrien#define mmSDMA3_RLC0_DOORBELL_OFFSET 0x015b 41760484Sobrien#define mmSDMA3_RLC0_DOORBELL_OFFSET_BASE_IDX 1 41860484Sobrien#define mmSDMA3_RLC0_CSA_ADDR_LO 0x015c 41960484Sobrien#define mmSDMA3_RLC0_CSA_ADDR_LO_BASE_IDX 1 42060484Sobrien#define mmSDMA3_RLC0_CSA_ADDR_HI 0x015d 42160484Sobrien#define mmSDMA3_RLC0_CSA_ADDR_HI_BASE_IDX 1 42260484Sobrien#define mmSDMA3_RLC0_IB_SUB_REMAIN 0x015f 42360484Sobrien#define mmSDMA3_RLC0_IB_SUB_REMAIN_BASE_IDX 1 42460484Sobrien#define mmSDMA3_RLC0_PREEMPT 0x0160 42560484Sobrien#define mmSDMA3_RLC0_PREEMPT_BASE_IDX 1 42660484Sobrien#define mmSDMA3_RLC0_DUMMY_REG 0x0161 42760484Sobrien#define mmSDMA3_RLC0_DUMMY_REG_BASE_IDX 1 42860484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI 0x0162 42960484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 43060484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO 0x0163 43160484Sobrien#define mmSDMA3_RLC0_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 43277298Sobrien#define mmSDMA3_RLC0_RB_AQL_CNTL 0x0164 43360484Sobrien#define mmSDMA3_RLC0_RB_AQL_CNTL_BASE_IDX 1 43460484Sobrien#define mmSDMA3_RLC0_MINOR_PTR_UPDATE 0x0165 43560484Sobrien#define mmSDMA3_RLC0_MINOR_PTR_UPDATE_BASE_IDX 1 43677298Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA0 0x0170 43760484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA0_BASE_IDX 1 43860484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA1 0x0171 43960484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA1_BASE_IDX 1 44077298Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA2 0x0172 44160484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA2_BASE_IDX 1 44260484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA3 0x0173 44360484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA3_BASE_IDX 1 44460484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA4 0x0174 44560484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA4_BASE_IDX 1 44660484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA5 0x0175 44760484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA5_BASE_IDX 1 44860484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA6 0x0176 44960484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA6_BASE_IDX 1 45060484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA7 0x0177 45160484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA7_BASE_IDX 1 45260484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA8 0x0178 45360484Sobrien#define mmSDMA3_RLC0_MIDCMD_DATA8_BASE_IDX 1 45460484Sobrien#define mmSDMA3_RLC0_MIDCMD_CNTL 0x0179 45560484Sobrien#define mmSDMA3_RLC0_MIDCMD_CNTL_BASE_IDX 1 45660484Sobrien#define mmSDMA3_RLC1_RB_CNTL 0x0188 45760484Sobrien#define mmSDMA3_RLC1_RB_CNTL_BASE_IDX 1 45860484Sobrien#define mmSDMA3_RLC1_RB_BASE 0x0189 45960484Sobrien#define mmSDMA3_RLC1_RB_BASE_BASE_IDX 1 46060484Sobrien#define mmSDMA3_RLC1_RB_BASE_HI 0x018a 46177298Sobrien#define mmSDMA3_RLC1_RB_BASE_HI_BASE_IDX 1 46260484Sobrien#define mmSDMA3_RLC1_RB_RPTR 0x018b 46360484Sobrien#define mmSDMA3_RLC1_RB_RPTR_BASE_IDX 1 46460484Sobrien#define mmSDMA3_RLC1_RB_RPTR_HI 0x018c 46560484Sobrien#define mmSDMA3_RLC1_RB_RPTR_HI_BASE_IDX 1 46660484Sobrien#define mmSDMA3_RLC1_RB_WPTR 0x018d 46760484Sobrien#define mmSDMA3_RLC1_RB_WPTR_BASE_IDX 1 46860484Sobrien#define mmSDMA3_RLC1_RB_WPTR_HI 0x018e 46960484Sobrien#define mmSDMA3_RLC1_RB_WPTR_HI_BASE_IDX 1 47060484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL 0x018f 47160484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_CNTL_BASE_IDX 1 47260484Sobrien#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI 0x0190 47377298Sobrien#define mmSDMA3_RLC1_RB_RPTR_ADDR_HI_BASE_IDX 1 47460484Sobrien#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO 0x0191 47577298Sobrien#define mmSDMA3_RLC1_RB_RPTR_ADDR_LO_BASE_IDX 1 47660484Sobrien#define mmSDMA3_RLC1_IB_CNTL 0x0192 47760484Sobrien#define mmSDMA3_RLC1_IB_CNTL_BASE_IDX 1 47860484Sobrien#define mmSDMA3_RLC1_IB_RPTR 0x0193 47977298Sobrien#define mmSDMA3_RLC1_IB_RPTR_BASE_IDX 1 48060484Sobrien#define mmSDMA3_RLC1_IB_OFFSET 0x0194 48160484Sobrien#define mmSDMA3_RLC1_IB_OFFSET_BASE_IDX 1 48260484Sobrien#define mmSDMA3_RLC1_IB_BASE_LO 0x0195 48360484Sobrien#define mmSDMA3_RLC1_IB_BASE_LO_BASE_IDX 1 48460484Sobrien#define mmSDMA3_RLC1_IB_BASE_HI 0x0196 48560484Sobrien#define mmSDMA3_RLC1_IB_BASE_HI_BASE_IDX 1 48660484Sobrien#define mmSDMA3_RLC1_IB_SIZE 0x0197 48760484Sobrien#define mmSDMA3_RLC1_IB_SIZE_BASE_IDX 1 48860484Sobrien#define mmSDMA3_RLC1_SKIP_CNTL 0x0198 48960484Sobrien#define mmSDMA3_RLC1_SKIP_CNTL_BASE_IDX 1 49060484Sobrien#define mmSDMA3_RLC1_CONTEXT_STATUS 0x0199 49160484Sobrien#define mmSDMA3_RLC1_CONTEXT_STATUS_BASE_IDX 1 49260484Sobrien#define mmSDMA3_RLC1_DOORBELL 0x019a 49360484Sobrien#define mmSDMA3_RLC1_DOORBELL_BASE_IDX 1 49460484Sobrien#define mmSDMA3_RLC1_STATUS 0x01b0 49560484Sobrien#define mmSDMA3_RLC1_STATUS_BASE_IDX 1 49660484Sobrien#define mmSDMA3_RLC1_DOORBELL_LOG 0x01b1 49760484Sobrien#define mmSDMA3_RLC1_DOORBELL_LOG_BASE_IDX 1 49860484Sobrien#define mmSDMA3_RLC1_WATERMARK 0x01b2 49960484Sobrien#define mmSDMA3_RLC1_WATERMARK_BASE_IDX 1 50060484Sobrien#define mmSDMA3_RLC1_DOORBELL_OFFSET 0x01b3 50160484Sobrien#define mmSDMA3_RLC1_DOORBELL_OFFSET_BASE_IDX 1 50260484Sobrien#define mmSDMA3_RLC1_CSA_ADDR_LO 0x01b4 50360484Sobrien#define mmSDMA3_RLC1_CSA_ADDR_LO_BASE_IDX 1 50460484Sobrien#define mmSDMA3_RLC1_CSA_ADDR_HI 0x01b5 50560484Sobrien#define mmSDMA3_RLC1_CSA_ADDR_HI_BASE_IDX 1 50660484Sobrien#define mmSDMA3_RLC1_IB_SUB_REMAIN 0x01b7 50760484Sobrien#define mmSDMA3_RLC1_IB_SUB_REMAIN_BASE_IDX 1 50860484Sobrien#define mmSDMA3_RLC1_PREEMPT 0x01b8 50960484Sobrien#define mmSDMA3_RLC1_PREEMPT_BASE_IDX 1 51060484Sobrien#define mmSDMA3_RLC1_DUMMY_REG 0x01b9 51160484Sobrien#define mmSDMA3_RLC1_DUMMY_REG_BASE_IDX 1 51260484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI 0x01ba 51360484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 51460484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO 0x01bb 51560484Sobrien#define mmSDMA3_RLC1_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 51660484Sobrien#define mmSDMA3_RLC1_RB_AQL_CNTL 0x01bc 51760484Sobrien#define mmSDMA3_RLC1_RB_AQL_CNTL_BASE_IDX 1 51860484Sobrien#define mmSDMA3_RLC1_MINOR_PTR_UPDATE 0x01bd 51960484Sobrien#define mmSDMA3_RLC1_MINOR_PTR_UPDATE_BASE_IDX 1 52060484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA0 0x01c8 52160484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA0_BASE_IDX 1 52260484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA1 0x01c9 52360484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA1_BASE_IDX 1 52460484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA2 0x01ca 52560484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA2_BASE_IDX 1 52660484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA3 0x01cb 52760484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA3_BASE_IDX 1 52860484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA4 0x01cc 52960484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA4_BASE_IDX 1 53060484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA5 0x01cd 53160484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA5_BASE_IDX 1 53260484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA6 0x01ce 53360484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA6_BASE_IDX 1 53460484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA7 0x01cf 53560484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA7_BASE_IDX 1 53660484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA8 0x01d0 53760484Sobrien#define mmSDMA3_RLC1_MIDCMD_DATA8_BASE_IDX 1 53860484Sobrien#define mmSDMA3_RLC1_MIDCMD_CNTL 0x01d1 53960484Sobrien#define mmSDMA3_RLC1_MIDCMD_CNTL_BASE_IDX 1 54060484Sobrien#define mmSDMA3_RLC2_RB_CNTL 0x01e0 54177298Sobrien#define mmSDMA3_RLC2_RB_CNTL_BASE_IDX 1 54260484Sobrien#define mmSDMA3_RLC2_RB_BASE 0x01e1 54360484Sobrien#define mmSDMA3_RLC2_RB_BASE_BASE_IDX 1 54460484Sobrien#define mmSDMA3_RLC2_RB_BASE_HI 0x01e2 54560484Sobrien#define mmSDMA3_RLC2_RB_BASE_HI_BASE_IDX 1 54660484Sobrien#define mmSDMA3_RLC2_RB_RPTR 0x01e3 54760484Sobrien#define mmSDMA3_RLC2_RB_RPTR_BASE_IDX 1 54860484Sobrien#define mmSDMA3_RLC2_RB_RPTR_HI 0x01e4 54960484Sobrien#define mmSDMA3_RLC2_RB_RPTR_HI_BASE_IDX 1 55060484Sobrien#define mmSDMA3_RLC2_RB_WPTR 0x01e5 55160484Sobrien#define mmSDMA3_RLC2_RB_WPTR_BASE_IDX 1 55260484Sobrien#define mmSDMA3_RLC2_RB_WPTR_HI 0x01e6 55360484Sobrien#define mmSDMA3_RLC2_RB_WPTR_HI_BASE_IDX 1 55460484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL 0x01e7 55560484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_CNTL_BASE_IDX 1 55660484Sobrien#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI 0x01e8 55760484Sobrien#define mmSDMA3_RLC2_RB_RPTR_ADDR_HI_BASE_IDX 1 55860484Sobrien#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO 0x01e9 55960484Sobrien#define mmSDMA3_RLC2_RB_RPTR_ADDR_LO_BASE_IDX 1 56060484Sobrien#define mmSDMA3_RLC2_IB_CNTL 0x01ea 56160484Sobrien#define mmSDMA3_RLC2_IB_CNTL_BASE_IDX 1 56260484Sobrien#define mmSDMA3_RLC2_IB_RPTR 0x01eb 56360484Sobrien#define mmSDMA3_RLC2_IB_RPTR_BASE_IDX 1 56460484Sobrien#define mmSDMA3_RLC2_IB_OFFSET 0x01ec 56560484Sobrien#define mmSDMA3_RLC2_IB_OFFSET_BASE_IDX 1 56660484Sobrien#define mmSDMA3_RLC2_IB_BASE_LO 0x01ed 56760484Sobrien#define mmSDMA3_RLC2_IB_BASE_LO_BASE_IDX 1 56860484Sobrien#define mmSDMA3_RLC2_IB_BASE_HI 0x01ee 56960484Sobrien#define mmSDMA3_RLC2_IB_BASE_HI_BASE_IDX 1 57060484Sobrien#define mmSDMA3_RLC2_IB_SIZE 0x01ef 57160484Sobrien#define mmSDMA3_RLC2_IB_SIZE_BASE_IDX 1 57260484Sobrien#define mmSDMA3_RLC2_SKIP_CNTL 0x01f0 57360484Sobrien#define mmSDMA3_RLC2_SKIP_CNTL_BASE_IDX 1 57477298Sobrien#define mmSDMA3_RLC2_CONTEXT_STATUS 0x01f1 57577298Sobrien#define mmSDMA3_RLC2_CONTEXT_STATUS_BASE_IDX 1 57677298Sobrien#define mmSDMA3_RLC2_DOORBELL 0x01f2 57777298Sobrien#define mmSDMA3_RLC2_DOORBELL_BASE_IDX 1 57877298Sobrien#define mmSDMA3_RLC2_STATUS 0x0208 57960484Sobrien#define mmSDMA3_RLC2_STATUS_BASE_IDX 1 58060484Sobrien#define mmSDMA3_RLC2_DOORBELL_LOG 0x0209 58160484Sobrien#define mmSDMA3_RLC2_DOORBELL_LOG_BASE_IDX 1 58260484Sobrien#define mmSDMA3_RLC2_WATERMARK 0x020a 58360484Sobrien#define mmSDMA3_RLC2_WATERMARK_BASE_IDX 1 58460484Sobrien#define mmSDMA3_RLC2_DOORBELL_OFFSET 0x020b 58560484Sobrien#define mmSDMA3_RLC2_DOORBELL_OFFSET_BASE_IDX 1 58660484Sobrien#define mmSDMA3_RLC2_CSA_ADDR_LO 0x020c 58760484Sobrien#define mmSDMA3_RLC2_CSA_ADDR_LO_BASE_IDX 1 58860484Sobrien#define mmSDMA3_RLC2_CSA_ADDR_HI 0x020d 58960484Sobrien#define mmSDMA3_RLC2_CSA_ADDR_HI_BASE_IDX 1 59060484Sobrien#define mmSDMA3_RLC2_IB_SUB_REMAIN 0x020f 59160484Sobrien#define mmSDMA3_RLC2_IB_SUB_REMAIN_BASE_IDX 1 59260484Sobrien#define mmSDMA3_RLC2_PREEMPT 0x0210 59360484Sobrien#define mmSDMA3_RLC2_PREEMPT_BASE_IDX 1 59460484Sobrien#define mmSDMA3_RLC2_DUMMY_REG 0x0211 59560484Sobrien#define mmSDMA3_RLC2_DUMMY_REG_BASE_IDX 1 59660484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI 0x0212 59760484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 59860484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO 0x0213 59960484Sobrien#define mmSDMA3_RLC2_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 60060484Sobrien#define mmSDMA3_RLC2_RB_AQL_CNTL 0x0214 60160484Sobrien#define mmSDMA3_RLC2_RB_AQL_CNTL_BASE_IDX 1 60260484Sobrien#define mmSDMA3_RLC2_MINOR_PTR_UPDATE 0x0215 60360484Sobrien#define mmSDMA3_RLC2_MINOR_PTR_UPDATE_BASE_IDX 1 60460484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA0 0x0220 60560484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA0_BASE_IDX 1 60660484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA1 0x0221 60760484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA1_BASE_IDX 1 60860484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA2 0x0222 60960484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA2_BASE_IDX 1 61060484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA3 0x0223 61160484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA3_BASE_IDX 1 61260484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA4 0x0224 61360484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA4_BASE_IDX 1 61460484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA5 0x0225 61560484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA5_BASE_IDX 1 61660484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA6 0x0226 61760484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA6_BASE_IDX 1 61860484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA7 0x0227 61960484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA7_BASE_IDX 1 62060484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA8 0x0228 62160484Sobrien#define mmSDMA3_RLC2_MIDCMD_DATA8_BASE_IDX 1 62260484Sobrien#define mmSDMA3_RLC2_MIDCMD_CNTL 0x0229 62360484Sobrien#define mmSDMA3_RLC2_MIDCMD_CNTL_BASE_IDX 1 62460484Sobrien#define mmSDMA3_RLC3_RB_CNTL 0x0238 62560484Sobrien#define mmSDMA3_RLC3_RB_CNTL_BASE_IDX 1 62660484Sobrien#define mmSDMA3_RLC3_RB_BASE 0x0239 62760484Sobrien#define mmSDMA3_RLC3_RB_BASE_BASE_IDX 1 62860484Sobrien#define mmSDMA3_RLC3_RB_BASE_HI 0x023a 62960484Sobrien#define mmSDMA3_RLC3_RB_BASE_HI_BASE_IDX 1 63060484Sobrien#define mmSDMA3_RLC3_RB_RPTR 0x023b 63160484Sobrien#define mmSDMA3_RLC3_RB_RPTR_BASE_IDX 1 63260484Sobrien#define mmSDMA3_RLC3_RB_RPTR_HI 0x023c 63360484Sobrien#define mmSDMA3_RLC3_RB_RPTR_HI_BASE_IDX 1 63460484Sobrien#define mmSDMA3_RLC3_RB_WPTR 0x023d 63560484Sobrien#define mmSDMA3_RLC3_RB_WPTR_BASE_IDX 1 63660484Sobrien#define mmSDMA3_RLC3_RB_WPTR_HI 0x023e 63760484Sobrien#define mmSDMA3_RLC3_RB_WPTR_HI_BASE_IDX 1 63860484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL 0x023f 63960484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_CNTL_BASE_IDX 1 64060484Sobrien#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI 0x0240 64160484Sobrien#define mmSDMA3_RLC3_RB_RPTR_ADDR_HI_BASE_IDX 1 64260484Sobrien#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO 0x0241 64360484Sobrien#define mmSDMA3_RLC3_RB_RPTR_ADDR_LO_BASE_IDX 1 64460484Sobrien#define mmSDMA3_RLC3_IB_CNTL 0x0242 64560484Sobrien#define mmSDMA3_RLC3_IB_CNTL_BASE_IDX 1 64660484Sobrien#define mmSDMA3_RLC3_IB_RPTR 0x0243 64760484Sobrien#define mmSDMA3_RLC3_IB_RPTR_BASE_IDX 1 64860484Sobrien#define mmSDMA3_RLC3_IB_OFFSET 0x0244 64960484Sobrien#define mmSDMA3_RLC3_IB_OFFSET_BASE_IDX 1 65060484Sobrien#define mmSDMA3_RLC3_IB_BASE_LO 0x0245 65160484Sobrien#define mmSDMA3_RLC3_IB_BASE_LO_BASE_IDX 1 65260484Sobrien#define mmSDMA3_RLC3_IB_BASE_HI 0x0246 65360484Sobrien#define mmSDMA3_RLC3_IB_BASE_HI_BASE_IDX 1 65460484Sobrien#define mmSDMA3_RLC3_IB_SIZE 0x0247 65560484Sobrien#define mmSDMA3_RLC3_IB_SIZE_BASE_IDX 1 65660484Sobrien#define mmSDMA3_RLC3_SKIP_CNTL 0x0248 65760484Sobrien#define mmSDMA3_RLC3_SKIP_CNTL_BASE_IDX 1 65860484Sobrien#define mmSDMA3_RLC3_CONTEXT_STATUS 0x0249 65960484Sobrien#define mmSDMA3_RLC3_CONTEXT_STATUS_BASE_IDX 1 66060484Sobrien#define mmSDMA3_RLC3_DOORBELL 0x024a 66160484Sobrien#define mmSDMA3_RLC3_DOORBELL_BASE_IDX 1 66260484Sobrien#define mmSDMA3_RLC3_STATUS 0x0260 66360484Sobrien#define mmSDMA3_RLC3_STATUS_BASE_IDX 1 66460484Sobrien#define mmSDMA3_RLC3_DOORBELL_LOG 0x0261 66560484Sobrien#define mmSDMA3_RLC3_DOORBELL_LOG_BASE_IDX 1 66660484Sobrien#define mmSDMA3_RLC3_WATERMARK 0x0262 66760484Sobrien#define mmSDMA3_RLC3_WATERMARK_BASE_IDX 1 66860484Sobrien#define mmSDMA3_RLC3_DOORBELL_OFFSET 0x0263 66960484Sobrien#define mmSDMA3_RLC3_DOORBELL_OFFSET_BASE_IDX 1 67060484Sobrien#define mmSDMA3_RLC3_CSA_ADDR_LO 0x0264 67160484Sobrien#define mmSDMA3_RLC3_CSA_ADDR_LO_BASE_IDX 1 67260484Sobrien#define mmSDMA3_RLC3_CSA_ADDR_HI 0x0265 67360484Sobrien#define mmSDMA3_RLC3_CSA_ADDR_HI_BASE_IDX 1 67460484Sobrien#define mmSDMA3_RLC3_IB_SUB_REMAIN 0x0267 67560484Sobrien#define mmSDMA3_RLC3_IB_SUB_REMAIN_BASE_IDX 1 67660484Sobrien#define mmSDMA3_RLC3_PREEMPT 0x0268 67760484Sobrien#define mmSDMA3_RLC3_PREEMPT_BASE_IDX 1 67860484Sobrien#define mmSDMA3_RLC3_DUMMY_REG 0x0269 67960484Sobrien#define mmSDMA3_RLC3_DUMMY_REG_BASE_IDX 1 68060484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI 0x026a 68160484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 68260484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO 0x026b 68360484Sobrien#define mmSDMA3_RLC3_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 68460484Sobrien#define mmSDMA3_RLC3_RB_AQL_CNTL 0x026c 68560484Sobrien#define mmSDMA3_RLC3_RB_AQL_CNTL_BASE_IDX 1 68660484Sobrien#define mmSDMA3_RLC3_MINOR_PTR_UPDATE 0x026d 68760484Sobrien#define mmSDMA3_RLC3_MINOR_PTR_UPDATE_BASE_IDX 1 68860484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA0 0x0278 68960484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA0_BASE_IDX 1 69060484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA1 0x0279 69160484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA1_BASE_IDX 1 69260484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA2 0x027a 69360484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA2_BASE_IDX 1 69460484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA3 0x027b 69560484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA3_BASE_IDX 1 69660484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA4 0x027c 69760484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA4_BASE_IDX 1 69860484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA5 0x027d 69960484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA5_BASE_IDX 1 70060484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA6 0x027e 70160484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA6_BASE_IDX 1 70260484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA7 0x027f 70360484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA7_BASE_IDX 1 70460484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA8 0x0280 70560484Sobrien#define mmSDMA3_RLC3_MIDCMD_DATA8_BASE_IDX 1 70660484Sobrien#define mmSDMA3_RLC3_MIDCMD_CNTL 0x0281 70760484Sobrien#define mmSDMA3_RLC3_MIDCMD_CNTL_BASE_IDX 1 70860484Sobrien#define mmSDMA3_RLC4_RB_CNTL 0x0290 70960484Sobrien#define mmSDMA3_RLC4_RB_CNTL_BASE_IDX 1 71060484Sobrien#define mmSDMA3_RLC4_RB_BASE 0x0291 71160484Sobrien#define mmSDMA3_RLC4_RB_BASE_BASE_IDX 1 71260484Sobrien#define mmSDMA3_RLC4_RB_BASE_HI 0x0292 71360484Sobrien#define mmSDMA3_RLC4_RB_BASE_HI_BASE_IDX 1 71460484Sobrien#define mmSDMA3_RLC4_RB_RPTR 0x0293 71560484Sobrien#define mmSDMA3_RLC4_RB_RPTR_BASE_IDX 1 71660484Sobrien#define mmSDMA3_RLC4_RB_RPTR_HI 0x0294 71760484Sobrien#define mmSDMA3_RLC4_RB_RPTR_HI_BASE_IDX 1 71860484Sobrien#define mmSDMA3_RLC4_RB_WPTR 0x0295 71960484Sobrien#define mmSDMA3_RLC4_RB_WPTR_BASE_IDX 1 72060484Sobrien#define mmSDMA3_RLC4_RB_WPTR_HI 0x0296 72160484Sobrien#define mmSDMA3_RLC4_RB_WPTR_HI_BASE_IDX 1 72260484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL 0x0297 72360484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_CNTL_BASE_IDX 1 72460484Sobrien#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI 0x0298 72560484Sobrien#define mmSDMA3_RLC4_RB_RPTR_ADDR_HI_BASE_IDX 1 72660484Sobrien#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO 0x0299 72760484Sobrien#define mmSDMA3_RLC4_RB_RPTR_ADDR_LO_BASE_IDX 1 72860484Sobrien#define mmSDMA3_RLC4_IB_CNTL 0x029a 72960484Sobrien#define mmSDMA3_RLC4_IB_CNTL_BASE_IDX 1 73060484Sobrien#define mmSDMA3_RLC4_IB_RPTR 0x029b 73160484Sobrien#define mmSDMA3_RLC4_IB_RPTR_BASE_IDX 1 73260484Sobrien#define mmSDMA3_RLC4_IB_OFFSET 0x029c 73360484Sobrien#define mmSDMA3_RLC4_IB_OFFSET_BASE_IDX 1 73460484Sobrien#define mmSDMA3_RLC4_IB_BASE_LO 0x029d 73560484Sobrien#define mmSDMA3_RLC4_IB_BASE_LO_BASE_IDX 1 73660484Sobrien#define mmSDMA3_RLC4_IB_BASE_HI 0x029e 73760484Sobrien#define mmSDMA3_RLC4_IB_BASE_HI_BASE_IDX 1 73860484Sobrien#define mmSDMA3_RLC4_IB_SIZE 0x029f 73960484Sobrien#define mmSDMA3_RLC4_IB_SIZE_BASE_IDX 1 74060484Sobrien#define mmSDMA3_RLC4_SKIP_CNTL 0x02a0 74160484Sobrien#define mmSDMA3_RLC4_SKIP_CNTL_BASE_IDX 1 74260484Sobrien#define mmSDMA3_RLC4_CONTEXT_STATUS 0x02a1 74360484Sobrien#define mmSDMA3_RLC4_CONTEXT_STATUS_BASE_IDX 1 74460484Sobrien#define mmSDMA3_RLC4_DOORBELL 0x02a2 74560484Sobrien#define mmSDMA3_RLC4_DOORBELL_BASE_IDX 1 74660484Sobrien#define mmSDMA3_RLC4_STATUS 0x02b8 74760484Sobrien#define mmSDMA3_RLC4_STATUS_BASE_IDX 1 74860484Sobrien#define mmSDMA3_RLC4_DOORBELL_LOG 0x02b9 74960484Sobrien#define mmSDMA3_RLC4_DOORBELL_LOG_BASE_IDX 1 75060484Sobrien#define mmSDMA3_RLC4_WATERMARK 0x02ba 75160484Sobrien#define mmSDMA3_RLC4_WATERMARK_BASE_IDX 1 75260484Sobrien#define mmSDMA3_RLC4_DOORBELL_OFFSET 0x02bb 75360484Sobrien#define mmSDMA3_RLC4_DOORBELL_OFFSET_BASE_IDX 1 75460484Sobrien#define mmSDMA3_RLC4_CSA_ADDR_LO 0x02bc 75560484Sobrien#define mmSDMA3_RLC4_CSA_ADDR_LO_BASE_IDX 1 75660484Sobrien#define mmSDMA3_RLC4_CSA_ADDR_HI 0x02bd 75760484Sobrien#define mmSDMA3_RLC4_CSA_ADDR_HI_BASE_IDX 1 75860484Sobrien#define mmSDMA3_RLC4_IB_SUB_REMAIN 0x02bf 75960484Sobrien#define mmSDMA3_RLC4_IB_SUB_REMAIN_BASE_IDX 1 76060484Sobrien#define mmSDMA3_RLC4_PREEMPT 0x02c0 76160484Sobrien#define mmSDMA3_RLC4_PREEMPT_BASE_IDX 1 76260484Sobrien#define mmSDMA3_RLC4_DUMMY_REG 0x02c1 76360484Sobrien#define mmSDMA3_RLC4_DUMMY_REG_BASE_IDX 1 76460484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI 0x02c2 76560484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 76660484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO 0x02c3 76760484Sobrien#define mmSDMA3_RLC4_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 76860484Sobrien#define mmSDMA3_RLC4_RB_AQL_CNTL 0x02c4 76960484Sobrien#define mmSDMA3_RLC4_RB_AQL_CNTL_BASE_IDX 1 77060484Sobrien#define mmSDMA3_RLC4_MINOR_PTR_UPDATE 0x02c5 77160484Sobrien#define mmSDMA3_RLC4_MINOR_PTR_UPDATE_BASE_IDX 1 77260484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA0 0x02d0 77360484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA0_BASE_IDX 1 77460484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA1 0x02d1 77560484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA1_BASE_IDX 1 77660484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA2 0x02d2 77760484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA2_BASE_IDX 1 77860484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA3 0x02d3 77960484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA3_BASE_IDX 1 78060484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA4 0x02d4 78160484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA4_BASE_IDX 1 78260484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA5 0x02d5 78360484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA5_BASE_IDX 1 78460484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA6 0x02d6 78560484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA6_BASE_IDX 1 78660484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA7 0x02d7 78760484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA7_BASE_IDX 1 78860484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA8 0x02d8 78960484Sobrien#define mmSDMA3_RLC4_MIDCMD_DATA8_BASE_IDX 1 79060484Sobrien#define mmSDMA3_RLC4_MIDCMD_CNTL 0x02d9 79160484Sobrien#define mmSDMA3_RLC4_MIDCMD_CNTL_BASE_IDX 1 79260484Sobrien#define mmSDMA3_RLC5_RB_CNTL 0x02e8 79360484Sobrien#define mmSDMA3_RLC5_RB_CNTL_BASE_IDX 1 79460484Sobrien#define mmSDMA3_RLC5_RB_BASE 0x02e9 79560484Sobrien#define mmSDMA3_RLC5_RB_BASE_BASE_IDX 1 79660484Sobrien#define mmSDMA3_RLC5_RB_BASE_HI 0x02ea 79760484Sobrien#define mmSDMA3_RLC5_RB_BASE_HI_BASE_IDX 1 79860484Sobrien#define mmSDMA3_RLC5_RB_RPTR 0x02eb 79960484Sobrien#define mmSDMA3_RLC5_RB_RPTR_BASE_IDX 1 80060484Sobrien#define mmSDMA3_RLC5_RB_RPTR_HI 0x02ec 80160484Sobrien#define mmSDMA3_RLC5_RB_RPTR_HI_BASE_IDX 1 80260484Sobrien#define mmSDMA3_RLC5_RB_WPTR 0x02ed 80360484Sobrien#define mmSDMA3_RLC5_RB_WPTR_BASE_IDX 1 80460484Sobrien#define mmSDMA3_RLC5_RB_WPTR_HI 0x02ee 80560484Sobrien#define mmSDMA3_RLC5_RB_WPTR_HI_BASE_IDX 1 80660484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL 0x02ef 80760484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_CNTL_BASE_IDX 1 80860484Sobrien#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI 0x02f0 80960484Sobrien#define mmSDMA3_RLC5_RB_RPTR_ADDR_HI_BASE_IDX 1 81060484Sobrien#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO 0x02f1 81160484Sobrien#define mmSDMA3_RLC5_RB_RPTR_ADDR_LO_BASE_IDX 1 81260484Sobrien#define mmSDMA3_RLC5_IB_CNTL 0x02f2 81360484Sobrien#define mmSDMA3_RLC5_IB_CNTL_BASE_IDX 1 81460484Sobrien#define mmSDMA3_RLC5_IB_RPTR 0x02f3 81560484Sobrien#define mmSDMA3_RLC5_IB_RPTR_BASE_IDX 1 81660484Sobrien#define mmSDMA3_RLC5_IB_OFFSET 0x02f4 81760484Sobrien#define mmSDMA3_RLC5_IB_OFFSET_BASE_IDX 1 81860484Sobrien#define mmSDMA3_RLC5_IB_BASE_LO 0x02f5 81960484Sobrien#define mmSDMA3_RLC5_IB_BASE_LO_BASE_IDX 1 82060484Sobrien#define mmSDMA3_RLC5_IB_BASE_HI 0x02f6 82160484Sobrien#define mmSDMA3_RLC5_IB_BASE_HI_BASE_IDX 1 82260484Sobrien#define mmSDMA3_RLC5_IB_SIZE 0x02f7 82360484Sobrien#define mmSDMA3_RLC5_IB_SIZE_BASE_IDX 1 82460484Sobrien#define mmSDMA3_RLC5_SKIP_CNTL 0x02f8 82560484Sobrien#define mmSDMA3_RLC5_SKIP_CNTL_BASE_IDX 1 82660484Sobrien#define mmSDMA3_RLC5_CONTEXT_STATUS 0x02f9 82760484Sobrien#define mmSDMA3_RLC5_CONTEXT_STATUS_BASE_IDX 1 82860484Sobrien#define mmSDMA3_RLC5_DOORBELL 0x02fa 82960484Sobrien#define mmSDMA3_RLC5_DOORBELL_BASE_IDX 1 83060484Sobrien#define mmSDMA3_RLC5_STATUS 0x0310 83160484Sobrien#define mmSDMA3_RLC5_STATUS_BASE_IDX 1 83260484Sobrien#define mmSDMA3_RLC5_DOORBELL_LOG 0x0311 83360484Sobrien#define mmSDMA3_RLC5_DOORBELL_LOG_BASE_IDX 1 83460484Sobrien#define mmSDMA3_RLC5_WATERMARK 0x0312 83560484Sobrien#define mmSDMA3_RLC5_WATERMARK_BASE_IDX 1 83660484Sobrien#define mmSDMA3_RLC5_DOORBELL_OFFSET 0x0313 83760484Sobrien#define mmSDMA3_RLC5_DOORBELL_OFFSET_BASE_IDX 1 83860484Sobrien#define mmSDMA3_RLC5_CSA_ADDR_LO 0x0314 83960484Sobrien#define mmSDMA3_RLC5_CSA_ADDR_LO_BASE_IDX 1 84060484Sobrien#define mmSDMA3_RLC5_CSA_ADDR_HI 0x0315 84160484Sobrien#define mmSDMA3_RLC5_CSA_ADDR_HI_BASE_IDX 1 84260484Sobrien#define mmSDMA3_RLC5_IB_SUB_REMAIN 0x0317 84360484Sobrien#define mmSDMA3_RLC5_IB_SUB_REMAIN_BASE_IDX 1 84460484Sobrien#define mmSDMA3_RLC5_PREEMPT 0x0318 84560484Sobrien#define mmSDMA3_RLC5_PREEMPT_BASE_IDX 1 84660484Sobrien#define mmSDMA3_RLC5_DUMMY_REG 0x0319 84760484Sobrien#define mmSDMA3_RLC5_DUMMY_REG_BASE_IDX 1 84860484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI 0x031a 84960484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 85060484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO 0x031b 85160484Sobrien#define mmSDMA3_RLC5_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 85260484Sobrien#define mmSDMA3_RLC5_RB_AQL_CNTL 0x031c 85360484Sobrien#define mmSDMA3_RLC5_RB_AQL_CNTL_BASE_IDX 1 85460484Sobrien#define mmSDMA3_RLC5_MINOR_PTR_UPDATE 0x031d 85560484Sobrien#define mmSDMA3_RLC5_MINOR_PTR_UPDATE_BASE_IDX 1 85660484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA0 0x0328 85760484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA0_BASE_IDX 1 85860484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA1 0x0329 85960484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA1_BASE_IDX 1 86060484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA2 0x032a 86160484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA2_BASE_IDX 1 86260484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA3 0x032b 86360484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA3_BASE_IDX 1 86460484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA4 0x032c 86560484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA4_BASE_IDX 1 86660484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA5 0x032d 86760484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA5_BASE_IDX 1 86860484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA6 0x032e 86960484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA6_BASE_IDX 1 87060484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA7 0x032f 87160484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA7_BASE_IDX 1 87260484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA8 0x0330 87360484Sobrien#define mmSDMA3_RLC5_MIDCMD_DATA8_BASE_IDX 1 87460484Sobrien#define mmSDMA3_RLC5_MIDCMD_CNTL 0x0331 87560484Sobrien#define mmSDMA3_RLC5_MIDCMD_CNTL_BASE_IDX 1 87660484Sobrien#define mmSDMA3_RLC6_RB_CNTL 0x0340 87760484Sobrien#define mmSDMA3_RLC6_RB_CNTL_BASE_IDX 1 87860484Sobrien#define mmSDMA3_RLC6_RB_BASE 0x0341 87960484Sobrien#define mmSDMA3_RLC6_RB_BASE_BASE_IDX 1 88077298Sobrien#define mmSDMA3_RLC6_RB_BASE_HI 0x0342 88160484Sobrien#define mmSDMA3_RLC6_RB_BASE_HI_BASE_IDX 1 88260484Sobrien#define mmSDMA3_RLC6_RB_RPTR 0x0343 88360484Sobrien#define mmSDMA3_RLC6_RB_RPTR_BASE_IDX 1 88460484Sobrien#define mmSDMA3_RLC6_RB_RPTR_HI 0x0344 88560484Sobrien#define mmSDMA3_RLC6_RB_RPTR_HI_BASE_IDX 1 88660484Sobrien#define mmSDMA3_RLC6_RB_WPTR 0x0345 88760484Sobrien#define mmSDMA3_RLC6_RB_WPTR_BASE_IDX 1 88860484Sobrien#define mmSDMA3_RLC6_RB_WPTR_HI 0x0346 88960484Sobrien#define mmSDMA3_RLC6_RB_WPTR_HI_BASE_IDX 1 89060484Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL 0x0347 89177298Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_CNTL_BASE_IDX 1 89277298Sobrien#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI 0x0348 89377298Sobrien#define mmSDMA3_RLC6_RB_RPTR_ADDR_HI_BASE_IDX 1 89477298Sobrien#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO 0x0349 89577298Sobrien#define mmSDMA3_RLC6_RB_RPTR_ADDR_LO_BASE_IDX 1 89677298Sobrien#define mmSDMA3_RLC6_IB_CNTL 0x034a 89777298Sobrien#define mmSDMA3_RLC6_IB_CNTL_BASE_IDX 1 89877298Sobrien#define mmSDMA3_RLC6_IB_RPTR 0x034b 89977298Sobrien#define mmSDMA3_RLC6_IB_RPTR_BASE_IDX 1 90077298Sobrien#define mmSDMA3_RLC6_IB_OFFSET 0x034c 90177298Sobrien#define mmSDMA3_RLC6_IB_OFFSET_BASE_IDX 1 90277298Sobrien#define mmSDMA3_RLC6_IB_BASE_LO 0x034d 90377298Sobrien#define mmSDMA3_RLC6_IB_BASE_LO_BASE_IDX 1 90477298Sobrien#define mmSDMA3_RLC6_IB_BASE_HI 0x034e 90577298Sobrien#define mmSDMA3_RLC6_IB_BASE_HI_BASE_IDX 1 90660484Sobrien#define mmSDMA3_RLC6_IB_SIZE 0x034f 90760484Sobrien#define mmSDMA3_RLC6_IB_SIZE_BASE_IDX 1 90860484Sobrien#define mmSDMA3_RLC6_SKIP_CNTL 0x0350 90960484Sobrien#define mmSDMA3_RLC6_SKIP_CNTL_BASE_IDX 1 91060484Sobrien#define mmSDMA3_RLC6_CONTEXT_STATUS 0x0351 91160484Sobrien#define mmSDMA3_RLC6_CONTEXT_STATUS_BASE_IDX 1 91260484Sobrien#define mmSDMA3_RLC6_DOORBELL 0x0352 91360484Sobrien#define mmSDMA3_RLC6_DOORBELL_BASE_IDX 1 91460484Sobrien#define mmSDMA3_RLC6_STATUS 0x0368 91560484Sobrien#define mmSDMA3_RLC6_STATUS_BASE_IDX 1 91660484Sobrien#define mmSDMA3_RLC6_DOORBELL_LOG 0x0369 91760484Sobrien#define mmSDMA3_RLC6_DOORBELL_LOG_BASE_IDX 1 91860484Sobrien#define mmSDMA3_RLC6_WATERMARK 0x036a 91960484Sobrien#define mmSDMA3_RLC6_WATERMARK_BASE_IDX 1 92060484Sobrien#define mmSDMA3_RLC6_DOORBELL_OFFSET 0x036b 92160484Sobrien#define mmSDMA3_RLC6_DOORBELL_OFFSET_BASE_IDX 1 92260484Sobrien#define mmSDMA3_RLC6_CSA_ADDR_LO 0x036c 92360484Sobrien#define mmSDMA3_RLC6_CSA_ADDR_LO_BASE_IDX 1 92460484Sobrien#define mmSDMA3_RLC6_CSA_ADDR_HI 0x036d 92560484Sobrien#define mmSDMA3_RLC6_CSA_ADDR_HI_BASE_IDX 1 92660484Sobrien#define mmSDMA3_RLC6_IB_SUB_REMAIN 0x036f 92760484Sobrien#define mmSDMA3_RLC6_IB_SUB_REMAIN_BASE_IDX 1 92860484Sobrien#define mmSDMA3_RLC6_PREEMPT 0x0370 92960484Sobrien#define mmSDMA3_RLC6_PREEMPT_BASE_IDX 1 93060484Sobrien#define mmSDMA3_RLC6_DUMMY_REG 0x0371 93160484Sobrien#define mmSDMA3_RLC6_DUMMY_REG_BASE_IDX 1 93260484Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI 0x0372 93360484Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 93460484Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO 0x0373 93560484Sobrien#define mmSDMA3_RLC6_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 93660484Sobrien#define mmSDMA3_RLC6_RB_AQL_CNTL 0x0374 93760484Sobrien#define mmSDMA3_RLC6_RB_AQL_CNTL_BASE_IDX 1 93860484Sobrien#define mmSDMA3_RLC6_MINOR_PTR_UPDATE 0x0375 93960484Sobrien#define mmSDMA3_RLC6_MINOR_PTR_UPDATE_BASE_IDX 1 94060484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA0 0x0380 94160484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA0_BASE_IDX 1 94260484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA1 0x0381 94360484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA1_BASE_IDX 1 94460484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA2 0x0382 94560484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA2_BASE_IDX 1 94660484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA3 0x0383 94760484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA3_BASE_IDX 1 94860484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA4 0x0384 94960484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA4_BASE_IDX 1 95060484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA5 0x0385 95160484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA5_BASE_IDX 1 95260484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA6 0x0386 95360484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA6_BASE_IDX 1 95460484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA7 0x0387 95560484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA7_BASE_IDX 1 95660484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA8 0x0388 95760484Sobrien#define mmSDMA3_RLC6_MIDCMD_DATA8_BASE_IDX 1 95860484Sobrien#define mmSDMA3_RLC6_MIDCMD_CNTL 0x0389 95960484Sobrien#define mmSDMA3_RLC6_MIDCMD_CNTL_BASE_IDX 1 96060484Sobrien#define mmSDMA3_RLC7_RB_CNTL 0x0398 96160484Sobrien#define mmSDMA3_RLC7_RB_CNTL_BASE_IDX 1 96260484Sobrien#define mmSDMA3_RLC7_RB_BASE 0x0399 96360484Sobrien#define mmSDMA3_RLC7_RB_BASE_BASE_IDX 1 96460484Sobrien#define mmSDMA3_RLC7_RB_BASE_HI 0x039a 96560484Sobrien#define mmSDMA3_RLC7_RB_BASE_HI_BASE_IDX 1 96660484Sobrien#define mmSDMA3_RLC7_RB_RPTR 0x039b 96760484Sobrien#define mmSDMA3_RLC7_RB_RPTR_BASE_IDX 1 96860484Sobrien#define mmSDMA3_RLC7_RB_RPTR_HI 0x039c 96960484Sobrien#define mmSDMA3_RLC7_RB_RPTR_HI_BASE_IDX 1 97060484Sobrien#define mmSDMA3_RLC7_RB_WPTR 0x039d 97160484Sobrien#define mmSDMA3_RLC7_RB_WPTR_BASE_IDX 1 97260484Sobrien#define mmSDMA3_RLC7_RB_WPTR_HI 0x039e 97360484Sobrien#define mmSDMA3_RLC7_RB_WPTR_HI_BASE_IDX 1 97460484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL 0x039f 97560484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_CNTL_BASE_IDX 1 97660484Sobrien#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI 0x03a0 97760484Sobrien#define mmSDMA3_RLC7_RB_RPTR_ADDR_HI_BASE_IDX 1 97860484Sobrien#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO 0x03a1 97960484Sobrien#define mmSDMA3_RLC7_RB_RPTR_ADDR_LO_BASE_IDX 1 98060484Sobrien#define mmSDMA3_RLC7_IB_CNTL 0x03a2 98160484Sobrien#define mmSDMA3_RLC7_IB_CNTL_BASE_IDX 1 98260484Sobrien#define mmSDMA3_RLC7_IB_RPTR 0x03a3 98360484Sobrien#define mmSDMA3_RLC7_IB_RPTR_BASE_IDX 1 98460484Sobrien#define mmSDMA3_RLC7_IB_OFFSET 0x03a4 98560484Sobrien#define mmSDMA3_RLC7_IB_OFFSET_BASE_IDX 1 98660484Sobrien#define mmSDMA3_RLC7_IB_BASE_LO 0x03a5 98760484Sobrien#define mmSDMA3_RLC7_IB_BASE_LO_BASE_IDX 1 98860484Sobrien#define mmSDMA3_RLC7_IB_BASE_HI 0x03a6 98960484Sobrien#define mmSDMA3_RLC7_IB_BASE_HI_BASE_IDX 1 99060484Sobrien#define mmSDMA3_RLC7_IB_SIZE 0x03a7 99160484Sobrien#define mmSDMA3_RLC7_IB_SIZE_BASE_IDX 1 99260484Sobrien#define mmSDMA3_RLC7_SKIP_CNTL 0x03a8 99360484Sobrien#define mmSDMA3_RLC7_SKIP_CNTL_BASE_IDX 1 99460484Sobrien#define mmSDMA3_RLC7_CONTEXT_STATUS 0x03a9 99560484Sobrien#define mmSDMA3_RLC7_CONTEXT_STATUS_BASE_IDX 1 99660484Sobrien#define mmSDMA3_RLC7_DOORBELL 0x03aa 99760484Sobrien#define mmSDMA3_RLC7_DOORBELL_BASE_IDX 1 99860484Sobrien#define mmSDMA3_RLC7_STATUS 0x03c0 99960484Sobrien#define mmSDMA3_RLC7_STATUS_BASE_IDX 1 100060484Sobrien#define mmSDMA3_RLC7_DOORBELL_LOG 0x03c1 100160484Sobrien#define mmSDMA3_RLC7_DOORBELL_LOG_BASE_IDX 1 100260484Sobrien#define mmSDMA3_RLC7_WATERMARK 0x03c2 100360484Sobrien#define mmSDMA3_RLC7_WATERMARK_BASE_IDX 1 100460484Sobrien#define mmSDMA3_RLC7_DOORBELL_OFFSET 0x03c3 100560484Sobrien#define mmSDMA3_RLC7_DOORBELL_OFFSET_BASE_IDX 1 100660484Sobrien#define mmSDMA3_RLC7_CSA_ADDR_LO 0x03c4 100760484Sobrien#define mmSDMA3_RLC7_CSA_ADDR_LO_BASE_IDX 1 100860484Sobrien#define mmSDMA3_RLC7_CSA_ADDR_HI 0x03c5 100960484Sobrien#define mmSDMA3_RLC7_CSA_ADDR_HI_BASE_IDX 1 101060484Sobrien#define mmSDMA3_RLC7_IB_SUB_REMAIN 0x03c7 101160484Sobrien#define mmSDMA3_RLC7_IB_SUB_REMAIN_BASE_IDX 1 101260484Sobrien#define mmSDMA3_RLC7_PREEMPT 0x03c8 101360484Sobrien#define mmSDMA3_RLC7_PREEMPT_BASE_IDX 1 101460484Sobrien#define mmSDMA3_RLC7_DUMMY_REG 0x03c9 101560484Sobrien#define mmSDMA3_RLC7_DUMMY_REG_BASE_IDX 1 101660484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI 0x03ca 101760484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_HI_BASE_IDX 1 101860484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO 0x03cb 101960484Sobrien#define mmSDMA3_RLC7_RB_WPTR_POLL_ADDR_LO_BASE_IDX 1 102060484Sobrien#define mmSDMA3_RLC7_RB_AQL_CNTL 0x03cc 102160484Sobrien#define mmSDMA3_RLC7_RB_AQL_CNTL_BASE_IDX 1 102260484Sobrien#define mmSDMA3_RLC7_MINOR_PTR_UPDATE 0x03cd 102360484Sobrien#define mmSDMA3_RLC7_MINOR_PTR_UPDATE_BASE_IDX 1 102460484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA0 0x03d8 102560484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA0_BASE_IDX 1 102660484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA1 0x03d9 102760484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA1_BASE_IDX 1 102860484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA2 0x03da 102960484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA2_BASE_IDX 1 103060484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA3 0x03db 103160484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA3_BASE_IDX 1 103260484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA4 0x03dc 103360484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA4_BASE_IDX 1 103460484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA5 0x03dd 103560484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA5_BASE_IDX 1 103660484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA6 0x03de 103760484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA6_BASE_IDX 1 103860484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA7 0x03df 103960484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA7_BASE_IDX 1 104060484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA8 0x03e0 104160484Sobrien#define mmSDMA3_RLC7_MIDCMD_DATA8_BASE_IDX 1 104260484Sobrien#define mmSDMA3_RLC7_MIDCMD_CNTL 0x03e1 104360484Sobrien#define mmSDMA3_RLC7_MIDCMD_CNTL_BASE_IDX 1 104460484Sobrien 104560484Sobrien#endif 104660484Sobrien