1/* $NetBSD: nbif_6_1_sh_mask.h,v 1.2 2021/12/18 23:45:17 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _nbif_6_1_SH_MASK_HEADER 24#define _nbif_6_1_SH_MASK_HEADER 25 26 27// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp 28//VENDOR_ID 29#define VENDOR_ID__VENDOR_ID__SHIFT 0x0 30//DEVICE_ID 31#define DEVICE_ID__DEVICE_ID__SHIFT 0x0 32//COMMAND 33#define COMMAND__IO_ACCESS_EN__SHIFT 0x0 34#define COMMAND__MEM_ACCESS_EN__SHIFT 0x1 35#define COMMAND__BUS_MASTER_EN__SHIFT 0x2 36#define COMMAND__SPECIAL_CYCLE_EN__SHIFT 0x3 37#define COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT 0x4 38#define COMMAND__PAL_SNOOP_EN__SHIFT 0x5 39#define COMMAND__PARITY_ERROR_RESPONSE__SHIFT 0x6 40#define COMMAND__AD_STEPPING__SHIFT 0x7 41#define COMMAND__SERR_EN__SHIFT 0x8 42#define COMMAND__FAST_B2B_EN__SHIFT 0x9 43#define COMMAND__INT_DIS__SHIFT 0xa 44//STATUS 45#define STATUS__INT_STATUS__SHIFT 0x3 46#define STATUS__CAP_LIST__SHIFT 0x4 47#define STATUS__PCI_66_EN__SHIFT 0x5 48#define STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 49#define STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 50#define STATUS__DEVSEL_TIMING__SHIFT 0x9 51#define STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 52#define STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 53#define STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 54#define STATUS__SIGNALED_SYSTEM_ERROR__SHIFT 0xe 55#define STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 56//REVISION_ID 57#define REVISION_ID__MINOR_REV_ID__SHIFT 0x0 58#define REVISION_ID__MAJOR_REV_ID__SHIFT 0x4 59//PROG_INTERFACE 60#define PROG_INTERFACE__PROG_INTERFACE__SHIFT 0x0 61//SUB_CLASS 62#define SUB_CLASS__SUB_CLASS__SHIFT 0x0 63//BASE_CLASS 64#define BASE_CLASS__BASE_CLASS__SHIFT 0x0 65//CACHE_LINE 66#define CACHE_LINE__CACHE_LINE_SIZE__SHIFT 0x0 67//LATENCY 68#define LATENCY__LATENCY_TIMER__SHIFT 0x0 69//HEADER 70#define HEADER__HEADER_TYPE__SHIFT 0x0 71#define HEADER__DEVICE_TYPE__SHIFT 0x7 72//BIST 73#define BIST__BIST_COMP__SHIFT 0x0 74#define BIST__BIST_STRT__SHIFT 0x6 75#define BIST__BIST_CAP__SHIFT 0x7 76//BASE_ADDR_1 77#define BASE_ADDR_1__BASE_ADDR__SHIFT 0x0 78//BASE_ADDR_2 79#define BASE_ADDR_2__BASE_ADDR__SHIFT 0x0 80//BASE_ADDR_3 81#define BASE_ADDR_3__BASE_ADDR__SHIFT 0x0 82//BASE_ADDR_4 83#define BASE_ADDR_4__BASE_ADDR__SHIFT 0x0 84//BASE_ADDR_5 85#define BASE_ADDR_5__BASE_ADDR__SHIFT 0x0 86//BASE_ADDR_6 87#define BASE_ADDR_6__BASE_ADDR__SHIFT 0x0 88//ADAPTER_ID 89#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 90#define ADAPTER_ID__SUBSYSTEM_ID__SHIFT 0x10 91//ROM_BASE_ADDR 92#define ROM_BASE_ADDR__BASE_ADDR__SHIFT 0x0 93//CAP_PTR 94#define CAP_PTR__CAP_PTR__SHIFT 0x0 95//INTERRUPT_LINE 96#define INTERRUPT_LINE__INTERRUPT_LINE__SHIFT 0x0 97//INTERRUPT_PIN 98#define INTERRUPT_PIN__INTERRUPT_PIN__SHIFT 0x0 99//MIN_GRANT 100#define MIN_GRANT__MIN_GNT__SHIFT 0x0 101//MAX_LATENCY 102#define MAX_LATENCY__MAX_LAT__SHIFT 0x0 103//VENDOR_CAP_LIST 104#define VENDOR_CAP_LIST__CAP_ID__SHIFT 0x0 105#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT 0x8 106#define VENDOR_CAP_LIST__LENGTH__SHIFT 0x10 107//ADAPTER_ID_W 108#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 109#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT 0x10 110//PMI_CAP_LIST 111#define PMI_CAP_LIST__CAP_ID__SHIFT 0x0 112#define PMI_CAP_LIST__NEXT_PTR__SHIFT 0x8 113//PMI_CAP 114#define PMI_CAP__VERSION__SHIFT 0x0 115#define PMI_CAP__PME_CLOCK__SHIFT 0x3 116#define PMI_CAP__DEV_SPECIFIC_INIT__SHIFT 0x5 117#define PMI_CAP__AUX_CURRENT__SHIFT 0x6 118#define PMI_CAP__D1_SUPPORT__SHIFT 0x9 119#define PMI_CAP__D2_SUPPORT__SHIFT 0xa 120#define PMI_CAP__PME_SUPPORT__SHIFT 0xb 121//PMI_STATUS_CNTL 122#define PMI_STATUS_CNTL__POWER_STATE__SHIFT 0x0 123#define PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT 0x3 124#define PMI_STATUS_CNTL__PME_EN__SHIFT 0x8 125#define PMI_STATUS_CNTL__DATA_SELECT__SHIFT 0x9 126#define PMI_STATUS_CNTL__DATA_SCALE__SHIFT 0xd 127#define PMI_STATUS_CNTL__PME_STATUS__SHIFT 0xf 128#define PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT 0x16 129#define PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT 0x17 130#define PMI_STATUS_CNTL__PMI_DATA__SHIFT 0x18 131//PCIE_CAP_LIST 132#define PCIE_CAP_LIST__CAP_ID__SHIFT 0x0 133#define PCIE_CAP_LIST__NEXT_PTR__SHIFT 0x8 134//PCIE_CAP 135#define PCIE_CAP__VERSION__SHIFT 0x0 136#define PCIE_CAP__DEVICE_TYPE__SHIFT 0x4 137#define PCIE_CAP__SLOT_IMPLEMENTED__SHIFT 0x8 138#define PCIE_CAP__INT_MESSAGE_NUM__SHIFT 0x9 139//DEVICE_CAP 140#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT 0x0 141#define DEVICE_CAP__PHANTOM_FUNC__SHIFT 0x3 142#define DEVICE_CAP__EXTENDED_TAG__SHIFT 0x5 143#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT 0x6 144#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT 0x9 145#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT 0xf 146#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT 0x12 147#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT 0x1a 148#define DEVICE_CAP__FLR_CAPABLE__SHIFT 0x1c 149//DEVICE_CNTL 150#define DEVICE_CNTL__CORR_ERR_EN__SHIFT 0x0 151#define DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT 0x1 152#define DEVICE_CNTL__FATAL_ERR_EN__SHIFT 0x2 153#define DEVICE_CNTL__USR_REPORT_EN__SHIFT 0x3 154#define DEVICE_CNTL__RELAXED_ORD_EN__SHIFT 0x4 155#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT 0x5 156#define DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT 0x8 157#define DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT 0x9 158#define DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT 0xa 159#define DEVICE_CNTL__NO_SNOOP_EN__SHIFT 0xb 160#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT 0xc 161#define DEVICE_CNTL__INITIATE_FLR__SHIFT 0xf 162//DEVICE_STATUS 163#define DEVICE_STATUS__CORR_ERR__SHIFT 0x0 164#define DEVICE_STATUS__NON_FATAL_ERR__SHIFT 0x1 165#define DEVICE_STATUS__FATAL_ERR__SHIFT 0x2 166#define DEVICE_STATUS__USR_DETECTED__SHIFT 0x3 167#define DEVICE_STATUS__AUX_PWR__SHIFT 0x4 168#define DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT 0x5 169//LINK_CAP 170#define LINK_CAP__LINK_SPEED__SHIFT 0x0 171#define LINK_CAP__LINK_WIDTH__SHIFT 0x4 172#define LINK_CAP__PM_SUPPORT__SHIFT 0xa 173#define LINK_CAP__L0S_EXIT_LATENCY__SHIFT 0xc 174#define LINK_CAP__L1_EXIT_LATENCY__SHIFT 0xf 175#define LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT 0x12 176#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT 0x13 177#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT 0x14 178#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT 0x15 179#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT 0x16 180#define LINK_CAP__PORT_NUMBER__SHIFT 0x18 181//LINK_CNTL 182#define LINK_CNTL__PM_CONTROL__SHIFT 0x0 183#define LINK_CNTL__READ_CPL_BOUNDARY__SHIFT 0x3 184#define LINK_CNTL__LINK_DIS__SHIFT 0x4 185#define LINK_CNTL__RETRAIN_LINK__SHIFT 0x5 186#define LINK_CNTL__COMMON_CLOCK_CFG__SHIFT 0x6 187#define LINK_CNTL__EXTENDED_SYNC__SHIFT 0x7 188#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT 0x8 189#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT 0x9 190#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT 0xa 191#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT 0xb 192//LINK_STATUS 193#define LINK_STATUS__CURRENT_LINK_SPEED__SHIFT 0x0 194#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT 0x4 195#define LINK_STATUS__LINK_TRAINING__SHIFT 0xb 196#define LINK_STATUS__SLOT_CLOCK_CFG__SHIFT 0xc 197#define LINK_STATUS__DL_ACTIVE__SHIFT 0xd 198#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT 0xe 199#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT 0xf 200//DEVICE_CAP2 201#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT 0x0 202#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT 0x4 203#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT 0x5 204#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT 0x6 205#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT 0x7 206#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT 0x8 207#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT 0x9 208#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT 0xa 209#define DEVICE_CAP2__LTR_SUPPORTED__SHIFT 0xb 210#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT 0xc 211#define DEVICE_CAP2__OBFF_SUPPORTED__SHIFT 0x12 212#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT 0x14 213#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT 0x15 214#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT 0x16 215//DEVICE_CNTL2 216#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT 0x0 217#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT 0x4 218#define DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT 0x5 219#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT 0x6 220#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT 0x7 221#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT 0x8 222#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT 0x9 223#define DEVICE_CNTL2__LTR_EN__SHIFT 0xa 224#define DEVICE_CNTL2__OBFF_EN__SHIFT 0xd 225#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT 0xf 226//DEVICE_STATUS2 227#define DEVICE_STATUS2__RESERVED__SHIFT 0x0 228//LINK_CAP2 229#define LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT 0x1 230#define LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT 0x8 231#define LINK_CAP2__RESERVED__SHIFT 0x9 232//LINK_CNTL2 233#define LINK_CNTL2__TARGET_LINK_SPEED__SHIFT 0x0 234#define LINK_CNTL2__ENTER_COMPLIANCE__SHIFT 0x4 235#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT 0x5 236#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT 0x6 237#define LINK_CNTL2__XMIT_MARGIN__SHIFT 0x7 238#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT 0xa 239#define LINK_CNTL2__COMPLIANCE_SOS__SHIFT 0xb 240#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT 0xc 241//LINK_STATUS2 242#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT 0x0 243#define LINK_STATUS2__EQUALIZATION_COMPLETE__SHIFT 0x1 244#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__SHIFT 0x2 245#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__SHIFT 0x3 246#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__SHIFT 0x4 247#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__SHIFT 0x5 248//SLOT_CAP2 249#define SLOT_CAP2__RESERVED__SHIFT 0x0 250//SLOT_CNTL2 251#define SLOT_CNTL2__RESERVED__SHIFT 0x0 252//SLOT_STATUS2 253#define SLOT_STATUS2__RESERVED__SHIFT 0x0 254//MSI_CAP_LIST 255#define MSI_CAP_LIST__CAP_ID__SHIFT 0x0 256#define MSI_CAP_LIST__NEXT_PTR__SHIFT 0x8 257//MSI_MSG_CNTL 258#define MSI_MSG_CNTL__MSI_EN__SHIFT 0x0 259#define MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT 0x1 260#define MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT 0x4 261#define MSI_MSG_CNTL__MSI_64BIT__SHIFT 0x7 262#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT 0x8 263//MSI_MSG_ADDR_LO 264#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT 0x2 265//MSI_MSG_ADDR_HI 266#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT 0x0 267//MSI_MSG_DATA 268#define MSI_MSG_DATA__MSI_DATA__SHIFT 0x0 269//MSI_MSG_DATA_64 270#define MSI_MSG_DATA_64__MSI_DATA_64__SHIFT 0x0 271//MSI_MASK 272#define MSI_MASK__MSI_MASK__SHIFT 0x0 273//MSI_PENDING 274#define MSI_PENDING__MSI_PENDING__SHIFT 0x0 275//MSI_MASK_64 276#define MSI_MASK_64__MSI_MASK_64__SHIFT 0x0 277//MSI_PENDING_64 278#define MSI_PENDING_64__MSI_PENDING_64__SHIFT 0x0 279//MSIX_CAP_LIST 280#define MSIX_CAP_LIST__CAP_ID__SHIFT 0x0 281#define MSIX_CAP_LIST__NEXT_PTR__SHIFT 0x8 282//MSIX_MSG_CNTL 283#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT 0x0 284#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT 0xe 285#define MSIX_MSG_CNTL__MSIX_EN__SHIFT 0xf 286//MSIX_TABLE 287#define MSIX_TABLE__MSIX_TABLE_BIR__SHIFT 0x0 288#define MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT 0x3 289//MSIX_PBA 290#define MSIX_PBA__MSIX_PBA_BIR__SHIFT 0x0 291#define MSIX_PBA__MSIX_PBA_OFFSET__SHIFT 0x3 292//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 293#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 294#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 295#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 296//PCIE_VENDOR_SPECIFIC_HDR 297#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT 0x0 298#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT 0x10 299#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT 0x14 300//PCIE_VENDOR_SPECIFIC1 301#define PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT 0x0 302//PCIE_VENDOR_SPECIFIC2 303#define PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT 0x0 304//PCIE_VC_ENH_CAP_LIST 305#define PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 306#define PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 307#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 308//PCIE_PORT_VC_CAP_REG1 309#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT 0x0 310#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT 0x4 311#define PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT 0x8 312#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT 0xa 313//PCIE_PORT_VC_CAP_REG2 314#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT 0x0 315#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT 0x18 316//PCIE_PORT_VC_CNTL 317#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT 0x0 318#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT 0x1 319//PCIE_PORT_VC_STATUS 320#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT 0x0 321//PCIE_VC0_RESOURCE_CAP 322#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 323#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 324#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 325#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 326//PCIE_VC0_RESOURCE_CNTL 327#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 328#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 329#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 330#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 331#define PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT 0x18 332#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 333//PCIE_VC0_RESOURCE_STATUS 334#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 335#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 336//PCIE_VC1_RESOURCE_CAP 337#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT 0x0 338#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT 0xf 339#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT 0x10 340#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT 0x18 341//PCIE_VC1_RESOURCE_CNTL 342#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT 0x0 343#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT 0x1 344#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT 0x10 345#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT 0x11 346#define PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT 0x18 347#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT 0x1f 348//PCIE_VC1_RESOURCE_STATUS 349#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT 0x0 350#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT 0x1 351//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 352#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 353#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 354#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 355//PCIE_DEV_SERIAL_NUM_DW1 356#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT 0x0 357//PCIE_DEV_SERIAL_NUM_DW2 358#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT 0x0 359//PCIE_ADV_ERR_RPT_ENH_CAP_LIST 360#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 361#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 362#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 363//PCIE_UNCORR_ERR_STATUS 364#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT 0x4 365#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT 0x5 366#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT 0xc 367#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT 0xd 368#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT 0xe 369#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT 0xf 370#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT 0x10 371#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT 0x11 372#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT 0x12 373#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT 0x13 374#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT 0x14 375#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT 0x15 376#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT 0x16 377#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT 0x17 378#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT 0x18 379#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT 0x19 380//PCIE_UNCORR_ERR_MASK 381#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT 0x4 382#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT 0x5 383#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT 0xc 384#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT 0xd 385#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT 0xe 386#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT 0xf 387#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT 0x10 388#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT 0x11 389#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT 0x12 390#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT 0x13 391#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT 0x14 392#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT 0x15 393#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT 0x16 394#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT 0x17 395#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT 0x18 396#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT 0x19 397//PCIE_UNCORR_ERR_SEVERITY 398#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT 0x4 399#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT 0x5 400#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT 0xc 401#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT 0xd 402#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT 0xe 403#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT 0xf 404#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT 0x10 405#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT 0x11 406#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT 0x12 407#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT 0x13 408#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT 0x14 409#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT 0x15 410#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT 0x16 411#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT 0x17 412#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT 0x18 413#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT 0x19 414//PCIE_CORR_ERR_STATUS 415#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT 0x0 416#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT 0x6 417#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT 0x7 418#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT 0x8 419#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT 0xc 420#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0xd 421#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT 0xe 422#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT 0xf 423//PCIE_CORR_ERR_MASK 424#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT 0x0 425#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT 0x6 426#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT 0x7 427#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT 0x8 428#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT 0xc 429#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT 0xd 430#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT 0xe 431#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT 0xf 432//PCIE_ADV_ERR_CAP_CNTL 433#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT 0x0 434#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT 0x5 435#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT 0x6 436#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT 0x7 437#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT 0x8 438#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT 0x9 439#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT 0xa 440#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT 0xb 441//PCIE_HDR_LOG0 442#define PCIE_HDR_LOG0__TLP_HDR__SHIFT 0x0 443//PCIE_HDR_LOG1 444#define PCIE_HDR_LOG1__TLP_HDR__SHIFT 0x0 445//PCIE_HDR_LOG2 446#define PCIE_HDR_LOG2__TLP_HDR__SHIFT 0x0 447//PCIE_HDR_LOG3 448#define PCIE_HDR_LOG3__TLP_HDR__SHIFT 0x0 449//PCIE_ROOT_ERR_CMD 450#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT 0x0 451#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT 0x1 452#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT 0x2 453//PCIE_ROOT_ERR_STATUS 454#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT 0x0 455#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT 0x1 456#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT 0x2 457#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT 0x3 458#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT 0x4 459#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT 0x5 460#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT 0x6 461#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT 0x1b 462//PCIE_ERR_SRC_ID 463#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT 0x0 464#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT 0x10 465//PCIE_TLP_PREFIX_LOG0 466#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT 0x0 467//PCIE_TLP_PREFIX_LOG1 468#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT 0x0 469//PCIE_TLP_PREFIX_LOG2 470#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT 0x0 471//PCIE_TLP_PREFIX_LOG3 472#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT 0x0 473//PCIE_BAR_ENH_CAP_LIST 474#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 475#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 476#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 477//PCIE_BAR1_CAP 478#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 479//PCIE_BAR1_CNTL 480#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT 0x0 481#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 482#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT 0x8 483//PCIE_BAR2_CAP 484#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 485//PCIE_BAR2_CNTL 486#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT 0x0 487#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 488#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT 0x8 489//PCIE_BAR3_CAP 490#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 491//PCIE_BAR3_CNTL 492#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT 0x0 493#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 494#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT 0x8 495//PCIE_BAR4_CAP 496#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 497//PCIE_BAR4_CNTL 498#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT 0x0 499#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 500#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT 0x8 501//PCIE_BAR5_CAP 502#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 503//PCIE_BAR5_CNTL 504#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT 0x0 505#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 506#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT 0x8 507//PCIE_BAR6_CAP 508#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT 0x4 509//PCIE_BAR6_CNTL 510#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT 0x0 511#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT 0x5 512#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT 0x8 513//PCIE_PWR_BUDGET_ENH_CAP_LIST 514#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 515#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 516#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 517//PCIE_PWR_BUDGET_DATA_SELECT 518#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT 0x0 519//PCIE_PWR_BUDGET_DATA 520#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT 0x0 521#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT 0x8 522#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT 0xa 523#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT 0xd 524#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT 0xf 525#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT 0x12 526//PCIE_PWR_BUDGET_CAP 527#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT 0x0 528//PCIE_DPA_ENH_CAP_LIST 529#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 530#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 531#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 532//PCIE_DPA_CAP 533#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT 0x0 534#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 535#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 536#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 537#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 538//PCIE_DPA_LATENCY_INDICATOR 539#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 540//PCIE_DPA_STATUS 541#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT 0x0 542#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT 0x8 543//PCIE_DPA_CNTL 544#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT 0x0 545//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 546#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 547//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 548#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 549//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 550#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 551//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 552#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 553//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 554#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 555//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 556#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 557//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 558#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 559//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 560#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 561//PCIE_SECONDARY_ENH_CAP_LIST 562#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 563#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 564#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 565//PCIE_LINK_CNTL3 566#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT 0x0 567#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT 0x1 568#define PCIE_LINK_CNTL3__RESERVED__SHIFT 0x2 569//PCIE_LANE_ERROR_STATUS 570#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT 0x0 571#define PCIE_LANE_ERROR_STATUS__RESERVED__SHIFT 0x10 572//PCIE_LANE_0_EQUALIZATION_CNTL 573#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 574#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 575#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 576#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 577#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 578//PCIE_LANE_1_EQUALIZATION_CNTL 579#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 580#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 581#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 582#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 583#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 584//PCIE_LANE_2_EQUALIZATION_CNTL 585#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 586#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 587#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 588#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 589#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 590//PCIE_LANE_3_EQUALIZATION_CNTL 591#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 592#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 593#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 594#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 595#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 596//PCIE_LANE_4_EQUALIZATION_CNTL 597#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 598#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 599#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 600#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 601#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 602//PCIE_LANE_5_EQUALIZATION_CNTL 603#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 604#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 605#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 606#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 607#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 608//PCIE_LANE_6_EQUALIZATION_CNTL 609#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 610#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 611#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 612#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 613#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 614//PCIE_LANE_7_EQUALIZATION_CNTL 615#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 616#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 617#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 618#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 619#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 620//PCIE_LANE_8_EQUALIZATION_CNTL 621#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 622#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 623#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 624#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 625#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 626//PCIE_LANE_9_EQUALIZATION_CNTL 627#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 628#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 629#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 630#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 631#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 632//PCIE_LANE_10_EQUALIZATION_CNTL 633#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 634#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 635#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 636#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 637#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 638//PCIE_LANE_11_EQUALIZATION_CNTL 639#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 640#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 641#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 642#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 643#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 644//PCIE_LANE_12_EQUALIZATION_CNTL 645#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 646#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 647#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 648#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 649#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 650//PCIE_LANE_13_EQUALIZATION_CNTL 651#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 652#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 653#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 654#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 655#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 656//PCIE_LANE_14_EQUALIZATION_CNTL 657#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 658#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 659#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 660#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 661#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 662//PCIE_LANE_15_EQUALIZATION_CNTL 663#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__SHIFT 0x0 664#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__SHIFT 0x4 665#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__SHIFT 0x8 666#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__SHIFT 0xc 667#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__SHIFT 0xf 668//PCIE_ACS_ENH_CAP_LIST 669#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 670#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 671#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 672//PCIE_ACS_CAP 673#define PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT 0x0 674#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT 0x1 675#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT 0x2 676#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT 0x3 677#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT 0x4 678#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT 0x5 679#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT 0x6 680#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT 0x8 681//PCIE_ACS_CNTL 682#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT 0x0 683#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT 0x1 684#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT 0x2 685#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT 0x3 686#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT 0x4 687#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT 0x5 688#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT 0x6 689//PCIE_ATS_ENH_CAP_LIST 690#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 691#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 692#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 693//PCIE_ATS_CAP 694#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT 0x0 695#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT 0x5 696#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT 0x6 697//PCIE_ATS_CNTL 698#define PCIE_ATS_CNTL__STU__SHIFT 0x0 699#define PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0xf 700//PCIE_PAGE_REQ_ENH_CAP_LIST 701#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 702#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 703#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 704//PCIE_PAGE_REQ_CNTL 705#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT 0x0 706#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT 0x1 707//PCIE_PAGE_REQ_STATUS 708#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT 0x0 709#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT 0x1 710#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT 0x8 711#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT 0xf 712//PCIE_OUTSTAND_PAGE_REQ_CAPACITY 713#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT 0x0 714//PCIE_OUTSTAND_PAGE_REQ_ALLOC 715#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT 0x0 716//PCIE_PASID_ENH_CAP_LIST 717#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 718#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 719#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 720//PCIE_PASID_CAP 721#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT 0x1 722#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT 0x2 723#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT 0x8 724//PCIE_PASID_CNTL 725#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT 0x0 726#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT 0x1 727#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT 0x2 728//PCIE_TPH_REQR_ENH_CAP_LIST 729#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 730#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 731#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 732//PCIE_TPH_REQR_CAP 733#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__SHIFT 0x0 734#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__SHIFT 0x1 735#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__SHIFT 0x2 736#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__SHIFT 0x8 737#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__SHIFT 0x9 738#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__SHIFT 0x10 739//PCIE_TPH_REQR_CNTL 740#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__SHIFT 0x0 741#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__SHIFT 0x8 742//PCIE_MC_ENH_CAP_LIST 743#define PCIE_MC_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 744#define PCIE_MC_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 745#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 746//PCIE_MC_CAP 747#define PCIE_MC_CAP__MC_MAX_GROUP__SHIFT 0x0 748#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__SHIFT 0x8 749#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__SHIFT 0xf 750//PCIE_MC_CNTL 751#define PCIE_MC_CNTL__MC_NUM_GROUP__SHIFT 0x0 752#define PCIE_MC_CNTL__MC_ENABLE__SHIFT 0xf 753//PCIE_MC_ADDR0 754#define PCIE_MC_ADDR0__MC_INDEX_POS__SHIFT 0x0 755#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__SHIFT 0xc 756//PCIE_MC_ADDR1 757#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__SHIFT 0x0 758//PCIE_MC_RCV0 759#define PCIE_MC_RCV0__MC_RECEIVE_0__SHIFT 0x0 760//PCIE_MC_RCV1 761#define PCIE_MC_RCV1__MC_RECEIVE_1__SHIFT 0x0 762//PCIE_MC_BLOCK_ALL0 763#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__SHIFT 0x0 764//PCIE_MC_BLOCK_ALL1 765#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__SHIFT 0x0 766//PCIE_MC_BLOCK_UNTRANSLATED_0 767#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__SHIFT 0x0 768//PCIE_MC_BLOCK_UNTRANSLATED_1 769#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__SHIFT 0x0 770//PCIE_LTR_ENH_CAP_LIST 771#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 772#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 773#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 774//PCIE_LTR_CAP 775#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT 0x0 776#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT 0xa 777#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT 0x10 778#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT 0x1a 779//PCIE_ARI_ENH_CAP_LIST 780#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 781#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 782#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 783//PCIE_ARI_CAP 784#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT 0x0 785#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT 0x1 786#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT 0x8 787//PCIE_ARI_CNTL 788#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT 0x0 789#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT 0x1 790#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT 0x4 791//PCIE_SRIOV_ENH_CAP_LIST 792#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT 0x0 793#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT 0x10 794#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT 0x14 795//PCIE_SRIOV_CAP 796#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT 0x0 797#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT 0x1 798#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT 0x15 799//PCIE_SRIOV_CONTROL 800#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT 0x0 801#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT 0x1 802#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT 0x2 803#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT 0x3 804#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT 0x4 805//PCIE_SRIOV_STATUS 806#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT 0x0 807//PCIE_SRIOV_INITIAL_VFS 808#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT 0x0 809//PCIE_SRIOV_TOTAL_VFS 810#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT 0x0 811//PCIE_SRIOV_NUM_VFS 812#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT 0x0 813//PCIE_SRIOV_FUNC_DEP_LINK 814#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT 0x0 815//PCIE_SRIOV_FIRST_VF_OFFSET 816#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT 0x0 817//PCIE_SRIOV_VF_STRIDE 818#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT 0x0 819//PCIE_SRIOV_VF_DEVICE_ID 820#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT 0x0 821//PCIE_SRIOV_SUPPORTED_PAGE_SIZE 822#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT 0x0 823//PCIE_SRIOV_SYSTEM_PAGE_SIZE 824#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT 0x0 825//PCIE_SRIOV_VF_BASE_ADDR_0 826#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT 0x0 827//PCIE_SRIOV_VF_BASE_ADDR_1 828#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT 0x0 829//PCIE_SRIOV_VF_BASE_ADDR_2 830#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT 0x0 831//PCIE_SRIOV_VF_BASE_ADDR_3 832#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT 0x0 833//PCIE_SRIOV_VF_BASE_ADDR_4 834#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT 0x0 835//PCIE_SRIOV_VF_BASE_ADDR_5 836#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT 0x0 837//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 838#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__SHIFT 0x0 839#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT 0x3 840//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 841#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT 0x0 842#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT 0x10 843#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT 0x14 844//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 845#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT 0x0 846#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT 0x10 847#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT 0x14 848//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 849#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT 0x0 850#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT 0x10 851//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 852#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__SHIFT 0x0 853#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x1 854#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__SHIFT 0x2 855#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x3 856#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__SHIFT 0x8 857#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x9 858#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__SHIFT 0xa 859#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0xb 860#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__SHIFT 0x10 861#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__SHIFT 0x11 862#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__SHIFT 0x12 863#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__SHIFT 0x13 864#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x18 865#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x19 866//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 867#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__SHIFT 0x0 868#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x1 869#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x2 870#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x3 871#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__SHIFT 0x8 872#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x9 873#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__SHIFT 0xa 874#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0xb 875#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__SHIFT 0x10 876#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT 0x11 877#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__SHIFT 0x12 878#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT 0x13 879#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT 0x18 880#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT 0x19 881//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 882#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT 0x0 883//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 884#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT 0x0 885#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT 0x8 886#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT 0xf 887#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT 0x10 888#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT 0x18 889//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 890#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT 0x0 891#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT 0x1 892#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT 0x2 893#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT 0x3 894#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT 0x4 895#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT 0x5 896#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT 0x6 897#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT 0x7 898#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT 0x8 899#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT 0x9 900#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT 0xa 901#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT 0xb 902#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT 0xc 903#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT 0xd 904#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT 0xe 905#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT 0xf 906#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT 0x10 907#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT 0x11 908#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT 0x12 909#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT 0x13 910#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT 0x14 911#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT 0x15 912#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT 0x16 913#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT 0x17 914#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT 0x18 915#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT 0x19 916#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT 0x1a 917#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT 0x1b 918#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT 0x1c 919#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT 0x1d 920#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT 0x1e 921#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT 0x1f 922//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 923#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT 0x0 924#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT 0x1 925//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 926#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__SHIFT 0x0 927#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__SHIFT 0x7 928#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__SHIFT 0xa 929//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 930#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT 0x0 931#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT 0x10 932//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 933#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__SHIFT 0x0 934#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__SHIFT 0x8 935#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__SHIFT 0x10 936//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 937#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__SHIFT 0x0 938#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__SHIFT 0x10 939//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 940#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__SHIFT 0x0 941#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__SHIFT 0x10 942//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 943#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__SHIFT 0x0 944#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__SHIFT 0x10 945//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 946#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__SHIFT 0x0 947#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__SHIFT 0x10 948//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 949#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__SHIFT 0x0 950#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__SHIFT 0x10 951//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 952#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__SHIFT 0x0 953#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__SHIFT 0x10 954//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 955#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__SHIFT 0x0 956#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__SHIFT 0x10 957//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 958#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__SHIFT 0x0 959#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__SHIFT 0x10 960//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 961#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__SHIFT 0x0 962#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__SHIFT 0x10 963//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 964#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__SHIFT 0x0 965#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__SHIFT 0x10 966//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 967#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__SHIFT 0x0 968#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__SHIFT 0x10 969//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 970#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__SHIFT 0x0 971#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__SHIFT 0x10 972//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 973#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__SHIFT 0x0 974#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__SHIFT 0x10 975//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 976#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__SHIFT 0x0 977#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__SHIFT 0x10 978//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 979#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__SHIFT 0x0 980#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__SHIFT 0x10 981//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 982#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__SHIFT 0x0 983#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__SHIFT 0x10 984//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 985#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__SHIFT 0x0 986//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 987#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__SHIFT 0x0 988//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 989#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__SHIFT 0x0 990//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 991#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__SHIFT 0x0 992//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 993#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__SHIFT 0x0 994//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 995#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__SHIFT 0x0 996//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 997#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__SHIFT 0x0 998//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 999#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__SHIFT 0x0 1000//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 1001#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__SHIFT 0x0 1002//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 1003#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__SHIFT 0x0 1004//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 1005#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__SHIFT 0x0 1006//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 1007#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__SHIFT 0x0 1008//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 1009#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__SHIFT 0x0 1010//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 1011#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__SHIFT 0x0 1012//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 1013#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__SHIFT 0x0 1014//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 1015#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__SHIFT 0x0 1016//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 1017#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__SHIFT 0x0 1018//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 1019#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__SHIFT 0x0 1020//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 1021#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__SHIFT 0x0 1022//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 1023#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__SHIFT 0x0 1024//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 1025#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__SHIFT 0x0 1026//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 1027#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__SHIFT 0x0 1028//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 1029#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__SHIFT 0x0 1030//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 1031#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__SHIFT 0x0 1032 1033 1034// addressBlock: bif_cfg_dev0_swds_bifcfgdecp 1035//SUB_BUS_NUMBER_LATENCY 1036#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT 0x0 1037#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT 0x8 1038#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT 0x10 1039#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT 0x18 1040//IO_BASE_LIMIT 1041#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT 0x0 1042#define IO_BASE_LIMIT__IO_BASE__SHIFT 0x4 1043#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT 0x8 1044#define IO_BASE_LIMIT__IO_LIMIT__SHIFT 0xc 1045//SECONDARY_STATUS 1046#define SECONDARY_STATUS__CAP_LIST__SHIFT 0x4 1047#define SECONDARY_STATUS__PCI_66_EN__SHIFT 0x5 1048#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT 0x7 1049#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT 0x8 1050#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT 0x9 1051#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT 0xb 1052#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT 0xc 1053#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT 0xd 1054#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT 0xe 1055#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT 0xf 1056//MEM_BASE_LIMIT 1057#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 1058#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT 0x4 1059#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 1060#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT 0x14 1061//PREF_BASE_LIMIT 1062#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 1063#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT 0x4 1064#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 1065#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT 0x14 1066//PREF_BASE_UPPER 1067#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT 0x0 1068//PREF_LIMIT_UPPER 1069#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT 0x0 1070//IO_BASE_LIMIT_HI 1071#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT 0x0 1072#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT 0x10 1073//IRQ_BRIDGE_CNTL 1074#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT 0x0 1075#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT 0x1 1076#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT 0x2 1077#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT 0x3 1078#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT 0x4 1079#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT 0x5 1080#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT 0x6 1081#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT 0x7 1082//SLOT_CAP 1083#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT 0x0 1084#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT 0x1 1085#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT 0x2 1086#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT 0x3 1087#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT 0x4 1088#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT 0x5 1089#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT 0x6 1090#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT 0x7 1091#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT 0xf 1092#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT 0x11 1093#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT 0x12 1094#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT 0x13 1095//SLOT_CNTL 1096#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT 0x0 1097#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT 0x1 1098#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT 0x2 1099#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT 0x3 1100#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT 0x4 1101#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT 0x5 1102#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT 0x6 1103#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT 0x8 1104#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT 0xa 1105#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT 0xb 1106#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT 0xc 1107//SLOT_STATUS 1108#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT 0x0 1109#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT 0x1 1110#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT 0x2 1111#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT 0x3 1112#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT 0x4 1113#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT 0x5 1114#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT 0x6 1115#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT 0x7 1116#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT 0x8 1117//SSID_CAP_LIST 1118#define SSID_CAP_LIST__CAP_ID__SHIFT 0x0 1119#define SSID_CAP_LIST__NEXT_PTR__SHIFT 0x8 1120//SSID_CAP 1121#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT 0x0 1122#define SSID_CAP__SUBSYSTEM_ID__SHIFT 0x10 1123 1124 1125// addressBlock: rcc_shadow_reg_shadowdec 1126//SHADOW_COMMAND 1127#define SHADOW_COMMAND__IOEN_UP__SHIFT 0x0 1128#define SHADOW_COMMAND__MEMEN_UP__SHIFT 0x1 1129//SHADOW_BASE_ADDR_1 1130#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT 0x0 1131//SHADOW_BASE_ADDR_2 1132#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT 0x0 1133//SHADOW_SUB_BUS_NUMBER_LATENCY 1134#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT 0x8 1135#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT 0x10 1136//SHADOW_IO_BASE_LIMIT 1137#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT 0x4 1138#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT 0xc 1139//SHADOW_MEM_BASE_LIMIT 1140#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT 0x0 1141#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT 0x4 1142#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT 0x10 1143#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT 0x14 1144//SHADOW_PREF_BASE_LIMIT 1145#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT 0x0 1146#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT 0x4 1147#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT 0x10 1148#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT 0x14 1149//SHADOW_PREF_BASE_UPPER 1150#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT 0x0 1151//SHADOW_PREF_LIMIT_UPPER 1152#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT 0x0 1153//SHADOW_IO_BASE_LIMIT_HI 1154#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT 0x0 1155#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT 0x10 1156//SHADOW_IRQ_BRIDGE_CNTL 1157#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT 0x2 1158#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT 0x3 1159#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT 0x4 1160#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT 0x6 1161//SUC_INDEX 1162#define SUC_INDEX__SUC_INDEX__SHIFT 0x0 1163//SUC_DATA 1164#define SUC_DATA__SUC_DATA__SHIFT 0x0 1165 1166 1167// addressBlock: bif_bx_pf_SUMDEC 1168//SUM_INDEX 1169#define SUM_INDEX__SUM_INDEX__SHIFT 0x0 1170//SUM_DATA 1171#define SUM_DATA__SUM_DATA__SHIFT 0x0 1172 1173 1174// addressBlock: gdc_GDCDEC 1175//A2S_CNTL_CL0 1176#define A2S_CNTL_CL0__NSNOOP_MAP__SHIFT 0x0 1177#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__SHIFT 0x2 1178#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__SHIFT 0x4 1179#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1180#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1181#define A2S_CNTL_CL0__BLKLVL_MAP__SHIFT 0xa 1182#define A2S_CNTL_CL0__DATERR_MAP__SHIFT 0xc 1183#define A2S_CNTL_CL0__EXOKAY_WR_MAP__SHIFT 0xe 1184#define A2S_CNTL_CL0__EXOKAY_RD_MAP__SHIFT 0x10 1185#define A2S_CNTL_CL0__RESP_WR_MAP__SHIFT 0x12 1186#define A2S_CNTL_CL0__RESP_RD_MAP__SHIFT 0x14 1187//A2S_CNTL_CL1 1188#define A2S_CNTL_CL1__NSNOOP_MAP__SHIFT 0x0 1189#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__SHIFT 0x2 1190#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__SHIFT 0x4 1191#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1192#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1193#define A2S_CNTL_CL1__BLKLVL_MAP__SHIFT 0xa 1194#define A2S_CNTL_CL1__DATERR_MAP__SHIFT 0xc 1195#define A2S_CNTL_CL1__EXOKAY_WR_MAP__SHIFT 0xe 1196#define A2S_CNTL_CL1__EXOKAY_RD_MAP__SHIFT 0x10 1197#define A2S_CNTL_CL1__RESP_WR_MAP__SHIFT 0x12 1198#define A2S_CNTL_CL1__RESP_RD_MAP__SHIFT 0x14 1199//A2S_CNTL_CL2 1200#define A2S_CNTL_CL2__NSNOOP_MAP__SHIFT 0x0 1201#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__SHIFT 0x2 1202#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__SHIFT 0x4 1203#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1204#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1205#define A2S_CNTL_CL2__BLKLVL_MAP__SHIFT 0xa 1206#define A2S_CNTL_CL2__DATERR_MAP__SHIFT 0xc 1207#define A2S_CNTL_CL2__EXOKAY_WR_MAP__SHIFT 0xe 1208#define A2S_CNTL_CL2__EXOKAY_RD_MAP__SHIFT 0x10 1209#define A2S_CNTL_CL2__RESP_WR_MAP__SHIFT 0x12 1210#define A2S_CNTL_CL2__RESP_RD_MAP__SHIFT 0x14 1211//A2S_CNTL_CL3 1212#define A2S_CNTL_CL3__NSNOOP_MAP__SHIFT 0x0 1213#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__SHIFT 0x2 1214#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__SHIFT 0x4 1215#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1216#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1217#define A2S_CNTL_CL3__BLKLVL_MAP__SHIFT 0xa 1218#define A2S_CNTL_CL3__DATERR_MAP__SHIFT 0xc 1219#define A2S_CNTL_CL3__EXOKAY_WR_MAP__SHIFT 0xe 1220#define A2S_CNTL_CL3__EXOKAY_RD_MAP__SHIFT 0x10 1221#define A2S_CNTL_CL3__RESP_WR_MAP__SHIFT 0x12 1222#define A2S_CNTL_CL3__RESP_RD_MAP__SHIFT 0x14 1223//A2S_CNTL_CL4 1224#define A2S_CNTL_CL4__NSNOOP_MAP__SHIFT 0x0 1225#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__SHIFT 0x2 1226#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__SHIFT 0x4 1227#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__SHIFT 0x6 1228#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__SHIFT 0x8 1229#define A2S_CNTL_CL4__BLKLVL_MAP__SHIFT 0xa 1230#define A2S_CNTL_CL4__DATERR_MAP__SHIFT 0xc 1231#define A2S_CNTL_CL4__EXOKAY_WR_MAP__SHIFT 0xe 1232#define A2S_CNTL_CL4__EXOKAY_RD_MAP__SHIFT 0x10 1233#define A2S_CNTL_CL4__RESP_WR_MAP__SHIFT 0x12 1234#define A2S_CNTL_CL4__RESP_RD_MAP__SHIFT 0x14 1235//A2S_CNTL_SW0 1236#define A2S_CNTL_SW0__WR_TAG_SET_MIN__SHIFT 0x0 1237#define A2S_CNTL_SW0__RD_TAG_SET_MIN__SHIFT 0x3 1238#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__SHIFT 0x6 1239#define A2S_CNTL_SW0__RSP_REORDER_DIS__SHIFT 0x7 1240#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__SHIFT 0x8 1241#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT 0x9 1242#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1243#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1244#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1245#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT 0x10 1246#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT 0x18 1247//A2S_CNTL_SW1 1248#define A2S_CNTL_SW1__WR_TAG_SET_MIN__SHIFT 0x0 1249#define A2S_CNTL_SW1__RD_TAG_SET_MIN__SHIFT 0x3 1250#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__SHIFT 0x6 1251#define A2S_CNTL_SW1__RSP_REORDER_DIS__SHIFT 0x7 1252#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__SHIFT 0x8 1253#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT 0x9 1254#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1255#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1256#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1257#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT 0x10 1258#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT 0x18 1259//A2S_CNTL_SW2 1260#define A2S_CNTL_SW2__WR_TAG_SET_MIN__SHIFT 0x0 1261#define A2S_CNTL_SW2__RD_TAG_SET_MIN__SHIFT 0x3 1262#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__SHIFT 0x6 1263#define A2S_CNTL_SW2__RSP_REORDER_DIS__SHIFT 0x7 1264#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__SHIFT 0x8 1265#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT 0x9 1266#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xa 1267#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__SHIFT 0xb 1268#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__SHIFT 0xc 1269#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT 0x10 1270#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT 0x18 1271//NGDC_MGCG_CTRL 1272#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT 0x0 1273#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT 0x1 1274#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT 0x2 1275//A2S_MISC_CNTL 1276#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT 0x0 1277#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__SHIFT 0x2 1278//NGDC_SDP_PORT_CTRL 1279#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT 0x0 1280//NGDC_RESERVED_0 1281#define NGDC_RESERVED_0__RESERVED__SHIFT 0x0 1282//NGDC_RESERVED_1 1283#define NGDC_RESERVED_1__RESERVED__SHIFT 0x0 1284//BIF_SDMA0_DOORBELL_RANGE 1285#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1286#define BIF_SDMA0_DOORBELL_RANGE__SIZE__SHIFT 0x10 1287//BIF_SDMA1_DOORBELL_RANGE 1288#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1289#define BIF_SDMA1_DOORBELL_RANGE__SIZE__SHIFT 0x10 1290//BIF_IH_DOORBELL_RANGE 1291#define BIF_IH_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1292#define BIF_IH_DOORBELL_RANGE__SIZE__SHIFT 0x10 1293//BIF_MMSCH0_DOORBELL_RANGE 1294#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__SHIFT 0x2 1295#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__SHIFT 0x10 1296//BIF_DOORBELL_FENCE_CNTL 1297#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__SHIFT 0x0 1298//S2A_MISC_CNTL 1299#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__SHIFT 0x0 1300#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__SHIFT 0x1 1301#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__SHIFT 0x2 1302//A2S_CNTL2_SEC_CL0 1303#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__SHIFT 0x0 1304//A2S_CNTL2_SEC_CL1 1305#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__SHIFT 0x0 1306//A2S_CNTL2_SEC_CL2 1307#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__SHIFT 0x0 1308//A2S_CNTL2_SEC_CL3 1309#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__SHIFT 0x0 1310//A2S_CNTL2_SEC_CL4 1311#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__SHIFT 0x0 1312 1313 1314// addressBlock: nbif_sion_SIONDEC 1315//SION_CL0_RdRsp_BurstTarget_REG0 1316#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1317//SION_CL0_RdRsp_BurstTarget_REG1 1318#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1319//SION_CL0_RdRsp_TimeSlot_REG0 1320#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1321//SION_CL0_RdRsp_TimeSlot_REG1 1322#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1323//SION_CL0_WrRsp_BurstTarget_REG0 1324#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1325//SION_CL0_WrRsp_BurstTarget_REG1 1326#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1327//SION_CL0_WrRsp_TimeSlot_REG0 1328#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1329//SION_CL0_WrRsp_TimeSlot_REG1 1330#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1331//SION_CL0_Req_BurstTarget_REG0 1332#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1333//SION_CL0_Req_BurstTarget_REG1 1334#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1335//SION_CL0_Req_TimeSlot_REG0 1336#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1337//SION_CL0_Req_TimeSlot_REG1 1338#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1339//SION_CL0_ReqPoolCredit_Alloc_REG0 1340#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1341//SION_CL0_ReqPoolCredit_Alloc_REG1 1342#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1343//SION_CL0_DataPoolCredit_Alloc_REG0 1344#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1345//SION_CL0_DataPoolCredit_Alloc_REG1 1346#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1347//SION_CL0_RdRspPoolCredit_Alloc_REG0 1348#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1349//SION_CL0_RdRspPoolCredit_Alloc_REG1 1350#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1351//SION_CL0_WrRspPoolCredit_Alloc_REG0 1352#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1353//SION_CL0_WrRspPoolCredit_Alloc_REG1 1354#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1355//SION_CL1_RdRsp_BurstTarget_REG0 1356#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1357//SION_CL1_RdRsp_BurstTarget_REG1 1358#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1359//SION_CL1_RdRsp_TimeSlot_REG0 1360#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1361//SION_CL1_RdRsp_TimeSlot_REG1 1362#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1363//SION_CL1_WrRsp_BurstTarget_REG0 1364#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1365//SION_CL1_WrRsp_BurstTarget_REG1 1366#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1367//SION_CL1_WrRsp_TimeSlot_REG0 1368#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1369//SION_CL1_WrRsp_TimeSlot_REG1 1370#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1371//SION_CL1_Req_BurstTarget_REG0 1372#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1373//SION_CL1_Req_BurstTarget_REG1 1374#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1375//SION_CL1_Req_TimeSlot_REG0 1376#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1377//SION_CL1_Req_TimeSlot_REG1 1378#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1379//SION_CL1_ReqPoolCredit_Alloc_REG0 1380#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1381//SION_CL1_ReqPoolCredit_Alloc_REG1 1382#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1383//SION_CL1_DataPoolCredit_Alloc_REG0 1384#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1385//SION_CL1_DataPoolCredit_Alloc_REG1 1386#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1387//SION_CL1_RdRspPoolCredit_Alloc_REG0 1388#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1389//SION_CL1_RdRspPoolCredit_Alloc_REG1 1390#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1391//SION_CL1_WrRspPoolCredit_Alloc_REG0 1392#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1393//SION_CL1_WrRspPoolCredit_Alloc_REG1 1394#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1395//SION_CL2_RdRsp_BurstTarget_REG0 1396#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1397//SION_CL2_RdRsp_BurstTarget_REG1 1398#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1399//SION_CL2_RdRsp_TimeSlot_REG0 1400#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1401//SION_CL2_RdRsp_TimeSlot_REG1 1402#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1403//SION_CL2_WrRsp_BurstTarget_REG0 1404#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1405//SION_CL2_WrRsp_BurstTarget_REG1 1406#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1407//SION_CL2_WrRsp_TimeSlot_REG0 1408#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1409//SION_CL2_WrRsp_TimeSlot_REG1 1410#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1411//SION_CL2_Req_BurstTarget_REG0 1412#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1413//SION_CL2_Req_BurstTarget_REG1 1414#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1415//SION_CL2_Req_TimeSlot_REG0 1416#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1417//SION_CL2_Req_TimeSlot_REG1 1418#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1419//SION_CL2_ReqPoolCredit_Alloc_REG0 1420#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1421//SION_CL2_ReqPoolCredit_Alloc_REG1 1422#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1423//SION_CL2_DataPoolCredit_Alloc_REG0 1424#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1425//SION_CL2_DataPoolCredit_Alloc_REG1 1426#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1427//SION_CL2_RdRspPoolCredit_Alloc_REG0 1428#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1429//SION_CL2_RdRspPoolCredit_Alloc_REG1 1430#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1431//SION_CL2_WrRspPoolCredit_Alloc_REG0 1432#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1433//SION_CL2_WrRspPoolCredit_Alloc_REG1 1434#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1435//SION_CL3_RdRsp_BurstTarget_REG0 1436#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1437//SION_CL3_RdRsp_BurstTarget_REG1 1438#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1439//SION_CL3_RdRsp_TimeSlot_REG0 1440#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1441//SION_CL3_RdRsp_TimeSlot_REG1 1442#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1443//SION_CL3_WrRsp_BurstTarget_REG0 1444#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1445//SION_CL3_WrRsp_BurstTarget_REG1 1446#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1447//SION_CL3_WrRsp_TimeSlot_REG0 1448#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1449//SION_CL3_WrRsp_TimeSlot_REG1 1450#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1451//SION_CL3_Req_BurstTarget_REG0 1452#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1453//SION_CL3_Req_BurstTarget_REG1 1454#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1455//SION_CL3_Req_TimeSlot_REG0 1456#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1457//SION_CL3_Req_TimeSlot_REG1 1458#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1459//SION_CL3_ReqPoolCredit_Alloc_REG0 1460#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1461//SION_CL3_ReqPoolCredit_Alloc_REG1 1462#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1463//SION_CL3_DataPoolCredit_Alloc_REG0 1464#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1465//SION_CL3_DataPoolCredit_Alloc_REG1 1466#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1467//SION_CL3_RdRspPoolCredit_Alloc_REG0 1468#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1469//SION_CL3_RdRspPoolCredit_Alloc_REG1 1470#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1471//SION_CL3_WrRspPoolCredit_Alloc_REG0 1472#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1473//SION_CL3_WrRspPoolCredit_Alloc_REG1 1474#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1475//SION_CL4_RdRsp_BurstTarget_REG0 1476#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1477//SION_CL4_RdRsp_BurstTarget_REG1 1478#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1479//SION_CL4_RdRsp_TimeSlot_REG0 1480#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1481//SION_CL4_RdRsp_TimeSlot_REG1 1482#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1483//SION_CL4_WrRsp_BurstTarget_REG0 1484#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1485//SION_CL4_WrRsp_BurstTarget_REG1 1486#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1487//SION_CL4_WrRsp_TimeSlot_REG0 1488#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1489//SION_CL4_WrRsp_TimeSlot_REG1 1490#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1491//SION_CL4_Req_BurstTarget_REG0 1492#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1493//SION_CL4_Req_BurstTarget_REG1 1494#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1495//SION_CL4_Req_TimeSlot_REG0 1496#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1497//SION_CL4_Req_TimeSlot_REG1 1498#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1499//SION_CL4_ReqPoolCredit_Alloc_REG0 1500#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1501//SION_CL4_ReqPoolCredit_Alloc_REG1 1502#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1503//SION_CL4_DataPoolCredit_Alloc_REG0 1504#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1505//SION_CL4_DataPoolCredit_Alloc_REG1 1506#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1507//SION_CL4_RdRspPoolCredit_Alloc_REG0 1508#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1509//SION_CL4_RdRspPoolCredit_Alloc_REG1 1510#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1511//SION_CL4_WrRspPoolCredit_Alloc_REG0 1512#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1513//SION_CL4_WrRspPoolCredit_Alloc_REG1 1514#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1515//SION_CL5_RdRsp_BurstTarget_REG0 1516#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT 0x0 1517//SION_CL5_RdRsp_BurstTarget_REG1 1518#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT 0x0 1519//SION_CL5_RdRsp_TimeSlot_REG0 1520#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT 0x0 1521//SION_CL5_RdRsp_TimeSlot_REG1 1522#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT 0x0 1523//SION_CL5_WrRsp_BurstTarget_REG0 1524#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT 0x0 1525//SION_CL5_WrRsp_BurstTarget_REG1 1526#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT 0x0 1527//SION_CL5_WrRsp_TimeSlot_REG0 1528#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT 0x0 1529//SION_CL5_WrRsp_TimeSlot_REG1 1530#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT 0x0 1531//SION_CL5_Req_BurstTarget_REG0 1532#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT 0x0 1533//SION_CL5_Req_BurstTarget_REG1 1534#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT 0x0 1535//SION_CL5_Req_TimeSlot_REG0 1536#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT 0x0 1537//SION_CL5_Req_TimeSlot_REG1 1538#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT 0x0 1539//SION_CL5_ReqPoolCredit_Alloc_REG0 1540#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT 0x0 1541//SION_CL5_ReqPoolCredit_Alloc_REG1 1542#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT 0x0 1543//SION_CL5_DataPoolCredit_Alloc_REG0 1544#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT 0x0 1545//SION_CL5_DataPoolCredit_Alloc_REG1 1546#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT 0x0 1547//SION_CL5_RdRspPoolCredit_Alloc_REG0 1548#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT 0x0 1549//SION_CL5_RdRspPoolCredit_Alloc_REG1 1550#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT 0x0 1551//SION_CL5_WrRspPoolCredit_Alloc_REG0 1552#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT 0x0 1553//SION_CL5_WrRspPoolCredit_Alloc_REG1 1554#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT 0x0 1555//SION_CNTL_REG0 1556#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT 0x0 1557#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT 0x1 1558#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT 0x2 1559#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT 0x3 1560#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT 0x4 1561#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT 0x5 1562#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT 0x6 1563#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT 0x7 1564#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT 0x8 1565#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT 0x9 1566#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT 0xa 1567#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT 0xb 1568#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT 0xc 1569#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT 0xd 1570#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT 0xe 1571#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT 0xf 1572#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT 0x10 1573#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT 0x11 1574#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT 0x12 1575#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT 0x13 1576//SION_CNTL_REG1 1577#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__SHIFT 0x0 1578#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__SHIFT 0x8 1579 1580 1581// addressBlock: syshub_mmreg_direct_syshubdirect 1582//SYSHUB_DS_CTRL_SOCCLK 1583#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 1584#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 1585#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 1586#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 1587#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 1588#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 1589#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 1590#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 1591#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 1592#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 1593#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 1594#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 1595#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 1596#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 1597#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 1598#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 1599#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 1600#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f 1601//SYSHUB_DS_CTRL2_SOCCLK 1602#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 1603//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 1604#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 1605#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 1606#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf 1607#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 1608#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 1609//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 1610#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 1611#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 1612#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf 1613#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 1614#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 1615//DMA_CLK0_SW0_SYSHUB_QOS_CNTL 1616#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1617#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1618#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1619//DMA_CLK0_SW1_SYSHUB_QOS_CNTL 1620#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1621#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1622#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1623//DMA_CLK0_SW0_CL0_CNTL 1624#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1625#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1626#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1627#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1628#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1629#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1630//DMA_CLK0_SW0_CL1_CNTL 1631#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1632#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1633#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1634#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1635#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1636#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1637//DMA_CLK0_SW0_CL2_CNTL 1638#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1639#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1640#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1641#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1642#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1643#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1644//DMA_CLK0_SW0_CL3_CNTL 1645#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1646#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1647#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1648#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1649#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1650#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1651//DMA_CLK0_SW0_CL4_CNTL 1652#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1653#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1654#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1655#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1656#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1657#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1658//DMA_CLK0_SW0_CL5_CNTL 1659#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1660#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1661#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1662#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1663#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1664#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1665//DMA_CLK0_SW1_CL0_CNTL 1666#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1667#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1668#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1669#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1670#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1671#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1672//DMA_CLK0_SW2_CL0_CNTL 1673#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1674#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1675#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1676#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1677#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1678#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1679//SYSHUB_CG_CNTL 1680#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 1681#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 1682#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 1683//SYSHUB_TRANS_IDLE 1684#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 1685#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 1686#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 1687#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 1688#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 1689#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 1690#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 1691#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 1692#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 1693#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 1694#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa 1695#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb 1696#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc 1697#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd 1698#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe 1699#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf 1700#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 1701//SYSHUB_HP_TIMER 1702#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 1703//SYSHUB_SCRATCH 1704#define SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 1705//SYSHUB_DS_CTRL_SHUBCLK 1706#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 1707#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 1708#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 1709#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 1710#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 1711#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 1712#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 1713#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 1714#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 1715#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 1716#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 1717#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 1718#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 1719#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 1720#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 1721#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 1722#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 1723#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f 1724//SYSHUB_DS_CTRL2_SHUBCLK 1725#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 1726//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 1727#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf 1728#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 1729//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 1730#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf 1731#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 1732//DMA_CLK1_SW0_SYSHUB_QOS_CNTL 1733#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1734#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1735#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1736//DMA_CLK1_SW1_SYSHUB_QOS_CNTL 1737#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 1738#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 1739#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 1740//DMA_CLK1_SW0_CL0_CNTL 1741#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1742#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1743#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1744#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1745#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1746#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1747//DMA_CLK1_SW0_CL1_CNTL 1748#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1749#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1750#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1751#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1752#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1753#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1754//DMA_CLK1_SW0_CL2_CNTL 1755#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1756#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1757#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1758#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1759#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1760#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1761//DMA_CLK1_SW0_CL3_CNTL 1762#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1763#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1764#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1765#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1766#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1767#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1768//DMA_CLK1_SW0_CL4_CNTL 1769#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1770#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1771#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1772#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1773#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1774#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1775//DMA_CLK1_SW1_CL0_CNTL 1776#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1777#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1778#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1779#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1780#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1781#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1782//DMA_CLK1_SW1_CL1_CNTL 1783#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1784#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1785#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1786#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1787#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1788#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1789//DMA_CLK1_SW1_CL2_CNTL 1790#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1791#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1792#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1793#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1794#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1795#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1796//DMA_CLK1_SW1_CL3_CNTL 1797#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1798#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1799#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1800#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1801#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1802#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1803//DMA_CLK1_SW1_CL4_CNTL 1804#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 1805#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 1806#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 1807#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 1808#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 1809#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 1810 1811 1812// addressBlock: gdc_ras_gdc_ras_regblk 1813//GDC_RAS_LEAF0_CTRL 1814#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 1815#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1816#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 1817#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 1818#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1819#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 1820#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1821#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 1822#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 1823#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 1824#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1825#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 1826//GDC_RAS_LEAF1_CTRL 1827#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 1828#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1829#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 1830#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 1831#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1832#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 1833#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1834#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 1835#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 1836#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 1837#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1838#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 1839//GDC_RAS_LEAF2_CTRL 1840#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 1841#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1842#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 1843#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 1844#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1845#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 1846#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1847#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 1848#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 1849#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 1850#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1851#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 1852//GDC_RAS_LEAF3_CTRL 1853#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__SHIFT 0x0 1854#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1855#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT 0x2 1856#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__SHIFT 0x4 1857#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1858#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT 0x6 1859#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1860#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__SHIFT 0x11 1861#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__SHIFT 0x12 1862#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__SHIFT 0x13 1863#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1864#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__SHIFT 0x15 1865//GDC_RAS_LEAF4_CTRL 1866#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__SHIFT 0x0 1867#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1868#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT 0x2 1869#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__SHIFT 0x4 1870#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1871#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT 0x6 1872#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1873#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__SHIFT 0x11 1874#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__SHIFT 0x12 1875#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__SHIFT 0x13 1876#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1877#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__SHIFT 0x15 1878//GDC_RAS_LEAF5_CTRL 1879#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__SHIFT 0x0 1880#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 1881#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT 0x2 1882#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__SHIFT 0x4 1883#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 1884#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT 0x6 1885#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__SHIFT 0x10 1886#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__SHIFT 0x11 1887#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__SHIFT 0x12 1888#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__SHIFT 0x13 1889#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__SHIFT 0x14 1890#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__SHIFT 0x15 1891 1892 1893// addressBlock: gdc_rst_GDCRST_DEC 1894//SHUB_PF_FLR_RST 1895#define SHUB_PF_FLR_RST__PF0_FLR_RST__SHIFT 0x0 1896#define SHUB_PF_FLR_RST__PF1_FLR_RST__SHIFT 0x1 1897#define SHUB_PF_FLR_RST__PF2_FLR_RST__SHIFT 0x2 1898#define SHUB_PF_FLR_RST__PF3_FLR_RST__SHIFT 0x3 1899#define SHUB_PF_FLR_RST__PF4_FLR_RST__SHIFT 0x4 1900#define SHUB_PF_FLR_RST__PF5_FLR_RST__SHIFT 0x5 1901#define SHUB_PF_FLR_RST__PF6_FLR_RST__SHIFT 0x6 1902#define SHUB_PF_FLR_RST__PF7_FLR_RST__SHIFT 0x7 1903//SHUB_GFX_DRV_MODE1_RST 1904#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__SHIFT 0x0 1905//SHUB_LINK_RESET 1906#define SHUB_LINK_RESET__LINK_RESET__SHIFT 0x0 1907//SHUB_PF0_VF_FLR_RST 1908#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 1909#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 1910#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 1911#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 1912#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 1913#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 1914#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 1915#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 1916#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 1917#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 1918#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa 1919#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb 1920#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc 1921#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd 1922#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe 1923#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf 1924#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f 1925//SHUB_HARD_RST_CTRL 1926#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT 0x0 1927#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT 0x1 1928#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT 0x2 1929#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 1930#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 1931//SHUB_SOFT_RST_CTRL 1932#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT 0x0 1933#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT 0x1 1934#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT 0x2 1935#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT 0x3 1936#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT 0x4 1937//SHUB_SDP_PORT_RST 1938#define SHUB_SDP_PORT_RST__SDP_PORT_RST__SHIFT 0x0 1939 1940 1941// addressBlock: bif_bx_pf_SYSDEC 1942//SBIOS_SCRATCH_0 1943#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__SHIFT 0x0 1944//SBIOS_SCRATCH_1 1945#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__SHIFT 0x0 1946//SBIOS_SCRATCH_2 1947#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__SHIFT 0x0 1948//SBIOS_SCRATCH_3 1949#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__SHIFT 0x0 1950//BIOS_SCRATCH_0 1951#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT 0x0 1952//BIOS_SCRATCH_1 1953#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT 0x0 1954//BIOS_SCRATCH_2 1955#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT 0x0 1956//BIOS_SCRATCH_3 1957#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT 0x0 1958//BIOS_SCRATCH_4 1959#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT 0x0 1960//BIOS_SCRATCH_5 1961#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT 0x0 1962//BIOS_SCRATCH_6 1963#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT 0x0 1964//BIOS_SCRATCH_7 1965#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT 0x0 1966//BIOS_SCRATCH_8 1967#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT 0x0 1968//BIOS_SCRATCH_9 1969#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT 0x0 1970//BIOS_SCRATCH_10 1971#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT 0x0 1972//BIOS_SCRATCH_11 1973#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT 0x0 1974//BIOS_SCRATCH_12 1975#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT 0x0 1976//BIOS_SCRATCH_13 1977#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT 0x0 1978//BIOS_SCRATCH_14 1979#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT 0x0 1980//BIOS_SCRATCH_15 1981#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT 0x0 1982//BIF_RLC_INTR_CNTL 1983#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__SHIFT 0x0 1984#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__SHIFT 0x1 1985#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__SHIFT 0x2 1986#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__SHIFT 0x3 1987//BIF_VCE_INTR_CNTL 1988#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__SHIFT 0x0 1989#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__SHIFT 0x1 1990#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__SHIFT 0x2 1991#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__SHIFT 0x3 1992//BIF_UVD_INTR_CNTL 1993#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__SHIFT 0x0 1994#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__SHIFT 0x1 1995#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__SHIFT 0x2 1996#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__SHIFT 0x3 1997//GFX_MMIOREG_CAM_ADDR0 1998#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT 0x0 1999//GFX_MMIOREG_CAM_REMAP_ADDR0 2000#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT 0x0 2001//GFX_MMIOREG_CAM_ADDR1 2002#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT 0x0 2003//GFX_MMIOREG_CAM_REMAP_ADDR1 2004#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT 0x0 2005//GFX_MMIOREG_CAM_ADDR2 2006#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT 0x0 2007//GFX_MMIOREG_CAM_REMAP_ADDR2 2008#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT 0x0 2009//GFX_MMIOREG_CAM_ADDR3 2010#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT 0x0 2011//GFX_MMIOREG_CAM_REMAP_ADDR3 2012#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT 0x0 2013//GFX_MMIOREG_CAM_ADDR4 2014#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT 0x0 2015//GFX_MMIOREG_CAM_REMAP_ADDR4 2016#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT 0x0 2017//GFX_MMIOREG_CAM_ADDR5 2018#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT 0x0 2019//GFX_MMIOREG_CAM_REMAP_ADDR5 2020#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT 0x0 2021//GFX_MMIOREG_CAM_ADDR6 2022#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT 0x0 2023//GFX_MMIOREG_CAM_REMAP_ADDR6 2024#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT 0x0 2025//GFX_MMIOREG_CAM_ADDR7 2026#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT 0x0 2027//GFX_MMIOREG_CAM_REMAP_ADDR7 2028#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT 0x0 2029//GFX_MMIOREG_CAM_CNTL 2030#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT 0x0 2031//GFX_MMIOREG_CAM_ZERO_CPL 2032#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT 0x0 2033//GFX_MMIOREG_CAM_ONE_CPL 2034#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT 0x0 2035//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 2036#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT 0x0 2037 2038 2039// addressBlock: bif_bx_pf_SYSPFVFDEC 2040//MM_INDEX 2041#define MM_INDEX__MM_OFFSET__SHIFT 0x0 2042#define MM_INDEX__MM_APER__SHIFT 0x1f 2043//MM_DATA 2044#define MM_DATA__MM_DATA__SHIFT 0x0 2045//MM_INDEX_HI 2046#define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 2047//SYSHUB_INDEX_OVLP 2048#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT 0x0 2049//SYSHUB_DATA_OVLP 2050#define SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT 0x0 2051//PCIE_INDEX 2052#define PCIE_INDEX__PCIE_INDEX__SHIFT 0x0 2053//PCIE_DATA 2054#define PCIE_DATA__PCIE_DATA__SHIFT 0x0 2055//PCIE_INDEX2 2056#define PCIE_INDEX2__PCIE_INDEX2__SHIFT 0x0 2057//PCIE_DATA2 2058#define PCIE_DATA2__PCIE_DATA2__SHIFT 0x0 2059 2060 2061// addressBlock: rcc_dwn_BIFDEC1 2062//DN_PCIE_RESERVED 2063#define DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT 0x0 2064//DN_PCIE_SCRATCH 2065#define DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 2066//DN_PCIE_CNTL 2067#define DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT 0x0 2068#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT 0x7 2069#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 2070//DN_PCIE_CONFIG_CNTL 2071#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT 0x19 2072//DN_PCIE_RX_CNTL2 2073#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT 0x1c 2074//DN_PCIE_BUS_CNTL 2075#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2076#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT 0x8 2077//DN_PCIE_CFG_CNTL 2078#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2079#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2080#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2081//DN_PCIE_STRAP_F0 2082#define DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT 0x0 2083#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT 0x11 2084#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT 0x15 2085//DN_PCIE_STRAP_MISC 2086#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT 0x18 2087#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 2088//DN_PCIE_STRAP_MISC2 2089#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT 0x2 2090 2091 2092// addressBlock: rcc_dwnp_BIFDEC1 2093//PCIEP_RESERVED 2094#define PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 2095//PCIEP_SCRATCH 2096#define PCIEP_SCRATCH__PCIEP_SCRATCH__SHIFT 0x0 2097//PCIE_ERR_CNTL 2098#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 2099#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 2100#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0xb 2101#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 2102//PCIE_RX_CNTL 2103#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 2104#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT 0x9 2105#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 2106#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT 0x15 2107#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT 0x1b 2108//PCIE_LC_SPEED_CNTL 2109#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 2110#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 2111//PCIE_LC_CNTL2 2112#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT 0x1b 2113//PCIEP_STRAP_MISC 2114#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT 0xa 2115//LTR_MSG_INFO_FROM_EP 2116#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT 0x0 2117 2118 2119// addressBlock: rcc_ep_BIFDEC1 2120//EP_PCIE_SCRATCH 2121#define EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT 0x0 2122//EP_PCIE_CNTL 2123#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT 0x7 2124#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT 0x8 2125#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT 0x1e 2126//EP_PCIE_INT_CNTL 2127#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT 0x0 2128#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT 0x1 2129#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT 0x2 2130#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT 0x3 2131#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT 0x4 2132#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT 0x6 2133//EP_PCIE_INT_STATUS 2134#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT 0x0 2135#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT 0x1 2136#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT 0x2 2137#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT 0x3 2138#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT 0x4 2139#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT 0x6 2140//EP_PCIE_RX_CNTL2 2141#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT 0x0 2142//EP_PCIE_BUS_CNTL 2143#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT 0x7 2144//EP_PCIE_CFG_CNTL 2145#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT 0x0 2146#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT 0x1 2147#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT 0x2 2148//EP_PCIE_OBFF_CNTL 2149#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__SHIFT 0x0 2150#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__SHIFT 0x1 2151#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__SHIFT 0x2 2152#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__SHIFT 0x3 2153#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__SHIFT 0x4 2154#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__SHIFT 0x8 2155#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__SHIFT 0xc 2156#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__SHIFT 0x10 2157#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__SHIFT 0x11 2158#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__SHIFT 0x12 2159#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__SHIFT 0x13 2160#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__SHIFT 0x14 2161//EP_PCIE_TX_LTR_CNTL 2162#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT 0x0 2163#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT 0x3 2164#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT 0x6 2165#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT 0x7 2166#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT 0xa 2167#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT 0xd 2168#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT 0xe 2169#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT 0xf 2170#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT 0x10 2171//EP_PCIE_STRAP_MISC 2172#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT 0x1d 2173//EP_PCIE_STRAP_MISC2 2174#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT 0x4 2175//EP_PCIE_STRAP_PI 2176//EP_PCIE_F0_DPA_CAP 2177#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT 0x8 2178#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT 0xc 2179#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT 0x10 2180#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT 0x18 2181//EP_PCIE_F0_DPA_LATENCY_INDICATOR 2182#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT 0x0 2183//EP_PCIE_F0_DPA_CNTL 2184#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT 0x0 2185#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT 0x8 2186//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 2187#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2188//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 2189#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2190//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 2191#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2192//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 2193#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2194//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 2195#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2196//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 2197#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2198//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 2199#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2200//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 2201#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT 0x0 2202//EP_PCIE_PME_CONTROL 2203#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT 0x0 2204//EP_PCIEP_RESERVED 2205#define EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT 0x0 2206//EP_PCIE_TX_CNTL 2207#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT 0xa 2208#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT 0xc 2209#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT 0x18 2210#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT 0x19 2211#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT 0x1a 2212//EP_PCIE_TX_REQUESTER_ID 2213#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT 0x0 2214#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT 0x3 2215#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT 0x8 2216//EP_PCIE_ERR_CNTL 2217#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT 0x0 2218#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT 0x8 2219#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT 0x11 2220#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT 0x12 2221#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT 0x18 2222#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT 0x19 2223#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT 0x1a 2224#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT 0x1b 2225#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT 0x1c 2226#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT 0x1d 2227#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT 0x1e 2228#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT 0x1f 2229//EP_PCIE_RX_CNTL 2230#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT 0x8 2231#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT 0x9 2232#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT 0x14 2233#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT 0x15 2234#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT 0x16 2235#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT 0x18 2236#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT 0x19 2237#define EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT 0x1a 2238//EP_PCIE_LC_SPEED_CNTL 2239#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT 0x0 2240#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT 0x1 2241 2242 2243// addressBlock: bif_bx_pf_BIFDEC1 2244//BIF_MM_INDACCESS_CNTL 2245#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1 2246//BUS_CNTL 2247#define BUS_CNTL__PMI_INT_DIS_EP__SHIFT 0x3 2248#define BUS_CNTL__PMI_INT_DIS_DN__SHIFT 0x4 2249#define BUS_CNTL__PMI_INT_DIS_SWUS__SHIFT 0x5 2250#define BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT 0x6 2251#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT 0x7 2252#define BUS_CNTL__SET_AZ_TC__SHIFT 0xa 2253#define BUS_CNTL__SET_MC_TC__SHIFT 0xd 2254#define BUS_CNTL__ZERO_BE_WR_EN__SHIFT 0x10 2255#define BUS_CNTL__ZERO_BE_RD_EN__SHIFT 0x11 2256#define BUS_CNTL__RD_STALL_IO_WR__SHIFT 0x12 2257#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT 0x13 2258#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT 0x14 2259#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT 0x15 2260#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT 0x16 2261#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT 0x17 2262#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT 0x18 2263//BIF_SCRATCH0 2264#define BIF_SCRATCH0__BIF_SCRATCH0__SHIFT 0x0 2265//BIF_SCRATCH1 2266#define BIF_SCRATCH1__BIF_SCRATCH1__SHIFT 0x0 2267//BX_RESET_EN 2268#define BX_RESET_EN__COR_RESET_EN__SHIFT 0x0 2269#define BX_RESET_EN__REG_RESET_EN__SHIFT 0x1 2270#define BX_RESET_EN__STY_RESET_EN__SHIFT 0x2 2271#define BX_RESET_EN__FLR_TWICE_EN__SHIFT 0x8 2272#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT 0x10 2273//MM_CFGREGS_CNTL 2274#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT 0x0 2275#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT 0x6 2276#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT 0x1f 2277//BX_RESET_CNTL 2278#define BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT 0x0 2279//INTERRUPT_CNTL 2280#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT 0x0 2281#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT 0x1 2282#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT 0x3 2283#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT 0x4 2284#define INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT 0x8 2285#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT 0xf 2286//INTERRUPT_CNTL2 2287#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT 0x0 2288//CLKREQB_PAD_CNTL 2289#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT 0x0 2290#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT 0x1 2291#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT 0x2 2292#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT 0x3 2293#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT 0x5 2294#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT 0x6 2295#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT 0x7 2296#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT 0x8 2297#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT 0x9 2298#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT 0xa 2299#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT 0xb 2300#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT 0xc 2301#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT 0xd 2302#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__SHIFT 0x18 2303//CLKREQB_PERF_COUNTER 2304#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__SHIFT 0x0 2305//BIF_CLK_CTRL 2306#define BIF_CLK_CTRL__BIF_XSTCLK_READY__SHIFT 0x0 2307#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__SHIFT 0x1 2308//BIF_FEATURES_CONTROL_MISC 2309#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT 0x0 2310#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT 0x1 2311#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT 0x2 2312#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT 0x3 2313#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__SHIFT 0x9 2314#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__SHIFT 0xa 2315#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0xb 2316#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT 0xc 2317#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT 0xd 2318#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT 0xf 2319#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__SHIFT 0x11 2320#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__SHIFT 0x12 2321#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT 0x18 2322//BIF_DOORBELL_CNTL 2323#define BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT 0x0 2324#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT 0x1 2325#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT 0x2 2326#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT 0x3 2327#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT 0x4 2328#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT 0x18 2329#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT 0x19 2330#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT 0x1a 2331#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT 0x1b 2332//BIF_DOORBELL_INT_CNTL 2333#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT 0x0 2334#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__SHIFT 0x1 2335#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT 0x10 2336#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__SHIFT 0x11 2337//BIF_SLVARB_MODE 2338#define BIF_SLVARB_MODE__SLVARB_MODE__SHIFT 0x0 2339//BIF_FB_EN 2340#define BIF_FB_EN__FB_READ_EN__SHIFT 0x0 2341#define BIF_FB_EN__FB_WRITE_EN__SHIFT 0x1 2342//BIF_BUSY_DELAY_CNTR 2343#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__SHIFT 0x0 2344//BIF_PERFMON_CNTL 2345#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__SHIFT 0x0 2346#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__SHIFT 0x1 2347#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__SHIFT 0x2 2348#define BIF_PERFMON_CNTL__PERF_SEL0__SHIFT 0x8 2349#define BIF_PERFMON_CNTL__PERF_SEL1__SHIFT 0xd 2350//BIF_PERFCOUNTER0_RESULT 2351#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 2352//BIF_PERFCOUNTER1_RESULT 2353#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__SHIFT 0x0 2354//BIF_MST_TRANS_PENDING_VF 2355#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT 0x0 2356//BIF_SLV_TRANS_PENDING_VF 2357#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT 0x0 2358//BACO_CNTL 2359#define BACO_CNTL__BACO_EN__SHIFT 0x0 2360#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__SHIFT 0x1 2361#define BACO_CNTL__BACO_DUMMY_EN__SHIFT 0x2 2362#define BACO_CNTL__BACO_POWER_OFF__SHIFT 0x3 2363#define BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT 0x5 2364#define BACO_CNTL__BACO_RST_INTR_MASK__SHIFT 0x6 2365#define BACO_CNTL__BACO_MODE__SHIFT 0x8 2366#define BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT 0x9 2367#define BACO_CNTL__BACO_AUTO_EXIT__SHIFT 0x1f 2368//BIF_BACO_EXIT_TIME0 2369#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT 0x0 2370//BIF_BACO_EXIT_TIMER1 2371#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT 0x0 2372#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT 0x1a 2373#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT 0x1b 2374#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT 0x1c 2375#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT 0x1d 2376#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT 0x1f 2377//BIF_BACO_EXIT_TIMER2 2378#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT 0x0 2379//BIF_BACO_EXIT_TIMER3 2380#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT 0x0 2381//BIF_BACO_EXIT_TIMER4 2382#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT 0x0 2383//MEM_TYPE_CNTL 2384#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT 0x0 2385//SMU_BIF_VDDGFX_PWR_STATUS 2386#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__SHIFT 0x0 2387//BIF_VDDGFX_GFX0_LOWER 2388#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__SHIFT 0x2 2389#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__SHIFT 0x1e 2390#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__SHIFT 0x1f 2391//BIF_VDDGFX_GFX0_UPPER 2392#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__SHIFT 0x2 2393//BIF_VDDGFX_GFX1_LOWER 2394#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__SHIFT 0x2 2395#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__SHIFT 0x1e 2396#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__SHIFT 0x1f 2397//BIF_VDDGFX_GFX1_UPPER 2398#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__SHIFT 0x2 2399//BIF_VDDGFX_GFX2_LOWER 2400#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__SHIFT 0x2 2401#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__SHIFT 0x1e 2402#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__SHIFT 0x1f 2403//BIF_VDDGFX_GFX2_UPPER 2404#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__SHIFT 0x2 2405//BIF_VDDGFX_GFX3_LOWER 2406#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__SHIFT 0x2 2407#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__SHIFT 0x1e 2408#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__SHIFT 0x1f 2409//BIF_VDDGFX_GFX3_UPPER 2410#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__SHIFT 0x2 2411//BIF_VDDGFX_GFX4_LOWER 2412#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__SHIFT 0x2 2413#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__SHIFT 0x1e 2414#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__SHIFT 0x1f 2415//BIF_VDDGFX_GFX4_UPPER 2416#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__SHIFT 0x2 2417//BIF_VDDGFX_GFX5_LOWER 2418#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__SHIFT 0x2 2419#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__SHIFT 0x1e 2420#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__SHIFT 0x1f 2421//BIF_VDDGFX_GFX5_UPPER 2422#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__SHIFT 0x2 2423//BIF_VDDGFX_RSV1_LOWER 2424#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__SHIFT 0x2 2425#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__SHIFT 0x1e 2426#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__SHIFT 0x1f 2427//BIF_VDDGFX_RSV1_UPPER 2428#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__SHIFT 0x2 2429//BIF_VDDGFX_RSV2_LOWER 2430#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__SHIFT 0x2 2431#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__SHIFT 0x1e 2432#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__SHIFT 0x1f 2433//BIF_VDDGFX_RSV2_UPPER 2434#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__SHIFT 0x2 2435//BIF_VDDGFX_RSV3_LOWER 2436#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__SHIFT 0x2 2437#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__SHIFT 0x1e 2438#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__SHIFT 0x1f 2439//BIF_VDDGFX_RSV3_UPPER 2440#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__SHIFT 0x2 2441//BIF_VDDGFX_RSV4_LOWER 2442#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__SHIFT 0x2 2443#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__SHIFT 0x1e 2444#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__SHIFT 0x1f 2445//BIF_VDDGFX_RSV4_UPPER 2446#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__SHIFT 0x2 2447//BIF_VDDGFX_FB_CMP 2448#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__SHIFT 0x0 2449#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__SHIFT 0x1 2450#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__SHIFT 0x2 2451#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__SHIFT 0x3 2452#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__SHIFT 0x4 2453#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__SHIFT 0x5 2454//BIF_DOORBELL_GBLAPER1_LOWER 2455#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__SHIFT 0x2 2456#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__SHIFT 0x1f 2457//BIF_DOORBELL_GBLAPER1_UPPER 2458#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__SHIFT 0x2 2459//BIF_DOORBELL_GBLAPER2_LOWER 2460#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__SHIFT 0x2 2461#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__SHIFT 0x1f 2462//BIF_DOORBELL_GBLAPER2_UPPER 2463#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__SHIFT 0x2 2464//REMAP_HDP_MEM_FLUSH_CNTL 2465#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT 0x2 2466//REMAP_HDP_REG_FLUSH_CNTL 2467#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT 0x2 2468//BIF_RB_CNTL 2469#define BIF_RB_CNTL__RB_ENABLE__SHIFT 0x0 2470#define BIF_RB_CNTL__RB_SIZE__SHIFT 0x1 2471#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT 0x8 2472#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT 0x9 2473#define BIF_RB_CNTL__BIF_RB_TRAN__SHIFT 0x11 2474#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT 0x1f 2475//BIF_RB_BASE 2476#define BIF_RB_BASE__ADDR__SHIFT 0x0 2477//BIF_RB_RPTR 2478#define BIF_RB_RPTR__OFFSET__SHIFT 0x2 2479//BIF_RB_WPTR 2480#define BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT 0x0 2481#define BIF_RB_WPTR__OFFSET__SHIFT 0x2 2482//BIF_RB_WPTR_ADDR_HI 2483#define BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT 0x0 2484//BIF_RB_WPTR_ADDR_LO 2485#define BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT 0x2 2486//MAILBOX_INDEX 2487#define MAILBOX_INDEX__MAILBOX_INDEX__SHIFT 0x0 2488//BIF_GPUIOV_RESET_NOTIFICATION 2489#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__SHIFT 0x0 2490//BIF_UVD_GPUIOV_CFG_SIZE 2491#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__SHIFT 0x0 2492//BIF_VCE_GPUIOV_CFG_SIZE 2493#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__SHIFT 0x0 2494//BIF_GFX_SDMA_GPUIOV_CFG_SIZE 2495#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__SHIFT 0x0 2496//BIF_GMI_WRR_WEIGHT 2497#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__SHIFT 0x0 2498#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__SHIFT 0x8 2499#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__SHIFT 0x10 2500//NBIF_STRAP_WRITE_CTRL 2501#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT 0x0 2502//BIF_PERSTB_PAD_CNTL 2503#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT 0x0 2504//BIF_PX_EN_PAD_CNTL 2505#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT 0x0 2506//BIF_REFPADKIN_PAD_CNTL 2507#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT 0x0 2508//BIF_CLKREQB_PAD_CNTL 2509#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT 0x0 2510 2511 2512// addressBlock: rcc_pf_0_BIFDEC1 2513//RCC_BACO_CNTL_MISC 2514#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT 0x0 2515#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT 0x1 2516//RCC_RESET_EN 2517#define RCC_RESET_EN__DB_APER_RESET_EN__SHIFT 0xf 2518//RCC_VDM_SUPPORT 2519#define RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT 0x0 2520#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT 0x1 2521#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT 0x2 2522#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT 0x3 2523#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT 0x4 2524//RCC_PEER_REG_RANGE0 2525#define RCC_PEER_REG_RANGE0__START_ADDR__SHIFT 0x0 2526#define RCC_PEER_REG_RANGE0__END_ADDR__SHIFT 0x10 2527//RCC_PEER_REG_RANGE1 2528#define RCC_PEER_REG_RANGE1__START_ADDR__SHIFT 0x0 2529#define RCC_PEER_REG_RANGE1__END_ADDR__SHIFT 0x10 2530//RCC_BUS_CNTL 2531#define RCC_BUS_CNTL__PMI_IO_DIS__SHIFT 0x2 2532#define RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT 0x3 2533#define RCC_BUS_CNTL__PMI_BM_DIS__SHIFT 0x4 2534#define RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT 0x5 2535#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT 0x6 2536#define RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT 0x7 2537#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT 0x8 2538#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT 0xc 2539#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT 0xd 2540#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x10 2541#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x11 2542#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x12 2543#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT 0x13 2544#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT 0x14 2545#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT 0x15 2546#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT 0x18 2547#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT 0x19 2548#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT 0x1c 2549#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT 0x1d 2550//RCC_CONFIG_CNTL 2551#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT 0x0 2552#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT 0x2 2553#define RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT 0x3 2554//RCC_CONFIG_F0_BASE 2555#define RCC_CONFIG_F0_BASE__F0_BASE__SHIFT 0x0 2556//RCC_CONFIG_APER_SIZE 2557#define RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT 0x0 2558//RCC_CONFIG_REG_APER_SIZE 2559#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT 0x0 2560//RCC_XDMA_LO 2561#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT 0x0 2562#define RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT 0x1f 2563//RCC_XDMA_HI 2564#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT 0x0 2565//RCC_FEATURES_CONTROL_MISC 2566#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__SHIFT 0x4 2567#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__SHIFT 0x5 2568#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__SHIFT 0x6 2569#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT 0x8 2570#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT 0x9 2571#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT 0xa 2572#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT 0xb 2573#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT 0xc 2574#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT 0xd 2575#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT 0xe 2576#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT 0xf 2577#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT 0x10 2578#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT 0x11 2579#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT 0x12 2580//RCC_BUSNUM_CNTL1 2581#define RCC_BUSNUM_CNTL1__ID_MASK__SHIFT 0x0 2582//RCC_BUSNUM_LIST0 2583#define RCC_BUSNUM_LIST0__ID0__SHIFT 0x0 2584#define RCC_BUSNUM_LIST0__ID1__SHIFT 0x8 2585#define RCC_BUSNUM_LIST0__ID2__SHIFT 0x10 2586#define RCC_BUSNUM_LIST0__ID3__SHIFT 0x18 2587//RCC_BUSNUM_LIST1 2588#define RCC_BUSNUM_LIST1__ID4__SHIFT 0x0 2589#define RCC_BUSNUM_LIST1__ID5__SHIFT 0x8 2590#define RCC_BUSNUM_LIST1__ID6__SHIFT 0x10 2591#define RCC_BUSNUM_LIST1__ID7__SHIFT 0x18 2592//RCC_BUSNUM_CNTL2 2593#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT 0x0 2594#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT 0x8 2595#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT 0x10 2596#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT 0x11 2597//RCC_CAPTURE_HOST_BUSNUM 2598#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT 0x0 2599//RCC_HOST_BUSNUM 2600#define RCC_HOST_BUSNUM__HOST_ID__SHIFT 0x0 2601//RCC_PEER0_FB_OFFSET_HI 2602#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT 0x0 2603//RCC_PEER0_FB_OFFSET_LO 2604#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT 0x0 2605#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT 0x1f 2606//RCC_PEER1_FB_OFFSET_HI 2607#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT 0x0 2608//RCC_PEER1_FB_OFFSET_LO 2609#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT 0x0 2610#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT 0x1f 2611//RCC_PEER2_FB_OFFSET_HI 2612#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT 0x0 2613//RCC_PEER2_FB_OFFSET_LO 2614#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT 0x0 2615#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT 0x1f 2616//RCC_PEER3_FB_OFFSET_HI 2617#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT 0x0 2618//RCC_PEER3_FB_OFFSET_LO 2619#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT 0x0 2620#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT 0x1f 2621//RCC_DEVFUNCNUM_LIST0 2622#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT 0x0 2623#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT 0x8 2624#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT 0x10 2625#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT 0x18 2626//RCC_DEVFUNCNUM_LIST1 2627#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT 0x0 2628#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT 0x8 2629#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT 0x10 2630#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT 0x18 2631//RCC_DEV0_LINK_CNTL 2632#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT 0x0 2633#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT 0x8 2634//RCC_CMN_LINK_CNTL 2635#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT 0x0 2636#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT 0x1 2637#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT 0x2 2638#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT 0x3 2639//RCC_EP_REQUESTERID_RESTORE 2640#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT 0x0 2641#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT 0x8 2642//RCC_LTR_LSWITCH_CNTL 2643#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT 0x0 2644//RCC_MH_ARB_CNTL 2645#define RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT 0x0 2646#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT 0x1 2647 2648 2649// addressBlock: rcc_pf_0_BIFDEC2 2650//GFXMSIX_VECT0_ADDR_LO 2651#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2652//GFXMSIX_VECT0_ADDR_HI 2653#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2654//GFXMSIX_VECT0_MSG_DATA 2655#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 2656//GFXMSIX_VECT0_CONTROL 2657#define GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 2658//GFXMSIX_VECT1_ADDR_LO 2659#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2660//GFXMSIX_VECT1_ADDR_HI 2661#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2662//GFXMSIX_VECT1_MSG_DATA 2663#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 2664//GFXMSIX_VECT1_CONTROL 2665#define GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 2666//GFXMSIX_VECT2_ADDR_LO 2667#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 2668//GFXMSIX_VECT2_ADDR_HI 2669#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 2670//GFXMSIX_VECT2_MSG_DATA 2671#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 2672//GFXMSIX_VECT2_CONTROL 2673#define GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 2674//GFXMSIX_PBA 2675#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT 0x0 2676#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT 0x1 2677#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT 0x2 2678 2679 2680// addressBlock: rcc_strap_BIFDEC1 2681//RCC_DEV0_PORT_STRAP0 2682#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 2683#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 2684#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 2685#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 2686#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 2687#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 2688#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 2689#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 2690#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c 2691#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f 2692//RCC_DEV0_PORT_STRAP1 2693#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 2694#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 2695//RCC_DEV0_PORT_STRAP2 2696#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 2697#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 2698#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 2699#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 2700#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 2701#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 2702#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 2703#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 2704#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 2705#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 2706#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc 2707#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd 2708#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe 2709#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf 2710#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 2711#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 2712#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 2713#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 2714#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 2715#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a 2716#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d 2717//RCC_DEV0_PORT_STRAP3 2718#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 2719#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 2720#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 2721#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 2722#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 2723#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 2724#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 2725#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 2726#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb 2727#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe 2728#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 2729#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 2730#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 2731#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b 2732#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d 2733#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e 2734#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f 2735//RCC_DEV0_PORT_STRAP4 2736#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 2737#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 2738#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 2739#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 2740//RCC_DEV0_PORT_STRAP5 2741#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 2742#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 2743#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 2744#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 2745#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 2746#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 2747#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 2748#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 2749#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 2750#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 2751#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 2752#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a 2753#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b 2754#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c 2755#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d 2756#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e 2757#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f 2758//RCC_DEV0_PORT_STRAP6 2759#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 2760#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 2761//RCC_DEV0_PORT_STRAP7 2762#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 2763#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 2764#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc 2765#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 2766#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 2767#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d 2768//RCC_DEV0_EPF0_STRAP0 2769#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 2770#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 2771#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 2772#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 2773#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c 2774#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d 2775#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e 2776#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f 2777//RCC_DEV0_EPF0_STRAP1 2778#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 2779#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 2780//RCC_DEV0_EPF0_STRAP13 2781#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 2782#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 2783#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 2784//RCC_DEV0_EPF0_STRAP2 2785#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 2786#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 2787#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 2788#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 2789#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 2790#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 2791#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe 2792#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf 2793#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 2794#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 2795#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 2796#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 2797#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 2798#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 2799#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 2800#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 2801#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b 2802#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c 2803#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d 2804#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e 2805#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f 2806//RCC_DEV0_EPF0_STRAP3 2807#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 2808#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 2809#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 2810#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 2811#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 2812#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 2813#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 2814#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 2815#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 2816#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a 2817#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b 2818//RCC_DEV0_EPF0_STRAP4 2819#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 2820#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 2821#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 2822#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 2823#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 2824#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c 2825#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f 2826//RCC_DEV0_EPF0_STRAP5 2827#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 2828//RCC_DEV0_EPF0_STRAP8 2829#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 2830#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 2831#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 2832#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 2833#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 2834#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 2835#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 2836#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 2837#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc 2838#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe 2839#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 2840#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 2841#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 2842#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 2843#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 2844#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a 2845#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b 2846#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e 2847//RCC_DEV0_EPF0_STRAP9 2848//RCC_DEV0_EPF1_STRAP0 2849#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 2850#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 2851#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 2852#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c 2853#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d 2854#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e 2855#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f 2856//RCC_DEV0_EPF1_STRAP10 2857#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 2858#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2859//RCC_DEV0_EPF1_STRAP11 2860#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 2861#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2862//RCC_DEV0_EPF1_STRAP12 2863#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 2864#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 2865//RCC_DEV0_EPF1_STRAP13 2866#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 2867#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 2868#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 2869//RCC_DEV0_EPF1_STRAP2 2870#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 2871#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 2872#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe 2873#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 2874#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 2875#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 2876#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 2877#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 2878#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 2879#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 2880#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 2881//RCC_DEV0_EPF1_STRAP3 2882#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 2883#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 2884#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 2885#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 2886#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 2887#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 2888#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 2889#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 2890#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a 2891#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b 2892//RCC_DEV0_EPF1_STRAP4 2893#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 2894#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 2895#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 2896#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 2897#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c 2898#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f 2899//RCC_DEV0_EPF1_STRAP5 2900#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 2901//RCC_DEV0_EPF1_STRAP6 2902#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 2903#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 2904#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 2905#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 2906#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 2907#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 2908#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 2909#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 2910#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 2911#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 2912//RCC_DEV0_EPF1_STRAP7 2913#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 2914#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 2915 2916 2917// addressBlock: bif_bx_pf_BIFPFVFDEC1 2918//BIF_BME_STATUS 2919#define BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT 0x0 2920#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT 0x10 2921//BIF_ATOMIC_ERR_LOG 2922#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT 0x0 2923#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT 0x1 2924#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT 0x10 2925#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT 0x11 2926//DOORBELL_SELFRING_GPA_APER_BASE_HIGH 2927#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT 0x0 2928//DOORBELL_SELFRING_GPA_APER_BASE_LOW 2929#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT 0x0 2930//DOORBELL_SELFRING_GPA_APER_CNTL 2931#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT 0x0 2932#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT 0x8 2933//HDP_REG_COHERENCY_FLUSH_CNTL 2934#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT 0x0 2935//HDP_MEM_COHERENCY_FLUSH_CNTL 2936#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT 0x0 2937//GPU_HDP_FLUSH_REQ 2938#define GPU_HDP_FLUSH_REQ__CP0__SHIFT 0x0 2939#define GPU_HDP_FLUSH_REQ__CP1__SHIFT 0x1 2940#define GPU_HDP_FLUSH_REQ__CP2__SHIFT 0x2 2941#define GPU_HDP_FLUSH_REQ__CP3__SHIFT 0x3 2942#define GPU_HDP_FLUSH_REQ__CP4__SHIFT 0x4 2943#define GPU_HDP_FLUSH_REQ__CP5__SHIFT 0x5 2944#define GPU_HDP_FLUSH_REQ__CP6__SHIFT 0x6 2945#define GPU_HDP_FLUSH_REQ__CP7__SHIFT 0x7 2946#define GPU_HDP_FLUSH_REQ__CP8__SHIFT 0x8 2947#define GPU_HDP_FLUSH_REQ__CP9__SHIFT 0x9 2948#define GPU_HDP_FLUSH_REQ__SDMA0__SHIFT 0xa 2949#define GPU_HDP_FLUSH_REQ__SDMA1__SHIFT 0xb 2950//GPU_HDP_FLUSH_DONE 2951#define GPU_HDP_FLUSH_DONE__CP0__SHIFT 0x0 2952#define GPU_HDP_FLUSH_DONE__CP1__SHIFT 0x1 2953#define GPU_HDP_FLUSH_DONE__CP2__SHIFT 0x2 2954#define GPU_HDP_FLUSH_DONE__CP3__SHIFT 0x3 2955#define GPU_HDP_FLUSH_DONE__CP4__SHIFT 0x4 2956#define GPU_HDP_FLUSH_DONE__CP5__SHIFT 0x5 2957#define GPU_HDP_FLUSH_DONE__CP6__SHIFT 0x6 2958#define GPU_HDP_FLUSH_DONE__CP7__SHIFT 0x7 2959#define GPU_HDP_FLUSH_DONE__CP8__SHIFT 0x8 2960#define GPU_HDP_FLUSH_DONE__CP9__SHIFT 0x9 2961#define GPU_HDP_FLUSH_DONE__SDMA0__SHIFT 0xa 2962#define GPU_HDP_FLUSH_DONE__SDMA1__SHIFT 0xb 2963//BIF_TRANS_PENDING 2964#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT 0x0 2965#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT 0x1 2966//MAILBOX_MSGBUF_TRN_DW0 2967#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT 0x0 2968//MAILBOX_MSGBUF_TRN_DW1 2969#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT 0x0 2970//MAILBOX_MSGBUF_TRN_DW2 2971#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT 0x0 2972//MAILBOX_MSGBUF_TRN_DW3 2973#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT 0x0 2974//MAILBOX_MSGBUF_RCV_DW0 2975#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT 0x0 2976//MAILBOX_MSGBUF_RCV_DW1 2977#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT 0x0 2978//MAILBOX_MSGBUF_RCV_DW2 2979#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT 0x0 2980//MAILBOX_MSGBUF_RCV_DW3 2981#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT 0x0 2982//MAILBOX_CONTROL 2983#define MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT 0x0 2984#define MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT 0x1 2985#define MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT 0x8 2986#define MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT 0x9 2987//MAILBOX_INT_CNTL 2988#define MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT 0x0 2989#define MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT 0x1 2990//BIF_VMHV_MAILBOX 2991#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT 0x0 2992#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT 0x1 2993#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT 0x8 2994#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT 0xf 2995#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT 0x10 2996#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT 0x17 2997#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT 0x18 2998#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT 0x19 2999 3000 3001// addressBlock: rcc_pf_0_BIFPFVFDEC1 3002//RCC_DOORBELL_APER_EN 3003#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT 0x0 3004//RCC_CONFIG_MEMSIZE 3005#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT 0x0 3006//RCC_CONFIG_RESERVED 3007#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT 0x0 3008//RCC_IOV_FUNC_IDENTIFIER 3009#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT 0x0 3010#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT 0x1f 3011 3012 3013// addressBlock: syshub_mmreg_ind_syshubdec 3014//SYSHUB_INDEX 3015#define SYSHUB_INDEX__INDEX__SHIFT 0x0 3016//SYSHUB_DATA 3017#define SYSHUB_DATA__DATA__SHIFT 0x0 3018 3019 3020// addressBlock: rcc_strap_rcc_strap_internal 3021//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 3022#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT 0x1 3023#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT 0x2 3024#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT 0x3 3025#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT 0x4 3026#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT 0x5 3027#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT 0x15 3028#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT 0x18 3029#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT 0x19 3030#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT 0x1c 3031#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT 0x1f 3032//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 3033#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT 0x0 3034#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT 0x10 3035//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 3036#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT 0x0 3037#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT 0x1 3038#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT 0x2 3039#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT 0x3 3040#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT 0x4 3041#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT 0x5 3042#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__SHIFT 0x6 3043#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT 0x7 3044#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT 0x8 3045#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT 0x9 3046#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT 0xc 3047#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT 0xd 3048#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT 0xe 3049#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT 0xf 3050#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT 0x10 3051#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT 0x11 3052#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT 0x13 3053#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x14 3054#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT 0x17 3055#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT 0x1a 3056#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT 0x1d 3057//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 3058#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT 0x0 3059#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT 0x1 3060#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT 0x2 3061#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT 0x3 3062#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT 0x6 3063#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT 0x7 3064#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT 0x8 3065#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT 0x9 3066#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0xb 3067#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0xe 3068#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT 0x12 3069#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT 0x15 3070#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT 0x19 3071#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT 0x1b 3072#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT 0x1d 3073#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__SHIFT 0x1e 3074#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT 0x1f 3075//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 3076#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT 0x0 3077#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT 0x8 3078#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT 0x10 3079#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT 0x18 3080//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 3081#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT 0x0 3082#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT 0x8 3083#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT 0x10 3084#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT 0x11 3085#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT 0x12 3086#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT 0x13 3087#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT 0x14 3088#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT 0x15 3089#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT 0x17 3090#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT 0x18 3091#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT 0x19 3092#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT 0x1a 3093#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT 0x1b 3094#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT 0x1c 3095#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT 0x1d 3096#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT 0x1e 3097#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT 0x1f 3098//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 3099#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT 0x0 3100#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT 0x1 3101//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 3102#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT 0x0 3103#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT 0x8 3104#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT 0xc 3105#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT 0x10 3106#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT 0x18 3107#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT 0x1d 3108//RCC_DEV1_PORT_STRAP0 3109#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__SHIFT 0x1 3110#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__SHIFT 0x2 3111#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__SHIFT 0x3 3112#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__SHIFT 0x4 3113#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__SHIFT 0x5 3114#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__SHIFT 0x15 3115#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__SHIFT 0x18 3116#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__SHIFT 0x19 3117#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__SHIFT 0x1c 3118#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__SHIFT 0x1f 3119//RCC_DEV1_PORT_STRAP1 3120#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__SHIFT 0x0 3121#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__SHIFT 0x10 3122//RCC_DEV1_PORT_STRAP2 3123#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__SHIFT 0x0 3124#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__SHIFT 0x1 3125#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__SHIFT 0x2 3126#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__SHIFT 0x3 3127#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__SHIFT 0x4 3128#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__SHIFT 0x5 3129#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__SHIFT 0x6 3130#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__SHIFT 0x7 3131#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__SHIFT 0x8 3132#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__SHIFT 0x9 3133#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__SHIFT 0xc 3134#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__SHIFT 0xd 3135#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__SHIFT 0xe 3136#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__SHIFT 0xf 3137#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__SHIFT 0x10 3138#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__SHIFT 0x11 3139#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__SHIFT 0x13 3140#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x14 3141#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__SHIFT 0x17 3142#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__SHIFT 0x1a 3143#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__SHIFT 0x1d 3144//RCC_DEV1_PORT_STRAP3 3145#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__SHIFT 0x0 3146#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__SHIFT 0x1 3147#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__SHIFT 0x2 3148#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__SHIFT 0x3 3149#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__SHIFT 0x6 3150#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__SHIFT 0x7 3151#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__SHIFT 0x8 3152#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__SHIFT 0x9 3153#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0xb 3154#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0xe 3155#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__SHIFT 0x12 3156#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__SHIFT 0x15 3157#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__SHIFT 0x19 3158#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__SHIFT 0x1b 3159#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__SHIFT 0x1d 3160#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__SHIFT 0x1e 3161#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__SHIFT 0x1f 3162//RCC_DEV1_PORT_STRAP4 3163#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__SHIFT 0x0 3164#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__SHIFT 0x8 3165#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__SHIFT 0x10 3166#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__SHIFT 0x18 3167//RCC_DEV1_PORT_STRAP5 3168#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__SHIFT 0x0 3169#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__SHIFT 0x8 3170#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__SHIFT 0x10 3171#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__SHIFT 0x11 3172#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__SHIFT 0x12 3173#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__SHIFT 0x13 3174#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__SHIFT 0x14 3175#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__SHIFT 0x15 3176#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__SHIFT 0x17 3177#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__SHIFT 0x18 3178#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__SHIFT 0x19 3179#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__SHIFT 0x1a 3180#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__SHIFT 0x1b 3181#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__SHIFT 0x1c 3182#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__SHIFT 0x1d 3183#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__SHIFT 0x1e 3184#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__SHIFT 0x1f 3185//RCC_DEV1_PORT_STRAP6 3186#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__SHIFT 0x0 3187#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__SHIFT 0x1 3188//RCC_DEV1_PORT_STRAP7 3189#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__SHIFT 0x0 3190#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__SHIFT 0x8 3191#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__SHIFT 0xc 3192#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__SHIFT 0x10 3193#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__SHIFT 0x18 3194#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__SHIFT 0x1d 3195//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 3196#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 3197#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 3198#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT 0x14 3199#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT 0x18 3200#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT 0x1c 3201#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT 0x1d 3202#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT 0x1e 3203#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT 0x1f 3204//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 3205#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT 0x0 3206#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT 0x10 3207//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 3208#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT 0x0 3209#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT 0x1 3210#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT 0x6 3211#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT 0x7 3212#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT 0x8 3213#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT 0x9 3214#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT 0xe 3215#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT 0xf 3216#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT 0x10 3217#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT 0x11 3218#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT 0x12 3219#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT 0x14 3220#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT 0x15 3221#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT 0x16 3222#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT 0x17 3223#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x18 3224#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT 0x1b 3225#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT 0x1c 3226#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT 0x1d 3227#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT 0x1e 3228#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT 0x1f 3229//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 3230#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT 0x0 3231#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT 0x1 3232#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT 0x2 3233#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT 0x12 3234#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT 0x13 3235#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT 0x14 3236#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT 0x15 3237#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT 0x18 3238#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__SHIFT 0x19 3239#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT 0x1a 3240#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT 0x1b 3241//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 3242#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__SHIFT 0x0 3243#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT 0x14 3244#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT 0x15 3245#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT 0x16 3246#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT 0x17 3247#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT 0x1c 3248#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT 0x1f 3249//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 3250#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT 0x0 3251//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 3252#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT 0x0 3253#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x1 3254#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT 0x3 3255#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT 0x4 3256#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT 0x5 3257#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT 0x7 3258#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT 0x8 3259#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT 0x9 3260#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT 0xc 3261#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT 0xe 3262#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT 0x10 3263#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT 0x13 3264#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT 0x16 3265#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__SHIFT 0x18 3266#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT 0x19 3267#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT 0x1a 3268#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT 0x1b 3269#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT 0x1e 3270//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 3271//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 3272#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT 0x0 3273#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT 0x8 3274#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT 0x10 3275//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 3276#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT 0x0 3277#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT 0x10 3278#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT 0x14 3279#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT 0x1c 3280#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT 0x1d 3281#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT 0x1e 3282#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT 0x1f 3283//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 3284#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT 0x7 3285#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT 0x8 3286#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT 0xe 3287#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT 0x10 3288#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT 0x11 3289#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__SHIFT 0x12 3290#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT 0x14 3291#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT 0x15 3292#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__SHIFT 0x16 3293#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__SHIFT 0x17 3294#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT 0x18 3295//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 3296#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT 0x0 3297#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT 0x1 3298#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT 0x2 3299#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT 0x12 3300#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT 0x13 3301#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT 0x14 3302#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT 0x18 3303#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__SHIFT 0x19 3304#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT 0x1a 3305#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT 0x1b 3306//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 3307#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT 0x14 3308#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT 0x15 3309#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT 0x16 3310#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT 0x17 3311#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT 0x1c 3312#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT 0x1f 3313//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 3314#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT 0x0 3315//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 3316#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT 0x0 3317#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x1 3318#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT 0x2 3319#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__SHIFT 0x4 3320#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT 0x8 3321#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x9 3322#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT 0x10 3323#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x11 3324#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT 0x18 3325#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT 0x19 3326//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 3327#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__SHIFT 0x0 3328#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__SHIFT 0x1 3329//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 3330#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__SHIFT 0x0 3331#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3332//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 3333#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__SHIFT 0x0 3334#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3335//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 3336#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__SHIFT 0x0 3337#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__SHIFT 0x1 3338//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 3339#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT 0x0 3340#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT 0x8 3341#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT 0x10 3342//RCC_DEV0_EPF2_STRAP0 3343#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__SHIFT 0x0 3344#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__SHIFT 0x10 3345#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__SHIFT 0x14 3346#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__SHIFT 0x1c 3347#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__SHIFT 0x1d 3348#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__SHIFT 0x1e 3349#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__SHIFT 0x1f 3350//RCC_DEV0_EPF2_STRAP2 3351#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__SHIFT 0x7 3352#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__SHIFT 0x8 3353#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__SHIFT 0xe 3354#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__SHIFT 0x10 3355#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__SHIFT 0x11 3356#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__SHIFT 0x14 3357#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__SHIFT 0x15 3358#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__SHIFT 0x17 3359#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__SHIFT 0x18 3360//RCC_DEV0_EPF2_STRAP3 3361#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__SHIFT 0x0 3362#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__SHIFT 0x1 3363#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__SHIFT 0x2 3364#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__SHIFT 0x12 3365#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__SHIFT 0x13 3366#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__SHIFT 0x14 3367#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__SHIFT 0x18 3368#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__SHIFT 0x19 3369#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__SHIFT 0x1a 3370#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__SHIFT 0x1b 3371//RCC_DEV0_EPF2_STRAP4 3372#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__SHIFT 0x14 3373#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__SHIFT 0x15 3374#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__SHIFT 0x16 3375#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__SHIFT 0x17 3376#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__SHIFT 0x1c 3377#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__SHIFT 0x1f 3378//RCC_DEV0_EPF2_STRAP5 3379#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__SHIFT 0x0 3380#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__SHIFT 0x18 3381//RCC_DEV0_EPF2_STRAP6 3382#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__SHIFT 0x0 3383#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x1 3384#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__SHIFT 0x4 3385#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__SHIFT 0x8 3386#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__SHIFT 0x9 3387//RCC_DEV0_EPF2_STRAP13 3388#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__SHIFT 0x0 3389#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__SHIFT 0x8 3390#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__SHIFT 0x10 3391//RCC_DEV0_EPF3_STRAP0 3392#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__SHIFT 0x0 3393#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__SHIFT 0x10 3394#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__SHIFT 0x14 3395#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__SHIFT 0x1c 3396#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__SHIFT 0x1d 3397#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__SHIFT 0x1e 3398#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__SHIFT 0x1f 3399//RCC_DEV0_EPF3_STRAP2 3400#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__SHIFT 0x7 3401#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__SHIFT 0x8 3402#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__SHIFT 0xe 3403#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__SHIFT 0x10 3404#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__SHIFT 0x11 3405#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__SHIFT 0x14 3406#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__SHIFT 0x15 3407#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__SHIFT 0x17 3408#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__SHIFT 0x18 3409//RCC_DEV0_EPF3_STRAP3 3410#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__SHIFT 0x0 3411#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__SHIFT 0x1 3412#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__SHIFT 0x2 3413#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__SHIFT 0x12 3414#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__SHIFT 0x13 3415#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__SHIFT 0x14 3416#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__SHIFT 0x18 3417#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__SHIFT 0x19 3418#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__SHIFT 0x1a 3419#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__SHIFT 0x1b 3420//RCC_DEV0_EPF3_STRAP4 3421#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__SHIFT 0x14 3422#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__SHIFT 0x15 3423#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__SHIFT 0x16 3424#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__SHIFT 0x17 3425#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__SHIFT 0x1c 3426#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__SHIFT 0x1f 3427//RCC_DEV0_EPF3_STRAP5 3428#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__SHIFT 0x0 3429#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__SHIFT 0x10 3430#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__SHIFT 0x14 3431//RCC_DEV0_EPF3_STRAP6 3432#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__SHIFT 0x0 3433#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__SHIFT 0x1 3434#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__SHIFT 0x4 3435//RCC_DEV0_EPF3_STRAP13 3436#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__SHIFT 0x0 3437#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__SHIFT 0x8 3438#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__SHIFT 0x10 3439//RCC_DEV0_EPF4_STRAP0 3440#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__SHIFT 0x0 3441#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__SHIFT 0x10 3442#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__SHIFT 0x14 3443#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__SHIFT 0x1c 3444#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__SHIFT 0x1d 3445#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__SHIFT 0x1e 3446#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__SHIFT 0x1f 3447//RCC_DEV0_EPF4_STRAP2 3448#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__SHIFT 0x7 3449#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__SHIFT 0x8 3450#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__SHIFT 0xe 3451#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__SHIFT 0x10 3452#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__SHIFT 0x11 3453#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__SHIFT 0x14 3454#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__SHIFT 0x15 3455#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__SHIFT 0x17 3456#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__SHIFT 0x18 3457//RCC_DEV0_EPF4_STRAP3 3458#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__SHIFT 0x0 3459#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__SHIFT 0x1 3460#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__SHIFT 0x2 3461#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__SHIFT 0x12 3462#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__SHIFT 0x13 3463#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__SHIFT 0x14 3464#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__SHIFT 0x18 3465#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__SHIFT 0x19 3466#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__SHIFT 0x1a 3467#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__SHIFT 0x1b 3468//RCC_DEV0_EPF4_STRAP4 3469#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__SHIFT 0x14 3470#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__SHIFT 0x15 3471#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__SHIFT 0x16 3472#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__SHIFT 0x17 3473#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__SHIFT 0x1c 3474#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__SHIFT 0x1f 3475//RCC_DEV0_EPF4_STRAP5 3476#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__SHIFT 0x0 3477#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__SHIFT 0x10 3478#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__SHIFT 0x14 3479//RCC_DEV0_EPF4_STRAP6 3480#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__SHIFT 0x0 3481#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x1 3482#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__SHIFT 0x4 3483#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__SHIFT 0x8 3484#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x9 3485#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__SHIFT 0x10 3486#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__SHIFT 0x11 3487//RCC_DEV0_EPF4_STRAP13 3488#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__SHIFT 0x0 3489#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__SHIFT 0x8 3490#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__SHIFT 0x10 3491//RCC_DEV0_EPF5_STRAP0 3492#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__SHIFT 0x0 3493#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__SHIFT 0x10 3494#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__SHIFT 0x14 3495#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__SHIFT 0x1c 3496#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__SHIFT 0x1d 3497#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__SHIFT 0x1e 3498#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__SHIFT 0x1f 3499//RCC_DEV0_EPF5_STRAP2 3500#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__SHIFT 0x7 3501#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__SHIFT 0x8 3502#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__SHIFT 0xe 3503#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__SHIFT 0x10 3504#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__SHIFT 0x11 3505#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__SHIFT 0x14 3506#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__SHIFT 0x15 3507#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__SHIFT 0x17 3508#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__SHIFT 0x18 3509//RCC_DEV0_EPF5_STRAP3 3510#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__SHIFT 0x0 3511#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__SHIFT 0x1 3512#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__SHIFT 0x2 3513#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__SHIFT 0x12 3514#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__SHIFT 0x13 3515#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__SHIFT 0x14 3516#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__SHIFT 0x18 3517#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__SHIFT 0x19 3518#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__SHIFT 0x1a 3519#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__SHIFT 0x1b 3520//RCC_DEV0_EPF5_STRAP4 3521#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__SHIFT 0x14 3522#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__SHIFT 0x15 3523#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__SHIFT 0x16 3524#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__SHIFT 0x17 3525#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__SHIFT 0x1c 3526#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__SHIFT 0x1f 3527//RCC_DEV0_EPF5_STRAP5 3528#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__SHIFT 0x0 3529//RCC_DEV0_EPF5_STRAP6 3530#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__SHIFT 0x0 3531#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x1 3532#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__SHIFT 0x4 3533#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__SHIFT 0x8 3534#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x9 3535#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__SHIFT 0x10 3536#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__SHIFT 0x11 3537//RCC_DEV0_EPF5_STRAP13 3538#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__SHIFT 0x0 3539#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__SHIFT 0x8 3540#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__SHIFT 0x10 3541//RCC_DEV0_EPF6_STRAP0 3542#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__SHIFT 0x0 3543#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__SHIFT 0x10 3544#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__SHIFT 0x14 3545#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__SHIFT 0x1c 3546#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__SHIFT 0x1d 3547#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__SHIFT 0x1e 3548#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__SHIFT 0x1f 3549//RCC_DEV0_EPF6_STRAP2 3550#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__SHIFT 0x7 3551#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__SHIFT 0x8 3552#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__SHIFT 0xe 3553#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__SHIFT 0x10 3554#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__SHIFT 0x11 3555#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__SHIFT 0x14 3556#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__SHIFT 0x15 3557#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__SHIFT 0x17 3558#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__SHIFT 0x18 3559//RCC_DEV0_EPF6_STRAP3 3560#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__SHIFT 0x0 3561#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__SHIFT 0x1 3562#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__SHIFT 0x2 3563#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__SHIFT 0x12 3564#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__SHIFT 0x13 3565#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__SHIFT 0x14 3566#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__SHIFT 0x18 3567#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__SHIFT 0x19 3568#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__SHIFT 0x1a 3569#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__SHIFT 0x1b 3570//RCC_DEV0_EPF6_STRAP4 3571#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__SHIFT 0x14 3572#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__SHIFT 0x15 3573#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__SHIFT 0x16 3574#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__SHIFT 0x17 3575#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__SHIFT 0x1c 3576#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__SHIFT 0x1f 3577//RCC_DEV0_EPF6_STRAP5 3578#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__SHIFT 0x0 3579//RCC_DEV0_EPF6_STRAP6 3580#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__SHIFT 0x0 3581#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x1 3582#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__SHIFT 0x4 3583#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__SHIFT 0x8 3584#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x9 3585#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__SHIFT 0x10 3586#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__SHIFT 0x11 3587//RCC_DEV0_EPF6_STRAP13 3588#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__SHIFT 0x0 3589#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__SHIFT 0x8 3590#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__SHIFT 0x10 3591//RCC_DEV0_EPF7_STRAP0 3592#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__SHIFT 0x0 3593#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__SHIFT 0x10 3594#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__SHIFT 0x14 3595#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__SHIFT 0x1c 3596#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__SHIFT 0x1d 3597#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__SHIFT 0x1e 3598#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__SHIFT 0x1f 3599//RCC_DEV0_EPF7_STRAP2 3600#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__SHIFT 0x7 3601#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__SHIFT 0x8 3602#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__SHIFT 0xe 3603#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__SHIFT 0x10 3604#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__SHIFT 0x11 3605#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__SHIFT 0x14 3606#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__SHIFT 0x15 3607#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__SHIFT 0x17 3608#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__SHIFT 0x18 3609//RCC_DEV0_EPF7_STRAP3 3610#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__SHIFT 0x0 3611#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__SHIFT 0x1 3612#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__SHIFT 0x2 3613#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__SHIFT 0x12 3614#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__SHIFT 0x13 3615#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__SHIFT 0x14 3616#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__SHIFT 0x18 3617#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__SHIFT 0x19 3618#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__SHIFT 0x1a 3619#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__SHIFT 0x1b 3620//RCC_DEV0_EPF7_STRAP4 3621#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__SHIFT 0x14 3622#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__SHIFT 0x15 3623#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__SHIFT 0x16 3624#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__SHIFT 0x17 3625#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__SHIFT 0x1c 3626#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__SHIFT 0x1f 3627//RCC_DEV0_EPF7_STRAP5 3628#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__SHIFT 0x0 3629//RCC_DEV0_EPF7_STRAP6 3630#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__SHIFT 0x0 3631#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x1 3632#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__SHIFT 0x4 3633#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__SHIFT 0x8 3634#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x9 3635#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__SHIFT 0x10 3636#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__SHIFT 0x11 3637//RCC_DEV0_EPF7_STRAP13 3638#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__SHIFT 0x0 3639#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__SHIFT 0x8 3640#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__SHIFT 0x10 3641//RCC_DEV1_EPF0_STRAP0 3642#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__SHIFT 0x0 3643#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__SHIFT 0x10 3644#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__SHIFT 0x14 3645#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__SHIFT 0x1c 3646#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__SHIFT 0x1d 3647#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__SHIFT 0x1e 3648#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__SHIFT 0x1f 3649//RCC_DEV1_EPF0_STRAP2 3650#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__SHIFT 0x7 3651#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__SHIFT 0x8 3652#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__SHIFT 0xe 3653#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__SHIFT 0xf 3654#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__SHIFT 0x10 3655#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__SHIFT 0x11 3656#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__SHIFT 0x14 3657#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__SHIFT 0x15 3658#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__SHIFT 0x17 3659#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__SHIFT 0x18 3660//RCC_DEV1_EPF0_STRAP3 3661#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__SHIFT 0x0 3662#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__SHIFT 0x1 3663#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__SHIFT 0x2 3664#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__SHIFT 0x12 3665#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__SHIFT 0x13 3666#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__SHIFT 0x14 3667#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__SHIFT 0x18 3668#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__SHIFT 0x19 3669#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__SHIFT 0x1a 3670#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__SHIFT 0x1b 3671//RCC_DEV1_EPF0_STRAP4 3672#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__SHIFT 0x14 3673#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__SHIFT 0x15 3674#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__SHIFT 0x16 3675#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__SHIFT 0x17 3676#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__SHIFT 0x1c 3677#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__SHIFT 0x1f 3678//RCC_DEV1_EPF0_STRAP5 3679#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__SHIFT 0x0 3680#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__SHIFT 0x18 3681//RCC_DEV1_EPF0_STRAP6 3682#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__SHIFT 0x0 3683#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__SHIFT 0x1 3684#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__SHIFT 0x4 3685//RCC_DEV1_EPF0_STRAP13 3686#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__SHIFT 0x0 3687#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__SHIFT 0x8 3688#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__SHIFT 0x10 3689//RCC_DEV1_EPF1_STRAP0 3690#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__SHIFT 0x0 3691#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__SHIFT 0x10 3692#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__SHIFT 0x14 3693#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__SHIFT 0x1c 3694#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__SHIFT 0x1d 3695#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__SHIFT 0x1e 3696#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__SHIFT 0x1f 3697//RCC_DEV1_EPF1_STRAP2 3698#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__SHIFT 0x7 3699#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__SHIFT 0x8 3700#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__SHIFT 0xe 3701#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__SHIFT 0x10 3702#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__SHIFT 0x11 3703#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__SHIFT 0x14 3704#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__SHIFT 0x15 3705#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__SHIFT 0x17 3706#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__SHIFT 0x18 3707//RCC_DEV1_EPF1_STRAP3 3708#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__SHIFT 0x0 3709#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__SHIFT 0x1 3710#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__SHIFT 0x2 3711#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__SHIFT 0x12 3712#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__SHIFT 0x13 3713#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__SHIFT 0x14 3714#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__SHIFT 0x18 3715#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__SHIFT 0x19 3716#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__SHIFT 0x1a 3717#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__SHIFT 0x1b 3718//RCC_DEV1_EPF1_STRAP4 3719#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__SHIFT 0x14 3720#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__SHIFT 0x15 3721#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__SHIFT 0x16 3722#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__SHIFT 0x17 3723#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__SHIFT 0x1c 3724#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__SHIFT 0x1f 3725//RCC_DEV1_EPF1_STRAP5 3726#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__SHIFT 0x0 3727//RCC_DEV1_EPF1_STRAP6 3728#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__SHIFT 0x0 3729#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x1 3730#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__SHIFT 0x4 3731#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__SHIFT 0x8 3732#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x9 3733#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__SHIFT 0x10 3734#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x11 3735#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__SHIFT 0x18 3736#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__SHIFT 0x19 3737//RCC_DEV1_EPF1_STRAP13 3738#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__SHIFT 0x0 3739#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__SHIFT 0x8 3740#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__SHIFT 0x10 3741//RCC_DEV1_EPF2_STRAP0 3742#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__SHIFT 0x0 3743#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__SHIFT 0x10 3744#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__SHIFT 0x14 3745#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__SHIFT 0x1c 3746#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__SHIFT 0x1d 3747#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__SHIFT 0x1e 3748#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__SHIFT 0x1f 3749//RCC_DEV1_EPF2_STRAP2 3750#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__SHIFT 0x7 3751#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__SHIFT 0x8 3752#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__SHIFT 0xe 3753#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__SHIFT 0x10 3754#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__SHIFT 0x11 3755#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__SHIFT 0x14 3756#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__SHIFT 0x15 3757#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__SHIFT 0x17 3758#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__SHIFT 0x18 3759//RCC_DEV1_EPF2_STRAP3 3760#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__SHIFT 0x0 3761#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__SHIFT 0x1 3762#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__SHIFT 0x2 3763#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__SHIFT 0x12 3764#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__SHIFT 0x13 3765#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__SHIFT 0x14 3766#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__SHIFT 0x18 3767#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__SHIFT 0x19 3768#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__SHIFT 0x1a 3769#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__SHIFT 0x1b 3770//RCC_DEV1_EPF2_STRAP4 3771#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__SHIFT 0x14 3772#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__SHIFT 0x15 3773#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__SHIFT 0x16 3774#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__SHIFT 0x17 3775#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__SHIFT 0x1c 3776#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__SHIFT 0x1f 3777//RCC_DEV1_EPF2_STRAP5 3778#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__SHIFT 0x0 3779//RCC_DEV1_EPF2_STRAP6 3780#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__SHIFT 0x0 3781#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x1 3782#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__SHIFT 0x4 3783#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__SHIFT 0x8 3784#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x9 3785#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__SHIFT 0x10 3786#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x11 3787#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__SHIFT 0x18 3788#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__SHIFT 0x19 3789//RCC_DEV1_EPF2_STRAP13 3790#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__SHIFT 0x0 3791#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__SHIFT 0x8 3792#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__SHIFT 0x10 3793 3794 3795// addressBlock: bif_rst_bif_rst_regblk 3796//HARD_RST_CTRL 3797#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 3798#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 3799#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 3800#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 3801#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 3802#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 3803#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 3804#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 3805#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c 3806#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d 3807#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e 3808#define HARD_RST_CTRL__CORE_RST_EN__SHIFT 0x1f 3809//RSMU_SOFT_RST_CTRL 3810#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__SHIFT 0x0 3811#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT 0x1 3812#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__SHIFT 0x2 3813#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT 0x3 3814#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__SHIFT 0x4 3815#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT 0x5 3816#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__SHIFT 0x6 3817#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT 0x7 3818#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT 0x1c 3819#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__SHIFT 0x1d 3820#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__SHIFT 0x1e 3821#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__SHIFT 0x1f 3822//SELF_SOFT_RST 3823#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT 0x0 3824#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT 0x1 3825#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT 0x2 3826#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT 0x3 3827#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT 0x4 3828#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT 0x5 3829#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT 0x6 3830#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT 0x7 3831#define SELF_SOFT_RST__SDP_PORT_RST__SHIFT 0x1b 3832#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT 0x1c 3833#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT 0x1d 3834#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT 0x1e 3835#define SELF_SOFT_RST__CORE_RST__SHIFT 0x1f 3836//GFX_DRV_MODE1_RST_CTRL 3837#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__SHIFT 0x0 3838#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT 0x1 3839#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT 0x2 3840#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__SHIFT 0x3 3841#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT 0x4 3842#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__SHIFT 0x5 3843#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT 0x6 3844#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__SHIFT 0x7 3845//BIF_RST_MISC_CTRL 3846#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT 0x0 3847#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT 0x2 3848#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT 0x4 3849#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT 0x5 3850#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT 0x6 3851#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT 0x8 3852#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT 0x9 3853#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT 0xa 3854#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT 0xd 3855#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT 0xf 3856#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT 0x11 3857#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT 0x17 3858#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT 0x18 3859//BIF_RST_MISC_CTRL2 3860#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT 0x10 3861#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT 0x11 3862#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT 0x12 3863#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT 0x1f 3864//BIF_RST_MISC_CTRL3 3865#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT 0x0 3866#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT 0x4 3867#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT 0x6 3868#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT 0x7 3869#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT 0xa 3870#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT 0xd 3871//BIF_RST_GFXVF_FLR_IDLE 3872#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__SHIFT 0x0 3873#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__SHIFT 0x1 3874#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__SHIFT 0x2 3875#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__SHIFT 0x3 3876#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__SHIFT 0x4 3877#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__SHIFT 0x5 3878#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__SHIFT 0x6 3879#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__SHIFT 0x7 3880#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__SHIFT 0x8 3881#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__SHIFT 0x9 3882#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__SHIFT 0xa 3883#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__SHIFT 0xb 3884#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__SHIFT 0xc 3885#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__SHIFT 0xd 3886#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__SHIFT 0xe 3887#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__SHIFT 0xf 3888#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT 0x1f 3889//DEV0_PF0_FLR_RST_CTRL 3890#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3891#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3892#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3893#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3894#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3895#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__SHIFT 0x5 3896#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__SHIFT 0x6 3897#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__SHIFT 0x7 3898#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT 0x8 3899#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT 0x9 3900#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT 0xa 3901#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT 0xb 3902#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT 0xc 3903#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__SHIFT 0xd 3904#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__SHIFT 0xe 3905#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__SHIFT 0xf 3906#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT 0x10 3907#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3908#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3909#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3910#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3911//DEV0_PF1_FLR_RST_CTRL 3912#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3913#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3914#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3915#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3916#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3917#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3918#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3919#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3920#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3921//DEV0_PF2_FLR_RST_CTRL 3922#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3923#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3924#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3925#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3926#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3927#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3928#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3929#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3930#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3931//DEV0_PF3_FLR_RST_CTRL 3932#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3933#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3934#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3935#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3936#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3937#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3938#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3939#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3940#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3941//DEV0_PF4_FLR_RST_CTRL 3942#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3943#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3944#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3945#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3946#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3947#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3948#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3949#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3950#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3951//DEV0_PF5_FLR_RST_CTRL 3952#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3953#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3954#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3955#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3956#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3957#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3958#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3959#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3960#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3961//DEV0_PF6_FLR_RST_CTRL 3962#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3963#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3964#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3965#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3966#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3967#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3968#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3969#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3970#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3971//DEV0_PF7_FLR_RST_CTRL 3972#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__SHIFT 0x0 3973#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 3974#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 3975#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__SHIFT 0x3 3976#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 3977#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT 0x11 3978#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT 0x12 3979#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT 0x17 3980#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT 0x19 3981//BIF_INST_RESET_INTR_STS 3982#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT 0x0 3983#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT 0x1 3984#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT 0x2 3985#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT 0x3 3986#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT 0x4 3987//BIF_PF_FLR_INTR_STS 3988#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT 0x0 3989#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT 0x1 3990#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__SHIFT 0x2 3991#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__SHIFT 0x3 3992#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__SHIFT 0x4 3993#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__SHIFT 0x5 3994#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__SHIFT 0x6 3995#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__SHIFT 0x7 3996//BIF_D3HOTD0_INTR_STS 3997#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT 0x0 3998#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT 0x1 3999#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__SHIFT 0x2 4000#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__SHIFT 0x3 4001#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__SHIFT 0x4 4002#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__SHIFT 0x5 4003#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__SHIFT 0x6 4004#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__SHIFT 0x7 4005//BIF_POWER_INTR_STS 4006#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT 0x0 4007#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT 0x10 4008//BIF_PF_DSTATE_INTR_STS 4009#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT 0x0 4010#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT 0x1 4011#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT 0x2 4012#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT 0x3 4013#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT 0x4 4014#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT 0x5 4015#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT 0x6 4016#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT 0x7 4017//BIF_PF0_VF_FLR_INTR_STS 4018#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__SHIFT 0x0 4019#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__SHIFT 0x1 4020#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__SHIFT 0x2 4021#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__SHIFT 0x3 4022#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__SHIFT 0x4 4023#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__SHIFT 0x5 4024#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__SHIFT 0x6 4025#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__SHIFT 0x7 4026#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__SHIFT 0x8 4027#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__SHIFT 0x9 4028#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__SHIFT 0xa 4029#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__SHIFT 0xb 4030#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__SHIFT 0xc 4031#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__SHIFT 0xd 4032#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__SHIFT 0xe 4033#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__SHIFT 0xf 4034#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__SHIFT 0x1f 4035//BIF_INST_RESET_INTR_MASK 4036#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT 0x0 4037#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT 0x1 4038#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT 0x2 4039#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT 0x3 4040#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT 0x4 4041//BIF_PF_FLR_INTR_MASK 4042#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT 0x0 4043#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT 0x1 4044#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__SHIFT 0x2 4045#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__SHIFT 0x3 4046#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__SHIFT 0x4 4047#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__SHIFT 0x5 4048#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__SHIFT 0x6 4049#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__SHIFT 0x7 4050//BIF_D3HOTD0_INTR_MASK 4051#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT 0x0 4052#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT 0x1 4053#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__SHIFT 0x2 4054#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__SHIFT 0x3 4055#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__SHIFT 0x4 4056#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__SHIFT 0x5 4057#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__SHIFT 0x6 4058#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__SHIFT 0x7 4059//BIF_POWER_INTR_MASK 4060#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT 0x0 4061#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT 0x10 4062//BIF_PF_DSTATE_INTR_MASK 4063#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT 0x0 4064#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT 0x1 4065#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT 0x2 4066#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT 0x3 4067#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT 0x4 4068#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT 0x5 4069#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT 0x6 4070#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT 0x7 4071//BIF_PF0_VF_FLR_INTR_MASK 4072#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__SHIFT 0x0 4073#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__SHIFT 0x1 4074#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__SHIFT 0x2 4075#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__SHIFT 0x3 4076#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__SHIFT 0x4 4077#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__SHIFT 0x5 4078#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__SHIFT 0x6 4079#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__SHIFT 0x7 4080#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__SHIFT 0x8 4081#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__SHIFT 0x9 4082#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__SHIFT 0xa 4083#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__SHIFT 0xb 4084#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__SHIFT 0xc 4085#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__SHIFT 0xd 4086#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__SHIFT 0xe 4087#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__SHIFT 0xf 4088#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__SHIFT 0x1f 4089//BIF_PF_FLR_RST 4090#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT 0x0 4091#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT 0x1 4092#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__SHIFT 0x2 4093#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__SHIFT 0x3 4094#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__SHIFT 0x4 4095#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__SHIFT 0x5 4096#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__SHIFT 0x6 4097#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__SHIFT 0x7 4098//BIF_PF0_VF_FLR_RST 4099#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__SHIFT 0x0 4100#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__SHIFT 0x1 4101#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__SHIFT 0x2 4102#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__SHIFT 0x3 4103#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__SHIFT 0x4 4104#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__SHIFT 0x5 4105#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__SHIFT 0x6 4106#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__SHIFT 0x7 4107#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__SHIFT 0x8 4108#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__SHIFT 0x9 4109#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__SHIFT 0xa 4110#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__SHIFT 0xb 4111#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__SHIFT 0xc 4112#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__SHIFT 0xd 4113#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__SHIFT 0xe 4114#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__SHIFT 0xf 4115#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__SHIFT 0x1f 4116//BIF_DEV0_PF0_DSTATE_VALUE 4117#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT 0x0 4118#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4119#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT 0x10 4120//BIF_DEV0_PF1_DSTATE_VALUE 4121#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT 0x0 4122#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4123#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT 0x10 4124//BIF_DEV0_PF2_DSTATE_VALUE 4125#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__SHIFT 0x0 4126#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4127#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__SHIFT 0x10 4128//BIF_DEV0_PF3_DSTATE_VALUE 4129#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__SHIFT 0x0 4130#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4131#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__SHIFT 0x10 4132//BIF_DEV0_PF4_DSTATE_VALUE 4133#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__SHIFT 0x0 4134#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4135#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__SHIFT 0x10 4136//BIF_DEV0_PF5_DSTATE_VALUE 4137#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__SHIFT 0x0 4138#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4139#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__SHIFT 0x10 4140//BIF_DEV0_PF6_DSTATE_VALUE 4141#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__SHIFT 0x0 4142#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4143#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__SHIFT 0x10 4144//BIF_DEV0_PF7_DSTATE_VALUE 4145#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__SHIFT 0x0 4146#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__SHIFT 0x2 4147#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__SHIFT 0x10 4148//DEV0_PF0_D3HOTD0_RST_CTRL 4149#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4150#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4151#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4152#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4153#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4154//DEV0_PF1_D3HOTD0_RST_CTRL 4155#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4156#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4157#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4158#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4159#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4160//DEV0_PF2_D3HOTD0_RST_CTRL 4161#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4162#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4163#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4164#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4165#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4166//DEV0_PF3_D3HOTD0_RST_CTRL 4167#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4168#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4169#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4170#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4171#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4172//DEV0_PF4_D3HOTD0_RST_CTRL 4173#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4174#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4175#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4176#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4177#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4178//DEV0_PF5_D3HOTD0_RST_CTRL 4179#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4180#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4181#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4182#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4183#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4184//DEV0_PF6_D3HOTD0_RST_CTRL 4185#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4186#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4187#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4188#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4189#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4190//DEV0_PF7_D3HOTD0_RST_CTRL 4191#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT 0x0 4192#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT 0x1 4193#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT 0x2 4194#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT 0x3 4195#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT 0x4 4196//BIF_PORT0_DSTATE_VALUE 4197#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT 0x0 4198#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT 0x10 4199 4200 4201// addressBlock: bif_misc_bif_misc_regblk 4202//MISC_SCRATCH 4203#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT 0x0 4204//INTR_LINE_POLARITY 4205#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT 0x0 4206//INTR_LINE_ENABLE 4207#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT 0x0 4208//OUTSTANDING_VC_ALLOC 4209#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT 0x0 4210#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT 0x2 4211#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT 0x4 4212#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT 0x6 4213#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT 0x8 4214#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT 0xa 4215#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT 0xc 4216#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT 0xe 4217#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT 0x10 4218#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT 0x18 4219#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT 0x1a 4220#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT 0x1c 4221//BIFC_MISC_CTRL0 4222#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT 0x0 4223#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT 0x1 4224#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT 0x8 4225#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__SHIFT 0x9 4226#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT 0xa 4227#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT 0x10 4228#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT 0x11 4229#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT 0x18 4230#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT 0x19 4231#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT 0x1a 4232#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT 0x1b 4233#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT 0x1c 4234#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT 0x1f 4235//BIFC_MISC_CTRL1 4236#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT 0x0 4237#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT 0x1 4238#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT 0x2 4239#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT 0x3 4240#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT 0x4 4241#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT 0x5 4242#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT 0x6 4243#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT 0x7 4244#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT 0x8 4245#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT 0xa 4246#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT 0xc 4247#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT 0xd 4248#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT 0xe 4249#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT 0xf 4250#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT 0x10 4251#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT 0x11 4252#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT 0x12 4253#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT 0x13 4254//BIFC_BME_ERR_LOG 4255#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x0 4256#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x1 4257#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x2 4258#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x3 4259#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x4 4260#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x5 4261#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x6 4262#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x7 4263#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT 0x10 4264#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT 0x11 4265#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__SHIFT 0x12 4266#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__SHIFT 0x13 4267#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__SHIFT 0x14 4268#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__SHIFT 0x15 4269#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__SHIFT 0x16 4270#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__SHIFT 0x17 4271//BIFC_RCCBIH_BME_ERR_LOG 4272#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x0 4273#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x1 4274#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x2 4275#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x3 4276#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x4 4277#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x5 4278#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x6 4279#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x7 4280#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT 0x10 4281#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT 0x11 4282#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__SHIFT 0x12 4283#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__SHIFT 0x13 4284#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__SHIFT 0x14 4285#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__SHIFT 0x15 4286#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__SHIFT 0x16 4287#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__SHIFT 0x17 4288//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 4289#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT 0x0 4290#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT 0x2 4291#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT 0x6 4292#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT 0x8 4293#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT 0xa 4294#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT 0xc 4295#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT 0x10 4296#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT 0x12 4297#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT 0x16 4298#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT 0x18 4299#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT 0x1a 4300#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT 0x1c 4301//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 4302#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT 0x0 4303#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT 0x2 4304#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT 0x6 4305#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT 0x8 4306#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT 0xa 4307#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT 0xc 4308#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT 0x10 4309#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT 0x12 4310#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT 0x16 4311#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT 0x18 4312#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT 0x1a 4313#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT 0x1c 4314//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 4315#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT 0x0 4316#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT 0x2 4317#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT 0x6 4318#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT 0x8 4319#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT 0xa 4320#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT 0xc 4321#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT 0x10 4322#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT 0x12 4323#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT 0x16 4324#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT 0x18 4325#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT 0x1a 4326#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT 0x1c 4327//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 4328#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT 0x0 4329#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT 0x2 4330#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT 0x6 4331#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT 0x8 4332#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT 0xa 4333#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT 0xc 4334#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT 0x10 4335#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT 0x12 4336#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT 0x16 4337#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT 0x18 4338#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT 0x1a 4339#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT 0x1c 4340//NBIF_VWIRE_CTRL 4341#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT 0x4 4342#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT 0x8 4343#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT 0x14 4344#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT 0x1a 4345//NBIF_SMN_VWR_VCHG_DIS_CTRL 4346#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__SHIFT 0x0 4347#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__SHIFT 0x1 4348#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__SHIFT 0x2 4349#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__SHIFT 0x3 4350#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__SHIFT 0x4 4351#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__SHIFT 0x5 4352#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__SHIFT 0x6 4353//NBIF_SMN_VWR_VCHG_RST_CTRL0 4354#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__SHIFT 0x0 4355#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__SHIFT 0x1 4356#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__SHIFT 0x2 4357#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__SHIFT 0x3 4358#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__SHIFT 0x4 4359#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__SHIFT 0x5 4360#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__SHIFT 0x6 4361//NBIF_SMN_VWR_VCHG_TRIG 4362#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__SHIFT 0x0 4363#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__SHIFT 0x1 4364#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__SHIFT 0x2 4365#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__SHIFT 0x3 4366#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__SHIFT 0x4 4367#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__SHIFT 0x5 4368#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__SHIFT 0x6 4369//NBIF_SMN_VWR_WTRIG_CNTL 4370#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__SHIFT 0x0 4371#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__SHIFT 0x1 4372#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__SHIFT 0x2 4373#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__SHIFT 0x3 4374#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__SHIFT 0x4 4375#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__SHIFT 0x5 4376#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__SHIFT 0x6 4377//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 4378#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__SHIFT 0x0 4379#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__SHIFT 0x1 4380#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__SHIFT 0x2 4381#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__SHIFT 0x3 4382#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__SHIFT 0x4 4383#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__SHIFT 0x5 4384#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__SHIFT 0x6 4385//NBIF_MGCG_CTRL 4386#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__SHIFT 0x0 4387#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__SHIFT 0x1 4388#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__SHIFT 0x2 4389//NBIF_DS_CTRL_LCLK 4390#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT 0x0 4391#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT 0x10 4392//SMN_MST_CNTL0 4393#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT 0x0 4394#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT 0x8 4395#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT 0x9 4396#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT 0xa 4397#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT 0xb 4398#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT 0x10 4399#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT 0x14 4400#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT 0x18 4401#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT 0x1c 4402//SMN_MST_EP_CNTL1 4403#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT 0x0 4404#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT 0x1 4405#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT 0x2 4406#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT 0x3 4407#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT 0x4 4408#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT 0x5 4409#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT 0x6 4410#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT 0x7 4411//SMN_MST_EP_CNTL2 4412#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT 0x0 4413#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT 0x1 4414#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT 0x2 4415#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT 0x3 4416#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT 0x4 4417#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT 0x5 4418#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT 0x6 4419#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT 0x7 4420//NBIF_SDP_VWR_VCHG_DIS_CTRL 4421#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT 0x0 4422#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT 0x1 4423#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT 0x2 4424#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT 0x3 4425#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT 0x4 4426#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT 0x5 4427#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT 0x6 4428#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT 0x7 4429#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT 0x18 4430//NBIF_SDP_VWR_VCHG_RST_CTRL0 4431#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT 0x0 4432#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT 0x1 4433#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT 0x2 4434#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT 0x3 4435#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT 0x4 4436#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT 0x5 4437#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT 0x6 4438#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT 0x7 4439#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT 0x18 4440//NBIF_SDP_VWR_VCHG_RST_CTRL1 4441#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT 0x0 4442#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT 0x1 4443#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT 0x2 4444#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT 0x3 4445#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT 0x4 4446#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT 0x5 4447#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT 0x6 4448#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT 0x7 4449#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT 0x18 4450//NBIF_SDP_VWR_VCHG_TRIG 4451#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT 0x0 4452#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT 0x1 4453#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT 0x2 4454#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT 0x3 4455#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT 0x4 4456#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT 0x5 4457#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT 0x6 4458#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT 0x7 4459#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT 0x18 4460//BME_DUMMY_CNTL_0 4461#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT 0x0 4462#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT 0x2 4463#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT 0x4 4464#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT 0x6 4465#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT 0x8 4466#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT 0xa 4467#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT 0xc 4468#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT 0xe 4469//BIFC_THT_CNTL 4470#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT 0x0 4471#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT 0x4 4472#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT 0x8 4473//BIFC_HSTARB_CNTL 4474#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT 0x0 4475//BIFC_GSI_CNTL 4476#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT 0x0 4477#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT 0x2 4478#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT 0x5 4479#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT 0x6 4480#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT 0x7 4481#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT 0x8 4482#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT 0x9 4483#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT 0xa 4484#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT 0xc 4485//BIFC_PCIEFUNC_CNTL 4486#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT 0x0 4487#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT 0x10 4488//BIFC_SDP_CNTL_0 4489#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT 0x0 4490#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT 0x6 4491#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT 0xc 4492#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT 0x12 4493//BIFC_PERF_CNTL_0 4494#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT 0x0 4495#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT 0x1 4496#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT 0x8 4497#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT 0x9 4498#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT 0x10 4499#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT 0x18 4500//BIFC_PERF_CNTL_1 4501#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT 0x0 4502#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT 0x1 4503#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT 0x8 4504#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT 0x9 4505#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT 0x10 4506#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT 0x18 4507//BIFC_PERF_CNT_MMIO_RD 4508#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__SHIFT 0x0 4509//BIFC_PERF_CNT_MMIO_WR 4510#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__SHIFT 0x0 4511//BIFC_PERF_CNT_DMA_RD 4512#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__SHIFT 0x0 4513//BIFC_PERF_CNT_DMA_WR 4514#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__SHIFT 0x0 4515//NBIF_REGIF_ERRSET_CTRL 4516#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT 0x0 4517//SMN_MST_EP_CNTL3 4518#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT 0x0 4519#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT 0x1 4520#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT 0x2 4521#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT 0x3 4522#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT 0x4 4523#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT 0x5 4524#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT 0x6 4525#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT 0x7 4526//SMN_MST_EP_CNTL4 4527#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT 0x0 4528#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT 0x1 4529#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT 0x2 4530#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT 0x3 4531#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT 0x4 4532#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT 0x5 4533#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT 0x6 4534#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT 0x7 4535//BIF_SELFRING_BUFFER_VID 4536#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT 0x0 4537#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__SHIFT 0x8 4538//BIF_SELFRING_VECTOR_CNTL 4539#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT 0x0 4540 4541 4542// addressBlock: bif_ras_bif_ras_regblk 4543//BIF_RAS_LEAF0_CTRL 4544#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__SHIFT 0x0 4545#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4546#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT 0x2 4547#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__SHIFT 0x4 4548#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4549#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT 0x6 4550#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4551#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__SHIFT 0x11 4552#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__SHIFT 0x12 4553#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__SHIFT 0x13 4554#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4555#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__SHIFT 0x15 4556//BIF_RAS_LEAF1_CTRL 4557#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__SHIFT 0x0 4558#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4559#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT 0x2 4560#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__SHIFT 0x4 4561#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4562#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT 0x6 4563#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4564#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__SHIFT 0x11 4565#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__SHIFT 0x12 4566#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__SHIFT 0x13 4567#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4568#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__SHIFT 0x15 4569//BIF_RAS_LEAF2_CTRL 4570#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__SHIFT 0x0 4571#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT 0x1 4572#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT 0x2 4573#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__SHIFT 0x4 4574#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT 0x5 4575#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT 0x6 4576#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__SHIFT 0x10 4577#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__SHIFT 0x11 4578#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__SHIFT 0x12 4579#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__SHIFT 0x13 4580#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__SHIFT 0x14 4581#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__SHIFT 0x15 4582//BIF_RAS_MISC_CTRL 4583#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__SHIFT 0x0 4584//BIF_IOHUB_RAS_IH_CNTL 4585#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__SHIFT 0x0 4586//BIF_RAS_VWR_FROM_IOHUB 4587#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__SHIFT 0x0 4588 4589 4590// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC 4591//RCC_PFC_LTR_CNTL 4592#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 4593#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa 4594#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf 4595#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 4596#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a 4597#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f 4598//RCC_PFC_PME_RESTORE 4599#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 4600#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 4601//RCC_PFC_STICKY_RESTORE_0 4602#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 4603#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 4604#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 4605#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 4606#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 4607#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 4608#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 4609#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 4610//RCC_PFC_STICKY_RESTORE_1 4611#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 4612//RCC_PFC_STICKY_RESTORE_2 4613#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 4614//RCC_PFC_STICKY_RESTORE_3 4615#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 4616//RCC_PFC_STICKY_RESTORE_4 4617#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 4618//RCC_PFC_STICKY_RESTORE_5 4619#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 4620//RCC_PFC_AUXPWR_CNTL 4621#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 4622#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 4623 4624 4625// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC 4626//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 4627#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT 0x0 4628#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT 0xa 4629#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT 0xf 4630#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT 0x10 4631#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT 0x1a 4632#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT 0x1f 4633//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 4634#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT 0x0 4635#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT 0x8 4636//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 4637#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT 0x0 4638#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT 0x1 4639#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT 0x2 4640#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT 0x3 4641#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT 0x4 4642#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT 0x5 4643#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT 0x6 4644#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT 0x7 4645//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 4646#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT 0x0 4647//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 4648#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT 0x0 4649//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 4650#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT 0x0 4651//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 4652#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT 0x0 4653//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 4654#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT 0x0 4655//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 4656#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT 0x0 4657#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT 0x3 4658 4659 4660// addressBlock: pciemsix_amdgfx_MSIXTDEC 4661//PCIEMSIX_VECT0_ADDR_LO 4662#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4663//PCIEMSIX_VECT0_ADDR_HI 4664#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4665//PCIEMSIX_VECT0_MSG_DATA 4666#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT 0x0 4667//PCIEMSIX_VECT0_CONTROL 4668#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__SHIFT 0x0 4669//PCIEMSIX_VECT1_ADDR_LO 4670#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4671//PCIEMSIX_VECT1_ADDR_HI 4672#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4673//PCIEMSIX_VECT1_MSG_DATA 4674#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT 0x0 4675//PCIEMSIX_VECT1_CONTROL 4676#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__SHIFT 0x0 4677//PCIEMSIX_VECT2_ADDR_LO 4678#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4679//PCIEMSIX_VECT2_ADDR_HI 4680#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4681//PCIEMSIX_VECT2_MSG_DATA 4682#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT 0x0 4683//PCIEMSIX_VECT2_CONTROL 4684#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__SHIFT 0x0 4685//PCIEMSIX_VECT3_ADDR_LO 4686#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4687//PCIEMSIX_VECT3_ADDR_HI 4688#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4689//PCIEMSIX_VECT3_MSG_DATA 4690#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT 0x0 4691//PCIEMSIX_VECT3_CONTROL 4692#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__SHIFT 0x0 4693//PCIEMSIX_VECT4_ADDR_LO 4694#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4695//PCIEMSIX_VECT4_ADDR_HI 4696#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4697//PCIEMSIX_VECT4_MSG_DATA 4698#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT 0x0 4699//PCIEMSIX_VECT4_CONTROL 4700#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__SHIFT 0x0 4701//PCIEMSIX_VECT5_ADDR_LO 4702#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4703//PCIEMSIX_VECT5_ADDR_HI 4704#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4705//PCIEMSIX_VECT5_MSG_DATA 4706#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT 0x0 4707//PCIEMSIX_VECT5_CONTROL 4708#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__SHIFT 0x0 4709//PCIEMSIX_VECT6_ADDR_LO 4710#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4711//PCIEMSIX_VECT6_ADDR_HI 4712#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4713//PCIEMSIX_VECT6_MSG_DATA 4714#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT 0x0 4715//PCIEMSIX_VECT6_CONTROL 4716#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__SHIFT 0x0 4717//PCIEMSIX_VECT7_ADDR_LO 4718#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4719//PCIEMSIX_VECT7_ADDR_HI 4720#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4721//PCIEMSIX_VECT7_MSG_DATA 4722#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT 0x0 4723//PCIEMSIX_VECT7_CONTROL 4724#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__SHIFT 0x0 4725//PCIEMSIX_VECT8_ADDR_LO 4726#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4727//PCIEMSIX_VECT8_ADDR_HI 4728#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4729//PCIEMSIX_VECT8_MSG_DATA 4730#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT 0x0 4731//PCIEMSIX_VECT8_CONTROL 4732#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__SHIFT 0x0 4733//PCIEMSIX_VECT9_ADDR_LO 4734#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4735//PCIEMSIX_VECT9_ADDR_HI 4736#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4737//PCIEMSIX_VECT9_MSG_DATA 4738#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__SHIFT 0x0 4739//PCIEMSIX_VECT9_CONTROL 4740#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__SHIFT 0x0 4741//PCIEMSIX_VECT10_ADDR_LO 4742#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4743//PCIEMSIX_VECT10_ADDR_HI 4744#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4745//PCIEMSIX_VECT10_MSG_DATA 4746#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__SHIFT 0x0 4747//PCIEMSIX_VECT10_CONTROL 4748#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__SHIFT 0x0 4749//PCIEMSIX_VECT11_ADDR_LO 4750#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4751//PCIEMSIX_VECT11_ADDR_HI 4752#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4753//PCIEMSIX_VECT11_MSG_DATA 4754#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__SHIFT 0x0 4755//PCIEMSIX_VECT11_CONTROL 4756#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__SHIFT 0x0 4757//PCIEMSIX_VECT12_ADDR_LO 4758#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4759//PCIEMSIX_VECT12_ADDR_HI 4760#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4761//PCIEMSIX_VECT12_MSG_DATA 4762#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__SHIFT 0x0 4763//PCIEMSIX_VECT12_CONTROL 4764#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__SHIFT 0x0 4765//PCIEMSIX_VECT13_ADDR_LO 4766#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4767//PCIEMSIX_VECT13_ADDR_HI 4768#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4769//PCIEMSIX_VECT13_MSG_DATA 4770#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__SHIFT 0x0 4771//PCIEMSIX_VECT13_CONTROL 4772#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__SHIFT 0x0 4773//PCIEMSIX_VECT14_ADDR_LO 4774#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4775//PCIEMSIX_VECT14_ADDR_HI 4776#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4777//PCIEMSIX_VECT14_MSG_DATA 4778#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__SHIFT 0x0 4779//PCIEMSIX_VECT14_CONTROL 4780#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__SHIFT 0x0 4781//PCIEMSIX_VECT15_ADDR_LO 4782#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4783//PCIEMSIX_VECT15_ADDR_HI 4784#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4785//PCIEMSIX_VECT15_MSG_DATA 4786#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__SHIFT 0x0 4787//PCIEMSIX_VECT15_CONTROL 4788#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__SHIFT 0x0 4789//PCIEMSIX_VECT16_ADDR_LO 4790#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4791//PCIEMSIX_VECT16_ADDR_HI 4792#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4793//PCIEMSIX_VECT16_MSG_DATA 4794#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__SHIFT 0x0 4795//PCIEMSIX_VECT16_CONTROL 4796#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__SHIFT 0x0 4797//PCIEMSIX_VECT17_ADDR_LO 4798#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4799//PCIEMSIX_VECT17_ADDR_HI 4800#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4801//PCIEMSIX_VECT17_MSG_DATA 4802#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__SHIFT 0x0 4803//PCIEMSIX_VECT17_CONTROL 4804#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__SHIFT 0x0 4805//PCIEMSIX_VECT18_ADDR_LO 4806#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4807//PCIEMSIX_VECT18_ADDR_HI 4808#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4809//PCIEMSIX_VECT18_MSG_DATA 4810#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__SHIFT 0x0 4811//PCIEMSIX_VECT18_CONTROL 4812#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__SHIFT 0x0 4813//PCIEMSIX_VECT19_ADDR_LO 4814#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4815//PCIEMSIX_VECT19_ADDR_HI 4816#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4817//PCIEMSIX_VECT19_MSG_DATA 4818#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__SHIFT 0x0 4819//PCIEMSIX_VECT19_CONTROL 4820#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__SHIFT 0x0 4821//PCIEMSIX_VECT20_ADDR_LO 4822#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4823//PCIEMSIX_VECT20_ADDR_HI 4824#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4825//PCIEMSIX_VECT20_MSG_DATA 4826#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__SHIFT 0x0 4827//PCIEMSIX_VECT20_CONTROL 4828#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__SHIFT 0x0 4829//PCIEMSIX_VECT21_ADDR_LO 4830#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4831//PCIEMSIX_VECT21_ADDR_HI 4832#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4833//PCIEMSIX_VECT21_MSG_DATA 4834#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__SHIFT 0x0 4835//PCIEMSIX_VECT21_CONTROL 4836#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__SHIFT 0x0 4837//PCIEMSIX_VECT22_ADDR_LO 4838#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4839//PCIEMSIX_VECT22_ADDR_HI 4840#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4841//PCIEMSIX_VECT22_MSG_DATA 4842#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__SHIFT 0x0 4843//PCIEMSIX_VECT22_CONTROL 4844#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__SHIFT 0x0 4845//PCIEMSIX_VECT23_ADDR_LO 4846#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4847//PCIEMSIX_VECT23_ADDR_HI 4848#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4849//PCIEMSIX_VECT23_MSG_DATA 4850#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__SHIFT 0x0 4851//PCIEMSIX_VECT23_CONTROL 4852#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__SHIFT 0x0 4853//PCIEMSIX_VECT24_ADDR_LO 4854#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4855//PCIEMSIX_VECT24_ADDR_HI 4856#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4857//PCIEMSIX_VECT24_MSG_DATA 4858#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__SHIFT 0x0 4859//PCIEMSIX_VECT24_CONTROL 4860#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__SHIFT 0x0 4861//PCIEMSIX_VECT25_ADDR_LO 4862#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4863//PCIEMSIX_VECT25_ADDR_HI 4864#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4865//PCIEMSIX_VECT25_MSG_DATA 4866#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__SHIFT 0x0 4867//PCIEMSIX_VECT25_CONTROL 4868#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__SHIFT 0x0 4869//PCIEMSIX_VECT26_ADDR_LO 4870#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4871//PCIEMSIX_VECT26_ADDR_HI 4872#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4873//PCIEMSIX_VECT26_MSG_DATA 4874#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__SHIFT 0x0 4875//PCIEMSIX_VECT26_CONTROL 4876#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__SHIFT 0x0 4877//PCIEMSIX_VECT27_ADDR_LO 4878#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4879//PCIEMSIX_VECT27_ADDR_HI 4880#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4881//PCIEMSIX_VECT27_MSG_DATA 4882#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__SHIFT 0x0 4883//PCIEMSIX_VECT27_CONTROL 4884#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__SHIFT 0x0 4885//PCIEMSIX_VECT28_ADDR_LO 4886#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4887//PCIEMSIX_VECT28_ADDR_HI 4888#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4889//PCIEMSIX_VECT28_MSG_DATA 4890#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__SHIFT 0x0 4891//PCIEMSIX_VECT28_CONTROL 4892#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__SHIFT 0x0 4893//PCIEMSIX_VECT29_ADDR_LO 4894#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4895//PCIEMSIX_VECT29_ADDR_HI 4896#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4897//PCIEMSIX_VECT29_MSG_DATA 4898#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__SHIFT 0x0 4899//PCIEMSIX_VECT29_CONTROL 4900#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__SHIFT 0x0 4901//PCIEMSIX_VECT30_ADDR_LO 4902#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4903//PCIEMSIX_VECT30_ADDR_HI 4904#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4905//PCIEMSIX_VECT30_MSG_DATA 4906#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__SHIFT 0x0 4907//PCIEMSIX_VECT30_CONTROL 4908#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__SHIFT 0x0 4909//PCIEMSIX_VECT31_ADDR_LO 4910#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__SHIFT 0x2 4911//PCIEMSIX_VECT31_ADDR_HI 4912#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__SHIFT 0x0 4913//PCIEMSIX_VECT31_MSG_DATA 4914#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__SHIFT 0x0 4915//PCIEMSIX_VECT31_CONTROL 4916#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__SHIFT 0x0 4917 4918 4919// addressBlock: pciemsix_amdgfx_MSIXPDEC 4920//PCIEMSIX_PBA 4921#define PCIEMSIX_PBA__MSIX_PENDING_BITS__SHIFT 0x0 4922 4923 4924// addressBlock: syshub_mmreg_ind_syshubind 4925//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 4926#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 4927#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 4928#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 4929#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 4930#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 4931#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 4932#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 4933#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 4934#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 4935#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 4936#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 4937#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 4938#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 4939#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 4940#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 4941#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 4942#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 4943#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT 0x1f 4944//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 4945#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT 0x0 4946//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 4947#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__SHIFT 0x0 4948#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__SHIFT 0x1 4949#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT 0xf 4950#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT 0x10 4951#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT 0x11 4952//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 4953#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__SHIFT 0x0 4954#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__SHIFT 0x1 4955#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT 0xf 4956#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT 0x10 4957#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT 0x11 4958//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 4959#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 4960#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 4961#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 4962//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 4963#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 4964#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 4965#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 4966//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 4967#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4968#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4969#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4970#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4971#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4972#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4973//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 4974#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4975#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4976#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4977#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4978#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4979#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4980//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 4981#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4982#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4983#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4984#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4985#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4986#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4987//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 4988#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4989#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4990#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4991#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4992#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 4993#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 4994//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 4995#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 4996#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 4997#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 4998#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 4999#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5000#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5001//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 5002#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5003#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5004#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5005#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5006#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5007#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5008//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 5009#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5010#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5011#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5012#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5013#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5014#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5015//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 5016#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5017#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5018#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5019#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5020#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5021#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5022//SYSHUBMMREGIND_SYSHUB_CG_CNTL 5023#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__SHIFT 0x0 5024#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__SHIFT 0x8 5025#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__SHIFT 0x10 5026//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE 5027#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__SHIFT 0x0 5028#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__SHIFT 0x1 5029#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__SHIFT 0x2 5030#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__SHIFT 0x3 5031#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__SHIFT 0x4 5032#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__SHIFT 0x5 5033#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__SHIFT 0x6 5034#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__SHIFT 0x7 5035#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__SHIFT 0x8 5036#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__SHIFT 0x9 5037#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__SHIFT 0xa 5038#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__SHIFT 0xb 5039#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__SHIFT 0xc 5040#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__SHIFT 0xd 5041#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__SHIFT 0xe 5042#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__SHIFT 0xf 5043#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__SHIFT 0x10 5044//SYSHUBMMREGIND_SYSHUB_HP_TIMER 5045#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__SHIFT 0x0 5046//SYSHUBMMREGIND_SYSHUB_SCRATCH 5047#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__SHIFT 0x0 5048//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 5049#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x0 5050#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1 5051#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x2 5052#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x3 5053#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x4 5054#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x5 5055#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x6 5056#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x7 5057#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x10 5058#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x11 5059#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x12 5060#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x13 5061#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x14 5062#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x15 5063#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x16 5064#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x17 5065#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT 0x1c 5066#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__SHIFT 0x1f 5067//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 5068#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__SHIFT 0x0 5069//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 5070#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__SHIFT 0xf 5071#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__SHIFT 0x10 5072//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 5073#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__SHIFT 0xf 5074#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__SHIFT 0x10 5075//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 5076#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 5077#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 5078#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 5079//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 5080#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT 0x0 5081#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT 0x1 5082#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT 0x5 5083//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 5084#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5085#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5086#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5087#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5088#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5089#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5090//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 5091#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5092#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5093#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5094#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5095#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5096#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5097//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 5098#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5099#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5100#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5101#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5102#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5103#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5104//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 5105#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5106#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5107#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5108#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5109#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5110#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5111//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 5112#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5113#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5114#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5115#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5116#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5117#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5118//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 5119#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5120#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5121#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5122#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5123#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5124#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5125//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 5126#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5127#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5128#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5129#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5130#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5131#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5132//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 5133#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5134#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5135#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5136#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5137#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5138#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5139//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 5140#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5141#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5142#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5143#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5144#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5145#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5146//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 5147#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__SHIFT 0x0 5148#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__SHIFT 0x1 5149#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT 0x8 5150#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT 0x9 5151#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__SHIFT 0x10 5152#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__SHIFT 0x18 5153//MASK 5154 5155 5156// addressBlock: bif_cfg_dev0_epf0_bifcfgdecp 5157//VENDOR_ID 5158#define VENDOR_ID__VENDOR_ID__MASK 0xFFFFL 5159//DEVICE_ID 5160#define DEVICE_ID__DEVICE_ID__MASK 0xFFFFL 5161//COMMAND 5162#define COMMAND__IO_ACCESS_EN__MASK 0x0001L 5163#define COMMAND__MEM_ACCESS_EN__MASK 0x0002L 5164#define COMMAND__BUS_MASTER_EN__MASK 0x0004L 5165#define COMMAND__SPECIAL_CYCLE_EN__MASK 0x0008L 5166#define COMMAND__MEM_WRITE_INVALIDATE_EN__MASK 0x0010L 5167#define COMMAND__PAL_SNOOP_EN__MASK 0x0020L 5168#define COMMAND__PARITY_ERROR_RESPONSE__MASK 0x0040L 5169#define COMMAND__AD_STEPPING__MASK 0x0080L 5170#define COMMAND__SERR_EN__MASK 0x0100L 5171#define COMMAND__FAST_B2B_EN__MASK 0x0200L 5172#define COMMAND__INT_DIS__MASK 0x0400L 5173//STATUS 5174#define STATUS__INT_STATUS__MASK 0x0008L 5175#define STATUS__CAP_LIST__MASK 0x0010L 5176#define STATUS__PCI_66_EN__MASK 0x0020L 5177#define STATUS__FAST_BACK_CAPABLE__MASK 0x0080L 5178#define STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L 5179#define STATUS__DEVSEL_TIMING__MASK 0x0600L 5180#define STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L 5181#define STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L 5182#define STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L 5183#define STATUS__SIGNALED_SYSTEM_ERROR__MASK 0x4000L 5184#define STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L 5185//REVISION_ID 5186#define REVISION_ID__MINOR_REV_ID__MASK 0x0FL 5187#define REVISION_ID__MAJOR_REV_ID__MASK 0xF0L 5188//PROG_INTERFACE 5189#define PROG_INTERFACE__PROG_INTERFACE__MASK 0xFFL 5190//SUB_CLASS 5191#define SUB_CLASS__SUB_CLASS__MASK 0xFFL 5192//BASE_CLASS 5193#define BASE_CLASS__BASE_CLASS__MASK 0xFFL 5194//CACHE_LINE 5195#define CACHE_LINE__CACHE_LINE_SIZE__MASK 0xFFL 5196//LATENCY 5197#define LATENCY__LATENCY_TIMER__MASK 0xFFL 5198//HEADER 5199#define HEADER__HEADER_TYPE__MASK 0x7FL 5200#define HEADER__DEVICE_TYPE__MASK 0x80L 5201//BIST 5202#define BIST__BIST_COMP__MASK 0x0FL 5203#define BIST__BIST_STRT__MASK 0x40L 5204#define BIST__BIST_CAP__MASK 0x80L 5205//BASE_ADDR_1 5206#define BASE_ADDR_1__BASE_ADDR__MASK 0xFFFFFFFFL 5207//BASE_ADDR_2 5208#define BASE_ADDR_2__BASE_ADDR__MASK 0xFFFFFFFFL 5209//BASE_ADDR_3 5210#define BASE_ADDR_3__BASE_ADDR__MASK 0xFFFFFFFFL 5211//BASE_ADDR_4 5212#define BASE_ADDR_4__BASE_ADDR__MASK 0xFFFFFFFFL 5213//BASE_ADDR_5 5214#define BASE_ADDR_5__BASE_ADDR__MASK 0xFFFFFFFFL 5215//BASE_ADDR_6 5216#define BASE_ADDR_6__BASE_ADDR__MASK 0xFFFFFFFFL 5217//ADAPTER_ID 5218#define ADAPTER_ID__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 5219#define ADAPTER_ID__SUBSYSTEM_ID__MASK 0xFFFF0000L 5220//ROM_BASE_ADDR 5221#define ROM_BASE_ADDR__BASE_ADDR__MASK 0xFFFFFFFFL 5222//CAP_PTR 5223#define CAP_PTR__CAP_PTR__MASK 0x000000FFL 5224//INTERRUPT_LINE 5225#define INTERRUPT_LINE__INTERRUPT_LINE__MASK 0xFFL 5226//INTERRUPT_PIN 5227#define INTERRUPT_PIN__INTERRUPT_PIN__MASK 0xFFL 5228//MIN_GRANT 5229#define MIN_GRANT__MIN_GNT__MASK 0xFFL 5230//MAX_LATENCY 5231#define MAX_LATENCY__MAX_LAT__MASK 0xFFL 5232//VENDOR_CAP_LIST 5233#define VENDOR_CAP_LIST__CAP_ID__MASK 0x000000FFL 5234#define VENDOR_CAP_LIST__NEXT_PTR__MASK 0x0000FF00L 5235#define VENDOR_CAP_LIST__LENGTH__MASK 0x00FF0000L 5236//ADAPTER_ID_W 5237#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 5238#define ADAPTER_ID_W__SUBSYSTEM_ID__MASK 0xFFFF0000L 5239//PMI_CAP_LIST 5240#define PMI_CAP_LIST__CAP_ID__MASK 0x00FFL 5241#define PMI_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5242//PMI_CAP 5243#define PMI_CAP__VERSION__MASK 0x0007L 5244#define PMI_CAP__PME_CLOCK__MASK 0x0008L 5245#define PMI_CAP__DEV_SPECIFIC_INIT__MASK 0x0020L 5246#define PMI_CAP__AUX_CURRENT__MASK 0x01C0L 5247#define PMI_CAP__D1_SUPPORT__MASK 0x0200L 5248#define PMI_CAP__D2_SUPPORT__MASK 0x0400L 5249#define PMI_CAP__PME_SUPPORT__MASK 0xF800L 5250//PMI_STATUS_CNTL 5251#define PMI_STATUS_CNTL__POWER_STATE__MASK 0x00000003L 5252#define PMI_STATUS_CNTL__NO_SOFT_RESET__MASK 0x00000008L 5253#define PMI_STATUS_CNTL__PME_EN__MASK 0x00000100L 5254#define PMI_STATUS_CNTL__DATA_SELECT__MASK 0x00001E00L 5255#define PMI_STATUS_CNTL__DATA_SCALE__MASK 0x00006000L 5256#define PMI_STATUS_CNTL__PME_STATUS__MASK 0x00008000L 5257#define PMI_STATUS_CNTL__B2_B3_SUPPORT__MASK 0x00400000L 5258#define PMI_STATUS_CNTL__BUS_PWR_EN__MASK 0x00800000L 5259#define PMI_STATUS_CNTL__PMI_DATA__MASK 0xFF000000L 5260//PCIE_CAP_LIST 5261#define PCIE_CAP_LIST__CAP_ID__MASK 0x00FFL 5262#define PCIE_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5263//PCIE_CAP 5264#define PCIE_CAP__VERSION__MASK 0x000FL 5265#define PCIE_CAP__DEVICE_TYPE__MASK 0x00F0L 5266#define PCIE_CAP__SLOT_IMPLEMENTED__MASK 0x0100L 5267#define PCIE_CAP__INT_MESSAGE_NUM__MASK 0x3E00L 5268//DEVICE_CAP 5269#define DEVICE_CAP__MAX_PAYLOAD_SUPPORT__MASK 0x00000007L 5270#define DEVICE_CAP__PHANTOM_FUNC__MASK 0x00000018L 5271#define DEVICE_CAP__EXTENDED_TAG__MASK 0x00000020L 5272#define DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__MASK 0x000001C0L 5273#define DEVICE_CAP__L1_ACCEPTABLE_LATENCY__MASK 0x00000E00L 5274#define DEVICE_CAP__ROLE_BASED_ERR_REPORTING__MASK 0x00008000L 5275#define DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__MASK 0x03FC0000L 5276#define DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__MASK 0x0C000000L 5277#define DEVICE_CAP__FLR_CAPABLE__MASK 0x10000000L 5278//DEVICE_CNTL 5279#define DEVICE_CNTL__CORR_ERR_EN__MASK 0x0001L 5280#define DEVICE_CNTL__NON_FATAL_ERR_EN__MASK 0x0002L 5281#define DEVICE_CNTL__FATAL_ERR_EN__MASK 0x0004L 5282#define DEVICE_CNTL__USR_REPORT_EN__MASK 0x0008L 5283#define DEVICE_CNTL__RELAXED_ORD_EN__MASK 0x0010L 5284#define DEVICE_CNTL__MAX_PAYLOAD_SIZE__MASK 0x00E0L 5285#define DEVICE_CNTL__EXTENDED_TAG_EN__MASK 0x0100L 5286#define DEVICE_CNTL__PHANTOM_FUNC_EN__MASK 0x0200L 5287#define DEVICE_CNTL__AUX_POWER_PM_EN__MASK 0x0400L 5288#define DEVICE_CNTL__NO_SNOOP_EN__MASK 0x0800L 5289#define DEVICE_CNTL__MAX_READ_REQUEST_SIZE__MASK 0x7000L 5290#define DEVICE_CNTL__INITIATE_FLR__MASK 0x8000L 5291//DEVICE_STATUS 5292#define DEVICE_STATUS__CORR_ERR__MASK 0x0001L 5293#define DEVICE_STATUS__NON_FATAL_ERR__MASK 0x0002L 5294#define DEVICE_STATUS__FATAL_ERR__MASK 0x0004L 5295#define DEVICE_STATUS__USR_DETECTED__MASK 0x0008L 5296#define DEVICE_STATUS__AUX_PWR__MASK 0x0010L 5297#define DEVICE_STATUS__TRANSACTIONS_PEND__MASK 0x0020L 5298//LINK_CAP 5299#define LINK_CAP__LINK_SPEED__MASK 0x0000000FL 5300#define LINK_CAP__LINK_WIDTH__MASK 0x000003F0L 5301#define LINK_CAP__PM_SUPPORT__MASK 0x00000C00L 5302#define LINK_CAP__L0S_EXIT_LATENCY__MASK 0x00007000L 5303#define LINK_CAP__L1_EXIT_LATENCY__MASK 0x00038000L 5304#define LINK_CAP__CLOCK_POWER_MANAGEMENT__MASK 0x00040000L 5305#define LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__MASK 0x00080000L 5306#define LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__MASK 0x00100000L 5307#define LINK_CAP__LINK_BW_NOTIFICATION_CAP__MASK 0x00200000L 5308#define LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__MASK 0x00400000L 5309#define LINK_CAP__PORT_NUMBER__MASK 0xFF000000L 5310//LINK_CNTL 5311#define LINK_CNTL__PM_CONTROL__MASK 0x0003L 5312#define LINK_CNTL__READ_CPL_BOUNDARY__MASK 0x0008L 5313#define LINK_CNTL__LINK_DIS__MASK 0x0010L 5314#define LINK_CNTL__RETRAIN_LINK__MASK 0x0020L 5315#define LINK_CNTL__COMMON_CLOCK_CFG__MASK 0x0040L 5316#define LINK_CNTL__EXTENDED_SYNC__MASK 0x0080L 5317#define LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__MASK 0x0100L 5318#define LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__MASK 0x0200L 5319#define LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__MASK 0x0400L 5320#define LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__MASK 0x0800L 5321//LINK_STATUS 5322#define LINK_STATUS__CURRENT_LINK_SPEED__MASK 0x000FL 5323#define LINK_STATUS__NEGOTIATED_LINK_WIDTH__MASK 0x03F0L 5324#define LINK_STATUS__LINK_TRAINING__MASK 0x0800L 5325#define LINK_STATUS__SLOT_CLOCK_CFG__MASK 0x1000L 5326#define LINK_STATUS__DL_ACTIVE__MASK 0x2000L 5327#define LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__MASK 0x4000L 5328#define LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__MASK 0x8000L 5329//DEVICE_CAP2 5330#define DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__MASK 0x0000000FL 5331#define DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__MASK 0x00000010L 5332#define DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__MASK 0x00000020L 5333#define DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__MASK 0x00000040L 5334#define DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__MASK 0x00000080L 5335#define DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__MASK 0x00000100L 5336#define DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__MASK 0x00000200L 5337#define DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__MASK 0x00000400L 5338#define DEVICE_CAP2__LTR_SUPPORTED__MASK 0x00000800L 5339#define DEVICE_CAP2__TPH_CPLR_SUPPORTED__MASK 0x00003000L 5340#define DEVICE_CAP2__OBFF_SUPPORTED__MASK 0x000C0000L 5341#define DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__MASK 0x00100000L 5342#define DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__MASK 0x00200000L 5343#define DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__MASK 0x00C00000L 5344//DEVICE_CNTL2 5345#define DEVICE_CNTL2__CPL_TIMEOUT_VALUE__MASK 0x000FL 5346#define DEVICE_CNTL2__CPL_TIMEOUT_DIS__MASK 0x0010L 5347#define DEVICE_CNTL2__ARI_FORWARDING_EN__MASK 0x0020L 5348#define DEVICE_CNTL2__ATOMICOP_REQUEST_EN__MASK 0x0040L 5349#define DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__MASK 0x0080L 5350#define DEVICE_CNTL2__IDO_REQUEST_ENABLE__MASK 0x0100L 5351#define DEVICE_CNTL2__IDO_COMPLETION_ENABLE__MASK 0x0200L 5352#define DEVICE_CNTL2__LTR_EN__MASK 0x0400L 5353#define DEVICE_CNTL2__OBFF_EN__MASK 0x6000L 5354#define DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__MASK 0x8000L 5355//DEVICE_STATUS2 5356#define DEVICE_STATUS2__RESERVED__MASK 0xFFFFL 5357//LINK_CAP2 5358#define LINK_CAP2__SUPPORTED_LINK_SPEED__MASK 0x000000FEL 5359#define LINK_CAP2__CROSSLINK_SUPPORTED__MASK 0x00000100L 5360#define LINK_CAP2__RESERVED__MASK 0xFFFFFE00L 5361//LINK_CNTL2 5362#define LINK_CNTL2__TARGET_LINK_SPEED__MASK 0x000FL 5363#define LINK_CNTL2__ENTER_COMPLIANCE__MASK 0x0010L 5364#define LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__MASK 0x0020L 5365#define LINK_CNTL2__SELECTABLE_DEEMPHASIS__MASK 0x0040L 5366#define LINK_CNTL2__XMIT_MARGIN__MASK 0x0380L 5367#define LINK_CNTL2__ENTER_MOD_COMPLIANCE__MASK 0x0400L 5368#define LINK_CNTL2__COMPLIANCE_SOS__MASK 0x0800L 5369#define LINK_CNTL2__COMPLIANCE_DEEMPHASIS__MASK 0xF000L 5370//LINK_STATUS2 5371#define LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__MASK 0x0001L 5372#define LINK_STATUS2__EQUALIZATION_COMPLETE__MASK 0x0002L 5373#define LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS__MASK 0x0004L 5374#define LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS__MASK 0x0008L 5375#define LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS__MASK 0x0010L 5376#define LINK_STATUS2__LINK_EQUALIZATION_REQUEST__MASK 0x0020L 5377//SLOT_CAP2 5378#define SLOT_CAP2__RESERVED__MASK 0xFFFFFFFFL 5379//SLOT_CNTL2 5380#define SLOT_CNTL2__RESERVED__MASK 0xFFFFL 5381//SLOT_STATUS2 5382#define SLOT_STATUS2__RESERVED__MASK 0xFFFFL 5383//MSI_CAP_LIST 5384#define MSI_CAP_LIST__CAP_ID__MASK 0x00FFL 5385#define MSI_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5386//MSI_MSG_CNTL 5387#define MSI_MSG_CNTL__MSI_EN__MASK 0x0001L 5388#define MSI_MSG_CNTL__MSI_MULTI_CAP__MASK 0x000EL 5389#define MSI_MSG_CNTL__MSI_MULTI_EN__MASK 0x0070L 5390#define MSI_MSG_CNTL__MSI_64BIT__MASK 0x0080L 5391#define MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__MASK 0x0100L 5392//MSI_MSG_ADDR_LO 5393#define MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__MASK 0xFFFFFFFCL 5394//MSI_MSG_ADDR_HI 5395#define MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__MASK 0xFFFFFFFFL 5396//MSI_MSG_DATA 5397#define MSI_MSG_DATA__MSI_DATA__MASK 0x0000FFFFL 5398//MSI_MSG_DATA_64 5399#define MSI_MSG_DATA_64__MSI_DATA_64__MASK 0x0000FFFFL 5400//MSI_MASK 5401#define MSI_MASK__MSI_MASK__MASK 0xFFFFFFFFL 5402//MSI_PENDING 5403#define MSI_PENDING__MSI_PENDING__MASK 0xFFFFFFFFL 5404//MSI_MASK_64 5405#define MSI_MASK_64__MSI_MASK_64__MASK 0xFFFFFFFFL 5406//MSI_PENDING_64 5407#define MSI_PENDING_64__MSI_PENDING_64__MASK 0xFFFFFFFFL 5408//MSIX_CAP_LIST 5409#define MSIX_CAP_LIST__CAP_ID__MASK 0x00FFL 5410#define MSIX_CAP_LIST__NEXT_PTR__MASK 0xFF00L 5411//MSIX_MSG_CNTL 5412#define MSIX_MSG_CNTL__MSIX_TABLE_SIZE__MASK 0x07FFL 5413#define MSIX_MSG_CNTL__MSIX_FUNC_MASK__MASK 0x4000L 5414#define MSIX_MSG_CNTL__MSIX_EN__MASK 0x8000L 5415//MSIX_TABLE 5416#define MSIX_TABLE__MSIX_TABLE_BIR__MASK 0x00000007L 5417#define MSIX_TABLE__MSIX_TABLE_OFFSET__MASK 0xFFFFFFF8L 5418//MSIX_PBA 5419#define MSIX_PBA__MSIX_PBA_BIR__MASK 0x00000007L 5420#define MSIX_PBA__MSIX_PBA_OFFSET__MASK 0xFFFFFFF8L 5421//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 5422#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5423#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5424#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5425//PCIE_VENDOR_SPECIFIC_HDR 5426#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__MASK 0x0000FFFFL 5427#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__MASK 0x000F0000L 5428#define PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__MASK 0xFFF00000L 5429//PCIE_VENDOR_SPECIFIC1 5430#define PCIE_VENDOR_SPECIFIC1__SCRATCH__MASK 0xFFFFFFFFL 5431//PCIE_VENDOR_SPECIFIC2 5432#define PCIE_VENDOR_SPECIFIC2__SCRATCH__MASK 0xFFFFFFFFL 5433//PCIE_VC_ENH_CAP_LIST 5434#define PCIE_VC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5435#define PCIE_VC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5436#define PCIE_VC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5437//PCIE_PORT_VC_CAP_REG1 5438#define PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__MASK 0x00000007L 5439#define PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__MASK 0x00000070L 5440#define PCIE_PORT_VC_CAP_REG1__REF_CLK__MASK 0x00000300L 5441#define PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__MASK 0x00000C00L 5442//PCIE_PORT_VC_CAP_REG2 5443#define PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__MASK 0x000000FFL 5444#define PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__MASK 0xFF000000L 5445//PCIE_PORT_VC_CNTL 5446#define PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__MASK 0x0001L 5447#define PCIE_PORT_VC_CNTL__VC_ARB_SELECT__MASK 0x000EL 5448//PCIE_PORT_VC_STATUS 5449#define PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__MASK 0x0001L 5450//PCIE_VC0_RESOURCE_CAP 5451#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL 5452#define PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L 5453#define PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L 5454#define PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L 5455//PCIE_VC0_RESOURCE_CNTL 5456#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L 5457#define PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL 5458#define PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L 5459#define PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L 5460#define PCIE_VC0_RESOURCE_CNTL__VC_ID__MASK 0x07000000L 5461#define PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L 5462//PCIE_VC0_RESOURCE_STATUS 5463#define PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L 5464#define PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L 5465//PCIE_VC1_RESOURCE_CAP 5466#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__MASK 0x000000FFL 5467#define PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__MASK 0x00008000L 5468#define PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__MASK 0x003F0000L 5469#define PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__MASK 0xFF000000L 5470//PCIE_VC1_RESOURCE_CNTL 5471#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__MASK 0x00000001L 5472#define PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__MASK 0x000000FEL 5473#define PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__MASK 0x00010000L 5474#define PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__MASK 0x000E0000L 5475#define PCIE_VC1_RESOURCE_CNTL__VC_ID__MASK 0x07000000L 5476#define PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__MASK 0x80000000L 5477//PCIE_VC1_RESOURCE_STATUS 5478#define PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__MASK 0x0001L 5479#define PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__MASK 0x0002L 5480//PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 5481#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5482#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5483#define PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5484//PCIE_DEV_SERIAL_NUM_DW1 5485#define PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__MASK 0xFFFFFFFFL 5486//PCIE_DEV_SERIAL_NUM_DW2 5487#define PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__MASK 0xFFFFFFFFL 5488//PCIE_ADV_ERR_RPT_ENH_CAP_LIST 5489#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5490#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5491#define PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5492//PCIE_UNCORR_ERR_STATUS 5493#define PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__MASK 0x00000010L 5494#define PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__MASK 0x00000020L 5495#define PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__MASK 0x00001000L 5496#define PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__MASK 0x00002000L 5497#define PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__MASK 0x00004000L 5498#define PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__MASK 0x00008000L 5499#define PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__MASK 0x00010000L 5500#define PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__MASK 0x00020000L 5501#define PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__MASK 0x00040000L 5502#define PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__MASK 0x00080000L 5503#define PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__MASK 0x00100000L 5504#define PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__MASK 0x00200000L 5505#define PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__MASK 0x00400000L 5506#define PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__MASK 0x00800000L 5507#define PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__MASK 0x01000000L 5508#define PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__MASK 0x02000000L 5509//PCIE_UNCORR_ERR_MASK 5510#define PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__MASK 0x00000010L 5511#define PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__MASK 0x00000020L 5512#define PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__MASK 0x00001000L 5513#define PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__MASK 0x00002000L 5514#define PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__MASK 0x00004000L 5515#define PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__MASK 0x00008000L 5516#define PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__MASK 0x00010000L 5517#define PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__MASK 0x00020000L 5518#define PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__MASK 0x00040000L 5519#define PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__MASK 0x00080000L 5520#define PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__MASK 0x00100000L 5521#define PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__MASK 0x00200000L 5522#define PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__MASK 0x00400000L 5523#define PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__MASK 0x00800000L 5524#define PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__MASK 0x01000000L 5525#define PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__MASK 0x02000000L 5526//PCIE_UNCORR_ERR_SEVERITY 5527#define PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__MASK 0x00000010L 5528#define PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__MASK 0x00000020L 5529#define PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__MASK 0x00001000L 5530#define PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__MASK 0x00002000L 5531#define PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__MASK 0x00004000L 5532#define PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__MASK 0x00008000L 5533#define PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__MASK 0x00010000L 5534#define PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__MASK 0x00020000L 5535#define PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__MASK 0x00040000L 5536#define PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__MASK 0x00080000L 5537#define PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__MASK 0x00100000L 5538#define PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__MASK 0x00200000L 5539#define PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__MASK 0x00400000L 5540#define PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__MASK 0x00800000L 5541#define PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__MASK 0x01000000L 5542#define PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__MASK 0x02000000L 5543//PCIE_CORR_ERR_STATUS 5544#define PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__MASK 0x00000001L 5545#define PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__MASK 0x00000040L 5546#define PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__MASK 0x00000080L 5547#define PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__MASK 0x00000100L 5548#define PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__MASK 0x00001000L 5549#define PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00002000L 5550#define PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__MASK 0x00004000L 5551#define PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__MASK 0x00008000L 5552//PCIE_CORR_ERR_MASK 5553#define PCIE_CORR_ERR_MASK__RCV_ERR_MASK__MASK 0x00000001L 5554#define PCIE_CORR_ERR_MASK__BAD_TLP_MASK__MASK 0x00000040L 5555#define PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__MASK 0x00000080L 5556#define PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__MASK 0x00000100L 5557#define PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__MASK 0x00001000L 5558#define PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__MASK 0x00002000L 5559#define PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__MASK 0x00004000L 5560#define PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__MASK 0x00008000L 5561//PCIE_ADV_ERR_CAP_CNTL 5562#define PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__MASK 0x0000001FL 5563#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__MASK 0x00000020L 5564#define PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__MASK 0x00000040L 5565#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__MASK 0x00000080L 5566#define PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__MASK 0x00000100L 5567#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__MASK 0x00000200L 5568#define PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__MASK 0x00000400L 5569#define PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__MASK 0x00000800L 5570//PCIE_HDR_LOG0 5571#define PCIE_HDR_LOG0__TLP_HDR__MASK 0xFFFFFFFFL 5572//PCIE_HDR_LOG1 5573#define PCIE_HDR_LOG1__TLP_HDR__MASK 0xFFFFFFFFL 5574//PCIE_HDR_LOG2 5575#define PCIE_HDR_LOG2__TLP_HDR__MASK 0xFFFFFFFFL 5576//PCIE_HDR_LOG3 5577#define PCIE_HDR_LOG3__TLP_HDR__MASK 0xFFFFFFFFL 5578//PCIE_ROOT_ERR_CMD 5579#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__MASK 0x00000001L 5580#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__MASK 0x00000002L 5581#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__MASK 0x00000004L 5582//PCIE_ROOT_ERR_STATUS 5583#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__MASK 0x00000001L 5584#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__MASK 0x00000002L 5585#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__MASK 0x00000004L 5586#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__MASK 0x00000008L 5587#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__MASK 0x00000010L 5588#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__MASK 0x00000020L 5589#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__MASK 0x00000040L 5590#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__MASK 0xF8000000L 5591//PCIE_ERR_SRC_ID 5592#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__MASK 0x0000FFFFL 5593#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__MASK 0xFFFF0000L 5594//PCIE_TLP_PREFIX_LOG0 5595#define PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__MASK 0xFFFFFFFFL 5596//PCIE_TLP_PREFIX_LOG1 5597#define PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__MASK 0xFFFFFFFFL 5598//PCIE_TLP_PREFIX_LOG2 5599#define PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__MASK 0xFFFFFFFFL 5600//PCIE_TLP_PREFIX_LOG3 5601#define PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__MASK 0xFFFFFFFFL 5602//PCIE_BAR_ENH_CAP_LIST 5603#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5604#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5605#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5606//PCIE_BAR1_CAP 5607#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5608//PCIE_BAR1_CNTL 5609#define PCIE_BAR1_CNTL__BAR_INDEX__MASK 0x0007L 5610#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5611#define PCIE_BAR1_CNTL__BAR_SIZE__MASK 0x1F00L 5612//PCIE_BAR2_CAP 5613#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5614//PCIE_BAR2_CNTL 5615#define PCIE_BAR2_CNTL__BAR_INDEX__MASK 0x0007L 5616#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5617#define PCIE_BAR2_CNTL__BAR_SIZE__MASK 0x1F00L 5618//PCIE_BAR3_CAP 5619#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5620//PCIE_BAR3_CNTL 5621#define PCIE_BAR3_CNTL__BAR_INDEX__MASK 0x0007L 5622#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5623#define PCIE_BAR3_CNTL__BAR_SIZE__MASK 0x1F00L 5624//PCIE_BAR4_CAP 5625#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5626//PCIE_BAR4_CNTL 5627#define PCIE_BAR4_CNTL__BAR_INDEX__MASK 0x0007L 5628#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5629#define PCIE_BAR4_CNTL__BAR_SIZE__MASK 0x1F00L 5630//PCIE_BAR5_CAP 5631#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5632//PCIE_BAR5_CNTL 5633#define PCIE_BAR5_CNTL__BAR_INDEX__MASK 0x0007L 5634#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5635#define PCIE_BAR5_CNTL__BAR_SIZE__MASK 0x1F00L 5636//PCIE_BAR6_CAP 5637#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__MASK 0x00FFFFF0L 5638//PCIE_BAR6_CNTL 5639#define PCIE_BAR6_CNTL__BAR_INDEX__MASK 0x0007L 5640#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__MASK 0x00E0L 5641#define PCIE_BAR6_CNTL__BAR_SIZE__MASK 0x1F00L 5642//PCIE_PWR_BUDGET_ENH_CAP_LIST 5643#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5644#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5645#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5646//PCIE_PWR_BUDGET_DATA_SELECT 5647#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__MASK 0xFFL 5648//PCIE_PWR_BUDGET_DATA 5649#define PCIE_PWR_BUDGET_DATA__BASE_POWER__MASK 0x000000FFL 5650#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__MASK 0x00000300L 5651#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__MASK 0x00001C00L 5652#define PCIE_PWR_BUDGET_DATA__PM_STATE__MASK 0x00006000L 5653#define PCIE_PWR_BUDGET_DATA__TYPE__MASK 0x00038000L 5654#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__MASK 0x001C0000L 5655//PCIE_PWR_BUDGET_CAP 5656#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__MASK 0x01L 5657//PCIE_DPA_ENH_CAP_LIST 5658#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5659#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5660#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5661//PCIE_DPA_CAP 5662#define PCIE_DPA_CAP__SUBSTATE_MAX__MASK 0x0000001FL 5663#define PCIE_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L 5664#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L 5665#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L 5666#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L 5667//PCIE_DPA_LATENCY_INDICATOR 5668#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL 5669//PCIE_DPA_STATUS 5670#define PCIE_DPA_STATUS__SUBSTATE_STATUS__MASK 0x001FL 5671#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__MASK 0x0100L 5672//PCIE_DPA_CNTL 5673#define PCIE_DPA_CNTL__SUBSTATE_CNTL__MASK 0x1FL 5674//PCIE_DPA_SUBSTATE_PWR_ALLOC_0 5675#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5676//PCIE_DPA_SUBSTATE_PWR_ALLOC_1 5677#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5678//PCIE_DPA_SUBSTATE_PWR_ALLOC_2 5679#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5680//PCIE_DPA_SUBSTATE_PWR_ALLOC_3 5681#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5682//PCIE_DPA_SUBSTATE_PWR_ALLOC_4 5683#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5684//PCIE_DPA_SUBSTATE_PWR_ALLOC_5 5685#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5686//PCIE_DPA_SUBSTATE_PWR_ALLOC_6 5687#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5688//PCIE_DPA_SUBSTATE_PWR_ALLOC_7 5689#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL 5690//PCIE_SECONDARY_ENH_CAP_LIST 5691#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5692#define PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5693#define PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5694//PCIE_LINK_CNTL3 5695#define PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__MASK 0x00000001L 5696#define PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__MASK 0x00000002L 5697#define PCIE_LINK_CNTL3__RESERVED__MASK 0xFFFFFFFCL 5698//PCIE_LANE_ERROR_STATUS 5699#define PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__MASK 0x0000FFFFL 5700#define PCIE_LANE_ERROR_STATUS__RESERVED__MASK 0xFFFF0000L 5701//PCIE_LANE_0_EQUALIZATION_CNTL 5702#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5703#define PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5704#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5705#define PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5706#define PCIE_LANE_0_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5707//PCIE_LANE_1_EQUALIZATION_CNTL 5708#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5709#define PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5710#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5711#define PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5712#define PCIE_LANE_1_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5713//PCIE_LANE_2_EQUALIZATION_CNTL 5714#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5715#define PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5716#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5717#define PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5718#define PCIE_LANE_2_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5719//PCIE_LANE_3_EQUALIZATION_CNTL 5720#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5721#define PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5722#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5723#define PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5724#define PCIE_LANE_3_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5725//PCIE_LANE_4_EQUALIZATION_CNTL 5726#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5727#define PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5728#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5729#define PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5730#define PCIE_LANE_4_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5731//PCIE_LANE_5_EQUALIZATION_CNTL 5732#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5733#define PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5734#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5735#define PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5736#define PCIE_LANE_5_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5737//PCIE_LANE_6_EQUALIZATION_CNTL 5738#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5739#define PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5740#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5741#define PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5742#define PCIE_LANE_6_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5743//PCIE_LANE_7_EQUALIZATION_CNTL 5744#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5745#define PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5746#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5747#define PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5748#define PCIE_LANE_7_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5749//PCIE_LANE_8_EQUALIZATION_CNTL 5750#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5751#define PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5752#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5753#define PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5754#define PCIE_LANE_8_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5755//PCIE_LANE_9_EQUALIZATION_CNTL 5756#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5757#define PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5758#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5759#define PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5760#define PCIE_LANE_9_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5761//PCIE_LANE_10_EQUALIZATION_CNTL 5762#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5763#define PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5764#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5765#define PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5766#define PCIE_LANE_10_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5767//PCIE_LANE_11_EQUALIZATION_CNTL 5768#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5769#define PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5770#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5771#define PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5772#define PCIE_LANE_11_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5773//PCIE_LANE_12_EQUALIZATION_CNTL 5774#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5775#define PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5776#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5777#define PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5778#define PCIE_LANE_12_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5779//PCIE_LANE_13_EQUALIZATION_CNTL 5780#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5781#define PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5782#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5783#define PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5784#define PCIE_LANE_13_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5785//PCIE_LANE_14_EQUALIZATION_CNTL 5786#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5787#define PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5788#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5789#define PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5790#define PCIE_LANE_14_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5791//PCIE_LANE_15_EQUALIZATION_CNTL 5792#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_TX_PRESET__MASK 0x000FL 5793#define PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_RX_PRESET_HINT__MASK 0x0070L 5794#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_TX_PRESET__MASK 0x0F00L 5795#define PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_RX_PRESET_HINT__MASK 0x7000L 5796#define PCIE_LANE_15_EQUALIZATION_CNTL__RESERVED__MASK 0x8000L 5797//PCIE_ACS_ENH_CAP_LIST 5798#define PCIE_ACS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5799#define PCIE_ACS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5800#define PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5801//PCIE_ACS_CAP 5802#define PCIE_ACS_CAP__SOURCE_VALIDATION__MASK 0x0001L 5803#define PCIE_ACS_CAP__TRANSLATION_BLOCKING__MASK 0x0002L 5804#define PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__MASK 0x0004L 5805#define PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__MASK 0x0008L 5806#define PCIE_ACS_CAP__UPSTREAM_FORWARDING__MASK 0x0010L 5807#define PCIE_ACS_CAP__P2P_EGRESS_CONTROL__MASK 0x0020L 5808#define PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__MASK 0x0040L 5809#define PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__MASK 0xFF00L 5810//PCIE_ACS_CNTL 5811#define PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__MASK 0x0001L 5812#define PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__MASK 0x0002L 5813#define PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__MASK 0x0004L 5814#define PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__MASK 0x0008L 5815#define PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__MASK 0x0010L 5816#define PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__MASK 0x0020L 5817#define PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__MASK 0x0040L 5818//PCIE_ATS_ENH_CAP_LIST 5819#define PCIE_ATS_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5820#define PCIE_ATS_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5821#define PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5822//PCIE_ATS_CAP 5823#define PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__MASK 0x001FL 5824#define PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__MASK 0x0020L 5825#define PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__MASK 0x0040L 5826//PCIE_ATS_CNTL 5827#define PCIE_ATS_CNTL__STU__MASK 0x001FL 5828#define PCIE_ATS_CNTL__ATC_ENABLE__MASK 0x8000L 5829//PCIE_PAGE_REQ_ENH_CAP_LIST 5830#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5831#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5832#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5833//PCIE_PAGE_REQ_CNTL 5834#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__MASK 0x0001L 5835#define PCIE_PAGE_REQ_CNTL__PRI_RESET__MASK 0x0002L 5836//PCIE_PAGE_REQ_STATUS 5837#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__MASK 0x0001L 5838#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__MASK 0x0002L 5839#define PCIE_PAGE_REQ_STATUS__STOPPED__MASK 0x0100L 5840#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__MASK 0x8000L 5841//PCIE_OUTSTAND_PAGE_REQ_CAPACITY 5842#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__MASK 0xFFFFFFFFL 5843//PCIE_OUTSTAND_PAGE_REQ_ALLOC 5844#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__MASK 0xFFFFFFFFL 5845//PCIE_PASID_ENH_CAP_LIST 5846#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5847#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5848#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5849//PCIE_PASID_CAP 5850#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__MASK 0x0002L 5851#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__MASK 0x0004L 5852#define PCIE_PASID_CAP__MAX_PASID_WIDTH__MASK 0x1F00L 5853//PCIE_PASID_CNTL 5854#define PCIE_PASID_CNTL__PASID_ENABLE__MASK 0x0001L 5855#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__MASK 0x0002L 5856#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__MASK 0x0004L 5857//PCIE_TPH_REQR_ENH_CAP_LIST 5858#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5859#define PCIE_TPH_REQR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5860#define PCIE_TPH_REQR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5861//PCIE_TPH_REQR_CAP 5862#define PCIE_TPH_REQR_CAP__TPH_REQR_NO_ST_MODE_SUPPORTED__MASK 0x00000001L 5863#define PCIE_TPH_REQR_CAP__TPH_REQR_INT_VEC_MODE_SUPPORTED__MASK 0x00000002L 5864#define PCIE_TPH_REQR_CAP__TPH_REQR_DEV_SPC_MODE_SUPPORTED__MASK 0x00000004L 5865#define PCIE_TPH_REQR_CAP__TPH_REQR_EXTND_TPH_REQR_SUPPORED__MASK 0x00000100L 5866#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_LOCATION__MASK 0x00000600L 5867#define PCIE_TPH_REQR_CAP__TPH_REQR_ST_TABLE_SIZE__MASK 0x07FF0000L 5868//PCIE_TPH_REQR_CNTL 5869#define PCIE_TPH_REQR_CNTL__TPH_REQR_ST_MODE_SEL__MASK 0x00000007L 5870#define PCIE_TPH_REQR_CNTL__TPH_REQR_EN__MASK 0x00000300L 5871//PCIE_MC_ENH_CAP_LIST 5872#define PCIE_MC_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5873#define PCIE_MC_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5874#define PCIE_MC_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5875//PCIE_MC_CAP 5876#define PCIE_MC_CAP__MC_MAX_GROUP__MASK 0x003FL 5877#define PCIE_MC_CAP__MC_WIN_SIZE_REQ__MASK 0x3F00L 5878#define PCIE_MC_CAP__MC_ECRC_REGEN_SUPP__MASK 0x8000L 5879//PCIE_MC_CNTL 5880#define PCIE_MC_CNTL__MC_NUM_GROUP__MASK 0x003FL 5881#define PCIE_MC_CNTL__MC_ENABLE__MASK 0x8000L 5882//PCIE_MC_ADDR0 5883#define PCIE_MC_ADDR0__MC_INDEX_POS__MASK 0x0000003FL 5884#define PCIE_MC_ADDR0__MC_BASE_ADDR_0__MASK 0xFFFFF000L 5885//PCIE_MC_ADDR1 5886#define PCIE_MC_ADDR1__MC_BASE_ADDR_1__MASK 0xFFFFFFFFL 5887//PCIE_MC_RCV0 5888#define PCIE_MC_RCV0__MC_RECEIVE_0__MASK 0xFFFFFFFFL 5889//PCIE_MC_RCV1 5890#define PCIE_MC_RCV1__MC_RECEIVE_1__MASK 0xFFFFFFFFL 5891//PCIE_MC_BLOCK_ALL0 5892#define PCIE_MC_BLOCK_ALL0__MC_BLOCK_ALL_0__MASK 0xFFFFFFFFL 5893//PCIE_MC_BLOCK_ALL1 5894#define PCIE_MC_BLOCK_ALL1__MC_BLOCK_ALL_1__MASK 0xFFFFFFFFL 5895//PCIE_MC_BLOCK_UNTRANSLATED_0 5896#define PCIE_MC_BLOCK_UNTRANSLATED_0__MC_BLOCK_UNTRANSLATED_0__MASK 0xFFFFFFFFL 5897//PCIE_MC_BLOCK_UNTRANSLATED_1 5898#define PCIE_MC_BLOCK_UNTRANSLATED_1__MC_BLOCK_UNTRANSLATED_1__MASK 0xFFFFFFFFL 5899//PCIE_LTR_ENH_CAP_LIST 5900#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5901#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5902#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5903//PCIE_LTR_CAP 5904#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__MASK 0x000003FFL 5905#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__MASK 0x00001C00L 5906#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__MASK 0x03FF0000L 5907#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__MASK 0x1C000000L 5908//PCIE_ARI_ENH_CAP_LIST 5909#define PCIE_ARI_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5910#define PCIE_ARI_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5911#define PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5912//PCIE_ARI_CAP 5913#define PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__MASK 0x0001L 5914#define PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__MASK 0x0002L 5915#define PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__MASK 0xFF00L 5916//PCIE_ARI_CNTL 5917#define PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__MASK 0x0001L 5918#define PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__MASK 0x0002L 5919#define PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__MASK 0x0070L 5920//PCIE_SRIOV_ENH_CAP_LIST 5921#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__MASK 0x0000FFFFL 5922#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__MASK 0x000F0000L 5923#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__MASK 0xFFF00000L 5924//PCIE_SRIOV_CAP 5925#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__MASK 0x00000001L 5926#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__MASK 0x00000002L 5927#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__MASK 0xFFE00000L 5928//PCIE_SRIOV_CONTROL 5929#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__MASK 0x0001L 5930#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__MASK 0x0002L 5931#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__MASK 0x0004L 5932#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__MASK 0x0008L 5933#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__MASK 0x0010L 5934//PCIE_SRIOV_STATUS 5935#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__MASK 0x0001L 5936//PCIE_SRIOV_INITIAL_VFS 5937#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__MASK 0xFFFFL 5938//PCIE_SRIOV_TOTAL_VFS 5939#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__MASK 0xFFFFL 5940//PCIE_SRIOV_NUM_VFS 5941#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__MASK 0xFFFFL 5942//PCIE_SRIOV_FUNC_DEP_LINK 5943#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__MASK 0x00FFL 5944//PCIE_SRIOV_FIRST_VF_OFFSET 5945#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__MASK 0xFFFFL 5946//PCIE_SRIOV_VF_STRIDE 5947#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__MASK 0xFFFFL 5948//PCIE_SRIOV_VF_DEVICE_ID 5949#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__MASK 0xFFFFL 5950//PCIE_SRIOV_SUPPORTED_PAGE_SIZE 5951#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__MASK 0xFFFFFFFFL 5952//PCIE_SRIOV_SYSTEM_PAGE_SIZE 5953#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__MASK 0xFFFFFFFFL 5954//PCIE_SRIOV_VF_BASE_ADDR_0 5955#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5956//PCIE_SRIOV_VF_BASE_ADDR_1 5957#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5958//PCIE_SRIOV_VF_BASE_ADDR_2 5959#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5960//PCIE_SRIOV_VF_BASE_ADDR_3 5961#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5962//PCIE_SRIOV_VF_BASE_ADDR_4 5963#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5964//PCIE_SRIOV_VF_BASE_ADDR_5 5965#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__MASK 0xFFFFFFFFL 5966//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 5967#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIF__MASK 0x00000007L 5968#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__MASK 0xFFFFFFF8L 5969//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 5970#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__MASK 0x0000FFFFL 5971#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__MASK 0x000F0000L 5972#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__MASK 0xFFF00000L 5973//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 5974#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__MASK 0x0000FFFFL 5975#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__MASK 0x000F0000L 5976#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__MASK 0xFFF00000L 5977//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 5978#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__MASK 0x00000001L 5979#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__MASK 0xFFFF0000L 5980//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 5981#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_CMD_COMPLETE_INTR_EN__MASK 0x00000001L 5982#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000002L 5983#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_HANG_NEED_FLR_INTR_EN__MASK 0x00000004L 5984#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__GFX_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000008L 5985#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_CMD_COMPLETE_INTR_EN__MASK 0x00000100L 5986#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00000200L 5987#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_HANG_NEED_FLR_INTR_EN__MASK 0x00000400L 5988#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__UVD_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00000800L 5989#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_CMD_COMPLETE_INTR_EN__MASK 0x00010000L 5990#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_SELF_RECOVERED_INTR_EN__MASK 0x00020000L 5991#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_HANG_NEED_FLR_INTR_EN__MASK 0x00040000L 5992#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__VCE_VM_BUSY_TRANSITION_INTR_EN__MASK 0x00080000L 5993#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__MASK 0x01000000L 5994#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__MASK 0x02000000L 5995//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 5996#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_CMD_COMPLETE_INTR_STATUS__MASK 0x00000001L 5997#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000002L 5998#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000004L 5999#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__GFX_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000008L 6000#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_CMD_COMPLETE_INTR_STATUS__MASK 0x00000100L 6001#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00000200L 6002#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_HANG_NEED_FLR_INTR_STATUS__MASK 0x00000400L 6003#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__UVD_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00000800L 6004#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_CMD_COMPLETE_INTR_STATUS__MASK 0x00010000L 6005#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_SELF_RECOVERED_INTR_STATUS__MASK 0x00020000L 6006#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_HANG_NEED_FLR_INTR_STATUS__MASK 0x00040000L 6007#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__VCE_VM_BUSY_TRANSITION_INTR_STATUS__MASK 0x00080000L 6008#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__MASK 0x01000000L 6009#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__MASK 0x02000000L 6010//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 6011#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__MASK 0x0001L 6012//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 6013#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__MASK 0x000000FFL 6014#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__MASK 0x00000F00L 6015#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__MASK 0x00008000L 6016#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__MASK 0x000F0000L 6017#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__MASK 0x01000000L 6018//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 6019#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__MASK 0x00000001L 6020#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__MASK 0x00000002L 6021#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__MASK 0x00000004L 6022#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__MASK 0x00000008L 6023#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__MASK 0x00000010L 6024#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__MASK 0x00000020L 6025#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__MASK 0x00000040L 6026#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__MASK 0x00000080L 6027#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__MASK 0x00000100L 6028#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__MASK 0x00000200L 6029#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__MASK 0x00000400L 6030#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__MASK 0x00000800L 6031#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__MASK 0x00001000L 6032#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__MASK 0x00002000L 6033#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__MASK 0x00004000L 6034#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__MASK 0x00008000L 6035#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__MASK 0x00010000L 6036#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__MASK 0x00020000L 6037#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__MASK 0x00040000L 6038#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__MASK 0x00080000L 6039#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__MASK 0x00100000L 6040#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__MASK 0x00200000L 6041#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__MASK 0x00400000L 6042#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__MASK 0x00800000L 6043#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__MASK 0x01000000L 6044#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__MASK 0x02000000L 6045#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__MASK 0x04000000L 6046#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__MASK 0x08000000L 6047#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__MASK 0x10000000L 6048#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__MASK 0x20000000L 6049#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__MASK 0x40000000L 6050#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__MASK 0x80000000L 6051//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 6052#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__MASK 0x00000001L 6053#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__MASK 0x00000002L 6054//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 6055#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_SIZE__MASK 0x0000007FL 6056#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__LOC__MASK 0x00000080L 6057#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT__CONTEXT_OFFSET__MASK 0xFFFFFC00L 6058//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 6059#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__MASK 0x0000FFFFL 6060#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__MASK 0xFFFF0000L 6061//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 6062#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__UVDSCH_OFFSET__MASK 0x000000FFL 6063#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__VCESCH_OFFSET__MASK 0x0000FF00L 6064#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS__GFXSCH_OFFSET__MASK 0x00FF0000L 6065//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 6066#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_SIZE__MASK 0x0000FFFFL 6067#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB__VF0_FB_OFFSET__MASK 0xFFFF0000L 6068//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 6069#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_SIZE__MASK 0x0000FFFFL 6070#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB__VF1_FB_OFFSET__MASK 0xFFFF0000L 6071//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 6072#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_SIZE__MASK 0x0000FFFFL 6073#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB__VF2_FB_OFFSET__MASK 0xFFFF0000L 6074//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 6075#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_SIZE__MASK 0x0000FFFFL 6076#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB__VF3_FB_OFFSET__MASK 0xFFFF0000L 6077//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 6078#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_SIZE__MASK 0x0000FFFFL 6079#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB__VF4_FB_OFFSET__MASK 0xFFFF0000L 6080//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 6081#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_SIZE__MASK 0x0000FFFFL 6082#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB__VF5_FB_OFFSET__MASK 0xFFFF0000L 6083//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 6084#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_SIZE__MASK 0x0000FFFFL 6085#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB__VF6_FB_OFFSET__MASK 0xFFFF0000L 6086//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 6087#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_SIZE__MASK 0x0000FFFFL 6088#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB__VF7_FB_OFFSET__MASK 0xFFFF0000L 6089//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 6090#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_SIZE__MASK 0x0000FFFFL 6091#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB__VF8_FB_OFFSET__MASK 0xFFFF0000L 6092//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 6093#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_SIZE__MASK 0x0000FFFFL 6094#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB__VF9_FB_OFFSET__MASK 0xFFFF0000L 6095//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 6096#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_SIZE__MASK 0x0000FFFFL 6097#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB__VF10_FB_OFFSET__MASK 0xFFFF0000L 6098//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 6099#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_SIZE__MASK 0x0000FFFFL 6100#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB__VF11_FB_OFFSET__MASK 0xFFFF0000L 6101//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 6102#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_SIZE__MASK 0x0000FFFFL 6103#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB__VF12_FB_OFFSET__MASK 0xFFFF0000L 6104//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 6105#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_SIZE__MASK 0x0000FFFFL 6106#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB__VF13_FB_OFFSET__MASK 0xFFFF0000L 6107//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 6108#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_SIZE__MASK 0x0000FFFFL 6109#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB__VF14_FB_OFFSET__MASK 0xFFFF0000L 6110//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 6111#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_SIZE__MASK 0x0000FFFFL 6112#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB__VF15_FB_OFFSET__MASK 0xFFFF0000L 6113//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 6114#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0__DW0__MASK 0xFFFFFFFFL 6115//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 6116#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1__DW1__MASK 0xFFFFFFFFL 6117//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 6118#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2__DW2__MASK 0xFFFFFFFFL 6119//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 6120#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3__DW3__MASK 0xFFFFFFFFL 6121//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 6122#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4__DW4__MASK 0xFFFFFFFFL 6123//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 6124#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5__DW5__MASK 0xFFFFFFFFL 6125//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 6126#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6__DW6__MASK 0xFFFFFFFFL 6127//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 6128#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7__DW7__MASK 0xFFFFFFFFL 6129//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 6130#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0__DW0__MASK 0xFFFFFFFFL 6131//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 6132#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1__DW1__MASK 0xFFFFFFFFL 6133//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 6134#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2__DW2__MASK 0xFFFFFFFFL 6135//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 6136#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3__DW3__MASK 0xFFFFFFFFL 6137//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 6138#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4__DW4__MASK 0xFFFFFFFFL 6139//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 6140#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5__DW5__MASK 0xFFFFFFFFL 6141//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 6142#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6__DW6__MASK 0xFFFFFFFFL 6143//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 6144#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7__DW7__MASK 0xFFFFFFFFL 6145//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 6146#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0__DW0__MASK 0xFFFFFFFFL 6147//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 6148#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1__DW1__MASK 0xFFFFFFFFL 6149//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 6150#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2__DW2__MASK 0xFFFFFFFFL 6151//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 6152#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3__DW3__MASK 0xFFFFFFFFL 6153//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 6154#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4__DW4__MASK 0xFFFFFFFFL 6155//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 6156#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5__DW5__MASK 0xFFFFFFFFL 6157//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 6158#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6__DW6__MASK 0xFFFFFFFFL 6159//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 6160#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7__DW7__MASK 0xFFFFFFFFL 6161 6162 6163// addressBlock: bif_cfg_dev0_swds_bifcfgdecp 6164//SUB_BUS_NUMBER_LATENCY 6165#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__MASK 0x000000FFL 6166#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__MASK 0x0000FF00L 6167#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__MASK 0x00FF0000L 6168#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__MASK 0xFF000000L 6169//IO_BASE_LIMIT 6170#define IO_BASE_LIMIT__IO_BASE_TYPE__MASK 0x000FL 6171#define IO_BASE_LIMIT__IO_BASE__MASK 0x00F0L 6172#define IO_BASE_LIMIT__IO_LIMIT_TYPE__MASK 0x0F00L 6173#define IO_BASE_LIMIT__IO_LIMIT__MASK 0xF000L 6174//SECONDARY_STATUS 6175#define SECONDARY_STATUS__CAP_LIST__MASK 0x0010L 6176#define SECONDARY_STATUS__PCI_66_EN__MASK 0x0020L 6177#define SECONDARY_STATUS__FAST_BACK_CAPABLE__MASK 0x0080L 6178#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__MASK 0x0100L 6179#define SECONDARY_STATUS__DEVSEL_TIMING__MASK 0x0600L 6180#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__MASK 0x0800L 6181#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__MASK 0x1000L 6182#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__MASK 0x2000L 6183#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__MASK 0x4000L 6184#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__MASK 0x8000L 6185//MEM_BASE_LIMIT 6186#define MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL 6187#define MEM_BASE_LIMIT__MEM_BASE_31_20__MASK 0x0000FFF0L 6188#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L 6189#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__MASK 0xFFF00000L 6190//PREF_BASE_LIMIT 6191#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL 6192#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__MASK 0x0000FFF0L 6193#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L 6194#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__MASK 0xFFF00000L 6195//PREF_BASE_UPPER 6196#define PREF_BASE_UPPER__PREF_BASE_UPPER__MASK 0xFFFFFFFFL 6197//PREF_LIMIT_UPPER 6198#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__MASK 0xFFFFFFFFL 6199//IO_BASE_LIMIT_HI 6200#define IO_BASE_LIMIT_HI__IO_BASE_31_16__MASK 0x0000FFFFL 6201#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__MASK 0xFFFF0000L 6202//IRQ_BRIDGE_CNTL 6203#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__MASK 0x0001L 6204#define IRQ_BRIDGE_CNTL__SERR_EN__MASK 0x0002L 6205#define IRQ_BRIDGE_CNTL__ISA_EN__MASK 0x0004L 6206#define IRQ_BRIDGE_CNTL__VGA_EN__MASK 0x0008L 6207#define IRQ_BRIDGE_CNTL__VGA_DEC__MASK 0x0010L 6208#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__MASK 0x0020L 6209#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__MASK 0x0040L 6210#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__MASK 0x0080L 6211//SLOT_CAP 6212#define SLOT_CAP__ATTN_BUTTON_PRESENT__MASK 0x00000001L 6213#define SLOT_CAP__PWR_CONTROLLER_PRESENT__MASK 0x00000002L 6214#define SLOT_CAP__MRL_SENSOR_PRESENT__MASK 0x00000004L 6215#define SLOT_CAP__ATTN_INDICATOR_PRESENT__MASK 0x00000008L 6216#define SLOT_CAP__PWR_INDICATOR_PRESENT__MASK 0x00000010L 6217#define SLOT_CAP__HOTPLUG_SURPRISE__MASK 0x00000020L 6218#define SLOT_CAP__HOTPLUG_CAPABLE__MASK 0x00000040L 6219#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__MASK 0x00007F80L 6220#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__MASK 0x00018000L 6221#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__MASK 0x00020000L 6222#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__MASK 0x00040000L 6223#define SLOT_CAP__PHYSICAL_SLOT_NUM__MASK 0xFFF80000L 6224//SLOT_CNTL 6225#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__MASK 0x0001L 6226#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__MASK 0x0002L 6227#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__MASK 0x0004L 6228#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__MASK 0x0008L 6229#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__MASK 0x0010L 6230#define SLOT_CNTL__HOTPLUG_INTR_EN__MASK 0x0020L 6231#define SLOT_CNTL__ATTN_INDICATOR_CNTL__MASK 0x00C0L 6232#define SLOT_CNTL__PWR_INDICATOR_CNTL__MASK 0x0300L 6233#define SLOT_CNTL__PWR_CONTROLLER_CNTL__MASK 0x0400L 6234#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__MASK 0x0800L 6235#define SLOT_CNTL__DL_STATE_CHANGED_EN__MASK 0x1000L 6236//SLOT_STATUS 6237#define SLOT_STATUS__ATTN_BUTTON_PRESSED__MASK 0x0001L 6238#define SLOT_STATUS__PWR_FAULT_DETECTED__MASK 0x0002L 6239#define SLOT_STATUS__MRL_SENSOR_CHANGED__MASK 0x0004L 6240#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__MASK 0x0008L 6241#define SLOT_STATUS__COMMAND_COMPLETED__MASK 0x0010L 6242#define SLOT_STATUS__MRL_SENSOR_STATE__MASK 0x0020L 6243#define SLOT_STATUS__PRESENCE_DETECT_STATE__MASK 0x0040L 6244#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__MASK 0x0080L 6245#define SLOT_STATUS__DL_STATE_CHANGED__MASK 0x0100L 6246//SSID_CAP_LIST 6247#define SSID_CAP_LIST__CAP_ID__MASK 0x00FFL 6248#define SSID_CAP_LIST__NEXT_PTR__MASK 0xFF00L 6249//SSID_CAP 6250#define SSID_CAP__SUBSYSTEM_VENDOR_ID__MASK 0x0000FFFFL 6251#define SSID_CAP__SUBSYSTEM_ID__MASK 0xFFFF0000L 6252 6253 6254// addressBlock: rcc_shadow_reg_shadowdec 6255//SHADOW_COMMAND 6256#define SHADOW_COMMAND__IOEN_UP__MASK 0x0001L 6257#define SHADOW_COMMAND__MEMEN_UP__MASK 0x0002L 6258//SHADOW_BASE_ADDR_1 6259#define SHADOW_BASE_ADDR_1__BAR1_UP__MASK 0xFFFFFFFFL 6260//SHADOW_BASE_ADDR_2 6261#define SHADOW_BASE_ADDR_2__BAR2_UP__MASK 0xFFFFFFFFL 6262//SHADOW_SUB_BUS_NUMBER_LATENCY 6263#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__MASK 0x0000FF00L 6264#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__MASK 0x00FF0000L 6265//SHADOW_IO_BASE_LIMIT 6266#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__MASK 0x00F0L 6267#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__MASK 0xF000L 6268//SHADOW_MEM_BASE_LIMIT 6269#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__MASK 0x0000000FL 6270#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__MASK 0x0000FFF0L 6271#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__MASK 0x000F0000L 6272#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__MASK 0xFFF00000L 6273//SHADOW_PREF_BASE_LIMIT 6274#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__MASK 0x0000000FL 6275#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__MASK 0x0000FFF0L 6276#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__MASK 0x000F0000L 6277#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__MASK 0xFFF00000L 6278//SHADOW_PREF_BASE_UPPER 6279#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__MASK 0xFFFFFFFFL 6280//SHADOW_PREF_LIMIT_UPPER 6281#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__MASK 0xFFFFFFFFL 6282//SHADOW_IO_BASE_LIMIT_HI 6283#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__MASK 0x0000FFFFL 6284#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__MASK 0xFFFF0000L 6285//SHADOW_IRQ_BRIDGE_CNTL 6286#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__MASK 0x0004L 6287#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__MASK 0x0008L 6288#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__MASK 0x0010L 6289#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__MASK 0x0040L 6290//SUC_INDEX 6291#define SUC_INDEX__SUC_INDEX__MASK 0xFFFFFFFFL 6292//SUC_DATA 6293#define SUC_DATA__SUC_DATA__MASK 0xFFFFFFFFL 6294 6295 6296// addressBlock: bif_bx_pf_SUMDEC 6297//SUM_INDEX 6298#define SUM_INDEX__SUM_INDEX__MASK 0xFFFFFFFFL 6299//SUM_DATA 6300#define SUM_DATA__SUM_DATA__MASK 0xFFFFFFFFL 6301 6302 6303// addressBlock: gdc_GDCDEC 6304//A2S_CNTL_CL0 6305#define A2S_CNTL_CL0__NSNOOP_MAP__MASK 0x00000003L 6306#define A2S_CNTL_CL0__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6307#define A2S_CNTL_CL0__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6308#define A2S_CNTL_CL0__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6309#define A2S_CNTL_CL0__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6310#define A2S_CNTL_CL0__BLKLVL_MAP__MASK 0x00000C00L 6311#define A2S_CNTL_CL0__DATERR_MAP__MASK 0x00003000L 6312#define A2S_CNTL_CL0__EXOKAY_WR_MAP__MASK 0x0000C000L 6313#define A2S_CNTL_CL0__EXOKAY_RD_MAP__MASK 0x00030000L 6314#define A2S_CNTL_CL0__RESP_WR_MAP__MASK 0x000C0000L 6315#define A2S_CNTL_CL0__RESP_RD_MAP__MASK 0x00300000L 6316//A2S_CNTL_CL1 6317#define A2S_CNTL_CL1__NSNOOP_MAP__MASK 0x00000003L 6318#define A2S_CNTL_CL1__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6319#define A2S_CNTL_CL1__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6320#define A2S_CNTL_CL1__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6321#define A2S_CNTL_CL1__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6322#define A2S_CNTL_CL1__BLKLVL_MAP__MASK 0x00000C00L 6323#define A2S_CNTL_CL1__DATERR_MAP__MASK 0x00003000L 6324#define A2S_CNTL_CL1__EXOKAY_WR_MAP__MASK 0x0000C000L 6325#define A2S_CNTL_CL1__EXOKAY_RD_MAP__MASK 0x00030000L 6326#define A2S_CNTL_CL1__RESP_WR_MAP__MASK 0x000C0000L 6327#define A2S_CNTL_CL1__RESP_RD_MAP__MASK 0x00300000L 6328//A2S_CNTL_CL2 6329#define A2S_CNTL_CL2__NSNOOP_MAP__MASK 0x00000003L 6330#define A2S_CNTL_CL2__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6331#define A2S_CNTL_CL2__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6332#define A2S_CNTL_CL2__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6333#define A2S_CNTL_CL2__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6334#define A2S_CNTL_CL2__BLKLVL_MAP__MASK 0x00000C00L 6335#define A2S_CNTL_CL2__DATERR_MAP__MASK 0x00003000L 6336#define A2S_CNTL_CL2__EXOKAY_WR_MAP__MASK 0x0000C000L 6337#define A2S_CNTL_CL2__EXOKAY_RD_MAP__MASK 0x00030000L 6338#define A2S_CNTL_CL2__RESP_WR_MAP__MASK 0x000C0000L 6339#define A2S_CNTL_CL2__RESP_RD_MAP__MASK 0x00300000L 6340//A2S_CNTL_CL3 6341#define A2S_CNTL_CL3__NSNOOP_MAP__MASK 0x00000003L 6342#define A2S_CNTL_CL3__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6343#define A2S_CNTL_CL3__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6344#define A2S_CNTL_CL3__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6345#define A2S_CNTL_CL3__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6346#define A2S_CNTL_CL3__BLKLVL_MAP__MASK 0x00000C00L 6347#define A2S_CNTL_CL3__DATERR_MAP__MASK 0x00003000L 6348#define A2S_CNTL_CL3__EXOKAY_WR_MAP__MASK 0x0000C000L 6349#define A2S_CNTL_CL3__EXOKAY_RD_MAP__MASK 0x00030000L 6350#define A2S_CNTL_CL3__RESP_WR_MAP__MASK 0x000C0000L 6351#define A2S_CNTL_CL3__RESP_RD_MAP__MASK 0x00300000L 6352//A2S_CNTL_CL4 6353#define A2S_CNTL_CL4__NSNOOP_MAP__MASK 0x00000003L 6354#define A2S_CNTL_CL4__REQPASSPW_VC0_MAP__MASK 0x0000000CL 6355#define A2S_CNTL_CL4__REQPASSPW_NVC0_MAP__MASK 0x00000030L 6356#define A2S_CNTL_CL4__REQRSPPASSPW_VC0_MAP__MASK 0x000000C0L 6357#define A2S_CNTL_CL4__REQRSPPASSPW_NVC0_MAP__MASK 0x00000300L 6358#define A2S_CNTL_CL4__BLKLVL_MAP__MASK 0x00000C00L 6359#define A2S_CNTL_CL4__DATERR_MAP__MASK 0x00003000L 6360#define A2S_CNTL_CL4__EXOKAY_WR_MAP__MASK 0x0000C000L 6361#define A2S_CNTL_CL4__EXOKAY_RD_MAP__MASK 0x00030000L 6362#define A2S_CNTL_CL4__RESP_WR_MAP__MASK 0x000C0000L 6363#define A2S_CNTL_CL4__RESP_RD_MAP__MASK 0x00300000L 6364//A2S_CNTL_SW0 6365#define A2S_CNTL_SW0__WR_TAG_SET_MIN__MASK 0x00000007L 6366#define A2S_CNTL_SW0__RD_TAG_SET_MIN__MASK 0x00000038L 6367#define A2S_CNTL_SW0__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6368#define A2S_CNTL_SW0__RSP_REORDER_DIS__MASK 0x00000080L 6369#define A2S_CNTL_SW0__WRRSP_ACCUM_SEL__MASK 0x00000100L 6370#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6371#define A2S_CNTL_SW0__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6372#define A2S_CNTL_SW0__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6373#define A2S_CNTL_SW0__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6374#define A2S_CNTL_SW0__WRR_RD_WEIGHT__MASK 0x00FF0000L 6375#define A2S_CNTL_SW0__WRR_WR_WEIGHT__MASK 0xFF000000L 6376//A2S_CNTL_SW1 6377#define A2S_CNTL_SW1__WR_TAG_SET_MIN__MASK 0x00000007L 6378#define A2S_CNTL_SW1__RD_TAG_SET_MIN__MASK 0x00000038L 6379#define A2S_CNTL_SW1__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6380#define A2S_CNTL_SW1__RSP_REORDER_DIS__MASK 0x00000080L 6381#define A2S_CNTL_SW1__WRRSP_ACCUM_SEL__MASK 0x00000100L 6382#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6383#define A2S_CNTL_SW1__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6384#define A2S_CNTL_SW1__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6385#define A2S_CNTL_SW1__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6386#define A2S_CNTL_SW1__WRR_RD_WEIGHT__MASK 0x00FF0000L 6387#define A2S_CNTL_SW1__WRR_WR_WEIGHT__MASK 0xFF000000L 6388//A2S_CNTL_SW2 6389#define A2S_CNTL_SW2__WR_TAG_SET_MIN__MASK 0x00000007L 6390#define A2S_CNTL_SW2__RD_TAG_SET_MIN__MASK 0x00000038L 6391#define A2S_CNTL_SW2__FORCE_RSP_REORDER_EN__MASK 0x00000040L 6392#define A2S_CNTL_SW2__RSP_REORDER_DIS__MASK 0x00000080L 6393#define A2S_CNTL_SW2__WRRSP_ACCUM_SEL__MASK 0x00000100L 6394#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__MASK 0x00000200L 6395#define A2S_CNTL_SW2__WRRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000400L 6396#define A2S_CNTL_SW2__RDRSP_TAGFIFO_CONT_RD_DIS__MASK 0x00000800L 6397#define A2S_CNTL_SW2__RDRSP_STS_DATSTS_PRIORITY__MASK 0x00001000L 6398#define A2S_CNTL_SW2__WRR_RD_WEIGHT__MASK 0x00FF0000L 6399#define A2S_CNTL_SW2__WRR_WR_WEIGHT__MASK 0xFF000000L 6400//NGDC_MGCG_CTRL 6401#define NGDC_MGCG_CTRL__NGDC_MGCG_EN__MASK 0x00000001L 6402#define NGDC_MGCG_CTRL__NGDC_MGCG_MODE__MASK 0x00000002L 6403#define NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__MASK 0x000003FCL 6404//A2S_MISC_CNTL 6405#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__MASK 0x00000003L 6406#define A2S_MISC_CNTL__RESERVE_2_CRED_FOR_NPWR_REQ_DIS__MASK 0x00000004L 6407//NGDC_SDP_PORT_CTRL 6408#define NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__MASK 0x0000003FL 6409//NGDC_RESERVED_0 6410#define NGDC_RESERVED_0__RESERVED__MASK 0xFFFFFFFFL 6411//NGDC_RESERVED_1 6412#define NGDC_RESERVED_1__RESERVED__MASK 0xFFFFFFFFL 6413//BIF_SDMA0_DOORBELL_RANGE 6414#define BIF_SDMA0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6415#define BIF_SDMA0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6416//BIF_SDMA1_DOORBELL_RANGE 6417#define BIF_SDMA1_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6418#define BIF_SDMA1_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6419//BIF_IH_DOORBELL_RANGE 6420#define BIF_IH_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6421#define BIF_IH_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6422//BIF_MMSCH0_DOORBELL_RANGE 6423#define BIF_MMSCH0_DOORBELL_RANGE__OFFSET__MASK 0x00000FFCL 6424#define BIF_MMSCH0_DOORBELL_RANGE__SIZE__MASK 0x001F0000L 6425//BIF_DOORBELL_FENCE_CNTL 6426#define BIF_DOORBELL_FENCE_CNTL__DOORBELL_FENCE_ENABLE__MASK 0x00000001L 6427//S2A_MISC_CNTL 6428#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA0_DIS__MASK 0x00000001L 6429#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_SDMA1_DIS__MASK 0x00000002L 6430#define S2A_MISC_CNTL__DOORBELL_64BIT_SUPPORT_CP_DIS__MASK 0x00000004L 6431//A2S_CNTL2_SEC_CL0 6432#define A2S_CNTL2_SEC_CL0__SECLVL_MAP__MASK 0x00000007L 6433//A2S_CNTL2_SEC_CL1 6434#define A2S_CNTL2_SEC_CL1__SECLVL_MAP__MASK 0x00000007L 6435//A2S_CNTL2_SEC_CL2 6436#define A2S_CNTL2_SEC_CL2__SECLVL_MAP__MASK 0x00000007L 6437//A2S_CNTL2_SEC_CL3 6438#define A2S_CNTL2_SEC_CL3__SECLVL_MAP__MASK 0x00000007L 6439//A2S_CNTL2_SEC_CL4 6440#define A2S_CNTL2_SEC_CL4__SECLVL_MAP__MASK 0x00000007L 6441 6442 6443// addressBlock: nbif_sion_SIONDEC 6444//SION_CL0_RdRsp_BurstTarget_REG0 6445#define SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6446//SION_CL0_RdRsp_BurstTarget_REG1 6447#define SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6448//SION_CL0_RdRsp_TimeSlot_REG0 6449#define SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6450//SION_CL0_RdRsp_TimeSlot_REG1 6451#define SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6452//SION_CL0_WrRsp_BurstTarget_REG0 6453#define SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6454//SION_CL0_WrRsp_BurstTarget_REG1 6455#define SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6456//SION_CL0_WrRsp_TimeSlot_REG0 6457#define SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6458//SION_CL0_WrRsp_TimeSlot_REG1 6459#define SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6460//SION_CL0_Req_BurstTarget_REG0 6461#define SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6462//SION_CL0_Req_BurstTarget_REG1 6463#define SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6464//SION_CL0_Req_TimeSlot_REG0 6465#define SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6466//SION_CL0_Req_TimeSlot_REG1 6467#define SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6468//SION_CL0_ReqPoolCredit_Alloc_REG0 6469#define SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6470//SION_CL0_ReqPoolCredit_Alloc_REG1 6471#define SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6472//SION_CL0_DataPoolCredit_Alloc_REG0 6473#define SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6474//SION_CL0_DataPoolCredit_Alloc_REG1 6475#define SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6476//SION_CL0_RdRspPoolCredit_Alloc_REG0 6477#define SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6478//SION_CL0_RdRspPoolCredit_Alloc_REG1 6479#define SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6480//SION_CL0_WrRspPoolCredit_Alloc_REG0 6481#define SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6482//SION_CL0_WrRspPoolCredit_Alloc_REG1 6483#define SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6484//SION_CL1_RdRsp_BurstTarget_REG0 6485#define SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6486//SION_CL1_RdRsp_BurstTarget_REG1 6487#define SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6488//SION_CL1_RdRsp_TimeSlot_REG0 6489#define SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6490//SION_CL1_RdRsp_TimeSlot_REG1 6491#define SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6492//SION_CL1_WrRsp_BurstTarget_REG0 6493#define SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6494//SION_CL1_WrRsp_BurstTarget_REG1 6495#define SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6496//SION_CL1_WrRsp_TimeSlot_REG0 6497#define SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6498//SION_CL1_WrRsp_TimeSlot_REG1 6499#define SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6500//SION_CL1_Req_BurstTarget_REG0 6501#define SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6502//SION_CL1_Req_BurstTarget_REG1 6503#define SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6504//SION_CL1_Req_TimeSlot_REG0 6505#define SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6506//SION_CL1_Req_TimeSlot_REG1 6507#define SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6508//SION_CL1_ReqPoolCredit_Alloc_REG0 6509#define SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6510//SION_CL1_ReqPoolCredit_Alloc_REG1 6511#define SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6512//SION_CL1_DataPoolCredit_Alloc_REG0 6513#define SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6514//SION_CL1_DataPoolCredit_Alloc_REG1 6515#define SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6516//SION_CL1_RdRspPoolCredit_Alloc_REG0 6517#define SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6518//SION_CL1_RdRspPoolCredit_Alloc_REG1 6519#define SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6520//SION_CL1_WrRspPoolCredit_Alloc_REG0 6521#define SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6522//SION_CL1_WrRspPoolCredit_Alloc_REG1 6523#define SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6524//SION_CL2_RdRsp_BurstTarget_REG0 6525#define SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6526//SION_CL2_RdRsp_BurstTarget_REG1 6527#define SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6528//SION_CL2_RdRsp_TimeSlot_REG0 6529#define SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6530//SION_CL2_RdRsp_TimeSlot_REG1 6531#define SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6532//SION_CL2_WrRsp_BurstTarget_REG0 6533#define SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6534//SION_CL2_WrRsp_BurstTarget_REG1 6535#define SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6536//SION_CL2_WrRsp_TimeSlot_REG0 6537#define SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6538//SION_CL2_WrRsp_TimeSlot_REG1 6539#define SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6540//SION_CL2_Req_BurstTarget_REG0 6541#define SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6542//SION_CL2_Req_BurstTarget_REG1 6543#define SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6544//SION_CL2_Req_TimeSlot_REG0 6545#define SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6546//SION_CL2_Req_TimeSlot_REG1 6547#define SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6548//SION_CL2_ReqPoolCredit_Alloc_REG0 6549#define SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6550//SION_CL2_ReqPoolCredit_Alloc_REG1 6551#define SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6552//SION_CL2_DataPoolCredit_Alloc_REG0 6553#define SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6554//SION_CL2_DataPoolCredit_Alloc_REG1 6555#define SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6556//SION_CL2_RdRspPoolCredit_Alloc_REG0 6557#define SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6558//SION_CL2_RdRspPoolCredit_Alloc_REG1 6559#define SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6560//SION_CL2_WrRspPoolCredit_Alloc_REG0 6561#define SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6562//SION_CL2_WrRspPoolCredit_Alloc_REG1 6563#define SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6564//SION_CL3_RdRsp_BurstTarget_REG0 6565#define SION_CL3_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6566//SION_CL3_RdRsp_BurstTarget_REG1 6567#define SION_CL3_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6568//SION_CL3_RdRsp_TimeSlot_REG0 6569#define SION_CL3_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6570//SION_CL3_RdRsp_TimeSlot_REG1 6571#define SION_CL3_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6572//SION_CL3_WrRsp_BurstTarget_REG0 6573#define SION_CL3_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6574//SION_CL3_WrRsp_BurstTarget_REG1 6575#define SION_CL3_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6576//SION_CL3_WrRsp_TimeSlot_REG0 6577#define SION_CL3_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6578//SION_CL3_WrRsp_TimeSlot_REG1 6579#define SION_CL3_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6580//SION_CL3_Req_BurstTarget_REG0 6581#define SION_CL3_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6582//SION_CL3_Req_BurstTarget_REG1 6583#define SION_CL3_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6584//SION_CL3_Req_TimeSlot_REG0 6585#define SION_CL3_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6586//SION_CL3_Req_TimeSlot_REG1 6587#define SION_CL3_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6588//SION_CL3_ReqPoolCredit_Alloc_REG0 6589#define SION_CL3_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6590//SION_CL3_ReqPoolCredit_Alloc_REG1 6591#define SION_CL3_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6592//SION_CL3_DataPoolCredit_Alloc_REG0 6593#define SION_CL3_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6594//SION_CL3_DataPoolCredit_Alloc_REG1 6595#define SION_CL3_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6596//SION_CL3_RdRspPoolCredit_Alloc_REG0 6597#define SION_CL3_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6598//SION_CL3_RdRspPoolCredit_Alloc_REG1 6599#define SION_CL3_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6600//SION_CL3_WrRspPoolCredit_Alloc_REG0 6601#define SION_CL3_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6602//SION_CL3_WrRspPoolCredit_Alloc_REG1 6603#define SION_CL3_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6604//SION_CL4_RdRsp_BurstTarget_REG0 6605#define SION_CL4_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6606//SION_CL4_RdRsp_BurstTarget_REG1 6607#define SION_CL4_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6608//SION_CL4_RdRsp_TimeSlot_REG0 6609#define SION_CL4_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6610//SION_CL4_RdRsp_TimeSlot_REG1 6611#define SION_CL4_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6612//SION_CL4_WrRsp_BurstTarget_REG0 6613#define SION_CL4_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6614//SION_CL4_WrRsp_BurstTarget_REG1 6615#define SION_CL4_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6616//SION_CL4_WrRsp_TimeSlot_REG0 6617#define SION_CL4_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6618//SION_CL4_WrRsp_TimeSlot_REG1 6619#define SION_CL4_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6620//SION_CL4_Req_BurstTarget_REG0 6621#define SION_CL4_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6622//SION_CL4_Req_BurstTarget_REG1 6623#define SION_CL4_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6624//SION_CL4_Req_TimeSlot_REG0 6625#define SION_CL4_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6626//SION_CL4_Req_TimeSlot_REG1 6627#define SION_CL4_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6628//SION_CL4_ReqPoolCredit_Alloc_REG0 6629#define SION_CL4_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6630//SION_CL4_ReqPoolCredit_Alloc_REG1 6631#define SION_CL4_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6632//SION_CL4_DataPoolCredit_Alloc_REG0 6633#define SION_CL4_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6634//SION_CL4_DataPoolCredit_Alloc_REG1 6635#define SION_CL4_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6636//SION_CL4_RdRspPoolCredit_Alloc_REG0 6637#define SION_CL4_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6638//SION_CL4_RdRspPoolCredit_Alloc_REG1 6639#define SION_CL4_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6640//SION_CL4_WrRspPoolCredit_Alloc_REG0 6641#define SION_CL4_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6642//SION_CL4_WrRspPoolCredit_Alloc_REG1 6643#define SION_CL4_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6644//SION_CL5_RdRsp_BurstTarget_REG0 6645#define SION_CL5_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6646//SION_CL5_RdRsp_BurstTarget_REG1 6647#define SION_CL5_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6648//SION_CL5_RdRsp_TimeSlot_REG0 6649#define SION_CL5_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6650//SION_CL5_RdRsp_TimeSlot_REG1 6651#define SION_CL5_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6652//SION_CL5_WrRsp_BurstTarget_REG0 6653#define SION_CL5_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__MASK 0xFFFFFFFFL 6654//SION_CL5_WrRsp_BurstTarget_REG1 6655#define SION_CL5_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__MASK 0xFFFFFFFFL 6656//SION_CL5_WrRsp_TimeSlot_REG0 6657#define SION_CL5_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__MASK 0xFFFFFFFFL 6658//SION_CL5_WrRsp_TimeSlot_REG1 6659#define SION_CL5_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__MASK 0xFFFFFFFFL 6660//SION_CL5_Req_BurstTarget_REG0 6661#define SION_CL5_Req_BurstTarget_REG0__Req_BurstTarget_31_0__MASK 0xFFFFFFFFL 6662//SION_CL5_Req_BurstTarget_REG1 6663#define SION_CL5_Req_BurstTarget_REG1__Req_BurstTarget_63_32__MASK 0xFFFFFFFFL 6664//SION_CL5_Req_TimeSlot_REG0 6665#define SION_CL5_Req_TimeSlot_REG0__Req_TimeSlot_31_0__MASK 0xFFFFFFFFL 6666//SION_CL5_Req_TimeSlot_REG1 6667#define SION_CL5_Req_TimeSlot_REG1__Req_TimeSlot_63_32__MASK 0xFFFFFFFFL 6668//SION_CL5_ReqPoolCredit_Alloc_REG0 6669#define SION_CL5_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6670//SION_CL5_ReqPoolCredit_Alloc_REG1 6671#define SION_CL5_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6672//SION_CL5_DataPoolCredit_Alloc_REG0 6673#define SION_CL5_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6674//SION_CL5_DataPoolCredit_Alloc_REG1 6675#define SION_CL5_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6676//SION_CL5_RdRspPoolCredit_Alloc_REG0 6677#define SION_CL5_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6678//SION_CL5_RdRspPoolCredit_Alloc_REG1 6679#define SION_CL5_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6680//SION_CL5_WrRspPoolCredit_Alloc_REG0 6681#define SION_CL5_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__MASK 0xFFFFFFFFL 6682//SION_CL5_WrRspPoolCredit_Alloc_REG1 6683#define SION_CL5_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__MASK 0xFFFFFFFFL 6684//SION_CNTL_REG0 6685#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__MASK 0x00000001L 6686#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__MASK 0x00000002L 6687#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__MASK 0x00000004L 6688#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__MASK 0x00000008L 6689#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__MASK 0x00000010L 6690#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__MASK 0x00000020L 6691#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__MASK 0x00000040L 6692#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__MASK 0x00000080L 6693#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__MASK 0x00000100L 6694#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__MASK 0x00000200L 6695#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__MASK 0x00000400L 6696#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__MASK 0x00000800L 6697#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__MASK 0x00001000L 6698#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__MASK 0x00002000L 6699#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__MASK 0x00004000L 6700#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__MASK 0x00008000L 6701#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__MASK 0x00010000L 6702#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__MASK 0x00020000L 6703#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__MASK 0x00040000L 6704#define SION_CNTL_REG0__NBIFSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__MASK 0x00080000L 6705//SION_CNTL_REG1 6706#define SION_CNTL_REG1__LIVELOCK_WATCHDOG_THRESHOLD__MASK 0x000000FFL 6707#define SION_CNTL_REG1__CG_OFF_HYSTERESIS__MASK 0x0000FF00L 6708 6709 6710// addressBlock: syshub_mmreg_direct_syshubdirect 6711//SYSHUB_DS_CTRL_SOCCLK 6712#define SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 6713#define SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 6714#define SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 6715#define SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 6716#define SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 6717#define SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 6718#define SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 6719#define SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 6720#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 6721#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 6722#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 6723#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 6724#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 6725#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 6726#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 6727#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 6728#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 6729#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L 6730//SYSHUB_DS_CTRL2_SOCCLK 6731#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL 6732//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 6733#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L 6734#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L 6735#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L 6736#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L 6737#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L 6738//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 6739#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L 6740#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L 6741#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L 6742#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L 6743#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L 6744//DMA_CLK0_SW0_SYSHUB_QOS_CNTL 6745#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6746#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6747#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6748//DMA_CLK0_SW1_SYSHUB_QOS_CNTL 6749#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6750#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6751#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6752//DMA_CLK0_SW0_CL0_CNTL 6753#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6754#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6755#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6756#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6757#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6758#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6759//DMA_CLK0_SW0_CL1_CNTL 6760#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6761#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6762#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6763#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6764#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6765#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6766//DMA_CLK0_SW0_CL2_CNTL 6767#define DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6768#define DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6769#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6770#define DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6771#define DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6772#define DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6773//DMA_CLK0_SW0_CL3_CNTL 6774#define DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6775#define DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6776#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6777#define DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6778#define DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6779#define DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6780//DMA_CLK0_SW0_CL4_CNTL 6781#define DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6782#define DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6783#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6784#define DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6785#define DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6786#define DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6787//DMA_CLK0_SW0_CL5_CNTL 6788#define DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6789#define DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6790#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6791#define DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6792#define DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6793#define DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6794//DMA_CLK0_SW1_CL0_CNTL 6795#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6796#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6797#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6798#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6799#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6800#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6801//DMA_CLK0_SW2_CL0_CNTL 6802#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6803#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6804#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6805#define DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6806#define DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6807#define DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6808//SYSHUB_CG_CNTL 6809#define SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L 6810#define SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L 6811#define SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L 6812//SYSHUB_TRANS_IDLE 6813#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L 6814#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L 6815#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L 6816#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L 6817#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L 6818#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L 6819#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L 6820#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L 6821#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L 6822#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L 6823#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L 6824#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L 6825#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L 6826#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L 6827#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L 6828#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L 6829#define SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L 6830//SYSHUB_HP_TIMER 6831#define SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL 6832//SYSHUB_SCRATCH 6833#define SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL 6834//SYSHUB_DS_CTRL_SHUBCLK 6835#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 6836#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 6837#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 6838#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 6839#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 6840#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 6841#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 6842#define SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 6843#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 6844#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 6845#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 6846#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 6847#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 6848#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 6849#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 6850#define SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 6851#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 6852#define SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L 6853//SYSHUB_DS_CTRL2_SHUBCLK 6854#define SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL 6855//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 6856#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L 6857#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L 6858//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 6859#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L 6860#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L 6861//DMA_CLK1_SW0_SYSHUB_QOS_CNTL 6862#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6863#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6864#define DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6865//DMA_CLK1_SW1_SYSHUB_QOS_CNTL 6866#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 6867#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 6868#define DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 6869//DMA_CLK1_SW0_CL0_CNTL 6870#define DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6871#define DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6872#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6873#define DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6874#define DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6875#define DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6876//DMA_CLK1_SW0_CL1_CNTL 6877#define DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6878#define DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6879#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6880#define DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6881#define DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6882#define DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6883//DMA_CLK1_SW0_CL2_CNTL 6884#define DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6885#define DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6886#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6887#define DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6888#define DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6889#define DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6890//DMA_CLK1_SW0_CL3_CNTL 6891#define DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6892#define DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6893#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6894#define DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6895#define DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6896#define DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6897//DMA_CLK1_SW0_CL4_CNTL 6898#define DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6899#define DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6900#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6901#define DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6902#define DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6903#define DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6904//DMA_CLK1_SW1_CL0_CNTL 6905#define DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6906#define DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6907#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6908#define DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6909#define DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6910#define DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6911//DMA_CLK1_SW1_CL1_CNTL 6912#define DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6913#define DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6914#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6915#define DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6916#define DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6917#define DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6918//DMA_CLK1_SW1_CL2_CNTL 6919#define DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6920#define DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6921#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6922#define DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6923#define DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6924#define DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6925//DMA_CLK1_SW1_CL3_CNTL 6926#define DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6927#define DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6928#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6929#define DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6930#define DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6931#define DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6932//DMA_CLK1_SW1_CL4_CNTL 6933#define DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 6934#define DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 6935#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 6936#define DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 6937#define DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 6938#define DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 6939 6940 6941// addressBlock: gdc_ras_gdc_ras_regblk 6942//GDC_RAS_LEAF0_CTRL 6943#define GDC_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L 6944#define GDC_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6945#define GDC_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L 6946#define GDC_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L 6947#define GDC_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6948#define GDC_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6949#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6950#define GDC_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6951#define GDC_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L 6952#define GDC_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6953#define GDC_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6954#define GDC_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L 6955//GDC_RAS_LEAF1_CTRL 6956#define GDC_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L 6957#define GDC_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6958#define GDC_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L 6959#define GDC_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L 6960#define GDC_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6961#define GDC_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6962#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6963#define GDC_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6964#define GDC_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L 6965#define GDC_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6966#define GDC_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6967#define GDC_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L 6968//GDC_RAS_LEAF2_CTRL 6969#define GDC_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L 6970#define GDC_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6971#define GDC_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L 6972#define GDC_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L 6973#define GDC_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6974#define GDC_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6975#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6976#define GDC_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6977#define GDC_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L 6978#define GDC_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6979#define GDC_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6980#define GDC_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L 6981//GDC_RAS_LEAF3_CTRL 6982#define GDC_RAS_LEAF3_CTRL__POISON_DET_EN__MASK 0x00000001L 6983#define GDC_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6984#define GDC_RAS_LEAF3_CTRL__POISON_STALL_EN__MASK 0x00000004L 6985#define GDC_RAS_LEAF3_CTRL__PARITY_DET_EN__MASK 0x00000010L 6986#define GDC_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 6987#define GDC_RAS_LEAF3_CTRL__PARITY_STALL_EN__MASK 0x00000040L 6988#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 6989#define GDC_RAS_LEAF3_CTRL__LINK_DIS_RECV__MASK 0x00020000L 6990#define GDC_RAS_LEAF3_CTRL__POISON_ERR_DET__MASK 0x00040000L 6991#define GDC_RAS_LEAF3_CTRL__PARITY_ERR_DET__MASK 0x00080000L 6992#define GDC_RAS_LEAF3_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 6993#define GDC_RAS_LEAF3_CTRL__EGRESS_STALLED__MASK 0x00200000L 6994//GDC_RAS_LEAF4_CTRL 6995#define GDC_RAS_LEAF4_CTRL__POISON_DET_EN__MASK 0x00000001L 6996#define GDC_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 6997#define GDC_RAS_LEAF4_CTRL__POISON_STALL_EN__MASK 0x00000004L 6998#define GDC_RAS_LEAF4_CTRL__PARITY_DET_EN__MASK 0x00000010L 6999#define GDC_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 7000#define GDC_RAS_LEAF4_CTRL__PARITY_STALL_EN__MASK 0x00000040L 7001#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 7002#define GDC_RAS_LEAF4_CTRL__LINK_DIS_RECV__MASK 0x00020000L 7003#define GDC_RAS_LEAF4_CTRL__POISON_ERR_DET__MASK 0x00040000L 7004#define GDC_RAS_LEAF4_CTRL__PARITY_ERR_DET__MASK 0x00080000L 7005#define GDC_RAS_LEAF4_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 7006#define GDC_RAS_LEAF4_CTRL__EGRESS_STALLED__MASK 0x00200000L 7007//GDC_RAS_LEAF5_CTRL 7008#define GDC_RAS_LEAF5_CTRL__POISON_DET_EN__MASK 0x00000001L 7009#define GDC_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 7010#define GDC_RAS_LEAF5_CTRL__POISON_STALL_EN__MASK 0x00000004L 7011#define GDC_RAS_LEAF5_CTRL__PARITY_DET_EN__MASK 0x00000010L 7012#define GDC_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 7013#define GDC_RAS_LEAF5_CTRL__PARITY_STALL_EN__MASK 0x00000040L 7014#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 7015#define GDC_RAS_LEAF5_CTRL__LINK_DIS_RECV__MASK 0x00020000L 7016#define GDC_RAS_LEAF5_CTRL__POISON_ERR_DET__MASK 0x00040000L 7017#define GDC_RAS_LEAF5_CTRL__PARITY_ERR_DET__MASK 0x00080000L 7018#define GDC_RAS_LEAF5_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 7019#define GDC_RAS_LEAF5_CTRL__EGRESS_STALLED__MASK 0x00200000L 7020 7021 7022// addressBlock: gdc_rst_GDCRST_DEC 7023//SHUB_PF_FLR_RST 7024#define SHUB_PF_FLR_RST__PF0_FLR_RST__MASK 0x00000001L 7025#define SHUB_PF_FLR_RST__PF1_FLR_RST__MASK 0x00000002L 7026#define SHUB_PF_FLR_RST__PF2_FLR_RST__MASK 0x00000004L 7027#define SHUB_PF_FLR_RST__PF3_FLR_RST__MASK 0x00000008L 7028#define SHUB_PF_FLR_RST__PF4_FLR_RST__MASK 0x00000010L 7029#define SHUB_PF_FLR_RST__PF5_FLR_RST__MASK 0x00000020L 7030#define SHUB_PF_FLR_RST__PF6_FLR_RST__MASK 0x00000040L 7031#define SHUB_PF_FLR_RST__PF7_FLR_RST__MASK 0x00000080L 7032//SHUB_GFX_DRV_MODE1_RST 7033#define SHUB_GFX_DRV_MODE1_RST__GFX_DRV_MODE1_RST__MASK 0x00000001L 7034//SHUB_LINK_RESET 7035#define SHUB_LINK_RESET__LINK_RESET__MASK 0x00000001L 7036//SHUB_PF0_VF_FLR_RST 7037#define SHUB_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L 7038#define SHUB_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L 7039#define SHUB_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L 7040#define SHUB_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L 7041#define SHUB_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L 7042#define SHUB_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L 7043#define SHUB_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L 7044#define SHUB_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L 7045#define SHUB_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L 7046#define SHUB_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L 7047#define SHUB_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L 7048#define SHUB_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L 7049#define SHUB_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L 7050#define SHUB_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L 7051#define SHUB_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L 7052#define SHUB_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L 7053#define SHUB_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L 7054//SHUB_HARD_RST_CTRL 7055#define SHUB_HARD_RST_CTRL__COR_RESET_EN__MASK 0x00000001L 7056#define SHUB_HARD_RST_CTRL__REG_RESET_EN__MASK 0x00000002L 7057#define SHUB_HARD_RST_CTRL__STY_RESET_EN__MASK 0x00000004L 7058#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L 7059#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L 7060//SHUB_SOFT_RST_CTRL 7061#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__MASK 0x00000001L 7062#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__MASK 0x00000002L 7063#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__MASK 0x00000004L 7064#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__MASK 0x00000008L 7065#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__MASK 0x00000010L 7066//SHUB_SDP_PORT_RST 7067#define SHUB_SDP_PORT_RST__SDP_PORT_RST__MASK 0x00000001L 7068 7069 7070// addressBlock: bif_bx_pf_SYSDEC 7071//SBIOS_SCRATCH_0 7072#define SBIOS_SCRATCH_0__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7073//SBIOS_SCRATCH_1 7074#define SBIOS_SCRATCH_1__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7075//SBIOS_SCRATCH_2 7076#define SBIOS_SCRATCH_2__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7077//SBIOS_SCRATCH_3 7078#define SBIOS_SCRATCH_3__SBIOS_SCRATCH_DW__MASK 0xFFFFFFFFL 7079//BIOS_SCRATCH_0 7080#define BIOS_SCRATCH_0__BIOS_SCRATCH_0__MASK 0xFFFFFFFFL 7081//BIOS_SCRATCH_1 7082#define BIOS_SCRATCH_1__BIOS_SCRATCH_1__MASK 0xFFFFFFFFL 7083//BIOS_SCRATCH_2 7084#define BIOS_SCRATCH_2__BIOS_SCRATCH_2__MASK 0xFFFFFFFFL 7085//BIOS_SCRATCH_3 7086#define BIOS_SCRATCH_3__BIOS_SCRATCH_3__MASK 0xFFFFFFFFL 7087//BIOS_SCRATCH_4 7088#define BIOS_SCRATCH_4__BIOS_SCRATCH_4__MASK 0xFFFFFFFFL 7089//BIOS_SCRATCH_5 7090#define BIOS_SCRATCH_5__BIOS_SCRATCH_5__MASK 0xFFFFFFFFL 7091//BIOS_SCRATCH_6 7092#define BIOS_SCRATCH_6__BIOS_SCRATCH_6__MASK 0xFFFFFFFFL 7093//BIOS_SCRATCH_7 7094#define BIOS_SCRATCH_7__BIOS_SCRATCH_7__MASK 0xFFFFFFFFL 7095//BIOS_SCRATCH_8 7096#define BIOS_SCRATCH_8__BIOS_SCRATCH_8__MASK 0xFFFFFFFFL 7097//BIOS_SCRATCH_9 7098#define BIOS_SCRATCH_9__BIOS_SCRATCH_9__MASK 0xFFFFFFFFL 7099//BIOS_SCRATCH_10 7100#define BIOS_SCRATCH_10__BIOS_SCRATCH_10__MASK 0xFFFFFFFFL 7101//BIOS_SCRATCH_11 7102#define BIOS_SCRATCH_11__BIOS_SCRATCH_11__MASK 0xFFFFFFFFL 7103//BIOS_SCRATCH_12 7104#define BIOS_SCRATCH_12__BIOS_SCRATCH_12__MASK 0xFFFFFFFFL 7105//BIOS_SCRATCH_13 7106#define BIOS_SCRATCH_13__BIOS_SCRATCH_13__MASK 0xFFFFFFFFL 7107//BIOS_SCRATCH_14 7108#define BIOS_SCRATCH_14__BIOS_SCRATCH_14__MASK 0xFFFFFFFFL 7109//BIOS_SCRATCH_15 7110#define BIOS_SCRATCH_15__BIOS_SCRATCH_15__MASK 0xFFFFFFFFL 7111//BIF_RLC_INTR_CNTL 7112#define BIF_RLC_INTR_CNTL__RLC_CMD_COMPLETE__MASK 0x00000001L 7113#define BIF_RLC_INTR_CNTL__RLC_HANG_SELF_RECOVERED__MASK 0x00000002L 7114#define BIF_RLC_INTR_CNTL__RLC_HANG_NEED_FLR__MASK 0x00000004L 7115#define BIF_RLC_INTR_CNTL__RLC_VM_BUSY_TRANSITION__MASK 0x00000008L 7116//BIF_VCE_INTR_CNTL 7117#define BIF_VCE_INTR_CNTL__VCE_CMD_COMPLETE__MASK 0x00000001L 7118#define BIF_VCE_INTR_CNTL__VCE_HANG_SELF_RECOVERED__MASK 0x00000002L 7119#define BIF_VCE_INTR_CNTL__VCE_HANG_NEED_FLR__MASK 0x00000004L 7120#define BIF_VCE_INTR_CNTL__VCE_VM_BUSY_TRANSITION__MASK 0x00000008L 7121//BIF_UVD_INTR_CNTL 7122#define BIF_UVD_INTR_CNTL__UVD_CMD_COMPLETE__MASK 0x00000001L 7123#define BIF_UVD_INTR_CNTL__UVD_HANG_SELF_RECOVERED__MASK 0x00000002L 7124#define BIF_UVD_INTR_CNTL__UVD_HANG_NEED_FLR__MASK 0x00000004L 7125#define BIF_UVD_INTR_CNTL__UVD_VM_BUSY_TRANSITION__MASK 0x00000008L 7126//GFX_MMIOREG_CAM_ADDR0 7127#define GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__MASK 0x000FFFFFL 7128//GFX_MMIOREG_CAM_REMAP_ADDR0 7129#define GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__MASK 0x000FFFFFL 7130//GFX_MMIOREG_CAM_ADDR1 7131#define GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__MASK 0x000FFFFFL 7132//GFX_MMIOREG_CAM_REMAP_ADDR1 7133#define GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__MASK 0x000FFFFFL 7134//GFX_MMIOREG_CAM_ADDR2 7135#define GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__MASK 0x000FFFFFL 7136//GFX_MMIOREG_CAM_REMAP_ADDR2 7137#define GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__MASK 0x000FFFFFL 7138//GFX_MMIOREG_CAM_ADDR3 7139#define GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__MASK 0x000FFFFFL 7140//GFX_MMIOREG_CAM_REMAP_ADDR3 7141#define GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__MASK 0x000FFFFFL 7142//GFX_MMIOREG_CAM_ADDR4 7143#define GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__MASK 0x000FFFFFL 7144//GFX_MMIOREG_CAM_REMAP_ADDR4 7145#define GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__MASK 0x000FFFFFL 7146//GFX_MMIOREG_CAM_ADDR5 7147#define GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__MASK 0x000FFFFFL 7148//GFX_MMIOREG_CAM_REMAP_ADDR5 7149#define GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__MASK 0x000FFFFFL 7150//GFX_MMIOREG_CAM_ADDR6 7151#define GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__MASK 0x000FFFFFL 7152//GFX_MMIOREG_CAM_REMAP_ADDR6 7153#define GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__MASK 0x000FFFFFL 7154//GFX_MMIOREG_CAM_ADDR7 7155#define GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__MASK 0x000FFFFFL 7156//GFX_MMIOREG_CAM_REMAP_ADDR7 7157#define GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__MASK 0x000FFFFFL 7158//GFX_MMIOREG_CAM_CNTL 7159#define GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__MASK 0x000000FFL 7160//GFX_MMIOREG_CAM_ZERO_CPL 7161#define GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__MASK 0xFFFFFFFFL 7162//GFX_MMIOREG_CAM_ONE_CPL 7163#define GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__MASK 0xFFFFFFFFL 7164//GFX_MMIOREG_CAM_PROGRAMMABLE_CPL 7165#define GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__MASK 0xFFFFFFFFL 7166 7167 7168// addressBlock: bif_bx_pf_SYSPFVFDEC 7169//MM_INDEX 7170#define MM_INDEX__MM_OFFSET__MASK 0x7FFFFFFFL 7171#define MM_INDEX__MM_APER__MASK 0x80000000L 7172//MM_DATA 7173#define MM_DATA__MM_DATA__MASK 0xFFFFFFFFL 7174//MM_INDEX_HI 7175#define MM_INDEX_HI__MM_OFFSET_HI__MASK 0xFFFFFFFFL 7176//SYSHUB_INDEX_OVLP 7177#define SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__MASK 0x003FFFFFL 7178//SYSHUB_DATA_OVLP 7179#define SYSHUB_DATA_OVLP__SYSHUB_DATA__MASK 0xFFFFFFFFL 7180//PCIE_INDEX 7181#define PCIE_INDEX__PCIE_INDEX__MASK 0xFFFFFFFFL 7182//PCIE_DATA 7183#define PCIE_DATA__PCIE_DATA__MASK 0xFFFFFFFFL 7184//PCIE_INDEX2 7185#define PCIE_INDEX2__PCIE_INDEX2__MASK 0xFFFFFFFFL 7186//PCIE_DATA2 7187#define PCIE_DATA2__PCIE_DATA2__MASK 0xFFFFFFFFL 7188 7189 7190// addressBlock: rcc_dwn_BIFDEC1 7191//DN_PCIE_RESERVED 7192#define DN_PCIE_RESERVED__PCIE_RESERVED__MASK 0xFFFFFFFFL 7193//DN_PCIE_SCRATCH 7194#define DN_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL 7195//DN_PCIE_CNTL 7196#define DN_PCIE_CNTL__HWINIT_WR_LOCK__MASK 0x00000001L 7197#define DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__MASK 0x00000080L 7198#define DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L 7199//DN_PCIE_CONFIG_CNTL 7200#define DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__MASK 0x06000000L 7201//DN_PCIE_RX_CNTL2 7202#define DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__MASK 0x70000000L 7203//DN_PCIE_BUS_CNTL 7204#define DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L 7205#define DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__MASK 0x00000100L 7206//DN_PCIE_CFG_CNTL 7207#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L 7208#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L 7209#define DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L 7210//DN_PCIE_STRAP_F0 7211#define DN_PCIE_STRAP_F0__STRAP_F0_EN__MASK 0x00000001L 7212#define DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__MASK 0x00020000L 7213#define DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__MASK 0x00E00000L 7214//DN_PCIE_STRAP_MISC 7215#define DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__MASK 0x01000000L 7216#define DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L 7217//DN_PCIE_STRAP_MISC2 7218#define DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__MASK 0x00000004L 7219 7220 7221// addressBlock: rcc_dwnp_BIFDEC1 7222//PCIEP_RESERVED 7223#define PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL 7224//PCIEP_SCRATCH 7225#define PCIEP_SCRATCH__PCIEP_SCRATCH__MASK 0xFFFFFFFFL 7226//PCIE_ERR_CNTL 7227#define PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L 7228#define PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L 7229#define PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x00000800L 7230#define PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L 7231//PCIE_RX_CNTL 7232#define PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L 7233#define PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__MASK 0x00000200L 7234#define PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L 7235#define PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__MASK 0x00200000L 7236#define PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__MASK 0x08000000L 7237//PCIE_LC_SPEED_CNTL 7238#define PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L 7239#define PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L 7240//PCIE_LC_CNTL2 7241#define PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__MASK 0x08000000L 7242//PCIEP_STRAP_MISC 7243#define PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__MASK 0x00000400L 7244//LTR_MSG_INFO_FROM_EP 7245#define LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__MASK 0xFFFFFFFFL 7246 7247 7248// addressBlock: rcc_ep_BIFDEC1 7249//EP_PCIE_SCRATCH 7250#define EP_PCIE_SCRATCH__PCIE_SCRATCH__MASK 0xFFFFFFFFL 7251//EP_PCIE_CNTL 7252#define EP_PCIE_CNTL__UR_ERR_REPORT_DIS__MASK 0x00000080L 7253#define EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__MASK 0x00000100L 7254#define EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__MASK 0x40000000L 7255//EP_PCIE_INT_CNTL 7256#define EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__MASK 0x00000001L 7257#define EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__MASK 0x00000002L 7258#define EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__MASK 0x00000004L 7259#define EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__MASK 0x00000008L 7260#define EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__MASK 0x00000010L 7261#define EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__MASK 0x00000040L 7262//EP_PCIE_INT_STATUS 7263#define EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__MASK 0x00000001L 7264#define EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__MASK 0x00000002L 7265#define EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__MASK 0x00000004L 7266#define EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__MASK 0x00000008L 7267#define EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__MASK 0x00000010L 7268#define EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__MASK 0x00000040L 7269//EP_PCIE_RX_CNTL2 7270#define EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__MASK 0x00000001L 7271//EP_PCIE_BUS_CNTL 7272#define EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__MASK 0x00000080L 7273//EP_PCIE_CFG_CNTL 7274#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__MASK 0x00000001L 7275#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__MASK 0x00000002L 7276#define EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__MASK 0x00000004L 7277//EP_PCIE_OBFF_CNTL 7278#define EP_PCIE_OBFF_CNTL__TX_OBFF_PRIV_DISABLE__MASK 0x00000001L 7279#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SIMPLE_MODE_EN__MASK 0x00000002L 7280#define EP_PCIE_OBFF_CNTL__TX_OBFF_HOSTMEM_TO_ACTIVE__MASK 0x00000004L 7281#define EP_PCIE_OBFF_CNTL__TX_OBFF_SLVCPL_TO_ACTIVE__MASK 0x00000008L 7282#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_PULSE_WIDTH__MASK 0x000000F0L 7283#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_MAX_TWO_FALLING_WIDTH__MASK 0x00000F00L 7284#define EP_PCIE_OBFF_CNTL__TX_OBFF_WAKE_SAMPLING_PERIOD__MASK 0x0000F000L 7285#define EP_PCIE_OBFF_CNTL__TX_OBFF_INTR_TO_ACTIVE__MASK 0x00010000L 7286#define EP_PCIE_OBFF_CNTL__TX_OBFF_ERR_TO_ACTIVE__MASK 0x00020000L 7287#define EP_PCIE_OBFF_CNTL__TX_OBFF_ANY_MSG_TO_ACTIVE__MASK 0x00040000L 7288#define EP_PCIE_OBFF_CNTL__TX_OBFF_ACCEPT_IN_NOND0__MASK 0x00080000L 7289#define EP_PCIE_OBFF_CNTL__TX_OBFF_PENDING_REQ_TO_ACTIVE__MASK 0x00F00000L 7290//EP_PCIE_TX_LTR_CNTL 7291#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__MASK 0x00000007L 7292#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__MASK 0x00000038L 7293#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__MASK 0x00000040L 7294#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__MASK 0x00000380L 7295#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__MASK 0x00001C00L 7296#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__MASK 0x00002000L 7297#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__MASK 0x00004000L 7298#define EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__MASK 0x00008000L 7299#define EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__MASK 0x00010000L 7300//EP_PCIE_STRAP_MISC 7301#define EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__MASK 0x20000000L 7302//EP_PCIE_STRAP_MISC2 7303#define EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__MASK 0x00000010L 7304//EP_PCIE_STRAP_PI 7305//EP_PCIE_F0_DPA_CAP 7306#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__MASK 0x00000300L 7307#define EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__MASK 0x00003000L 7308#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__MASK 0x00FF0000L 7309#define EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__MASK 0xFF000000L 7310//EP_PCIE_F0_DPA_LATENCY_INDICATOR 7311#define EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__MASK 0xFFL 7312//EP_PCIE_F0_DPA_CNTL 7313#define EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__MASK 0x001FL 7314#define EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__MASK 0x0100L 7315//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 7316#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7317//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 7318#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7319//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 7320#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7321//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 7322#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7323//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 7324#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7325//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 7326#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7327//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 7328#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7329//PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 7330#define PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__MASK 0xFFL 7331//EP_PCIE_PME_CONTROL 7332#define EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__MASK 0x1FL 7333//EP_PCIEP_RESERVED 7334#define EP_PCIEP_RESERVED__PCIEP_RESERVED__MASK 0xFFFFFFFFL 7335//EP_PCIE_TX_CNTL 7336#define EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__MASK 0x00000C00L 7337#define EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__MASK 0x00003000L 7338#define EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__MASK 0x01000000L 7339#define EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__MASK 0x02000000L 7340#define EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__MASK 0x04000000L 7341//EP_PCIE_TX_REQUESTER_ID 7342#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__MASK 0x00000007L 7343#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__MASK 0x000000F8L 7344#define EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__MASK 0x0000FF00L 7345//EP_PCIE_ERR_CNTL 7346#define EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__MASK 0x00000001L 7347#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__MASK 0x00000700L 7348#define EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__MASK 0x00020000L 7349#define EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__MASK 0x00040000L 7350#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__MASK 0x01000000L 7351#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__MASK 0x02000000L 7352#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__MASK 0x04000000L 7353#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__MASK 0x08000000L 7354#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__MASK 0x10000000L 7355#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__MASK 0x20000000L 7356#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__MASK 0x40000000L 7357#define EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__MASK 0x80000000L 7358//EP_PCIE_RX_CNTL 7359#define EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__MASK 0x00000100L 7360#define EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__MASK 0x00000200L 7361#define EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__MASK 0x00100000L 7362#define EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__MASK 0x00200000L 7363#define EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__MASK 0x00400000L 7364#define EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__MASK 0x01000000L 7365#define EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__MASK 0x02000000L 7366#define EP_PCIE_RX_CNTL__RX_TPH_DIS__MASK 0x04000000L 7367//EP_PCIE_LC_SPEED_CNTL 7368#define EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__MASK 0x00000001L 7369#define EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__MASK 0x00000002L 7370 7371 7372// addressBlock: bif_bx_pf_BIFDEC1 7373//BIF_MM_INDACCESS_CNTL 7374#define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__MASK 0x00000002L 7375//BUS_CNTL 7376#define BUS_CNTL__PMI_INT_DIS_EP__MASK 0x00000008L 7377#define BUS_CNTL__PMI_INT_DIS_DN__MASK 0x00000010L 7378#define BUS_CNTL__PMI_INT_DIS_SWUS__MASK 0x00000020L 7379#define BUS_CNTL__VGA_REG_COHERENCY_DIS__MASK 0x00000040L 7380#define BUS_CNTL__VGA_MEM_COHERENCY_DIS__MASK 0x00000080L 7381#define BUS_CNTL__SET_AZ_TC__MASK 0x00001C00L 7382#define BUS_CNTL__SET_MC_TC__MASK 0x0000E000L 7383#define BUS_CNTL__ZERO_BE_WR_EN__MASK 0x00010000L 7384#define BUS_CNTL__ZERO_BE_RD_EN__MASK 0x00020000L 7385#define BUS_CNTL__RD_STALL_IO_WR__MASK 0x00040000L 7386#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__MASK 0x00080000L 7387#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__MASK 0x00100000L 7388#define BUS_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__MASK 0x00200000L 7389#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__MASK 0x00400000L 7390#define BUS_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__MASK 0x00800000L 7391#define BUS_CNTL__UR_OVRD_FOR_ECRC_EN__MASK 0x01000000L 7392//BIF_SCRATCH0 7393#define BIF_SCRATCH0__BIF_SCRATCH0__MASK 0xFFFFFFFFL 7394//BIF_SCRATCH1 7395#define BIF_SCRATCH1__BIF_SCRATCH1__MASK 0xFFFFFFFFL 7396//BX_RESET_EN 7397#define BX_RESET_EN__COR_RESET_EN__MASK 0x00000001L 7398#define BX_RESET_EN__REG_RESET_EN__MASK 0x00000002L 7399#define BX_RESET_EN__STY_RESET_EN__MASK 0x00000004L 7400#define BX_RESET_EN__FLR_TWICE_EN__MASK 0x00000100L 7401#define BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__MASK 0x00010000L 7402//MM_CFGREGS_CNTL 7403#define MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__MASK 0x00000007L 7404#define MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__MASK 0x000000C0L 7405#define MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__MASK 0x80000000L 7406//BX_RESET_CNTL 7407#define BX_RESET_CNTL__LINK_TRAIN_EN__MASK 0x00000001L 7408//INTERRUPT_CNTL 7409#define INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__MASK 0x00000001L 7410#define INTERRUPT_CNTL__IH_DUMMY_RD_EN__MASK 0x00000002L 7411#define INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__MASK 0x00000008L 7412#define INTERRUPT_CNTL__IH_INTR_DLY_CNTR__MASK 0x000000F0L 7413#define INTERRUPT_CNTL__GEN_IH_INT_EN__MASK 0x00000100L 7414#define INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__MASK 0x00008000L 7415//INTERRUPT_CNTL2 7416#define INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__MASK 0xFFFFFFFFL 7417//CLKREQB_PAD_CNTL 7418#define CLKREQB_PAD_CNTL__CLKREQB_PAD_A__MASK 0x00000001L 7419#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__MASK 0x00000002L 7420#define CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__MASK 0x00000004L 7421#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__MASK 0x00000018L 7422#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__MASK 0x00000020L 7423#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__MASK 0x00000040L 7424#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__MASK 0x00000080L 7425#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__MASK 0x00000100L 7426#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__MASK 0x00000200L 7427#define CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__MASK 0x00000400L 7428#define CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__MASK 0x00000800L 7429#define CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__MASK 0x00001000L 7430#define CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__MASK 0x00002000L 7431#define CLKREQB_PAD_CNTL__CLKREQB_PERF_COUNTER_UPPER__MASK 0xFF000000L 7432//CLKREQB_PERF_COUNTER 7433#define CLKREQB_PERF_COUNTER__CLKREQB_PERF_COUNTER_LOWER__MASK 0xFFFFFFFFL 7434//BIF_CLK_CTRL 7435#define BIF_CLK_CTRL__BIF_XSTCLK_READY__MASK 0x00000001L 7436#define BIF_CLK_CTRL__BACO_XSTCLK_SWITCH_BYPASS__MASK 0x00000002L 7437//BIF_FEATURES_CONTROL_MISC 7438#define BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__MASK 0x00000001L 7439#define BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__MASK 0x00000002L 7440#define BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__MASK 0x00000004L 7441#define BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__MASK 0x00000008L 7442#define BIF_FEATURES_CONTROL_MISC__MC_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000200L 7443#define BIF_FEATURES_CONTROL_MISC__AZ_BIF_REQ_ID_ROUTING_DIS__MASK 0x00000400L 7444#define BIF_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000800L 7445#define BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__MASK 0x00001000L 7446#define BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__MASK 0x00002000L 7447#define BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__MASK 0x00008000L 7448#define BIF_FEATURES_CONTROL_MISC__FLR_MST_PEND_CHK_DIS__MASK 0x00020000L 7449#define BIF_FEATURES_CONTROL_MISC__FLR_SLV_PEND_CHK_DIS__MASK 0x00040000L 7450#define BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__MASK 0x01000000L 7451//BIF_DOORBELL_CNTL 7452#define BIF_DOORBELL_CNTL__SELF_RING_DIS__MASK 0x00000001L 7453#define BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__MASK 0x00000002L 7454#define BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__MASK 0x00000004L 7455#define BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__MASK 0x00000008L 7456#define BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__MASK 0x00000010L 7457#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__MASK 0x01000000L 7458#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__MASK 0x02000000L 7459#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__MASK 0x04000000L 7460#define BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__MASK 0x08000000L 7461//BIF_DOORBELL_INT_CNTL 7462#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__MASK 0x00000001L 7463#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_STATUS__MASK 0x00000002L 7464#define BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__MASK 0x00010000L 7465#define BIF_DOORBELL_INT_CNTL__IOHC_RAS_INTERRUPT_CLEAR__MASK 0x00020000L 7466//BIF_SLVARB_MODE 7467#define BIF_SLVARB_MODE__SLVARB_MODE__MASK 0x00000003L 7468//BIF_FB_EN 7469#define BIF_FB_EN__FB_READ_EN__MASK 0x00000001L 7470#define BIF_FB_EN__FB_WRITE_EN__MASK 0x00000002L 7471//BIF_BUSY_DELAY_CNTR 7472#define BIF_BUSY_DELAY_CNTR__DELAY_CNT__MASK 0x0000003FL 7473//BIF_PERFMON_CNTL 7474#define BIF_PERFMON_CNTL__PERFCOUNTER_EN__MASK 0x00000001L 7475#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET0__MASK 0x00000002L 7476#define BIF_PERFMON_CNTL__PERFCOUNTER_RESET1__MASK 0x00000004L 7477#define BIF_PERFMON_CNTL__PERF_SEL0__MASK 0x00001F00L 7478#define BIF_PERFMON_CNTL__PERF_SEL1__MASK 0x0003E000L 7479//BIF_PERFCOUNTER0_RESULT 7480#define BIF_PERFCOUNTER0_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL 7481//BIF_PERFCOUNTER1_RESULT 7482#define BIF_PERFCOUNTER1_RESULT__PERFCOUNTER_RESULT__MASK 0xFFFFFFFFL 7483//BIF_MST_TRANS_PENDING_VF 7484#define BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__MASK 0x0000FFFFL 7485//BIF_SLV_TRANS_PENDING_VF 7486#define BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__MASK 0x0000FFFFL 7487//BACO_CNTL 7488#define BACO_CNTL__BACO_EN__MASK 0x00000001L 7489#define BACO_CNTL__BACO_BIF_LCLK_SWITCH__MASK 0x00000002L 7490#define BACO_CNTL__BACO_DUMMY_EN__MASK 0x00000004L 7491#define BACO_CNTL__BACO_POWER_OFF__MASK 0x00000008L 7492#define BACO_CNTL__BACO_DSTATE_BYPASS__MASK 0x00000020L 7493#define BACO_CNTL__BACO_RST_INTR_MASK__MASK 0x00000040L 7494#define BACO_CNTL__BACO_MODE__MASK 0x00000100L 7495#define BACO_CNTL__RCU_BIF_CONFIG_DONE__MASK 0x00000200L 7496#define BACO_CNTL__BACO_AUTO_EXIT__MASK 0x80000000L 7497//BIF_BACO_EXIT_TIME0 7498#define BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__MASK 0x000FFFFFL 7499//BIF_BACO_EXIT_TIMER1 7500#define BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__MASK 0x000FFFFFL 7501#define BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__MASK 0x04000000L 7502#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__MASK 0x08000000L 7503#define BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__MASK 0x10000000L 7504#define BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__MASK 0x60000000L 7505#define BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__MASK 0x80000000L 7506//BIF_BACO_EXIT_TIMER2 7507#define BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__MASK 0x000FFFFFL 7508//BIF_BACO_EXIT_TIMER3 7509#define BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__MASK 0x000FFFFFL 7510//BIF_BACO_EXIT_TIMER4 7511#define BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__MASK 0x000FFFFFL 7512//MEM_TYPE_CNTL 7513#define MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__MASK 0x00000001L 7514//SMU_BIF_VDDGFX_PWR_STATUS 7515#define SMU_BIF_VDDGFX_PWR_STATUS__VDDGFX_GFX_PWR_OFF__MASK 0x00000001L 7516//BIF_VDDGFX_GFX0_LOWER 7517#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_LOWER__MASK 0x0003FFFCL 7518#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_CMP_EN__MASK 0x40000000L 7519#define BIF_VDDGFX_GFX0_LOWER__VDDGFX_GFX0_REG_STALL_EN__MASK 0x80000000L 7520//BIF_VDDGFX_GFX0_UPPER 7521#define BIF_VDDGFX_GFX0_UPPER__VDDGFX_GFX0_REG_UPPER__MASK 0x0003FFFCL 7522//BIF_VDDGFX_GFX1_LOWER 7523#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_LOWER__MASK 0x0003FFFCL 7524#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_CMP_EN__MASK 0x40000000L 7525#define BIF_VDDGFX_GFX1_LOWER__VDDGFX_GFX1_REG_STALL_EN__MASK 0x80000000L 7526//BIF_VDDGFX_GFX1_UPPER 7527#define BIF_VDDGFX_GFX1_UPPER__VDDGFX_GFX1_REG_UPPER__MASK 0x0003FFFCL 7528//BIF_VDDGFX_GFX2_LOWER 7529#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_LOWER__MASK 0x0003FFFCL 7530#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_CMP_EN__MASK 0x40000000L 7531#define BIF_VDDGFX_GFX2_LOWER__VDDGFX_GFX2_REG_STALL_EN__MASK 0x80000000L 7532//BIF_VDDGFX_GFX2_UPPER 7533#define BIF_VDDGFX_GFX2_UPPER__VDDGFX_GFX2_REG_UPPER__MASK 0x0003FFFCL 7534//BIF_VDDGFX_GFX3_LOWER 7535#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_LOWER__MASK 0x0003FFFCL 7536#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_CMP_EN__MASK 0x40000000L 7537#define BIF_VDDGFX_GFX3_LOWER__VDDGFX_GFX3_REG_STALL_EN__MASK 0x80000000L 7538//BIF_VDDGFX_GFX3_UPPER 7539#define BIF_VDDGFX_GFX3_UPPER__VDDGFX_GFX3_REG_UPPER__MASK 0x0003FFFCL 7540//BIF_VDDGFX_GFX4_LOWER 7541#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_LOWER__MASK 0x0003FFFCL 7542#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_CMP_EN__MASK 0x40000000L 7543#define BIF_VDDGFX_GFX4_LOWER__VDDGFX_GFX4_REG_STALL_EN__MASK 0x80000000L 7544//BIF_VDDGFX_GFX4_UPPER 7545#define BIF_VDDGFX_GFX4_UPPER__VDDGFX_GFX4_REG_UPPER__MASK 0x0003FFFCL 7546//BIF_VDDGFX_GFX5_LOWER 7547#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_LOWER__MASK 0x0003FFFCL 7548#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_CMP_EN__MASK 0x40000000L 7549#define BIF_VDDGFX_GFX5_LOWER__VDDGFX_GFX5_REG_STALL_EN__MASK 0x80000000L 7550//BIF_VDDGFX_GFX5_UPPER 7551#define BIF_VDDGFX_GFX5_UPPER__VDDGFX_GFX5_REG_UPPER__MASK 0x0003FFFCL 7552//BIF_VDDGFX_RSV1_LOWER 7553#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_LOWER__MASK 0x0003FFFCL 7554#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_CMP_EN__MASK 0x40000000L 7555#define BIF_VDDGFX_RSV1_LOWER__VDDGFX_RSV1_REG_STALL_EN__MASK 0x80000000L 7556//BIF_VDDGFX_RSV1_UPPER 7557#define BIF_VDDGFX_RSV1_UPPER__VDDGFX_RSV1_REG_UPPER__MASK 0x0003FFFCL 7558//BIF_VDDGFX_RSV2_LOWER 7559#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_LOWER__MASK 0x0003FFFCL 7560#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_CMP_EN__MASK 0x40000000L 7561#define BIF_VDDGFX_RSV2_LOWER__VDDGFX_RSV2_REG_STALL_EN__MASK 0x80000000L 7562//BIF_VDDGFX_RSV2_UPPER 7563#define BIF_VDDGFX_RSV2_UPPER__VDDGFX_RSV2_REG_UPPER__MASK 0x0003FFFCL 7564//BIF_VDDGFX_RSV3_LOWER 7565#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_LOWER__MASK 0x0003FFFCL 7566#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_CMP_EN__MASK 0x40000000L 7567#define BIF_VDDGFX_RSV3_LOWER__VDDGFX_RSV3_REG_STALL_EN__MASK 0x80000000L 7568//BIF_VDDGFX_RSV3_UPPER 7569#define BIF_VDDGFX_RSV3_UPPER__VDDGFX_RSV3_REG_UPPER__MASK 0x0003FFFCL 7570//BIF_VDDGFX_RSV4_LOWER 7571#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_LOWER__MASK 0x0003FFFCL 7572#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_CMP_EN__MASK 0x40000000L 7573#define BIF_VDDGFX_RSV4_LOWER__VDDGFX_RSV4_REG_STALL_EN__MASK 0x80000000L 7574//BIF_VDDGFX_RSV4_UPPER 7575#define BIF_VDDGFX_RSV4_UPPER__VDDGFX_RSV4_REG_UPPER__MASK 0x0003FFFCL 7576//BIF_VDDGFX_FB_CMP 7577#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_CMP_EN__MASK 0x00000001L 7578#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_HDP_STALL_EN__MASK 0x00000002L 7579#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_CMP_EN__MASK 0x00000004L 7580#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_XDMA_STALL_EN__MASK 0x00000008L 7581#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_CMP_EN__MASK 0x00000010L 7582#define BIF_VDDGFX_FB_CMP__VDDGFX_FB_VGA_STALL_EN__MASK 0x00000020L 7583//BIF_DOORBELL_GBLAPER1_LOWER 7584#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_LOWER__MASK 0x00000FFCL 7585#define BIF_DOORBELL_GBLAPER1_LOWER__DOORBELL_GBLAPER1_EN__MASK 0x80000000L 7586//BIF_DOORBELL_GBLAPER1_UPPER 7587#define BIF_DOORBELL_GBLAPER1_UPPER__DOORBELL_GBLAPER1_UPPER__MASK 0x00000FFCL 7588//BIF_DOORBELL_GBLAPER2_LOWER 7589#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_LOWER__MASK 0x00000FFCL 7590#define BIF_DOORBELL_GBLAPER2_LOWER__DOORBELL_GBLAPER2_EN__MASK 0x80000000L 7591//BIF_DOORBELL_GBLAPER2_UPPER 7592#define BIF_DOORBELL_GBLAPER2_UPPER__DOORBELL_GBLAPER2_UPPER__MASK 0x00000FFCL 7593//REMAP_HDP_MEM_FLUSH_CNTL 7594#define REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL 7595//REMAP_HDP_REG_FLUSH_CNTL 7596#define REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__MASK 0x0007FFFCL 7597//BIF_RB_CNTL 7598#define BIF_RB_CNTL__RB_ENABLE__MASK 0x00000001L 7599#define BIF_RB_CNTL__RB_SIZE__MASK 0x0000003EL 7600#define BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__MASK 0x00000100L 7601#define BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__MASK 0x00003E00L 7602#define BIF_RB_CNTL__BIF_RB_TRAN__MASK 0x00020000L 7603#define BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__MASK 0x80000000L 7604//BIF_RB_BASE 7605#define BIF_RB_BASE__ADDR__MASK 0xFFFFFFFFL 7606//BIF_RB_RPTR 7607#define BIF_RB_RPTR__OFFSET__MASK 0x0003FFFCL 7608//BIF_RB_WPTR 7609#define BIF_RB_WPTR__BIF_RB_OVERFLOW__MASK 0x00000001L 7610#define BIF_RB_WPTR__OFFSET__MASK 0x0003FFFCL 7611//BIF_RB_WPTR_ADDR_HI 7612#define BIF_RB_WPTR_ADDR_HI__ADDR__MASK 0x000000FFL 7613//BIF_RB_WPTR_ADDR_LO 7614#define BIF_RB_WPTR_ADDR_LO__ADDR__MASK 0xFFFFFFFCL 7615//MAILBOX_INDEX 7616#define MAILBOX_INDEX__MAILBOX_INDEX__MASK 0x0000001FL 7617//BIF_GPUIOV_RESET_NOTIFICATION 7618#define BIF_GPUIOV_RESET_NOTIFICATION__RESET_NOTIFICATION__MASK 0xFFFFFFFFL 7619//BIF_UVD_GPUIOV_CFG_SIZE 7620#define BIF_UVD_GPUIOV_CFG_SIZE__UVD_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7621//BIF_VCE_GPUIOV_CFG_SIZE 7622#define BIF_VCE_GPUIOV_CFG_SIZE__VCE_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7623//BIF_GFX_SDMA_GPUIOV_CFG_SIZE 7624#define BIF_GFX_SDMA_GPUIOV_CFG_SIZE__GFX_SDMA_GPUIOV_CFG_SIZE__MASK 0x0000000FL 7625//BIF_GMI_WRR_WEIGHT 7626#define BIF_GMI_WRR_WEIGHT__GMI_REQ_REALTIME_WEIGHT__MASK 0x000000FFL 7627#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_P_WEIGHT__MASK 0x0000FF00L 7628#define BIF_GMI_WRR_WEIGHT__GMI_REQ_NORM_NP_WEIGHT__MASK 0x00FF0000L 7629//NBIF_STRAP_WRITE_CTRL 7630#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__MASK 0x00000001L 7631//BIF_PERSTB_PAD_CNTL 7632#define BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__MASK 0x0000FFFFL 7633//BIF_PX_EN_PAD_CNTL 7634#define BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__MASK 0x000000FFL 7635//BIF_REFPADKIN_PAD_CNTL 7636#define BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__MASK 0x000000FFL 7637//BIF_CLKREQB_PAD_CNTL 7638#define BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__MASK 0x00FFFFFFL 7639 7640 7641// addressBlock: rcc_pf_0_BIFDEC1 7642//RCC_BACO_CNTL_MISC 7643#define RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__MASK 0x00000001L 7644#define RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__MASK 0x00000002L 7645//RCC_RESET_EN 7646#define RCC_RESET_EN__DB_APER_RESET_EN__MASK 0x00008000L 7647//RCC_VDM_SUPPORT 7648#define RCC_VDM_SUPPORT__MCTP_SUPPORT__MASK 0x00000001L 7649#define RCC_VDM_SUPPORT__AMPTP_SUPPORT__MASK 0x00000002L 7650#define RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__MASK 0x00000004L 7651#define RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__MASK 0x00000008L 7652#define RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__MASK 0x00000010L 7653//RCC_PEER_REG_RANGE0 7654#define RCC_PEER_REG_RANGE0__START_ADDR__MASK 0x0000FFFFL 7655#define RCC_PEER_REG_RANGE0__END_ADDR__MASK 0xFFFF0000L 7656//RCC_PEER_REG_RANGE1 7657#define RCC_PEER_REG_RANGE1__START_ADDR__MASK 0x0000FFFFL 7658#define RCC_PEER_REG_RANGE1__END_ADDR__MASK 0xFFFF0000L 7659//RCC_BUS_CNTL 7660#define RCC_BUS_CNTL__PMI_IO_DIS__MASK 0x00000004L 7661#define RCC_BUS_CNTL__PMI_MEM_DIS__MASK 0x00000008L 7662#define RCC_BUS_CNTL__PMI_BM_DIS__MASK 0x00000010L 7663#define RCC_BUS_CNTL__PMI_IO_DIS_DN__MASK 0x00000020L 7664#define RCC_BUS_CNTL__PMI_MEM_DIS_DN__MASK 0x00000040L 7665#define RCC_BUS_CNTL__PMI_IO_DIS_UP__MASK 0x00000080L 7666#define RCC_BUS_CNTL__PMI_MEM_DIS_UP__MASK 0x00000100L 7667#define RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__MASK 0x00001000L 7668#define RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__MASK 0x00002000L 7669#define RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__MASK 0x00010000L 7670#define RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__MASK 0x00020000L 7671#define RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__MASK 0x00040000L 7672#define RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__MASK 0x00080000L 7673#define RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__MASK 0x00100000L 7674#define RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__MASK 0x00200000L 7675#define RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__MASK 0x01000000L 7676#define RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__MASK 0x0E000000L 7677#define RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__MASK 0x10000000L 7678#define RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__MASK 0xE0000000L 7679//RCC_CONFIG_CNTL 7680#define RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__MASK 0x00000001L 7681#define RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__MASK 0x00000004L 7682#define RCC_CONFIG_CNTL__GRPH_ADRSEL__MASK 0x00000018L 7683//RCC_CONFIG_F0_BASE 7684#define RCC_CONFIG_F0_BASE__F0_BASE__MASK 0xFFFFFFFFL 7685//RCC_CONFIG_APER_SIZE 7686#define RCC_CONFIG_APER_SIZE__APER_SIZE__MASK 0xFFFFFFFFL 7687//RCC_CONFIG_REG_APER_SIZE 7688#define RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__MASK 0x000FFFFFL 7689//RCC_XDMA_LO 7690#define RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__MASK 0x1FFFFFFFL 7691#define RCC_XDMA_LO__BIF_XDMA_APER_EN__MASK 0x80000000L 7692//RCC_XDMA_HI 7693#define RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__MASK 0x1FFFFFFFL 7694//RCC_FEATURES_CONTROL_MISC 7695#define RCC_FEATURES_CONTROL_MISC__UR_PSN_PKT_REPORT_POISON_DIS__MASK 0x00000010L 7696#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_ALL_DIS__MASK 0x00000020L 7697#define RCC_FEATURES_CONTROL_MISC__POST_PSN_ONLY_PKT_REPORT_UR_PART_DIS__MASK 0x00000040L 7698#define RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__MASK 0x00000100L 7699#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__MASK 0x00000200L 7700#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__MASK 0x00000400L 7701#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__MASK 0x00000800L 7702#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__MASK 0x00001000L 7703#define RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__MASK 0x00002000L 7704#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__MASK 0x00004000L 7705#define RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__MASK 0x00008000L 7706#define RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__MASK 0x00010000L 7707#define RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__MASK 0x00020000L 7708#define RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__MASK 0x00040000L 7709//RCC_BUSNUM_CNTL1 7710#define RCC_BUSNUM_CNTL1__ID_MASK__MASK 0x000000FFL 7711//RCC_BUSNUM_LIST0 7712#define RCC_BUSNUM_LIST0__ID0__MASK 0x000000FFL 7713#define RCC_BUSNUM_LIST0__ID1__MASK 0x0000FF00L 7714#define RCC_BUSNUM_LIST0__ID2__MASK 0x00FF0000L 7715#define RCC_BUSNUM_LIST0__ID3__MASK 0xFF000000L 7716//RCC_BUSNUM_LIST1 7717#define RCC_BUSNUM_LIST1__ID4__MASK 0x000000FFL 7718#define RCC_BUSNUM_LIST1__ID5__MASK 0x0000FF00L 7719#define RCC_BUSNUM_LIST1__ID6__MASK 0x00FF0000L 7720#define RCC_BUSNUM_LIST1__ID7__MASK 0xFF000000L 7721//RCC_BUSNUM_CNTL2 7722#define RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__MASK 0x000000FFL 7723#define RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__MASK 0x00000100L 7724#define RCC_BUSNUM_CNTL2__HDPREG_CNTL__MASK 0x00010000L 7725#define RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__MASK 0x00020000L 7726//RCC_CAPTURE_HOST_BUSNUM 7727#define RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__MASK 0x00000001L 7728//RCC_HOST_BUSNUM 7729#define RCC_HOST_BUSNUM__HOST_ID__MASK 0x0000FFFFL 7730//RCC_PEER0_FB_OFFSET_HI 7731#define RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__MASK 0x000FFFFFL 7732//RCC_PEER0_FB_OFFSET_LO 7733#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__MASK 0x000FFFFFL 7734#define RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__MASK 0x80000000L 7735//RCC_PEER1_FB_OFFSET_HI 7736#define RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__MASK 0x000FFFFFL 7737//RCC_PEER1_FB_OFFSET_LO 7738#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__MASK 0x000FFFFFL 7739#define RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__MASK 0x80000000L 7740//RCC_PEER2_FB_OFFSET_HI 7741#define RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__MASK 0x000FFFFFL 7742//RCC_PEER2_FB_OFFSET_LO 7743#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__MASK 0x000FFFFFL 7744#define RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__MASK 0x80000000L 7745//RCC_PEER3_FB_OFFSET_HI 7746#define RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__MASK 0x000FFFFFL 7747//RCC_PEER3_FB_OFFSET_LO 7748#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__MASK 0x000FFFFFL 7749#define RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__MASK 0x80000000L 7750//RCC_DEVFUNCNUM_LIST0 7751#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__MASK 0x000000FFL 7752#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__MASK 0x0000FF00L 7753#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__MASK 0x00FF0000L 7754#define RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__MASK 0xFF000000L 7755//RCC_DEVFUNCNUM_LIST1 7756#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__MASK 0x000000FFL 7757#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__MASK 0x0000FF00L 7758#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__MASK 0x00FF0000L 7759#define RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__MASK 0xFF000000L 7760//RCC_DEV0_LINK_CNTL 7761#define RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__MASK 0x00000001L 7762#define RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__MASK 0x00000100L 7763//RCC_CMN_LINK_CNTL 7764#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__MASK 0x00000001L 7765#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__MASK 0x00000002L 7766#define RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__MASK 0x00000004L 7767#define RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__MASK 0x00000008L 7768//RCC_EP_REQUESTERID_RESTORE 7769#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__MASK 0x000000FFL 7770#define RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__MASK 0x00001F00L 7771//RCC_LTR_LSWITCH_CNTL 7772#define RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__MASK 0x000003FFL 7773//RCC_MH_ARB_CNTL 7774#define RCC_MH_ARB_CNTL__MH_ARB_MODE__MASK 0x00000001L 7775#define RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__MASK 0x00007FFEL 7776 7777 7778// addressBlock: rcc_pf_0_BIFDEC2 7779//GFXMSIX_VECT0_ADDR_LO 7780#define GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7781//GFXMSIX_VECT0_ADDR_HI 7782#define GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7783//GFXMSIX_VECT0_MSG_DATA 7784#define GFXMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7785//GFXMSIX_VECT0_CONTROL 7786#define GFXMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L 7787//GFXMSIX_VECT1_ADDR_LO 7788#define GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7789//GFXMSIX_VECT1_ADDR_HI 7790#define GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7791//GFXMSIX_VECT1_MSG_DATA 7792#define GFXMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7793//GFXMSIX_VECT1_CONTROL 7794#define GFXMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L 7795//GFXMSIX_VECT2_ADDR_LO 7796#define GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 7797//GFXMSIX_VECT2_ADDR_HI 7798#define GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 7799//GFXMSIX_VECT2_MSG_DATA 7800#define GFXMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 7801//GFXMSIX_VECT2_CONTROL 7802#define GFXMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L 7803//GFXMSIX_PBA 7804#define GFXMSIX_PBA__MSIX_PENDING_BITS_0__MASK 0x00000001L 7805#define GFXMSIX_PBA__MSIX_PENDING_BITS_1__MASK 0x00000002L 7806#define GFXMSIX_PBA__MSIX_PENDING_BITS_2__MASK 0x00000004L 7807 7808 7809// addressBlock: rcc_strap_BIFDEC1 7810//RCC_DEV0_PORT_STRAP0 7811#define RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L 7812#define RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L 7813#define RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L 7814#define RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L 7815#define RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L 7816#define RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L 7817#define RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L 7818#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L 7819#define RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L 7820#define RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L 7821//RCC_DEV0_PORT_STRAP1 7822#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL 7823#define RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L 7824//RCC_DEV0_PORT_STRAP2 7825#define RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L 7826#define RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L 7827#define RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L 7828#define RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L 7829#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L 7830#define RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L 7831#define RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L 7832#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L 7833#define RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L 7834#define RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L 7835#define RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L 7836#define RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L 7837#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L 7838#define RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L 7839#define RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L 7840#define RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L 7841#define RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L 7842#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L 7843#define RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L 7844#define RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L 7845#define RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L 7846//RCC_DEV0_PORT_STRAP3 7847#define RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L 7848#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L 7849#define RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L 7850#define RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L 7851#define RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L 7852#define RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L 7853#define RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L 7854#define RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L 7855#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L 7856#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L 7857#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L 7858#define RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L 7859#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L 7860#define RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L 7861#define RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L 7862#define RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L 7863#define RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L 7864//RCC_DEV0_PORT_STRAP4 7865#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL 7866#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L 7867#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L 7868#define RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L 7869//RCC_DEV0_PORT_STRAP5 7870#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL 7871#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L 7872#define RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L 7873#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L 7874#define RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L 7875#define RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L 7876#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L 7877#define RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L 7878#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L 7879#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L 7880#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L 7881#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L 7882#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L 7883#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L 7884#define RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L 7885#define RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L 7886#define RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L 7887//RCC_DEV0_PORT_STRAP6 7888#define RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L 7889#define RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L 7890//RCC_DEV0_PORT_STRAP7 7891#define RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL 7892#define RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L 7893#define RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L 7894#define RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L 7895#define RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L 7896#define RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L 7897//RCC_DEV0_EPF0_STRAP0 7898#define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 7899#define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L 7900#define RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L 7901#define RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L 7902#define RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L 7903#define RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L 7904#define RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L 7905#define RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L 7906//RCC_DEV0_EPF0_STRAP1 7907#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 7908#define RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L 7909//RCC_DEV0_EPF0_STRAP13 7910#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL 7911#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L 7912#define RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L 7913//RCC_DEV0_EPF0_STRAP2 7914#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L 7915#define RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL 7916#define RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L 7917#define RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L 7918#define RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L 7919#define RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L 7920#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L 7921#define RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L 7922#define RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L 7923#define RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L 7924#define RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L 7925#define RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L 7926#define RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L 7927#define RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L 7928#define RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L 7929#define RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L 7930#define RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L 7931#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L 7932#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L 7933#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L 7934#define RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L 7935//RCC_DEV0_EPF0_STRAP3 7936#define RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L 7937#define RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L 7938#define RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL 7939#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L 7940#define RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L 7941#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L 7942#define RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L 7943#define RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L 7944#define RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L 7945#define RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L 7946#define RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L 7947//RCC_DEV0_EPF0_STRAP4 7948#define RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL 7949#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L 7950#define RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L 7951#define RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L 7952#define RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L 7953#define RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L 7954#define RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L 7955//RCC_DEV0_EPF0_STRAP5 7956#define RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL 7957//RCC_DEV0_EPF0_STRAP8 7958#define RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L 7959#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L 7960#define RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L 7961#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L 7962#define RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L 7963#define RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L 7964#define RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L 7965#define RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L 7966#define RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L 7967#define RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L 7968#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L 7969#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L 7970#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L 7971#define RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L 7972#define RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L 7973#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L 7974#define RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L 7975#define RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L 7976//RCC_DEV0_EPF0_STRAP9 7977//RCC_DEV0_EPF1_STRAP0 7978#define RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL 7979#define RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L 7980#define RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L 7981#define RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L 7982#define RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L 7983#define RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L 7984#define RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L 7985//RCC_DEV0_EPF1_STRAP10 7986#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7987#define RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7988//RCC_DEV0_EPF1_STRAP11 7989#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7990#define RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7991//RCC_DEV0_EPF1_STRAP12 7992#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L 7993#define RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 7994//RCC_DEV0_EPF1_STRAP13 7995#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL 7996#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L 7997#define RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L 7998//RCC_DEV0_EPF1_STRAP2 7999#define RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L 8000#define RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L 8001#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L 8002#define RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L 8003#define RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L 8004#define RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L 8005#define RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L 8006#define RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L 8007#define RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L 8008#define RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L 8009#define RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L 8010//RCC_DEV0_EPF1_STRAP3 8011#define RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L 8012#define RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L 8013#define RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL 8014#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L 8015#define RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L 8016#define RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L 8017#define RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L 8018#define RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L 8019#define RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L 8020#define RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L 8021//RCC_DEV0_EPF1_STRAP4 8022#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L 8023#define RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L 8024#define RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L 8025#define RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L 8026#define RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L 8027#define RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L 8028//RCC_DEV0_EPF1_STRAP5 8029#define RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL 8030//RCC_DEV0_EPF1_STRAP6 8031#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L 8032#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L 8033#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L 8034#define RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L 8035#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L 8036#define RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L 8037#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L 8038#define RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L 8039#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L 8040#define RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L 8041//RCC_DEV0_EPF1_STRAP7 8042#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L 8043#define RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL 8044 8045 8046// addressBlock: bif_bx_pf_BIFPFVFDEC1 8047//BIF_BME_STATUS 8048#define BIF_BME_STATUS__DMA_ON_BME_LOW__MASK 0x00000001L 8049#define BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__MASK 0x00010000L 8050//BIF_ATOMIC_ERR_LOG 8051#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__MASK 0x00000001L 8052#define BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__MASK 0x00000002L 8053#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__MASK 0x00010000L 8054#define BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__MASK 0x00020000L 8055//DOORBELL_SELFRING_GPA_APER_BASE_HIGH 8056#define DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__MASK 0xFFFFFFFFL 8057//DOORBELL_SELFRING_GPA_APER_BASE_LOW 8058#define DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__MASK 0xFFFFFFFFL 8059//DOORBELL_SELFRING_GPA_APER_CNTL 8060#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__MASK 0x00000001L 8061#define DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__MASK 0x0000FF00L 8062//HDP_REG_COHERENCY_FLUSH_CNTL 8063#define HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__MASK 0x00000001L 8064//HDP_MEM_COHERENCY_FLUSH_CNTL 8065#define HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__MASK 0x00000001L 8066//GPU_HDP_FLUSH_REQ 8067#define GPU_HDP_FLUSH_REQ__CP0__MASK 0x00000001L 8068#define GPU_HDP_FLUSH_REQ__CP1__MASK 0x00000002L 8069#define GPU_HDP_FLUSH_REQ__CP2__MASK 0x00000004L 8070#define GPU_HDP_FLUSH_REQ__CP3__MASK 0x00000008L 8071#define GPU_HDP_FLUSH_REQ__CP4__MASK 0x00000010L 8072#define GPU_HDP_FLUSH_REQ__CP5__MASK 0x00000020L 8073#define GPU_HDP_FLUSH_REQ__CP6__MASK 0x00000040L 8074#define GPU_HDP_FLUSH_REQ__CP7__MASK 0x00000080L 8075#define GPU_HDP_FLUSH_REQ__CP8__MASK 0x00000100L 8076#define GPU_HDP_FLUSH_REQ__CP9__MASK 0x00000200L 8077#define GPU_HDP_FLUSH_REQ__SDMA0__MASK 0x00000400L 8078#define GPU_HDP_FLUSH_REQ__SDMA1__MASK 0x00000800L 8079//GPU_HDP_FLUSH_DONE 8080#define GPU_HDP_FLUSH_DONE__CP0__MASK 0x00000001L 8081#define GPU_HDP_FLUSH_DONE__CP1__MASK 0x00000002L 8082#define GPU_HDP_FLUSH_DONE__CP2__MASK 0x00000004L 8083#define GPU_HDP_FLUSH_DONE__CP3__MASK 0x00000008L 8084#define GPU_HDP_FLUSH_DONE__CP4__MASK 0x00000010L 8085#define GPU_HDP_FLUSH_DONE__CP5__MASK 0x00000020L 8086#define GPU_HDP_FLUSH_DONE__CP6__MASK 0x00000040L 8087#define GPU_HDP_FLUSH_DONE__CP7__MASK 0x00000080L 8088#define GPU_HDP_FLUSH_DONE__CP8__MASK 0x00000100L 8089#define GPU_HDP_FLUSH_DONE__CP9__MASK 0x00000200L 8090#define GPU_HDP_FLUSH_DONE__SDMA0__MASK 0x00000400L 8091#define GPU_HDP_FLUSH_DONE__SDMA1__MASK 0x00000800L 8092//BIF_TRANS_PENDING 8093#define BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__MASK 0x00000001L 8094#define BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__MASK 0x00000002L 8095//MAILBOX_MSGBUF_TRN_DW0 8096#define MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL 8097//MAILBOX_MSGBUF_TRN_DW1 8098#define MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL 8099//MAILBOX_MSGBUF_TRN_DW2 8100#define MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL 8101//MAILBOX_MSGBUF_TRN_DW3 8102#define MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL 8103//MAILBOX_MSGBUF_RCV_DW0 8104#define MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__MASK 0xFFFFFFFFL 8105//MAILBOX_MSGBUF_RCV_DW1 8106#define MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__MASK 0xFFFFFFFFL 8107//MAILBOX_MSGBUF_RCV_DW2 8108#define MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__MASK 0xFFFFFFFFL 8109//MAILBOX_MSGBUF_RCV_DW3 8110#define MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__MASK 0xFFFFFFFFL 8111//MAILBOX_CONTROL 8112#define MAILBOX_CONTROL__TRN_MSG_VALID__MASK 0x00000001L 8113#define MAILBOX_CONTROL__TRN_MSG_ACK__MASK 0x00000002L 8114#define MAILBOX_CONTROL__RCV_MSG_VALID__MASK 0x00000100L 8115#define MAILBOX_CONTROL__RCV_MSG_ACK__MASK 0x00000200L 8116//MAILBOX_INT_CNTL 8117#define MAILBOX_INT_CNTL__VALID_INT_EN__MASK 0x00000001L 8118#define MAILBOX_INT_CNTL__ACK_INT_EN__MASK 0x00000002L 8119//BIF_VMHV_MAILBOX 8120#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__MASK 0x00000001L 8121#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__MASK 0x00000002L 8122#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__MASK 0x00000F00L 8123#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__MASK 0x00008000L 8124#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__MASK 0x000F0000L 8125#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__MASK 0x00800000L 8126#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__MASK 0x01000000L 8127#define BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__MASK 0x02000000L 8128 8129 8130// addressBlock: rcc_pf_0_BIFPFVFDEC1 8131//RCC_DOORBELL_APER_EN 8132#define RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__MASK 0x00000001L 8133//RCC_CONFIG_MEMSIZE 8134#define RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__MASK 0xFFFFFFFFL 8135//RCC_CONFIG_RESERVED 8136#define RCC_CONFIG_RESERVED__CONFIG_RESERVED__MASK 0xFFFFFFFFL 8137//RCC_IOV_FUNC_IDENTIFIER 8138#define RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__MASK 0x00000001L 8139#define RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__MASK 0x80000000L 8140 8141 8142// addressBlock: syshub_mmreg_ind_syshubdec 8143//SYSHUB_INDEX 8144#define SYSHUB_INDEX__INDEX__MASK 0xFFFFFFFFL 8145//SYSHUB_DATA 8146#define SYSHUB_DATA__DATA__MASK 0xFFFFFFFFL 8147 8148 8149// addressBlock: rcc_strap_rcc_strap_internal 8150//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0 8151#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__MASK 0x00000002L 8152#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__MASK 0x00000004L 8153#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__MASK 0x00000008L 8154#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__MASK 0x00000010L 8155#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__MASK 0x001FFFE0L 8156#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__MASK 0x00E00000L 8157#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__MASK 0x01000000L 8158#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__MASK 0x0E000000L 8159#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__MASK 0x70000000L 8160#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__MASK 0x80000000L 8161//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1 8162#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__MASK 0x0000FFFFL 8163#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__MASK 0xFFFF0000L 8164//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2 8165#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__MASK 0x00000001L 8166#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__MASK 0x00000002L 8167#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__MASK 0x00000004L 8168#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__MASK 0x00000008L 8169#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__MASK 0x00000010L 8170#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__MASK 0x00000020L 8171#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV0__MASK 0x00000040L 8172#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__MASK 0x00000080L 8173#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__MASK 0x00000100L 8174#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__MASK 0x00000E00L 8175#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__MASK 0x00001000L 8176#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__MASK 0x00002000L 8177#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__MASK 0x00004000L 8178#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__MASK 0x00008000L 8179#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__MASK 0x00010000L 8180#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV0__MASK 0x00060000L 8181#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV0__MASK 0x00080000L 8182#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__MASK 0x00700000L 8183#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__MASK 0x03800000L 8184#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__MASK 0x1C000000L 8185#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__MASK 0xE0000000L 8186//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3 8187#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__MASK 0x00000001L 8188#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__MASK 0x00000002L 8189#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__MASK 0x00000004L 8190#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__MASK 0x00000038L 8191#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__MASK 0x00000040L 8192#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__MASK 0x00000080L 8193#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__MASK 0x00000100L 8194#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__MASK 0x00000600L 8195#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x00003800L 8196#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__MASK 0x0003C000L 8197#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__MASK 0x001C0000L 8198#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__MASK 0x01E00000L 8199#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__MASK 0x06000000L 8200#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__MASK 0x18000000L 8201#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__MASK 0x20000000L 8202#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV0__MASK 0x40000000L 8203#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__MASK 0x80000000L 8204//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4 8205#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__MASK 0x000000FFL 8206#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__MASK 0x0000FF00L 8207#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__MASK 0x00FF0000L 8208#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__MASK 0xFF000000L 8209//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5 8210#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__MASK 0x000000FFL 8211#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__MASK 0x0000FF00L 8212#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__MASK 0x00010000L 8213#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__MASK 0x00020000L 8214#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__MASK 0x00040000L 8215#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__MASK 0x00080000L 8216#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__MASK 0x00100000L 8217#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__MASK 0x00200000L 8218#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__MASK 0x00800000L 8219#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__MASK 0x01000000L 8220#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__MASK 0x02000000L 8221#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__MASK 0x04000000L 8222#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__MASK 0x08000000L 8223#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__MASK 0x10000000L 8224#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__MASK 0x20000000L 8225#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__MASK 0x40000000L 8226#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__MASK 0x80000000L 8227//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6 8228#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__MASK 0x00000001L 8229#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__MASK 0x00000002L 8230//RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7 8231#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__MASK 0x000000FFL 8232#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__MASK 0x00000F00L 8233#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__MASK 0x0000F000L 8234#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__MASK 0x00FF0000L 8235#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__MASK 0x1F000000L 8236#define RCCSTRAPRCCSTRAP_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__MASK 0xE0000000L 8237//RCC_DEV1_PORT_STRAP0 8238#define RCC_DEV1_PORT_STRAP0__STRAP_ARI_EN_DN_DEV1__MASK 0x00000002L 8239#define RCC_DEV1_PORT_STRAP0__STRAP_ACS_EN_DN_DEV1__MASK 0x00000004L 8240#define RCC_DEV1_PORT_STRAP0__STRAP_AER_EN_DN_DEV1__MASK 0x00000008L 8241#define RCC_DEV1_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV1__MASK 0x00000010L 8242#define RCC_DEV1_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV1__MASK 0x001FFFE0L 8243#define RCC_DEV1_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV1__MASK 0x00E00000L 8244#define RCC_DEV1_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV1__MASK 0x01000000L 8245#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV1__MASK 0x0E000000L 8246#define RCC_DEV1_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV1__MASK 0x70000000L 8247#define RCC_DEV1_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV1__MASK 0x80000000L 8248//RCC_DEV1_PORT_STRAP1 8249#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV1__MASK 0x0000FFFFL 8250#define RCC_DEV1_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV1__MASK 0xFFFF0000L 8251//RCC_DEV1_PORT_STRAP2 8252#define RCC_DEV1_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV1__MASK 0x00000001L 8253#define RCC_DEV1_PORT_STRAP2__STRAP_DSN_EN_DN_DEV1__MASK 0x00000002L 8254#define RCC_DEV1_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV1__MASK 0x00000004L 8255#define RCC_DEV1_PORT_STRAP2__STRAP_ECN1P1_EN_DEV1__MASK 0x00000008L 8256#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV1__MASK 0x00000010L 8257#define RCC_DEV1_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV1__MASK 0x00000020L 8258#define RCC_DEV1_PORT_STRAP2__STRAP_ERR_REPORTING_DIS_DEV1__MASK 0x00000040L 8259#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV1__MASK 0x00000080L 8260#define RCC_DEV1_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV1__MASK 0x00000100L 8261#define RCC_DEV1_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV1__MASK 0x00000E00L 8262#define RCC_DEV1_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV1__MASK 0x00001000L 8263#define RCC_DEV1_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV1__MASK 0x00002000L 8264#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV1__MASK 0x00004000L 8265#define RCC_DEV1_PORT_STRAP2__STRAP_GEN2_EN_DEV1__MASK 0x00008000L 8266#define RCC_DEV1_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV1__MASK 0x00010000L 8267#define RCC_DEV1_PORT_STRAP2__STRAP_TARGET_LINK_SPEED_DEV1__MASK 0x00060000L 8268#define RCC_DEV1_PORT_STRAP2__STRAP_INTERNAL_ERR_EN_DEV1__MASK 0x00080000L 8269#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV1__MASK 0x00700000L 8270#define RCC_DEV1_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV1__MASK 0x03800000L 8271#define RCC_DEV1_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV1__MASK 0x1C000000L 8272#define RCC_DEV1_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV1__MASK 0xE0000000L 8273//RCC_DEV1_PORT_STRAP3 8274#define RCC_DEV1_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV1__MASK 0x00000001L 8275#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DEV1__MASK 0x00000002L 8276#define RCC_DEV1_PORT_STRAP3__STRAP_LTR_EN_DN_DEV1__MASK 0x00000004L 8277#define RCC_DEV1_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV1__MASK 0x00000038L 8278#define RCC_DEV1_PORT_STRAP3__STRAP_MSI_EN_DN_DEV1__MASK 0x00000040L 8279#define RCC_DEV1_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV1__MASK 0x00000080L 8280#define RCC_DEV1_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV1__MASK 0x00000100L 8281#define RCC_DEV1_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV1__MASK 0x00000600L 8282#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x00003800L 8283#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV1__MASK 0x0003C000L 8284#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV1__MASK 0x001C0000L 8285#define RCC_DEV1_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV1__MASK 0x01E00000L 8286#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DEV1__MASK 0x06000000L 8287#define RCC_DEV1_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV1__MASK 0x18000000L 8288#define RCC_DEV1_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV1__MASK 0x20000000L 8289#define RCC_DEV1_PORT_STRAP3__STRAP_VENDOR_ID_BIT_DN_DEV1__MASK 0x40000000L 8290#define RCC_DEV1_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV1__MASK 0x80000000L 8291//RCC_DEV1_PORT_STRAP4 8292#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV1__MASK 0x000000FFL 8293#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV1__MASK 0x0000FF00L 8294#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV1__MASK 0x00FF0000L 8295#define RCC_DEV1_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV1__MASK 0xFF000000L 8296//RCC_DEV1_PORT_STRAP5 8297#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV1__MASK 0x000000FFL 8298#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV1__MASK 0x0000FF00L 8299#define RCC_DEV1_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV1__MASK 0x00010000L 8300#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV1__MASK 0x00020000L 8301#define RCC_DEV1_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV1__MASK 0x00040000L 8302#define RCC_DEV1_PORT_STRAP5__STRAP_VC_EN_DN_DEV1__MASK 0x00080000L 8303#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DEV1__MASK 0x00100000L 8304#define RCC_DEV1_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV1__MASK 0x00200000L 8305#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV1__MASK 0x00800000L 8306#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV1__MASK 0x01000000L 8307#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV1__MASK 0x02000000L 8308#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV1__MASK 0x04000000L 8309#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV1__MASK 0x08000000L 8310#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV1__MASK 0x10000000L 8311#define RCC_DEV1_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV1__MASK 0x20000000L 8312#define RCC_DEV1_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV1__MASK 0x40000000L 8313#define RCC_DEV1_PORT_STRAP5__STRAP_SSID_EN_DEV1__MASK 0x80000000L 8314//RCC_DEV1_PORT_STRAP6 8315#define RCC_DEV1_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV1__MASK 0x00000001L 8316#define RCC_DEV1_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV1__MASK 0x00000002L 8317//RCC_DEV1_PORT_STRAP7 8318#define RCC_DEV1_PORT_STRAP7__STRAP_PORT_NUMBER_DEV1__MASK 0x000000FFL 8319#define RCC_DEV1_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV1__MASK 0x00000F00L 8320#define RCC_DEV1_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV1__MASK 0x0000F000L 8321#define RCC_DEV1_PORT_STRAP7__STRAP_RP_BUSNUM_DEV1__MASK 0x00FF0000L 8322#define RCC_DEV1_PORT_STRAP7__STRAP_DN_DEVNUM_DEV1__MASK 0x1F000000L 8323#define RCC_DEV1_PORT_STRAP7__STRAP_DN_FUNCID_DEV1__MASK 0xE0000000L 8324//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0 8325#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 8326#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__MASK 0x000F0000L 8327#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__MASK 0x00F00000L 8328#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__MASK 0x0F000000L 8329#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__MASK 0x10000000L 8330#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__MASK 0x20000000L 8331#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__MASK 0x40000000L 8332#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__MASK 0x80000000L 8333//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1 8334#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__MASK 0x0000FFFFL 8335#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__MASK 0xFFFF0000L 8336//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2 8337#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__MASK 0x00000001L 8338#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__MASK 0x0000003EL 8339#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__MASK 0x00000040L 8340#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__MASK 0x00000080L 8341#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__MASK 0x00000100L 8342#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__MASK 0x00003E00L 8343#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__MASK 0x00004000L 8344#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__MASK 0x00008000L 8345#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__MASK 0x00010000L 8346#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__MASK 0x00020000L 8347#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__MASK 0x00040000L 8348#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__MASK 0x00100000L 8349#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__MASK 0x00200000L 8350#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__MASK 0x00400000L 8351#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__MASK 0x00800000L 8352#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__MASK 0x07000000L 8353#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__MASK 0x08000000L 8354#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__MASK 0x10000000L 8355#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__MASK 0x20000000L 8356#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__MASK 0x40000000L 8357#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__MASK 0x80000000L 8358//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3 8359#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__MASK 0x00000001L 8360#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__MASK 0x00000002L 8361#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__MASK 0x0003FFFCL 8362#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__MASK 0x00040000L 8363#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__MASK 0x00080000L 8364#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__MASK 0x00100000L 8365#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__MASK 0x00E00000L 8366#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__MASK 0x01000000L 8367#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F0__MASK 0x02000000L 8368#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__MASK 0x04000000L 8369#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__MASK 0x08000000L 8370//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4 8371#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_MSIX_TABLE_OFFSET_DEV0_F0__MASK 0x000FFFFFL 8372#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__MASK 0x00100000L 8373#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__MASK 0x00200000L 8374#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__MASK 0x00400000L 8375#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__MASK 0x0F800000L 8376#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__MASK 0x70000000L 8377#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__MASK 0x80000000L 8378//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5 8379#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__MASK 0x0000FFFFL 8380//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8 8381#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__MASK 0x00000001L 8382#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00000006L 8383#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__MASK 0x00000008L 8384#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_ALWAYS_ON_DEV0_F0__MASK 0x00000010L 8385#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__MASK 0x00000060L 8386#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__MASK 0x00000080L 8387#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__MASK 0x00000100L 8388#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_MEM_AP_SIZE_DEV0_F0__MASK 0x00000E00L 8389#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__MASK 0x00003000L 8390#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__MASK 0x0000C000L 8391#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__MASK 0x00070000L 8392#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MEM_AP_SIZE_DEV0_F0__MASK 0x00380000L 8393#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__MASK 0x00C00000L 8394#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VGA_DIS_DEV0_F0__MASK 0x01000000L 8395#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__MASK 0x02000000L 8396#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_PROT_DIS_DEV0_F0__MASK 0x04000000L 8397#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__MASK 0x38000000L 8398#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__MASK 0xC0000000L 8399//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP9 8400//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13 8401#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__MASK 0x000000FFL 8402#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__MASK 0x0000FF00L 8403#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__MASK 0x00FF0000L 8404//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0 8405#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__MASK 0x0000FFFFL 8406#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__MASK 0x000F0000L 8407#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__MASK 0x00F00000L 8408#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__MASK 0x10000000L 8409#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__MASK 0x20000000L 8410#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__MASK 0x40000000L 8411#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__MASK 0x80000000L 8412//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2 8413#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__MASK 0x00000080L 8414#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__MASK 0x00000100L 8415#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__MASK 0x00004000L 8416#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__MASK 0x00010000L 8417#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__MASK 0x00020000L 8418#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_ATS_EN_DEV0_F1__MASK 0x00040000L 8419#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__MASK 0x00100000L 8420#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__MASK 0x00200000L 8421#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_DSN_EN_DEV0_F1__MASK 0x00400000L 8422#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_VC_EN_DEV0_F1__MASK 0x00800000L 8423#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__MASK 0x07000000L 8424//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3 8425#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__MASK 0x00000001L 8426#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__MASK 0x00000002L 8427#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__MASK 0x0003FFFCL 8428#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__MASK 0x00040000L 8429#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__MASK 0x00080000L 8430#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__MASK 0x00100000L 8431#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__MASK 0x01000000L 8432#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F1__MASK 0x02000000L 8433#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__MASK 0x04000000L 8434#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__MASK 0x08000000L 8435//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4 8436#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__MASK 0x00100000L 8437#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__MASK 0x00200000L 8438#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__MASK 0x00400000L 8439#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__MASK 0x0F800000L 8440#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__MASK 0x70000000L 8441#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__MASK 0x80000000L 8442//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5 8443#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__MASK 0x0000FFFFL 8444//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6 8445#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__MASK 0x00000001L 8446#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000002L 8447#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__MASK 0x00000004L 8448#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F1__MASK 0x00000070L 8449#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__MASK 0x00000100L 8450#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__MASK 0x00000200L 8451#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__MASK 0x00010000L 8452#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__MASK 0x00020000L 8453#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__MASK 0x01000000L 8454#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__MASK 0x02000000L 8455//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7 8456#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_EN_DEV0_F1__MASK 0x00000001L 8457#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP7__STRAP_ROM_APER_SIZE_DEV0_F1__MASK 0x0000001EL 8458//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10 8459#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8460#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP10__STRAP_APER1_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8461//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11 8462#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8463#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP11__STRAP_APER2_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8464//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12 8465#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_EN_DEV0_F1__MASK 0x00000001L 8466#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP12__STRAP_APER3_RESIZE_SUPPORT_DEV0_F1__MASK 0x001FFFFEL 8467//RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13 8468#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__MASK 0x000000FFL 8469#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__MASK 0x0000FF00L 8470#define RCCSTRAPRCCSTRAP_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__MASK 0x00FF0000L 8471//RCC_DEV0_EPF2_STRAP0 8472#define RCC_DEV0_EPF2_STRAP0__STRAP_DEVICE_ID_DEV0_F2__MASK 0x0000FFFFL 8473#define RCC_DEV0_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F2__MASK 0x000F0000L 8474#define RCC_DEV0_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV0_F2__MASK 0x00F00000L 8475#define RCC_DEV0_EPF2_STRAP0__STRAP_FUNC_EN_DEV0_F2__MASK 0x10000000L 8476#define RCC_DEV0_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F2__MASK 0x20000000L 8477#define RCC_DEV0_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV0_F2__MASK 0x40000000L 8478#define RCC_DEV0_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV0_F2__MASK 0x80000000L 8479//RCC_DEV0_EPF2_STRAP2 8480#define RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2__MASK 0x00000080L 8481#define RCC_DEV0_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F2__MASK 0x00000100L 8482#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F2__MASK 0x00004000L 8483#define RCC_DEV0_EPF2_STRAP2__STRAP_AER_EN_DEV0_F2__MASK 0x00010000L 8484#define RCC_DEV0_EPF2_STRAP2__STRAP_ACS_EN_DEV0_F2__MASK 0x00020000L 8485#define RCC_DEV0_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F2__MASK 0x00100000L 8486#define RCC_DEV0_EPF2_STRAP2__STRAP_DPA_EN_DEV0_F2__MASK 0x00200000L 8487#define RCC_DEV0_EPF2_STRAP2__STRAP_VC_EN_DEV0_F2__MASK 0x00800000L 8488#define RCC_DEV0_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F2__MASK 0x07000000L 8489//RCC_DEV0_EPF2_STRAP3 8490#define RCC_DEV0_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F2__MASK 0x00000001L 8491#define RCC_DEV0_EPF2_STRAP3__STRAP_PWR_EN_DEV0_F2__MASK 0x00000002L 8492#define RCC_DEV0_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV0_F2__MASK 0x0003FFFCL 8493#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_EN_DEV0_F2__MASK 0x00040000L 8494#define RCC_DEV0_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F2__MASK 0x00080000L 8495#define RCC_DEV0_EPF2_STRAP3__STRAP_MSIX_EN_DEV0_F2__MASK 0x00100000L 8496#define RCC_DEV0_EPF2_STRAP3__STRAP_PMC_DSI_DEV0_F2__MASK 0x01000000L 8497#define RCC_DEV0_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F2__MASK 0x02000000L 8498#define RCC_DEV0_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F2__MASK 0x04000000L 8499#define RCC_DEV0_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F2__MASK 0x08000000L 8500//RCC_DEV0_EPF2_STRAP4 8501#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F2__MASK 0x00100000L 8502#define RCC_DEV0_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV0_F2__MASK 0x00200000L 8503#define RCC_DEV0_EPF2_STRAP4__STRAP_FLR_EN_DEV0_F2__MASK 0x00400000L 8504#define RCC_DEV0_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV0_F2__MASK 0x0F800000L 8505#define RCC_DEV0_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F2__MASK 0x70000000L 8506#define RCC_DEV0_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F2__MASK 0x80000000L 8507//RCC_DEV0_EPF2_STRAP5 8508#define RCC_DEV0_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F2__MASK 0x0000FFFFL 8509#define RCC_DEV0_EPF2_STRAP5__STRAP_SATAIDP_EN_DEV0_F2__MASK 0x01000000L 8510//RCC_DEV0_EPF2_STRAP6 8511#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_EN_DEV0_F2__MASK 0x00000001L 8512#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000002L 8513#define RCC_DEV0_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F2__MASK 0x00000070L 8514#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_EN_DEV0_F2__MASK 0x00000100L 8515#define RCC_DEV0_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F2__MASK 0x00000200L 8516//RCC_DEV0_EPF2_STRAP13 8517#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F2__MASK 0x000000FFL 8518#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F2__MASK 0x0000FF00L 8519#define RCC_DEV0_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F2__MASK 0x00FF0000L 8520//RCC_DEV0_EPF3_STRAP0 8521#define RCC_DEV0_EPF3_STRAP0__STRAP_DEVICE_ID_DEV0_F3__MASK 0x0000FFFFL 8522#define RCC_DEV0_EPF3_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F3__MASK 0x000F0000L 8523#define RCC_DEV0_EPF3_STRAP0__STRAP_MINOR_REV_ID_DEV0_F3__MASK 0x00F00000L 8524#define RCC_DEV0_EPF3_STRAP0__STRAP_FUNC_EN_DEV0_F3__MASK 0x10000000L 8525#define RCC_DEV0_EPF3_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F3__MASK 0x20000000L 8526#define RCC_DEV0_EPF3_STRAP0__STRAP_D1_SUPPORT_DEV0_F3__MASK 0x40000000L 8527#define RCC_DEV0_EPF3_STRAP0__STRAP_D2_SUPPORT_DEV0_F3__MASK 0x80000000L 8528//RCC_DEV0_EPF3_STRAP2 8529#define RCC_DEV0_EPF3_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F3__MASK 0x00000080L 8530#define RCC_DEV0_EPF3_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F3__MASK 0x00000100L 8531#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F3__MASK 0x00004000L 8532#define RCC_DEV0_EPF3_STRAP2__STRAP_AER_EN_DEV0_F3__MASK 0x00010000L 8533#define RCC_DEV0_EPF3_STRAP2__STRAP_ACS_EN_DEV0_F3__MASK 0x00020000L 8534#define RCC_DEV0_EPF3_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F3__MASK 0x00100000L 8535#define RCC_DEV0_EPF3_STRAP2__STRAP_DPA_EN_DEV0_F3__MASK 0x00200000L 8536#define RCC_DEV0_EPF3_STRAP2__STRAP_VC_EN_DEV0_F3__MASK 0x00800000L 8537#define RCC_DEV0_EPF3_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F3__MASK 0x07000000L 8538//RCC_DEV0_EPF3_STRAP3 8539#define RCC_DEV0_EPF3_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F3__MASK 0x00000001L 8540#define RCC_DEV0_EPF3_STRAP3__STRAP_PWR_EN_DEV0_F3__MASK 0x00000002L 8541#define RCC_DEV0_EPF3_STRAP3__STRAP_SUBSYS_ID_DEV0_F3__MASK 0x0003FFFCL 8542#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_EN_DEV0_F3__MASK 0x00040000L 8543#define RCC_DEV0_EPF3_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F3__MASK 0x00080000L 8544#define RCC_DEV0_EPF3_STRAP3__STRAP_MSIX_EN_DEV0_F3__MASK 0x00100000L 8545#define RCC_DEV0_EPF3_STRAP3__STRAP_PMC_DSI_DEV0_F3__MASK 0x01000000L 8546#define RCC_DEV0_EPF3_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F3__MASK 0x02000000L 8547#define RCC_DEV0_EPF3_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F3__MASK 0x04000000L 8548#define RCC_DEV0_EPF3_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F3__MASK 0x08000000L 8549//RCC_DEV0_EPF3_STRAP4 8550#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F3__MASK 0x00100000L 8551#define RCC_DEV0_EPF3_STRAP4__STRAP_ATOMIC_EN_DEV0_F3__MASK 0x00200000L 8552#define RCC_DEV0_EPF3_STRAP4__STRAP_FLR_EN_DEV0_F3__MASK 0x00400000L 8553#define RCC_DEV0_EPF3_STRAP4__STRAP_PME_SUPPORT_DEV0_F3__MASK 0x0F800000L 8554#define RCC_DEV0_EPF3_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F3__MASK 0x70000000L 8555#define RCC_DEV0_EPF3_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F3__MASK 0x80000000L 8556//RCC_DEV0_EPF3_STRAP5 8557#define RCC_DEV0_EPF3_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F3__MASK 0x0000FFFFL 8558#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESEL_DEV0_F3__MASK 0x000F0000L 8559#define RCC_DEV0_EPF3_STRAP5__STRAP_USB_DBESELD_DEV0_F3__MASK 0x00F00000L 8560//RCC_DEV0_EPF3_STRAP6 8561#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_EN_DEV0_F3__MASK 0x00000001L 8562#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F3__MASK 0x00000002L 8563#define RCC_DEV0_EPF3_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F3__MASK 0x00000070L 8564//RCC_DEV0_EPF3_STRAP13 8565#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F3__MASK 0x000000FFL 8566#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F3__MASK 0x0000FF00L 8567#define RCC_DEV0_EPF3_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F3__MASK 0x00FF0000L 8568//RCC_DEV0_EPF4_STRAP0 8569#define RCC_DEV0_EPF4_STRAP0__STRAP_DEVICE_ID_DEV0_F4__MASK 0x0000FFFFL 8570#define RCC_DEV0_EPF4_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F4__MASK 0x000F0000L 8571#define RCC_DEV0_EPF4_STRAP0__STRAP_MINOR_REV_ID_DEV0_F4__MASK 0x00F00000L 8572#define RCC_DEV0_EPF4_STRAP0__STRAP_FUNC_EN_DEV0_F4__MASK 0x10000000L 8573#define RCC_DEV0_EPF4_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F4__MASK 0x20000000L 8574#define RCC_DEV0_EPF4_STRAP0__STRAP_D1_SUPPORT_DEV0_F4__MASK 0x40000000L 8575#define RCC_DEV0_EPF4_STRAP0__STRAP_D2_SUPPORT_DEV0_F4__MASK 0x80000000L 8576//RCC_DEV0_EPF4_STRAP2 8577#define RCC_DEV0_EPF4_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F4__MASK 0x00000080L 8578#define RCC_DEV0_EPF4_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F4__MASK 0x00000100L 8579#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F4__MASK 0x00004000L 8580#define RCC_DEV0_EPF4_STRAP2__STRAP_AER_EN_DEV0_F4__MASK 0x00010000L 8581#define RCC_DEV0_EPF4_STRAP2__STRAP_ACS_EN_DEV0_F4__MASK 0x00020000L 8582#define RCC_DEV0_EPF4_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F4__MASK 0x00100000L 8583#define RCC_DEV0_EPF4_STRAP2__STRAP_DPA_EN_DEV0_F4__MASK 0x00200000L 8584#define RCC_DEV0_EPF4_STRAP2__STRAP_VC_EN_DEV0_F4__MASK 0x00800000L 8585#define RCC_DEV0_EPF4_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F4__MASK 0x07000000L 8586//RCC_DEV0_EPF4_STRAP3 8587#define RCC_DEV0_EPF4_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F4__MASK 0x00000001L 8588#define RCC_DEV0_EPF4_STRAP3__STRAP_PWR_EN_DEV0_F4__MASK 0x00000002L 8589#define RCC_DEV0_EPF4_STRAP3__STRAP_SUBSYS_ID_DEV0_F4__MASK 0x0003FFFCL 8590#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_EN_DEV0_F4__MASK 0x00040000L 8591#define RCC_DEV0_EPF4_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F4__MASK 0x00080000L 8592#define RCC_DEV0_EPF4_STRAP3__STRAP_MSIX_EN_DEV0_F4__MASK 0x00100000L 8593#define RCC_DEV0_EPF4_STRAP3__STRAP_PMC_DSI_DEV0_F4__MASK 0x01000000L 8594#define RCC_DEV0_EPF4_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F4__MASK 0x02000000L 8595#define RCC_DEV0_EPF4_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F4__MASK 0x04000000L 8596#define RCC_DEV0_EPF4_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F4__MASK 0x08000000L 8597//RCC_DEV0_EPF4_STRAP4 8598#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F4__MASK 0x00100000L 8599#define RCC_DEV0_EPF4_STRAP4__STRAP_ATOMIC_EN_DEV0_F4__MASK 0x00200000L 8600#define RCC_DEV0_EPF4_STRAP4__STRAP_FLR_EN_DEV0_F4__MASK 0x00400000L 8601#define RCC_DEV0_EPF4_STRAP4__STRAP_PME_SUPPORT_DEV0_F4__MASK 0x0F800000L 8602#define RCC_DEV0_EPF4_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F4__MASK 0x70000000L 8603#define RCC_DEV0_EPF4_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F4__MASK 0x80000000L 8604//RCC_DEV0_EPF4_STRAP5 8605#define RCC_DEV0_EPF4_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F4__MASK 0x0000FFFFL 8606#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESEL_DEV0_F4__MASK 0x000F0000L 8607#define RCC_DEV0_EPF4_STRAP5__STRAP_USB_DBESELD_DEV0_F4__MASK 0x00F00000L 8608//RCC_DEV0_EPF4_STRAP6 8609#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_EN_DEV0_F4__MASK 0x00000001L 8610#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000002L 8611#define RCC_DEV0_EPF4_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F4__MASK 0x00000070L 8612#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_EN_DEV0_F4__MASK 0x00000100L 8613#define RCC_DEV0_EPF4_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F4__MASK 0x00000200L 8614#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_EN_DEV0_F4__MASK 0x00010000L 8615#define RCC_DEV0_EPF4_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F4__MASK 0x00020000L 8616//RCC_DEV0_EPF4_STRAP13 8617#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F4__MASK 0x000000FFL 8618#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F4__MASK 0x0000FF00L 8619#define RCC_DEV0_EPF4_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F4__MASK 0x00FF0000L 8620//RCC_DEV0_EPF5_STRAP0 8621#define RCC_DEV0_EPF5_STRAP0__STRAP_DEVICE_ID_DEV0_F5__MASK 0x0000FFFFL 8622#define RCC_DEV0_EPF5_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F5__MASK 0x000F0000L 8623#define RCC_DEV0_EPF5_STRAP0__STRAP_MINOR_REV_ID_DEV0_F5__MASK 0x00F00000L 8624#define RCC_DEV0_EPF5_STRAP0__STRAP_FUNC_EN_DEV0_F5__MASK 0x10000000L 8625#define RCC_DEV0_EPF5_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F5__MASK 0x20000000L 8626#define RCC_DEV0_EPF5_STRAP0__STRAP_D1_SUPPORT_DEV0_F5__MASK 0x40000000L 8627#define RCC_DEV0_EPF5_STRAP0__STRAP_D2_SUPPORT_DEV0_F5__MASK 0x80000000L 8628//RCC_DEV0_EPF5_STRAP2 8629#define RCC_DEV0_EPF5_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F5__MASK 0x00000080L 8630#define RCC_DEV0_EPF5_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F5__MASK 0x00000100L 8631#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F5__MASK 0x00004000L 8632#define RCC_DEV0_EPF5_STRAP2__STRAP_AER_EN_DEV0_F5__MASK 0x00010000L 8633#define RCC_DEV0_EPF5_STRAP2__STRAP_ACS_EN_DEV0_F5__MASK 0x00020000L 8634#define RCC_DEV0_EPF5_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F5__MASK 0x00100000L 8635#define RCC_DEV0_EPF5_STRAP2__STRAP_DPA_EN_DEV0_F5__MASK 0x00200000L 8636#define RCC_DEV0_EPF5_STRAP2__STRAP_VC_EN_DEV0_F5__MASK 0x00800000L 8637#define RCC_DEV0_EPF5_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F5__MASK 0x07000000L 8638//RCC_DEV0_EPF5_STRAP3 8639#define RCC_DEV0_EPF5_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F5__MASK 0x00000001L 8640#define RCC_DEV0_EPF5_STRAP3__STRAP_PWR_EN_DEV0_F5__MASK 0x00000002L 8641#define RCC_DEV0_EPF5_STRAP3__STRAP_SUBSYS_ID_DEV0_F5__MASK 0x0003FFFCL 8642#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_EN_DEV0_F5__MASK 0x00040000L 8643#define RCC_DEV0_EPF5_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F5__MASK 0x00080000L 8644#define RCC_DEV0_EPF5_STRAP3__STRAP_MSIX_EN_DEV0_F5__MASK 0x00100000L 8645#define RCC_DEV0_EPF5_STRAP3__STRAP_PMC_DSI_DEV0_F5__MASK 0x01000000L 8646#define RCC_DEV0_EPF5_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F5__MASK 0x02000000L 8647#define RCC_DEV0_EPF5_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F5__MASK 0x04000000L 8648#define RCC_DEV0_EPF5_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F5__MASK 0x08000000L 8649//RCC_DEV0_EPF5_STRAP4 8650#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F5__MASK 0x00100000L 8651#define RCC_DEV0_EPF5_STRAP4__STRAP_ATOMIC_EN_DEV0_F5__MASK 0x00200000L 8652#define RCC_DEV0_EPF5_STRAP4__STRAP_FLR_EN_DEV0_F5__MASK 0x00400000L 8653#define RCC_DEV0_EPF5_STRAP4__STRAP_PME_SUPPORT_DEV0_F5__MASK 0x0F800000L 8654#define RCC_DEV0_EPF5_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F5__MASK 0x70000000L 8655#define RCC_DEV0_EPF5_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F5__MASK 0x80000000L 8656//RCC_DEV0_EPF5_STRAP5 8657#define RCC_DEV0_EPF5_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F5__MASK 0x0000FFFFL 8658//RCC_DEV0_EPF5_STRAP6 8659#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_EN_DEV0_F5__MASK 0x00000001L 8660#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000002L 8661#define RCC_DEV0_EPF5_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F5__MASK 0x00000070L 8662#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_EN_DEV0_F5__MASK 0x00000100L 8663#define RCC_DEV0_EPF5_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F5__MASK 0x00000200L 8664#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_EN_DEV0_F5__MASK 0x00010000L 8665#define RCC_DEV0_EPF5_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F5__MASK 0x00020000L 8666//RCC_DEV0_EPF5_STRAP13 8667#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F5__MASK 0x000000FFL 8668#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F5__MASK 0x0000FF00L 8669#define RCC_DEV0_EPF5_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F5__MASK 0x00FF0000L 8670//RCC_DEV0_EPF6_STRAP0 8671#define RCC_DEV0_EPF6_STRAP0__STRAP_DEVICE_ID_DEV0_F6__MASK 0x0000FFFFL 8672#define RCC_DEV0_EPF6_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F6__MASK 0x000F0000L 8673#define RCC_DEV0_EPF6_STRAP0__STRAP_MINOR_REV_ID_DEV0_F6__MASK 0x00F00000L 8674#define RCC_DEV0_EPF6_STRAP0__STRAP_FUNC_EN_DEV0_F6__MASK 0x10000000L 8675#define RCC_DEV0_EPF6_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F6__MASK 0x20000000L 8676#define RCC_DEV0_EPF6_STRAP0__STRAP_D1_SUPPORT_DEV0_F6__MASK 0x40000000L 8677#define RCC_DEV0_EPF6_STRAP0__STRAP_D2_SUPPORT_DEV0_F6__MASK 0x80000000L 8678//RCC_DEV0_EPF6_STRAP2 8679#define RCC_DEV0_EPF6_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F6__MASK 0x00000080L 8680#define RCC_DEV0_EPF6_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F6__MASK 0x00000100L 8681#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F6__MASK 0x00004000L 8682#define RCC_DEV0_EPF6_STRAP2__STRAP_AER_EN_DEV0_F6__MASK 0x00010000L 8683#define RCC_DEV0_EPF6_STRAP2__STRAP_ACS_EN_DEV0_F6__MASK 0x00020000L 8684#define RCC_DEV0_EPF6_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F6__MASK 0x00100000L 8685#define RCC_DEV0_EPF6_STRAP2__STRAP_DPA_EN_DEV0_F6__MASK 0x00200000L 8686#define RCC_DEV0_EPF6_STRAP2__STRAP_VC_EN_DEV0_F6__MASK 0x00800000L 8687#define RCC_DEV0_EPF6_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F6__MASK 0x07000000L 8688//RCC_DEV0_EPF6_STRAP3 8689#define RCC_DEV0_EPF6_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F6__MASK 0x00000001L 8690#define RCC_DEV0_EPF6_STRAP3__STRAP_PWR_EN_DEV0_F6__MASK 0x00000002L 8691#define RCC_DEV0_EPF6_STRAP3__STRAP_SUBSYS_ID_DEV0_F6__MASK 0x0003FFFCL 8692#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_EN_DEV0_F6__MASK 0x00040000L 8693#define RCC_DEV0_EPF6_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F6__MASK 0x00080000L 8694#define RCC_DEV0_EPF6_STRAP3__STRAP_MSIX_EN_DEV0_F6__MASK 0x00100000L 8695#define RCC_DEV0_EPF6_STRAP3__STRAP_PMC_DSI_DEV0_F6__MASK 0x01000000L 8696#define RCC_DEV0_EPF6_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F6__MASK 0x02000000L 8697#define RCC_DEV0_EPF6_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F6__MASK 0x04000000L 8698#define RCC_DEV0_EPF6_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F6__MASK 0x08000000L 8699//RCC_DEV0_EPF6_STRAP4 8700#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F6__MASK 0x00100000L 8701#define RCC_DEV0_EPF6_STRAP4__STRAP_ATOMIC_EN_DEV0_F6__MASK 0x00200000L 8702#define RCC_DEV0_EPF6_STRAP4__STRAP_FLR_EN_DEV0_F6__MASK 0x00400000L 8703#define RCC_DEV0_EPF6_STRAP4__STRAP_PME_SUPPORT_DEV0_F6__MASK 0x0F800000L 8704#define RCC_DEV0_EPF6_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F6__MASK 0x70000000L 8705#define RCC_DEV0_EPF6_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F6__MASK 0x80000000L 8706//RCC_DEV0_EPF6_STRAP5 8707#define RCC_DEV0_EPF6_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F6__MASK 0x0000FFFFL 8708//RCC_DEV0_EPF6_STRAP6 8709#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_EN_DEV0_F6__MASK 0x00000001L 8710#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000002L 8711#define RCC_DEV0_EPF6_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F6__MASK 0x00000070L 8712#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_EN_DEV0_F6__MASK 0x00000100L 8713#define RCC_DEV0_EPF6_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F6__MASK 0x00000200L 8714#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_EN_DEV0_F6__MASK 0x00010000L 8715#define RCC_DEV0_EPF6_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F6__MASK 0x00020000L 8716//RCC_DEV0_EPF6_STRAP13 8717#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F6__MASK 0x000000FFL 8718#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F6__MASK 0x0000FF00L 8719#define RCC_DEV0_EPF6_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F6__MASK 0x00FF0000L 8720//RCC_DEV0_EPF7_STRAP0 8721#define RCC_DEV0_EPF7_STRAP0__STRAP_DEVICE_ID_DEV0_F7__MASK 0x0000FFFFL 8722#define RCC_DEV0_EPF7_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F7__MASK 0x000F0000L 8723#define RCC_DEV0_EPF7_STRAP0__STRAP_MINOR_REV_ID_DEV0_F7__MASK 0x00F00000L 8724#define RCC_DEV0_EPF7_STRAP0__STRAP_FUNC_EN_DEV0_F7__MASK 0x10000000L 8725#define RCC_DEV0_EPF7_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F7__MASK 0x20000000L 8726#define RCC_DEV0_EPF7_STRAP0__STRAP_D1_SUPPORT_DEV0_F7__MASK 0x40000000L 8727#define RCC_DEV0_EPF7_STRAP0__STRAP_D2_SUPPORT_DEV0_F7__MASK 0x80000000L 8728//RCC_DEV0_EPF7_STRAP2 8729#define RCC_DEV0_EPF7_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F7__MASK 0x00000080L 8730#define RCC_DEV0_EPF7_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F7__MASK 0x00000100L 8731#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F7__MASK 0x00004000L 8732#define RCC_DEV0_EPF7_STRAP2__STRAP_AER_EN_DEV0_F7__MASK 0x00010000L 8733#define RCC_DEV0_EPF7_STRAP2__STRAP_ACS_EN_DEV0_F7__MASK 0x00020000L 8734#define RCC_DEV0_EPF7_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F7__MASK 0x00100000L 8735#define RCC_DEV0_EPF7_STRAP2__STRAP_DPA_EN_DEV0_F7__MASK 0x00200000L 8736#define RCC_DEV0_EPF7_STRAP2__STRAP_VC_EN_DEV0_F7__MASK 0x00800000L 8737#define RCC_DEV0_EPF7_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F7__MASK 0x07000000L 8738//RCC_DEV0_EPF7_STRAP3 8739#define RCC_DEV0_EPF7_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F7__MASK 0x00000001L 8740#define RCC_DEV0_EPF7_STRAP3__STRAP_PWR_EN_DEV0_F7__MASK 0x00000002L 8741#define RCC_DEV0_EPF7_STRAP3__STRAP_SUBSYS_ID_DEV0_F7__MASK 0x0003FFFCL 8742#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_EN_DEV0_F7__MASK 0x00040000L 8743#define RCC_DEV0_EPF7_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F7__MASK 0x00080000L 8744#define RCC_DEV0_EPF7_STRAP3__STRAP_MSIX_EN_DEV0_F7__MASK 0x00100000L 8745#define RCC_DEV0_EPF7_STRAP3__STRAP_PMC_DSI_DEV0_F7__MASK 0x01000000L 8746#define RCC_DEV0_EPF7_STRAP3__STRAP_VENDOR_ID_BIT_DEV0_F7__MASK 0x02000000L 8747#define RCC_DEV0_EPF7_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F7__MASK 0x04000000L 8748#define RCC_DEV0_EPF7_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F7__MASK 0x08000000L 8749//RCC_DEV0_EPF7_STRAP4 8750#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F7__MASK 0x00100000L 8751#define RCC_DEV0_EPF7_STRAP4__STRAP_ATOMIC_EN_DEV0_F7__MASK 0x00200000L 8752#define RCC_DEV0_EPF7_STRAP4__STRAP_FLR_EN_DEV0_F7__MASK 0x00400000L 8753#define RCC_DEV0_EPF7_STRAP4__STRAP_PME_SUPPORT_DEV0_F7__MASK 0x0F800000L 8754#define RCC_DEV0_EPF7_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F7__MASK 0x70000000L 8755#define RCC_DEV0_EPF7_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F7__MASK 0x80000000L 8756//RCC_DEV0_EPF7_STRAP5 8757#define RCC_DEV0_EPF7_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F7__MASK 0x0000FFFFL 8758//RCC_DEV0_EPF7_STRAP6 8759#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_EN_DEV0_F7__MASK 0x00000001L 8760#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000002L 8761#define RCC_DEV0_EPF7_STRAP6__STRAP_APER0_AP_SIZE_DEV0_F7__MASK 0x00000070L 8762#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_EN_DEV0_F7__MASK 0x00000100L 8763#define RCC_DEV0_EPF7_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F7__MASK 0x00000200L 8764#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_EN_DEV0_F7__MASK 0x00010000L 8765#define RCC_DEV0_EPF7_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F7__MASK 0x00020000L 8766//RCC_DEV0_EPF7_STRAP13 8767#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F7__MASK 0x000000FFL 8768#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F7__MASK 0x0000FF00L 8769#define RCC_DEV0_EPF7_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F7__MASK 0x00FF0000L 8770//RCC_DEV1_EPF0_STRAP0 8771#define RCC_DEV1_EPF0_STRAP0__STRAP_DEVICE_ID_DEV1_F0__MASK 0x0000FFFFL 8772#define RCC_DEV1_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F0__MASK 0x000F0000L 8773#define RCC_DEV1_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV1_F0__MASK 0x00F00000L 8774#define RCC_DEV1_EPF0_STRAP0__STRAP_FUNC_EN_DEV1_F0__MASK 0x10000000L 8775#define RCC_DEV1_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F0__MASK 0x20000000L 8776#define RCC_DEV1_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV1_F0__MASK 0x40000000L 8777#define RCC_DEV1_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV1_F0__MASK 0x80000000L 8778//RCC_DEV1_EPF0_STRAP2 8779#define RCC_DEV1_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F0__MASK 0x00000080L 8780#define RCC_DEV1_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F0__MASK 0x00000100L 8781#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F0__MASK 0x00004000L 8782#define RCC_DEV1_EPF0_STRAP2__STRAP_ARI_EN_DEV1_F0__MASK 0x00008000L 8783#define RCC_DEV1_EPF0_STRAP2__STRAP_AER_EN_DEV1_F0__MASK 0x00010000L 8784#define RCC_DEV1_EPF0_STRAP2__STRAP_ACS_EN_DEV1_F0__MASK 0x00020000L 8785#define RCC_DEV1_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F0__MASK 0x00100000L 8786#define RCC_DEV1_EPF0_STRAP2__STRAP_DPA_EN_DEV1_F0__MASK 0x00200000L 8787#define RCC_DEV1_EPF0_STRAP2__STRAP_VC_EN_DEV1_F0__MASK 0x00800000L 8788#define RCC_DEV1_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F0__MASK 0x07000000L 8789//RCC_DEV1_EPF0_STRAP3 8790#define RCC_DEV1_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F0__MASK 0x00000001L 8791#define RCC_DEV1_EPF0_STRAP3__STRAP_PWR_EN_DEV1_F0__MASK 0x00000002L 8792#define RCC_DEV1_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV1_F0__MASK 0x0003FFFCL 8793#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_EN_DEV1_F0__MASK 0x00040000L 8794#define RCC_DEV1_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F0__MASK 0x00080000L 8795#define RCC_DEV1_EPF0_STRAP3__STRAP_MSIX_EN_DEV1_F0__MASK 0x00100000L 8796#define RCC_DEV1_EPF0_STRAP3__STRAP_PMC_DSI_DEV1_F0__MASK 0x01000000L 8797#define RCC_DEV1_EPF0_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F0__MASK 0x02000000L 8798#define RCC_DEV1_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F0__MASK 0x04000000L 8799#define RCC_DEV1_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F0__MASK 0x08000000L 8800//RCC_DEV1_EPF0_STRAP4 8801#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F0__MASK 0x00100000L 8802#define RCC_DEV1_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV1_F0__MASK 0x00200000L 8803#define RCC_DEV1_EPF0_STRAP4__STRAP_FLR_EN_DEV1_F0__MASK 0x00400000L 8804#define RCC_DEV1_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV1_F0__MASK 0x0F800000L 8805#define RCC_DEV1_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F0__MASK 0x70000000L 8806#define RCC_DEV1_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F0__MASK 0x80000000L 8807//RCC_DEV1_EPF0_STRAP5 8808#define RCC_DEV1_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F0__MASK 0x0000FFFFL 8809#define RCC_DEV1_EPF0_STRAP5__STRAP_SATAIDP_EN_DEV1_F0__MASK 0x01000000L 8810//RCC_DEV1_EPF0_STRAP6 8811#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_EN_DEV1_F0__MASK 0x00000001L 8812#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F0__MASK 0x00000002L 8813#define RCC_DEV1_EPF0_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F0__MASK 0x00000070L 8814//RCC_DEV1_EPF0_STRAP13 8815#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F0__MASK 0x000000FFL 8816#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F0__MASK 0x0000FF00L 8817#define RCC_DEV1_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F0__MASK 0x00FF0000L 8818//RCC_DEV1_EPF1_STRAP0 8819#define RCC_DEV1_EPF1_STRAP0__STRAP_DEVICE_ID_DEV1_F1__MASK 0x0000FFFFL 8820#define RCC_DEV1_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F1__MASK 0x000F0000L 8821#define RCC_DEV1_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV1_F1__MASK 0x00F00000L 8822#define RCC_DEV1_EPF1_STRAP0__STRAP_FUNC_EN_DEV1_F1__MASK 0x10000000L 8823#define RCC_DEV1_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F1__MASK 0x20000000L 8824#define RCC_DEV1_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV1_F1__MASK 0x40000000L 8825#define RCC_DEV1_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV1_F1__MASK 0x80000000L 8826//RCC_DEV1_EPF1_STRAP2 8827#define RCC_DEV1_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F1__MASK 0x00000080L 8828#define RCC_DEV1_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F1__MASK 0x00000100L 8829#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F1__MASK 0x00004000L 8830#define RCC_DEV1_EPF1_STRAP2__STRAP_AER_EN_DEV1_F1__MASK 0x00010000L 8831#define RCC_DEV1_EPF1_STRAP2__STRAP_ACS_EN_DEV1_F1__MASK 0x00020000L 8832#define RCC_DEV1_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F1__MASK 0x00100000L 8833#define RCC_DEV1_EPF1_STRAP2__STRAP_DPA_EN_DEV1_F1__MASK 0x00200000L 8834#define RCC_DEV1_EPF1_STRAP2__STRAP_VC_EN_DEV1_F1__MASK 0x00800000L 8835#define RCC_DEV1_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F1__MASK 0x07000000L 8836//RCC_DEV1_EPF1_STRAP3 8837#define RCC_DEV1_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F1__MASK 0x00000001L 8838#define RCC_DEV1_EPF1_STRAP3__STRAP_PWR_EN_DEV1_F1__MASK 0x00000002L 8839#define RCC_DEV1_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV1_F1__MASK 0x0003FFFCL 8840#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_EN_DEV1_F1__MASK 0x00040000L 8841#define RCC_DEV1_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F1__MASK 0x00080000L 8842#define RCC_DEV1_EPF1_STRAP3__STRAP_MSIX_EN_DEV1_F1__MASK 0x00100000L 8843#define RCC_DEV1_EPF1_STRAP3__STRAP_PMC_DSI_DEV1_F1__MASK 0x01000000L 8844#define RCC_DEV1_EPF1_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F1__MASK 0x02000000L 8845#define RCC_DEV1_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F1__MASK 0x04000000L 8846#define RCC_DEV1_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F1__MASK 0x08000000L 8847//RCC_DEV1_EPF1_STRAP4 8848#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F1__MASK 0x00100000L 8849#define RCC_DEV1_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV1_F1__MASK 0x00200000L 8850#define RCC_DEV1_EPF1_STRAP4__STRAP_FLR_EN_DEV1_F1__MASK 0x00400000L 8851#define RCC_DEV1_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV1_F1__MASK 0x0F800000L 8852#define RCC_DEV1_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F1__MASK 0x70000000L 8853#define RCC_DEV1_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F1__MASK 0x80000000L 8854//RCC_DEV1_EPF1_STRAP5 8855#define RCC_DEV1_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F1__MASK 0x0000FFFFL 8856//RCC_DEV1_EPF1_STRAP6 8857#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_EN_DEV1_F1__MASK 0x00000001L 8858#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000002L 8859#define RCC_DEV1_EPF1_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F1__MASK 0x00000070L 8860#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_EN_DEV1_F1__MASK 0x00000100L 8861#define RCC_DEV1_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F1__MASK 0x00000200L 8862#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_EN_DEV1_F1__MASK 0x00010000L 8863#define RCC_DEV1_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F1__MASK 0x00020000L 8864#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_EN_DEV1_F1__MASK 0x01000000L 8865#define RCC_DEV1_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F1__MASK 0x02000000L 8866//RCC_DEV1_EPF1_STRAP13 8867#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F1__MASK 0x000000FFL 8868#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F1__MASK 0x0000FF00L 8869#define RCC_DEV1_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F1__MASK 0x00FF0000L 8870//RCC_DEV1_EPF2_STRAP0 8871#define RCC_DEV1_EPF2_STRAP0__STRAP_DEVICE_ID_DEV1_F2__MASK 0x0000FFFFL 8872#define RCC_DEV1_EPF2_STRAP0__STRAP_MAJOR_REV_ID_DEV1_F2__MASK 0x000F0000L 8873#define RCC_DEV1_EPF2_STRAP0__STRAP_MINOR_REV_ID_DEV1_F2__MASK 0x00F00000L 8874#define RCC_DEV1_EPF2_STRAP0__STRAP_FUNC_EN_DEV1_F2__MASK 0x10000000L 8875#define RCC_DEV1_EPF2_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV1_F2__MASK 0x20000000L 8876#define RCC_DEV1_EPF2_STRAP0__STRAP_D1_SUPPORT_DEV1_F2__MASK 0x40000000L 8877#define RCC_DEV1_EPF2_STRAP0__STRAP_D2_SUPPORT_DEV1_F2__MASK 0x80000000L 8878//RCC_DEV1_EPF2_STRAP2 8879#define RCC_DEV1_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV1_F2__MASK 0x00000080L 8880#define RCC_DEV1_EPF2_STRAP2__STRAP_RESIZE_BAR_EN_DEV1_F2__MASK 0x00000100L 8881#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV1_F2__MASK 0x00004000L 8882#define RCC_DEV1_EPF2_STRAP2__STRAP_AER_EN_DEV1_F2__MASK 0x00010000L 8883#define RCC_DEV1_EPF2_STRAP2__STRAP_ACS_EN_DEV1_F2__MASK 0x00020000L 8884#define RCC_DEV1_EPF2_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV1_F2__MASK 0x00100000L 8885#define RCC_DEV1_EPF2_STRAP2__STRAP_DPA_EN_DEV1_F2__MASK 0x00200000L 8886#define RCC_DEV1_EPF2_STRAP2__STRAP_VC_EN_DEV1_F2__MASK 0x00800000L 8887#define RCC_DEV1_EPF2_STRAP2__STRAP_MSI_MULTI_CAP_DEV1_F2__MASK 0x07000000L 8888//RCC_DEV1_EPF2_STRAP3 8889#define RCC_DEV1_EPF2_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV1_F2__MASK 0x00000001L 8890#define RCC_DEV1_EPF2_STRAP3__STRAP_PWR_EN_DEV1_F2__MASK 0x00000002L 8891#define RCC_DEV1_EPF2_STRAP3__STRAP_SUBSYS_ID_DEV1_F2__MASK 0x0003FFFCL 8892#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_EN_DEV1_F2__MASK 0x00040000L 8893#define RCC_DEV1_EPF2_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV1_F2__MASK 0x00080000L 8894#define RCC_DEV1_EPF2_STRAP3__STRAP_MSIX_EN_DEV1_F2__MASK 0x00100000L 8895#define RCC_DEV1_EPF2_STRAP3__STRAP_PMC_DSI_DEV1_F2__MASK 0x01000000L 8896#define RCC_DEV1_EPF2_STRAP3__STRAP_VENDOR_ID_BIT_DEV1_F2__MASK 0x02000000L 8897#define RCC_DEV1_EPF2_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV1_F2__MASK 0x04000000L 8898#define RCC_DEV1_EPF2_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV1_F2__MASK 0x08000000L 8899//RCC_DEV1_EPF2_STRAP4 8900#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV1_F2__MASK 0x00100000L 8901#define RCC_DEV1_EPF2_STRAP4__STRAP_ATOMIC_EN_DEV1_F2__MASK 0x00200000L 8902#define RCC_DEV1_EPF2_STRAP4__STRAP_FLR_EN_DEV1_F2__MASK 0x00400000L 8903#define RCC_DEV1_EPF2_STRAP4__STRAP_PME_SUPPORT_DEV1_F2__MASK 0x0F800000L 8904#define RCC_DEV1_EPF2_STRAP4__STRAP_INTERRUPT_PIN_DEV1_F2__MASK 0x70000000L 8905#define RCC_DEV1_EPF2_STRAP4__STRAP_AUXPWR_SUPPORT_DEV1_F2__MASK 0x80000000L 8906//RCC_DEV1_EPF2_STRAP5 8907#define RCC_DEV1_EPF2_STRAP5__STRAP_SUBSYS_VEN_ID_DEV1_F2__MASK 0x0000FFFFL 8908//RCC_DEV1_EPF2_STRAP6 8909#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_EN_DEV1_F2__MASK 0x00000001L 8910#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000002L 8911#define RCC_DEV1_EPF2_STRAP6__STRAP_APER0_AP_SIZE_DEV1_F2__MASK 0x00000070L 8912#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_EN_DEV1_F2__MASK 0x00000100L 8913#define RCC_DEV1_EPF2_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV1_F2__MASK 0x00000200L 8914#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_EN_DEV1_F2__MASK 0x00010000L 8915#define RCC_DEV1_EPF2_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV1_F2__MASK 0x00020000L 8916#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_EN_DEV1_F2__MASK 0x01000000L 8917#define RCC_DEV1_EPF2_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV1_F2__MASK 0x02000000L 8918//RCC_DEV1_EPF2_STRAP13 8919#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_PIF_DEV1_F2__MASK 0x000000FFL 8920#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_SUB_DEV1_F2__MASK 0x0000FF00L 8921#define RCC_DEV1_EPF2_STRAP13__STRAP_CLASS_CODE_BASE_DEV1_F2__MASK 0x00FF0000L 8922 8923 8924// addressBlock: bif_rst_bif_rst_regblk 8925//HARD_RST_CTRL 8926#define HARD_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L 8927#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L 8928#define HARD_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L 8929#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L 8930#define HARD_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L 8931#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L 8932#define HARD_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L 8933#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L 8934#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L 8935#define HARD_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L 8936#define HARD_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L 8937#define HARD_RST_CTRL__CORE_RST_EN__MASK 0x80000000L 8938//RSMU_SOFT_RST_CTRL 8939#define RSMU_SOFT_RST_CTRL__DSPT_CFG_RST_EN__MASK 0x00000001L 8940#define RSMU_SOFT_RST_CTRL__DSPT_CFG_STICKY_RST_EN__MASK 0x00000002L 8941#define RSMU_SOFT_RST_CTRL__DSPT_PRV_RST_EN__MASK 0x00000004L 8942#define RSMU_SOFT_RST_CTRL__DSPT_PRV_STICKY_RST_EN__MASK 0x00000008L 8943#define RSMU_SOFT_RST_CTRL__EP_CFG_RST_EN__MASK 0x00000010L 8944#define RSMU_SOFT_RST_CTRL__EP_CFG_STICKY_RST_EN__MASK 0x00000020L 8945#define RSMU_SOFT_RST_CTRL__EP_PRV_RST_EN__MASK 0x00000040L 8946#define RSMU_SOFT_RST_CTRL__EP_PRV_STICKY_RST_EN__MASK 0x00000080L 8947#define RSMU_SOFT_RST_CTRL__SWUS_SHADOW_RST_EN__MASK 0x10000000L 8948#define RSMU_SOFT_RST_CTRL__CORE_STICKY_RST_EN__MASK 0x20000000L 8949#define RSMU_SOFT_RST_CTRL__RELOAD_STRAP_EN__MASK 0x40000000L 8950#define RSMU_SOFT_RST_CTRL__CORE_RST_EN__MASK 0x80000000L 8951//SELF_SOFT_RST 8952#define SELF_SOFT_RST__DSPT0_CFG_RST__MASK 0x00000001L 8953#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__MASK 0x00000002L 8954#define SELF_SOFT_RST__DSPT0_PRV_RST__MASK 0x00000004L 8955#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__MASK 0x00000008L 8956#define SELF_SOFT_RST__EP0_CFG_RST__MASK 0x00000010L 8957#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__MASK 0x00000020L 8958#define SELF_SOFT_RST__EP0_PRV_RST__MASK 0x00000040L 8959#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__MASK 0x00000080L 8960#define SELF_SOFT_RST__SDP_PORT_RST__MASK 0x08000000L 8961#define SELF_SOFT_RST__SWUS_SHADOW_RST__MASK 0x10000000L 8962#define SELF_SOFT_RST__CORE_STICKY_RST__MASK 0x20000000L 8963#define SELF_SOFT_RST__RELOAD_STRAP__MASK 0x40000000L 8964#define SELF_SOFT_RST__CORE_RST__MASK 0x80000000L 8965//GFX_DRV_MODE1_RST_CTRL 8966#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_RST__MASK 0x00000001L 8967#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_FLR_EXC_RST__MASK 0x00000002L 8968#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_CFG_STICKY_RST__MASK 0x00000004L 8969#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_RST__MASK 0x00000008L 8970#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_PF_PRV_STICKY_RST__MASK 0x00000010L 8971#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_RST__MASK 0x00000020L 8972#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_CFG_STICKY_RST__MASK 0x00000040L 8973#define GFX_DRV_MODE1_RST_CTRL__DRV_MODE1_VF_PRV_RST__MASK 0x00000080L 8974//BIF_RST_MISC_CTRL 8975#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__MASK 0x00000001L 8976#define BIF_RST_MISC_CTRL__DRV_RST_MODE__MASK 0x0000000CL 8977#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__MASK 0x00000010L 8978#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__MASK 0x00000020L 8979#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__MASK 0x00000040L 8980#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__MASK 0x00000100L 8981#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__MASK 0x00000200L 8982#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__MASK 0x00001C00L 8983#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__MASK 0x00006000L 8984#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__MASK 0x00018000L 8985#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__MASK 0x00060000L 8986#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__MASK 0x00800000L 8987#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__MASK 0x03000000L 8988//BIF_RST_MISC_CTRL2 8989#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__MASK 0x00010000L 8990#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__MASK 0x00020000L 8991#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__MASK 0x00040000L 8992#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__MASK 0x80000000L 8993//BIF_RST_MISC_CTRL3 8994#define BIF_RST_MISC_CTRL3__TIMER_SCALE__MASK 0x0000000FL 8995#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__MASK 0x00000030L 8996#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__MASK 0x00000040L 8997#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__MASK 0x00000380L 8998#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__MASK 0x00001C00L 8999#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__MASK 0x0000E000L 9000//BIF_RST_GFXVF_FLR_IDLE 9001#define BIF_RST_GFXVF_FLR_IDLE__VF0_TRANS_IDLE__MASK 0x00000001L 9002#define BIF_RST_GFXVF_FLR_IDLE__VF1_TRANS_IDLE__MASK 0x00000002L 9003#define BIF_RST_GFXVF_FLR_IDLE__VF2_TRANS_IDLE__MASK 0x00000004L 9004#define BIF_RST_GFXVF_FLR_IDLE__VF3_TRANS_IDLE__MASK 0x00000008L 9005#define BIF_RST_GFXVF_FLR_IDLE__VF4_TRANS_IDLE__MASK 0x00000010L 9006#define BIF_RST_GFXVF_FLR_IDLE__VF5_TRANS_IDLE__MASK 0x00000020L 9007#define BIF_RST_GFXVF_FLR_IDLE__VF6_TRANS_IDLE__MASK 0x00000040L 9008#define BIF_RST_GFXVF_FLR_IDLE__VF7_TRANS_IDLE__MASK 0x00000080L 9009#define BIF_RST_GFXVF_FLR_IDLE__VF8_TRANS_IDLE__MASK 0x00000100L 9010#define BIF_RST_GFXVF_FLR_IDLE__VF9_TRANS_IDLE__MASK 0x00000200L 9011#define BIF_RST_GFXVF_FLR_IDLE__VF10_TRANS_IDLE__MASK 0x00000400L 9012#define BIF_RST_GFXVF_FLR_IDLE__VF11_TRANS_IDLE__MASK 0x00000800L 9013#define BIF_RST_GFXVF_FLR_IDLE__VF12_TRANS_IDLE__MASK 0x00001000L 9014#define BIF_RST_GFXVF_FLR_IDLE__VF13_TRANS_IDLE__MASK 0x00002000L 9015#define BIF_RST_GFXVF_FLR_IDLE__VF14_TRANS_IDLE__MASK 0x00004000L 9016#define BIF_RST_GFXVF_FLR_IDLE__VF15_TRANS_IDLE__MASK 0x00008000L 9017#define BIF_RST_GFXVF_FLR_IDLE__SOFTPF_TRANS_IDLE__MASK 0x80000000L 9018//DEV0_PF0_FLR_RST_CTRL 9019#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9020#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9021#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9022#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9023#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9024#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_EN__MASK 0x00000020L 9025#define DEV0_PF0_FLR_RST_CTRL__VF_CFG_STICKY_EN__MASK 0x00000040L 9026#define DEV0_PF0_FLR_RST_CTRL__VF_PRV_EN__MASK 0x00000080L 9027#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__MASK 0x00000100L 9028#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__MASK 0x00000200L 9029#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__MASK 0x00000400L 9030#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__MASK 0x00000800L 9031#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__MASK 0x00001000L 9032#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_EN__MASK 0x00002000L 9033#define DEV0_PF0_FLR_RST_CTRL__VF_VF_CFG_STICKY_EN__MASK 0x00004000L 9034#define DEV0_PF0_FLR_RST_CTRL__VF_VF_PRV_EN__MASK 0x00008000L 9035#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__MASK 0x00010000L 9036#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9037#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9038#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9039#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9040//DEV0_PF1_FLR_RST_CTRL 9041#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9042#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9043#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9044#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9045#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9046#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9047#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9048#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9049#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9050//DEV0_PF2_FLR_RST_CTRL 9051#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9052#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9053#define DEV0_PF2_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9054#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9055#define DEV0_PF2_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9056#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9057#define DEV0_PF2_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9058#define DEV0_PF2_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9059#define DEV0_PF2_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9060//DEV0_PF3_FLR_RST_CTRL 9061#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9062#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9063#define DEV0_PF3_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9064#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9065#define DEV0_PF3_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9066#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9067#define DEV0_PF3_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9068#define DEV0_PF3_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9069#define DEV0_PF3_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9070//DEV0_PF4_FLR_RST_CTRL 9071#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9072#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9073#define DEV0_PF4_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9074#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9075#define DEV0_PF4_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9076#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9077#define DEV0_PF4_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9078#define DEV0_PF4_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9079#define DEV0_PF4_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9080//DEV0_PF5_FLR_RST_CTRL 9081#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9082#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9083#define DEV0_PF5_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9084#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9085#define DEV0_PF5_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9086#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9087#define DEV0_PF5_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9088#define DEV0_PF5_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9089#define DEV0_PF5_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9090//DEV0_PF6_FLR_RST_CTRL 9091#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9092#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9093#define DEV0_PF6_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9094#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9095#define DEV0_PF6_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9096#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9097#define DEV0_PF6_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9098#define DEV0_PF6_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9099#define DEV0_PF6_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9100//DEV0_PF7_FLR_RST_CTRL 9101#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9102#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9103#define DEV0_PF7_FLR_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9104#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9105#define DEV0_PF7_FLR_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9106#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_MODE__MASK 0x00020000L 9107#define DEV0_PF7_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__MASK 0x001C0000L 9108#define DEV0_PF7_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__MASK 0x01800000L 9109#define DEV0_PF7_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__MASK 0x06000000L 9110//BIF_INST_RESET_INTR_STS 9111#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__MASK 0x00000001L 9112#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__MASK 0x00000002L 9113#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__MASK 0x00000004L 9114#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__MASK 0x00000008L 9115#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__MASK 0x00000010L 9116//BIF_PF_FLR_INTR_STS 9117#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__MASK 0x00000001L 9118#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__MASK 0x00000002L 9119#define BIF_PF_FLR_INTR_STS__DEV0_PF2_FLR_INTR_STS__MASK 0x00000004L 9120#define BIF_PF_FLR_INTR_STS__DEV0_PF3_FLR_INTR_STS__MASK 0x00000008L 9121#define BIF_PF_FLR_INTR_STS__DEV0_PF4_FLR_INTR_STS__MASK 0x00000010L 9122#define BIF_PF_FLR_INTR_STS__DEV0_PF5_FLR_INTR_STS__MASK 0x00000020L 9123#define BIF_PF_FLR_INTR_STS__DEV0_PF6_FLR_INTR_STS__MASK 0x00000040L 9124#define BIF_PF_FLR_INTR_STS__DEV0_PF7_FLR_INTR_STS__MASK 0x00000080L 9125//BIF_D3HOTD0_INTR_STS 9126#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__MASK 0x00000001L 9127#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__MASK 0x00000002L 9128#define BIF_D3HOTD0_INTR_STS__DEV0_PF2_D3HOTD0_INTR_STS__MASK 0x00000004L 9129#define BIF_D3HOTD0_INTR_STS__DEV0_PF3_D3HOTD0_INTR_STS__MASK 0x00000008L 9130#define BIF_D3HOTD0_INTR_STS__DEV0_PF4_D3HOTD0_INTR_STS__MASK 0x00000010L 9131#define BIF_D3HOTD0_INTR_STS__DEV0_PF5_D3HOTD0_INTR_STS__MASK 0x00000020L 9132#define BIF_D3HOTD0_INTR_STS__DEV0_PF6_D3HOTD0_INTR_STS__MASK 0x00000040L 9133#define BIF_D3HOTD0_INTR_STS__DEV0_PF7_D3HOTD0_INTR_STS__MASK 0x00000080L 9134//BIF_POWER_INTR_STS 9135#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__MASK 0x00000001L 9136#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__MASK 0x00010000L 9137//BIF_PF_DSTATE_INTR_STS 9138#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__MASK 0x00000001L 9139#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__MASK 0x00000002L 9140#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__MASK 0x00000004L 9141#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__MASK 0x00000008L 9142#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__MASK 0x00000010L 9143#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__MASK 0x00000020L 9144#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__MASK 0x00000040L 9145#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__MASK 0x00000080L 9146//BIF_PF0_VF_FLR_INTR_STS 9147#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF0_FLR_INTR_STS__MASK 0x00000001L 9148#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF1_FLR_INTR_STS__MASK 0x00000002L 9149#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF2_FLR_INTR_STS__MASK 0x00000004L 9150#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF3_FLR_INTR_STS__MASK 0x00000008L 9151#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF4_FLR_INTR_STS__MASK 0x00000010L 9152#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF5_FLR_INTR_STS__MASK 0x00000020L 9153#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF6_FLR_INTR_STS__MASK 0x00000040L 9154#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF7_FLR_INTR_STS__MASK 0x00000080L 9155#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF8_FLR_INTR_STS__MASK 0x00000100L 9156#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF9_FLR_INTR_STS__MASK 0x00000200L 9157#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF10_FLR_INTR_STS__MASK 0x00000400L 9158#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF11_FLR_INTR_STS__MASK 0x00000800L 9159#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF12_FLR_INTR_STS__MASK 0x00001000L 9160#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF13_FLR_INTR_STS__MASK 0x00002000L 9161#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF14_FLR_INTR_STS__MASK 0x00004000L 9162#define BIF_PF0_VF_FLR_INTR_STS__PF0_VF15_FLR_INTR_STS__MASK 0x00008000L 9163#define BIF_PF0_VF_FLR_INTR_STS__PF0_SOFTPF_FLR_INTR_STS__MASK 0x80000000L 9164//BIF_INST_RESET_INTR_MASK 9165#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__MASK 0x00000001L 9166#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__MASK 0x00000002L 9167#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__MASK 0x00000004L 9168#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__MASK 0x00000008L 9169#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__MASK 0x00000010L 9170//BIF_PF_FLR_INTR_MASK 9171#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__MASK 0x00000001L 9172#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__MASK 0x00000002L 9173#define BIF_PF_FLR_INTR_MASK__DEV0_PF2_FLR_INTR_MASK__MASK 0x00000004L 9174#define BIF_PF_FLR_INTR_MASK__DEV0_PF3_FLR_INTR_MASK__MASK 0x00000008L 9175#define BIF_PF_FLR_INTR_MASK__DEV0_PF4_FLR_INTR_MASK__MASK 0x00000010L 9176#define BIF_PF_FLR_INTR_MASK__DEV0_PF5_FLR_INTR_MASK__MASK 0x00000020L 9177#define BIF_PF_FLR_INTR_MASK__DEV0_PF6_FLR_INTR_MASK__MASK 0x00000040L 9178#define BIF_PF_FLR_INTR_MASK__DEV0_PF7_FLR_INTR_MASK__MASK 0x00000080L 9179//BIF_D3HOTD0_INTR_MASK 9180#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__MASK 0x00000001L 9181#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__MASK 0x00000002L 9182#define BIF_D3HOTD0_INTR_MASK__DEV0_PF2_D3HOTD0_INTR_MASK__MASK 0x00000004L 9183#define BIF_D3HOTD0_INTR_MASK__DEV0_PF3_D3HOTD0_INTR_MASK__MASK 0x00000008L 9184#define BIF_D3HOTD0_INTR_MASK__DEV0_PF4_D3HOTD0_INTR_MASK__MASK 0x00000010L 9185#define BIF_D3HOTD0_INTR_MASK__DEV0_PF5_D3HOTD0_INTR_MASK__MASK 0x00000020L 9186#define BIF_D3HOTD0_INTR_MASK__DEV0_PF6_D3HOTD0_INTR_MASK__MASK 0x00000040L 9187#define BIF_D3HOTD0_INTR_MASK__DEV0_PF7_D3HOTD0_INTR_MASK__MASK 0x00000080L 9188//BIF_POWER_INTR_MASK 9189#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__MASK 0x00000001L 9190#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__MASK 0x00010000L 9191//BIF_PF_DSTATE_INTR_MASK 9192#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__MASK 0x00000001L 9193#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__MASK 0x00000002L 9194#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__MASK 0x00000004L 9195#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__MASK 0x00000008L 9196#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__MASK 0x00000010L 9197#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__MASK 0x00000020L 9198#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__MASK 0x00000040L 9199#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__MASK 0x00000080L 9200//BIF_PF0_VF_FLR_INTR_MASK 9201#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF0_FLR_INTR_MASK__MASK 0x00000001L 9202#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF1_FLR_INTR_MASK__MASK 0x00000002L 9203#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF2_FLR_INTR_MASK__MASK 0x00000004L 9204#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF3_FLR_INTR_MASK__MASK 0x00000008L 9205#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF4_FLR_INTR_MASK__MASK 0x00000010L 9206#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF5_FLR_INTR_MASK__MASK 0x00000020L 9207#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF6_FLR_INTR_MASK__MASK 0x00000040L 9208#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF7_FLR_INTR_MASK__MASK 0x00000080L 9209#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF8_FLR_INTR_MASK__MASK 0x00000100L 9210#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF9_FLR_INTR_MASK__MASK 0x00000200L 9211#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF10_FLR_INTR_MASK__MASK 0x00000400L 9212#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF11_FLR_INTR_MASK__MASK 0x00000800L 9213#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF12_FLR_INTR_MASK__MASK 0x00001000L 9214#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF13_FLR_INTR_MASK__MASK 0x00002000L 9215#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF14_FLR_INTR_MASK__MASK 0x00004000L 9216#define BIF_PF0_VF_FLR_INTR_MASK__PF0_VF15_FLR_INTR_MASK__MASK 0x00008000L 9217#define BIF_PF0_VF_FLR_INTR_MASK__PF0_SOFTPF_FLR_INTR_MASK__MASK 0x80000000L 9218//BIF_PF_FLR_RST 9219#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__MASK 0x00000001L 9220#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__MASK 0x00000002L 9221#define BIF_PF_FLR_RST__DEV0_PF2_FLR_RST__MASK 0x00000004L 9222#define BIF_PF_FLR_RST__DEV0_PF3_FLR_RST__MASK 0x00000008L 9223#define BIF_PF_FLR_RST__DEV0_PF4_FLR_RST__MASK 0x00000010L 9224#define BIF_PF_FLR_RST__DEV0_PF5_FLR_RST__MASK 0x00000020L 9225#define BIF_PF_FLR_RST__DEV0_PF6_FLR_RST__MASK 0x00000040L 9226#define BIF_PF_FLR_RST__DEV0_PF7_FLR_RST__MASK 0x00000080L 9227//BIF_PF0_VF_FLR_RST 9228#define BIF_PF0_VF_FLR_RST__PF0_VF0_FLR_RST__MASK 0x00000001L 9229#define BIF_PF0_VF_FLR_RST__PF0_VF1_FLR_RST__MASK 0x00000002L 9230#define BIF_PF0_VF_FLR_RST__PF0_VF2_FLR_RST__MASK 0x00000004L 9231#define BIF_PF0_VF_FLR_RST__PF0_VF3_FLR_RST__MASK 0x00000008L 9232#define BIF_PF0_VF_FLR_RST__PF0_VF4_FLR_RST__MASK 0x00000010L 9233#define BIF_PF0_VF_FLR_RST__PF0_VF5_FLR_RST__MASK 0x00000020L 9234#define BIF_PF0_VF_FLR_RST__PF0_VF6_FLR_RST__MASK 0x00000040L 9235#define BIF_PF0_VF_FLR_RST__PF0_VF7_FLR_RST__MASK 0x00000080L 9236#define BIF_PF0_VF_FLR_RST__PF0_VF8_FLR_RST__MASK 0x00000100L 9237#define BIF_PF0_VF_FLR_RST__PF0_VF9_FLR_RST__MASK 0x00000200L 9238#define BIF_PF0_VF_FLR_RST__PF0_VF10_FLR_RST__MASK 0x00000400L 9239#define BIF_PF0_VF_FLR_RST__PF0_VF11_FLR_RST__MASK 0x00000800L 9240#define BIF_PF0_VF_FLR_RST__PF0_VF12_FLR_RST__MASK 0x00001000L 9241#define BIF_PF0_VF_FLR_RST__PF0_VF13_FLR_RST__MASK 0x00002000L 9242#define BIF_PF0_VF_FLR_RST__PF0_VF14_FLR_RST__MASK 0x00004000L 9243#define BIF_PF0_VF_FLR_RST__PF0_VF15_FLR_RST__MASK 0x00008000L 9244#define BIF_PF0_VF_FLR_RST__PF0_SOFTPF_FLR_RST__MASK 0x80000000L 9245//BIF_DEV0_PF0_DSTATE_VALUE 9246#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__MASK 0x00000003L 9247#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9248#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__MASK 0x00030000L 9249//BIF_DEV0_PF1_DSTATE_VALUE 9250#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__MASK 0x00000003L 9251#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9252#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__MASK 0x00030000L 9253//BIF_DEV0_PF2_DSTATE_VALUE 9254#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_TGT_VALUE__MASK 0x00000003L 9255#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9256#define BIF_DEV0_PF2_DSTATE_VALUE__DEV0_PF2_DSTATE_ACK_VALUE__MASK 0x00030000L 9257//BIF_DEV0_PF3_DSTATE_VALUE 9258#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_TGT_VALUE__MASK 0x00000003L 9259#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9260#define BIF_DEV0_PF3_DSTATE_VALUE__DEV0_PF3_DSTATE_ACK_VALUE__MASK 0x00030000L 9261//BIF_DEV0_PF4_DSTATE_VALUE 9262#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_TGT_VALUE__MASK 0x00000003L 9263#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9264#define BIF_DEV0_PF4_DSTATE_VALUE__DEV0_PF4_DSTATE_ACK_VALUE__MASK 0x00030000L 9265//BIF_DEV0_PF5_DSTATE_VALUE 9266#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_TGT_VALUE__MASK 0x00000003L 9267#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9268#define BIF_DEV0_PF5_DSTATE_VALUE__DEV0_PF5_DSTATE_ACK_VALUE__MASK 0x00030000L 9269//BIF_DEV0_PF6_DSTATE_VALUE 9270#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_TGT_VALUE__MASK 0x00000003L 9271#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9272#define BIF_DEV0_PF6_DSTATE_VALUE__DEV0_PF6_DSTATE_ACK_VALUE__MASK 0x00030000L 9273//BIF_DEV0_PF7_DSTATE_VALUE 9274#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_TGT_VALUE__MASK 0x00000003L 9275#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_NEED_D3TOD0_RESET__MASK 0x00000004L 9276#define BIF_DEV0_PF7_DSTATE_VALUE__DEV0_PF7_DSTATE_ACK_VALUE__MASK 0x00030000L 9277//DEV0_PF0_D3HOTD0_RST_CTRL 9278#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9279#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9280#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9281#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9282#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9283//DEV0_PF1_D3HOTD0_RST_CTRL 9284#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9285#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9286#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9287#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9288#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9289//DEV0_PF2_D3HOTD0_RST_CTRL 9290#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9291#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9292#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9293#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9294#define DEV0_PF2_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9295//DEV0_PF3_D3HOTD0_RST_CTRL 9296#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9297#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9298#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9299#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9300#define DEV0_PF3_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9301//DEV0_PF4_D3HOTD0_RST_CTRL 9302#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9303#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9304#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9305#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9306#define DEV0_PF4_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9307//DEV0_PF5_D3HOTD0_RST_CTRL 9308#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9309#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9310#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9311#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9312#define DEV0_PF5_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9313//DEV0_PF6_D3HOTD0_RST_CTRL 9314#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9315#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9316#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9317#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9318#define DEV0_PF6_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9319//DEV0_PF7_D3HOTD0_RST_CTRL 9320#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_EN__MASK 0x00000001L 9321#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__MASK 0x00000002L 9322#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__MASK 0x00000004L 9323#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_EN__MASK 0x00000008L 9324#define DEV0_PF7_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__MASK 0x00000010L 9325//BIF_PORT0_DSTATE_VALUE 9326#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__MASK 0x00000003L 9327#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__MASK 0x00030000L 9328 9329 9330// addressBlock: bif_misc_bif_misc_regblk 9331//MISC_SCRATCH 9332#define MISC_SCRATCH__MISC_SCRATCH0__MASK 0xFFFFFFFFL 9333//INTR_LINE_POLARITY 9334#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__MASK 0x000000FFL 9335//INTR_LINE_ENABLE 9336#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__MASK 0x000000FFL 9337//OUTSTANDING_VC_ALLOC 9338#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__MASK 0x00000003L 9339#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__MASK 0x0000000CL 9340#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__MASK 0x00000030L 9341#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__MASK 0x000000C0L 9342#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__MASK 0x00000300L 9343#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__MASK 0x00000C00L 9344#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__MASK 0x00003000L 9345#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__MASK 0x0000C000L 9346#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__MASK 0x000F0000L 9347#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__MASK 0x03000000L 9348#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__MASK 0x0C000000L 9349#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__MASK 0xF0000000L 9350//BIFC_MISC_CTRL0 9351#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__MASK 0x00000001L 9352#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__MASK 0x00000006L 9353#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__MASK 0x00000100L 9354#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK__MASK 0x00000200L 9355#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__MASK 0x00000400L 9356#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__MASK 0x00010000L 9357#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__MASK 0x00020000L 9358#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__MASK 0x01000000L 9359#define BIFC_MISC_CTRL0__VC7_DMA_IOCFG_DIS__MASK 0x02000000L 9360#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__MASK 0x04000000L 9361#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__MASK 0x08000000L 9362#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__MASK 0x10000000L 9363#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__MASK 0x80000000L 9364//BIFC_MISC_CTRL1 9365#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__MASK 0x00000001L 9366#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__MASK 0x00000002L 9367#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__MASK 0x00000004L 9368#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__MASK 0x00000008L 9369#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__MASK 0x00000010L 9370#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__MASK 0x00000020L 9371#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__MASK 0x00000040L 9372#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__MASK 0x00000080L 9373#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__MASK 0x00000300L 9374#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__MASK 0x00000C00L 9375#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__MASK 0x00001000L 9376#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__MASK 0x00002000L 9377#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__MASK 0x00004000L 9378#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__MASK 0x00008000L 9379#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__MASK 0x00010000L 9380#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__MASK 0x00020000L 9381#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__MASK 0x00040000L 9382#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__MASK 0x00080000L 9383//BIFC_BME_ERR_LOG 9384#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F0__MASK 0x00000001L 9385#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F1__MASK 0x00000002L 9386#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F2__MASK 0x00000004L 9387#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F3__MASK 0x00000008L 9388#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F4__MASK 0x00000010L 9389#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F5__MASK 0x00000020L 9390#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F6__MASK 0x00000040L 9391#define BIFC_BME_ERR_LOG__DMA_ON_BME_LOW_DEV0_F7__MASK 0x00000080L 9392#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F0__MASK 0x00010000L 9393#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F1__MASK 0x00020000L 9394#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F2__MASK 0x00040000L 9395#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F3__MASK 0x00080000L 9396#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F4__MASK 0x00100000L 9397#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F5__MASK 0x00200000L 9398#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F6__MASK 0x00400000L 9399#define BIFC_BME_ERR_LOG__CLEAR_DMA_ON_BME_LOW_DEV0_F7__MASK 0x00800000L 9400//BIFC_RCCBIH_BME_ERR_LOG 9401#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00000001L 9402#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00000002L 9403#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00000004L 9404#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00000008L 9405#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00000010L 9406#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00000020L 9407#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00000040L 9408#define BIFC_RCCBIH_BME_ERR_LOG__RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00000080L 9409#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__MASK 0x00010000L 9410#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__MASK 0x00020000L 9411#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F2__MASK 0x00040000L 9412#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F3__MASK 0x00080000L 9413#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F4__MASK 0x00100000L 9414#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F5__MASK 0x00200000L 9415#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F6__MASK 0x00400000L 9416#define BIFC_RCCBIH_BME_ERR_LOG__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F7__MASK 0x00800000L 9417//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1 9418#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__MASK 0x00000003L 9419#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__MASK 0x0000000CL 9420#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__MASK 0x000000C0L 9421#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__MASK 0x00000300L 9422#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__MASK 0x00000C00L 9423#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__MASK 0x00003000L 9424#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__MASK 0x00030000L 9425#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__MASK 0x000C0000L 9426#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__MASK 0x00C00000L 9427#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__MASK 0x03000000L 9428#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__MASK 0x0C000000L 9429#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__MASK 0x30000000L 9430//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3 9431#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__MASK 0x00000003L 9432#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__MASK 0x0000000CL 9433#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__MASK 0x000000C0L 9434#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__MASK 0x00000300L 9435#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__MASK 0x00000C00L 9436#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__MASK 0x00003000L 9437#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__MASK 0x00030000L 9438#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__MASK 0x000C0000L 9439#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__MASK 0x00C00000L 9440#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__MASK 0x03000000L 9441#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__MASK 0x0C000000L 9442#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__MASK 0x30000000L 9443//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5 9444#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__MASK 0x00000003L 9445#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__MASK 0x0000000CL 9446#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__MASK 0x000000C0L 9447#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__MASK 0x00000300L 9448#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__MASK 0x00000C00L 9449#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__MASK 0x00003000L 9450#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__MASK 0x00030000L 9451#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__MASK 0x000C0000L 9452#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__MASK 0x00C00000L 9453#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__MASK 0x03000000L 9454#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__MASK 0x0C000000L 9455#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__MASK 0x30000000L 9456//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7 9457#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__MASK 0x00000003L 9458#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__MASK 0x0000000CL 9459#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__MASK 0x000000C0L 9460#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__MASK 0x00000300L 9461#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__MASK 0x00000C00L 9462#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__MASK 0x00003000L 9463#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__MASK 0x00030000L 9464#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__MASK 0x000C0000L 9465#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__MASK 0x00C00000L 9466#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__MASK 0x03000000L 9467#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__MASK 0x0C000000L 9468#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__MASK 0x30000000L 9469//NBIF_VWIRE_CTRL 9470#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__MASK 0x000000F0L 9471#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__MASK 0x00000100L 9472#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__MASK 0x00F00000L 9473#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__MASK 0x0C000000L 9474//NBIF_SMN_VWR_VCHG_DIS_CTRL 9475#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET0_DIS__MASK 0x00000001L 9476#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET1_DIS__MASK 0x00000002L 9477#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET2_DIS__MASK 0x00000004L 9478#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET3_DIS__MASK 0x00000008L 9479#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET4_DIS__MASK 0x00000010L 9480#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET5_DIS__MASK 0x00000020L 9481#define NBIF_SMN_VWR_VCHG_DIS_CTRL__SMN_VWR_VCHG_SET6_DIS__MASK 0x00000040L 9482//NBIF_SMN_VWR_VCHG_RST_CTRL0 9483#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET0_RST_DEF_REV__MASK 0x00000001L 9484#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET1_RST_DEF_REV__MASK 0x00000002L 9485#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET2_RST_DEF_REV__MASK 0x00000004L 9486#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET3_RST_DEF_REV__MASK 0x00000008L 9487#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET4_RST_DEF_REV__MASK 0x00000010L 9488#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET5_RST_DEF_REV__MASK 0x00000020L 9489#define NBIF_SMN_VWR_VCHG_RST_CTRL0__SMN_VWR_VCHG_SET6_RST_DEF_REV__MASK 0x00000040L 9490//NBIF_SMN_VWR_VCHG_TRIG 9491#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET0_TRIG__MASK 0x00000001L 9492#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET1_TRIG__MASK 0x00000002L 9493#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET2_TRIG__MASK 0x00000004L 9494#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET3_TRIG__MASK 0x00000008L 9495#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET4_TRIG__MASK 0x00000010L 9496#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET5_TRIG__MASK 0x00000020L 9497#define NBIF_SMN_VWR_VCHG_TRIG__SMN_VWR_VCHG_SET6_TRIG__MASK 0x00000040L 9498//NBIF_SMN_VWR_WTRIG_CNTL 9499#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET0_DIS__MASK 0x00000001L 9500#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET1_DIS__MASK 0x00000002L 9501#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET2_DIS__MASK 0x00000004L 9502#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET3_DIS__MASK 0x00000008L 9503#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET4_DIS__MASK 0x00000010L 9504#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET5_DIS__MASK 0x00000020L 9505#define NBIF_SMN_VWR_WTRIG_CNTL__SMN_VWR_WTRIG_SET6_DIS__MASK 0x00000040L 9506//NBIF_SMN_VWR_VCHG_DIS_CTRL_1 9507#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET0_DIFFDET_DEF_REV__MASK 0x00000001L 9508#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET1_DIFFDET_DEF_REV__MASK 0x00000002L 9509#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET2_DIFFDET_DEF_REV__MASK 0x00000004L 9510#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET3_DIFFDET_DEF_REV__MASK 0x00000008L 9511#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET4_DIFFDET_DEF_REV__MASK 0x00000010L 9512#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET5_DIFFDET_DEF_REV__MASK 0x00000020L 9513#define NBIF_SMN_VWR_VCHG_DIS_CTRL_1__SMN_VWR_VCHG_SET6_DIFFDET_DEF_REV__MASK 0x00000040L 9514//NBIF_MGCG_CTRL 9515#define NBIF_MGCG_CTRL__NBIF_MGCG_EN__MASK 0x00000001L 9516#define NBIF_MGCG_CTRL__NBIF_MGCG_MODE__MASK 0x00000002L 9517#define NBIF_MGCG_CTRL__NBIF_MGCG_HYSTERESIS__MASK 0x000003FCL 9518//NBIF_DS_CTRL_LCLK 9519#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__MASK 0x00000001L 9520#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__MASK 0xFFFF0000L 9521//SMN_MST_CNTL0 9522#define SMN_MST_CNTL0__SMN_ARB_MODE__MASK 0x00000003L 9523#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__MASK 0x00000100L 9524#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__MASK 0x00000200L 9525#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__MASK 0x00000400L 9526#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__MASK 0x00000800L 9527#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__MASK 0x00010000L 9528#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__MASK 0x00100000L 9529#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__MASK 0x01000000L 9530#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__MASK 0x10000000L 9531//SMN_MST_EP_CNTL1 9532#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__MASK 0x00000001L 9533#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__MASK 0x00000002L 9534#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__MASK 0x00000004L 9535#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__MASK 0x00000008L 9536#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__MASK 0x00000010L 9537#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__MASK 0x00000020L 9538#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__MASK 0x00000040L 9539#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__MASK 0x00000080L 9540//SMN_MST_EP_CNTL2 9541#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__MASK 0x00000001L 9542#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__MASK 0x00000002L 9543#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__MASK 0x00000004L 9544#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__MASK 0x00000008L 9545#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__MASK 0x00000010L 9546#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__MASK 0x00000020L 9547#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__MASK 0x00000040L 9548#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__MASK 0x00000080L 9549//NBIF_SDP_VWR_VCHG_DIS_CTRL 9550#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__MASK 0x00000001L 9551#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__MASK 0x00000002L 9552#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__MASK 0x00000004L 9553#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__MASK 0x00000008L 9554#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__MASK 0x00000010L 9555#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__MASK 0x00000020L 9556#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__MASK 0x00000040L 9557#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__MASK 0x00000080L 9558#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__MASK 0x01000000L 9559//NBIF_SDP_VWR_VCHG_RST_CTRL0 9560#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__MASK 0x00000001L 9561#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__MASK 0x00000002L 9562#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__MASK 0x00000004L 9563#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__MASK 0x00000008L 9564#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__MASK 0x00000010L 9565#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__MASK 0x00000020L 9566#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__MASK 0x00000040L 9567#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__MASK 0x00000080L 9568#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__MASK 0x01000000L 9569//NBIF_SDP_VWR_VCHG_RST_CTRL1 9570#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__MASK 0x00000001L 9571#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__MASK 0x00000002L 9572#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__MASK 0x00000004L 9573#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__MASK 0x00000008L 9574#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__MASK 0x00000010L 9575#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__MASK 0x00000020L 9576#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__MASK 0x00000040L 9577#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__MASK 0x00000080L 9578#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__MASK 0x01000000L 9579//NBIF_SDP_VWR_VCHG_TRIG 9580#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__MASK 0x00000001L 9581#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__MASK 0x00000002L 9582#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__MASK 0x00000004L 9583#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__MASK 0x00000008L 9584#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__MASK 0x00000010L 9585#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__MASK 0x00000020L 9586#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__MASK 0x00000040L 9587#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__MASK 0x00000080L 9588#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__MASK 0x01000000L 9589//BME_DUMMY_CNTL_0 9590#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__MASK 0x00000003L 9591#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__MASK 0x0000000CL 9592#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__MASK 0x00000030L 9593#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__MASK 0x000000C0L 9594#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__MASK 0x00000300L 9595#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__MASK 0x00000C00L 9596#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__MASK 0x00003000L 9597#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__MASK 0x0000C000L 9598//BIFC_THT_CNTL 9599#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__MASK 0x0000000FL 9600#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__MASK 0x000000F0L 9601#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__MASK 0x00000F00L 9602//BIFC_HSTARB_CNTL 9603#define BIFC_HSTARB_CNTL__SLVARB_MODE__MASK 0x00000003L 9604//BIFC_GSI_CNTL 9605#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__MASK 0x00000003L 9606#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__MASK 0x0000001CL 9607#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__MASK 0x00000020L 9608#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__MASK 0x00000040L 9609#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__MASK 0x00000080L 9610#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__MASK 0x00000100L 9611#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__MASK 0x00000200L 9612#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__MASK 0x00000C00L 9613#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__MASK 0x00003000L 9614//BIFC_PCIEFUNC_CNTL 9615#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__MASK 0x0000FFFFL 9616#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__MASK 0x00010000L 9617//BIFC_SDP_CNTL_0 9618#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__MASK 0x0000003FL 9619#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__MASK 0x00000FC0L 9620#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__MASK 0x0003F000L 9621#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__MASK 0x00FC0000L 9622//BIFC_PERF_CNTL_0 9623#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__MASK 0x00000001L 9624#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__MASK 0x00000002L 9625#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__MASK 0x00000100L 9626#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__MASK 0x00000200L 9627#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__MASK 0x001F0000L 9628#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__MASK 0x1F000000L 9629//BIFC_PERF_CNTL_1 9630#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__MASK 0x00000001L 9631#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__MASK 0x00000002L 9632#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__MASK 0x00000100L 9633#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__MASK 0x00000200L 9634#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__MASK 0x003F0000L 9635#define BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__MASK 0x7F000000L 9636//BIFC_PERF_CNT_MMIO_RD 9637#define BIFC_PERF_CNT_MMIO_RD__PERF_CNT_MMIO_RD_VALUE__MASK 0xFFFFFFFFL 9638//BIFC_PERF_CNT_MMIO_WR 9639#define BIFC_PERF_CNT_MMIO_WR__PERF_CNT_MMIO_WR_VALUE__MASK 0xFFFFFFFFL 9640//BIFC_PERF_CNT_DMA_RD 9641#define BIFC_PERF_CNT_DMA_RD__PERF_CNT_DMA_RD_VALUE__MASK 0xFFFFFFFFL 9642//BIFC_PERF_CNT_DMA_WR 9643#define BIFC_PERF_CNT_DMA_WR__PERF_CNT_DMA_WR_VALUE__MASK 0xFFFFFFFFL 9644//NBIF_REGIF_ERRSET_CTRL 9645#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__MASK 0x00000001L 9646//SMN_MST_EP_CNTL3 9647#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__MASK 0x00000001L 9648#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__MASK 0x00000002L 9649#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__MASK 0x00000004L 9650#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__MASK 0x00000008L 9651#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__MASK 0x00000010L 9652#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__MASK 0x00000020L 9653#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__MASK 0x00000040L 9654#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__MASK 0x00000080L 9655//SMN_MST_EP_CNTL4 9656#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__MASK 0x00000001L 9657#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__MASK 0x00000002L 9658#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__MASK 0x00000004L 9659#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__MASK 0x00000008L 9660#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__MASK 0x00000010L 9661#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__MASK 0x00000020L 9662#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__MASK 0x00000040L 9663#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__MASK 0x00000080L 9664//BIF_SELFRING_BUFFER_VID 9665#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__MASK 0x000000FFL 9666#define BIF_SELFRING_BUFFER_VID__IOHUB_RAS_INTR_CID__MASK 0x0000FF00L 9667//BIF_SELFRING_VECTOR_CNTL 9668#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__MASK 0x00000001L 9669 9670 9671// addressBlock: bif_ras_bif_ras_regblk 9672//BIF_RAS_LEAF0_CTRL 9673#define BIF_RAS_LEAF0_CTRL__POISON_DET_EN__MASK 0x00000001L 9674#define BIF_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9675#define BIF_RAS_LEAF0_CTRL__POISON_STALL_EN__MASK 0x00000004L 9676#define BIF_RAS_LEAF0_CTRL__PARITY_DET_EN__MASK 0x00000010L 9677#define BIF_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9678#define BIF_RAS_LEAF0_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9679#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9680#define BIF_RAS_LEAF0_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9681#define BIF_RAS_LEAF0_CTRL__POISON_ERR_DET__MASK 0x00040000L 9682#define BIF_RAS_LEAF0_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9683#define BIF_RAS_LEAF0_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9684#define BIF_RAS_LEAF0_CTRL__EGRESS_STALLED__MASK 0x00200000L 9685//BIF_RAS_LEAF1_CTRL 9686#define BIF_RAS_LEAF1_CTRL__POISON_DET_EN__MASK 0x00000001L 9687#define BIF_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9688#define BIF_RAS_LEAF1_CTRL__POISON_STALL_EN__MASK 0x00000004L 9689#define BIF_RAS_LEAF1_CTRL__PARITY_DET_EN__MASK 0x00000010L 9690#define BIF_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9691#define BIF_RAS_LEAF1_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9692#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9693#define BIF_RAS_LEAF1_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9694#define BIF_RAS_LEAF1_CTRL__POISON_ERR_DET__MASK 0x00040000L 9695#define BIF_RAS_LEAF1_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9696#define BIF_RAS_LEAF1_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9697#define BIF_RAS_LEAF1_CTRL__EGRESS_STALLED__MASK 0x00200000L 9698//BIF_RAS_LEAF2_CTRL 9699#define BIF_RAS_LEAF2_CTRL__POISON_DET_EN__MASK 0x00000001L 9700#define BIF_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__MASK 0x00000002L 9701#define BIF_RAS_LEAF2_CTRL__POISON_STALL_EN__MASK 0x00000004L 9702#define BIF_RAS_LEAF2_CTRL__PARITY_DET_EN__MASK 0x00000010L 9703#define BIF_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__MASK 0x00000020L 9704#define BIF_RAS_LEAF2_CTRL__PARITY_STALL_EN__MASK 0x00000040L 9705#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_RECV__MASK 0x00010000L 9706#define BIF_RAS_LEAF2_CTRL__LINK_DIS_RECV__MASK 0x00020000L 9707#define BIF_RAS_LEAF2_CTRL__POISON_ERR_DET__MASK 0x00040000L 9708#define BIF_RAS_LEAF2_CTRL__PARITY_ERR_DET__MASK 0x00080000L 9709#define BIF_RAS_LEAF2_CTRL__ERR_EVENT_SENT__MASK 0x00100000L 9710#define BIF_RAS_LEAF2_CTRL__EGRESS_STALLED__MASK 0x00200000L 9711//BIF_RAS_MISC_CTRL 9712#define BIF_RAS_MISC_CTRL__LINKDIS_TRIG_ERREVENT_EN__MASK 0x00000001L 9713//BIF_IOHUB_RAS_IH_CNTL 9714#define BIF_IOHUB_RAS_IH_CNTL__RAS_IH_INTR_EN__MASK 0x00000001L 9715//BIF_RAS_VWR_FROM_IOHUB 9716#define BIF_RAS_VWR_FROM_IOHUB__RAS_IH_INTR_TRIG__MASK 0x00000001L 9717 9718 9719// addressBlock: rcc_pfc_amdgfx_RCCPFCDEC 9720//RCC_PFC_LTR_CNTL 9721#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL 9722#define RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L 9723#define RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L 9724#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L 9725#define RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L 9726#define RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L 9727//RCC_PFC_PME_RESTORE 9728#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L 9729#define RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L 9730//RCC_PFC_STICKY_RESTORE_0 9731#define RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L 9732#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L 9733#define RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L 9734#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L 9735#define RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L 9736#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L 9737#define RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L 9738#define RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L 9739//RCC_PFC_STICKY_RESTORE_1 9740#define RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL 9741//RCC_PFC_STICKY_RESTORE_2 9742#define RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL 9743//RCC_PFC_STICKY_RESTORE_3 9744#define RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL 9745//RCC_PFC_STICKY_RESTORE_4 9746#define RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL 9747//RCC_PFC_STICKY_RESTORE_5 9748#define RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL 9749//RCC_PFC_AUXPWR_CNTL 9750#define RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L 9751#define RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L 9752 9753 9754// addressBlock: rcc_pfc_amdgfxaz_RCCPFCDEC 9755//RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL 9756#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__MASK 0x000003FFL 9757#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__MASK 0x00001C00L 9758#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__MASK 0x00008000L 9759#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__MASK 0x03FF0000L 9760#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__MASK 0x1C000000L 9761#define RCCPFCAMDGFXAZ_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__MASK 0x80000000L 9762//RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE 9763#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__MASK 0x00000001L 9764#define RCCPFCAMDGFXAZ_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__MASK 0x00000100L 9765//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0 9766#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__MASK 0x00000001L 9767#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__MASK 0x00000002L 9768#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__MASK 0x00000004L 9769#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__MASK 0x00000008L 9770#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__MASK 0x00000010L 9771#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__MASK 0x00000020L 9772#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__MASK 0x00000040L 9773#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__MASK 0x00000080L 9774//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1 9775#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__MASK 0xFFFFFFFFL 9776//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2 9777#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__MASK 0xFFFFFFFFL 9778//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3 9779#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__MASK 0xFFFFFFFFL 9780//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4 9781#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__MASK 0xFFFFFFFFL 9782//RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5 9783#define RCCPFCAMDGFXAZ_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__MASK 0xFFFFFFFFL 9784//RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL 9785#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__MASK 0x00000007L 9786#define RCCPFCAMDGFXAZ_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__MASK 0x00000008L 9787 9788 9789// addressBlock: pciemsix_amdgfx_MSIXTDEC 9790//PCIEMSIX_VECT0_ADDR_LO 9791#define PCIEMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9792//PCIEMSIX_VECT0_ADDR_HI 9793#define PCIEMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9794//PCIEMSIX_VECT0_MSG_DATA 9795#define PCIEMSIX_VECT0_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9796//PCIEMSIX_VECT0_CONTROL 9797#define PCIEMSIX_VECT0_CONTROL__MASK_BIT__MASK 0x00000001L 9798//PCIEMSIX_VECT1_ADDR_LO 9799#define PCIEMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9800//PCIEMSIX_VECT1_ADDR_HI 9801#define PCIEMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9802//PCIEMSIX_VECT1_MSG_DATA 9803#define PCIEMSIX_VECT1_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9804//PCIEMSIX_VECT1_CONTROL 9805#define PCIEMSIX_VECT1_CONTROL__MASK_BIT__MASK 0x00000001L 9806//PCIEMSIX_VECT2_ADDR_LO 9807#define PCIEMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9808//PCIEMSIX_VECT2_ADDR_HI 9809#define PCIEMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9810//PCIEMSIX_VECT2_MSG_DATA 9811#define PCIEMSIX_VECT2_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9812//PCIEMSIX_VECT2_CONTROL 9813#define PCIEMSIX_VECT2_CONTROL__MASK_BIT__MASK 0x00000001L 9814//PCIEMSIX_VECT3_ADDR_LO 9815#define PCIEMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9816//PCIEMSIX_VECT3_ADDR_HI 9817#define PCIEMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9818//PCIEMSIX_VECT3_MSG_DATA 9819#define PCIEMSIX_VECT3_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9820//PCIEMSIX_VECT3_CONTROL 9821#define PCIEMSIX_VECT3_CONTROL__MASK_BIT__MASK 0x00000001L 9822//PCIEMSIX_VECT4_ADDR_LO 9823#define PCIEMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9824//PCIEMSIX_VECT4_ADDR_HI 9825#define PCIEMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9826//PCIEMSIX_VECT4_MSG_DATA 9827#define PCIEMSIX_VECT4_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9828//PCIEMSIX_VECT4_CONTROL 9829#define PCIEMSIX_VECT4_CONTROL__MASK_BIT__MASK 0x00000001L 9830//PCIEMSIX_VECT5_ADDR_LO 9831#define PCIEMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9832//PCIEMSIX_VECT5_ADDR_HI 9833#define PCIEMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9834//PCIEMSIX_VECT5_MSG_DATA 9835#define PCIEMSIX_VECT5_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9836//PCIEMSIX_VECT5_CONTROL 9837#define PCIEMSIX_VECT5_CONTROL__MASK_BIT__MASK 0x00000001L 9838//PCIEMSIX_VECT6_ADDR_LO 9839#define PCIEMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9840//PCIEMSIX_VECT6_ADDR_HI 9841#define PCIEMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9842//PCIEMSIX_VECT6_MSG_DATA 9843#define PCIEMSIX_VECT6_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9844//PCIEMSIX_VECT6_CONTROL 9845#define PCIEMSIX_VECT6_CONTROL__MASK_BIT__MASK 0x00000001L 9846//PCIEMSIX_VECT7_ADDR_LO 9847#define PCIEMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9848//PCIEMSIX_VECT7_ADDR_HI 9849#define PCIEMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9850//PCIEMSIX_VECT7_MSG_DATA 9851#define PCIEMSIX_VECT7_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9852//PCIEMSIX_VECT7_CONTROL 9853#define PCIEMSIX_VECT7_CONTROL__MASK_BIT__MASK 0x00000001L 9854//PCIEMSIX_VECT8_ADDR_LO 9855#define PCIEMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9856//PCIEMSIX_VECT8_ADDR_HI 9857#define PCIEMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9858//PCIEMSIX_VECT8_MSG_DATA 9859#define PCIEMSIX_VECT8_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9860//PCIEMSIX_VECT8_CONTROL 9861#define PCIEMSIX_VECT8_CONTROL__MASK_BIT__MASK 0x00000001L 9862//PCIEMSIX_VECT9_ADDR_LO 9863#define PCIEMSIX_VECT9_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9864//PCIEMSIX_VECT9_ADDR_HI 9865#define PCIEMSIX_VECT9_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9866//PCIEMSIX_VECT9_MSG_DATA 9867#define PCIEMSIX_VECT9_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9868//PCIEMSIX_VECT9_CONTROL 9869#define PCIEMSIX_VECT9_CONTROL__MASK_BIT__MASK 0x00000001L 9870//PCIEMSIX_VECT10_ADDR_LO 9871#define PCIEMSIX_VECT10_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9872//PCIEMSIX_VECT10_ADDR_HI 9873#define PCIEMSIX_VECT10_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9874//PCIEMSIX_VECT10_MSG_DATA 9875#define PCIEMSIX_VECT10_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9876//PCIEMSIX_VECT10_CONTROL 9877#define PCIEMSIX_VECT10_CONTROL__MASK_BIT__MASK 0x00000001L 9878//PCIEMSIX_VECT11_ADDR_LO 9879#define PCIEMSIX_VECT11_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9880//PCIEMSIX_VECT11_ADDR_HI 9881#define PCIEMSIX_VECT11_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9882//PCIEMSIX_VECT11_MSG_DATA 9883#define PCIEMSIX_VECT11_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9884//PCIEMSIX_VECT11_CONTROL 9885#define PCIEMSIX_VECT11_CONTROL__MASK_BIT__MASK 0x00000001L 9886//PCIEMSIX_VECT12_ADDR_LO 9887#define PCIEMSIX_VECT12_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9888//PCIEMSIX_VECT12_ADDR_HI 9889#define PCIEMSIX_VECT12_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9890//PCIEMSIX_VECT12_MSG_DATA 9891#define PCIEMSIX_VECT12_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9892//PCIEMSIX_VECT12_CONTROL 9893#define PCIEMSIX_VECT12_CONTROL__MASK_BIT__MASK 0x00000001L 9894//PCIEMSIX_VECT13_ADDR_LO 9895#define PCIEMSIX_VECT13_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9896//PCIEMSIX_VECT13_ADDR_HI 9897#define PCIEMSIX_VECT13_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9898//PCIEMSIX_VECT13_MSG_DATA 9899#define PCIEMSIX_VECT13_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9900//PCIEMSIX_VECT13_CONTROL 9901#define PCIEMSIX_VECT13_CONTROL__MASK_BIT__MASK 0x00000001L 9902//PCIEMSIX_VECT14_ADDR_LO 9903#define PCIEMSIX_VECT14_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9904//PCIEMSIX_VECT14_ADDR_HI 9905#define PCIEMSIX_VECT14_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9906//PCIEMSIX_VECT14_MSG_DATA 9907#define PCIEMSIX_VECT14_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9908//PCIEMSIX_VECT14_CONTROL 9909#define PCIEMSIX_VECT14_CONTROL__MASK_BIT__MASK 0x00000001L 9910//PCIEMSIX_VECT15_ADDR_LO 9911#define PCIEMSIX_VECT15_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9912//PCIEMSIX_VECT15_ADDR_HI 9913#define PCIEMSIX_VECT15_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9914//PCIEMSIX_VECT15_MSG_DATA 9915#define PCIEMSIX_VECT15_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9916//PCIEMSIX_VECT15_CONTROL 9917#define PCIEMSIX_VECT15_CONTROL__MASK_BIT__MASK 0x00000001L 9918//PCIEMSIX_VECT16_ADDR_LO 9919#define PCIEMSIX_VECT16_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9920//PCIEMSIX_VECT16_ADDR_HI 9921#define PCIEMSIX_VECT16_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9922//PCIEMSIX_VECT16_MSG_DATA 9923#define PCIEMSIX_VECT16_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9924//PCIEMSIX_VECT16_CONTROL 9925#define PCIEMSIX_VECT16_CONTROL__MASK_BIT__MASK 0x00000001L 9926//PCIEMSIX_VECT17_ADDR_LO 9927#define PCIEMSIX_VECT17_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9928//PCIEMSIX_VECT17_ADDR_HI 9929#define PCIEMSIX_VECT17_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9930//PCIEMSIX_VECT17_MSG_DATA 9931#define PCIEMSIX_VECT17_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9932//PCIEMSIX_VECT17_CONTROL 9933#define PCIEMSIX_VECT17_CONTROL__MASK_BIT__MASK 0x00000001L 9934//PCIEMSIX_VECT18_ADDR_LO 9935#define PCIEMSIX_VECT18_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9936//PCIEMSIX_VECT18_ADDR_HI 9937#define PCIEMSIX_VECT18_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9938//PCIEMSIX_VECT18_MSG_DATA 9939#define PCIEMSIX_VECT18_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9940//PCIEMSIX_VECT18_CONTROL 9941#define PCIEMSIX_VECT18_CONTROL__MASK_BIT__MASK 0x00000001L 9942//PCIEMSIX_VECT19_ADDR_LO 9943#define PCIEMSIX_VECT19_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9944//PCIEMSIX_VECT19_ADDR_HI 9945#define PCIEMSIX_VECT19_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9946//PCIEMSIX_VECT19_MSG_DATA 9947#define PCIEMSIX_VECT19_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9948//PCIEMSIX_VECT19_CONTROL 9949#define PCIEMSIX_VECT19_CONTROL__MASK_BIT__MASK 0x00000001L 9950//PCIEMSIX_VECT20_ADDR_LO 9951#define PCIEMSIX_VECT20_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9952//PCIEMSIX_VECT20_ADDR_HI 9953#define PCIEMSIX_VECT20_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9954//PCIEMSIX_VECT20_MSG_DATA 9955#define PCIEMSIX_VECT20_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9956//PCIEMSIX_VECT20_CONTROL 9957#define PCIEMSIX_VECT20_CONTROL__MASK_BIT__MASK 0x00000001L 9958//PCIEMSIX_VECT21_ADDR_LO 9959#define PCIEMSIX_VECT21_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9960//PCIEMSIX_VECT21_ADDR_HI 9961#define PCIEMSIX_VECT21_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9962//PCIEMSIX_VECT21_MSG_DATA 9963#define PCIEMSIX_VECT21_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9964//PCIEMSIX_VECT21_CONTROL 9965#define PCIEMSIX_VECT21_CONTROL__MASK_BIT__MASK 0x00000001L 9966//PCIEMSIX_VECT22_ADDR_LO 9967#define PCIEMSIX_VECT22_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9968//PCIEMSIX_VECT22_ADDR_HI 9969#define PCIEMSIX_VECT22_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9970//PCIEMSIX_VECT22_MSG_DATA 9971#define PCIEMSIX_VECT22_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9972//PCIEMSIX_VECT22_CONTROL 9973#define PCIEMSIX_VECT22_CONTROL__MASK_BIT__MASK 0x00000001L 9974//PCIEMSIX_VECT23_ADDR_LO 9975#define PCIEMSIX_VECT23_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9976//PCIEMSIX_VECT23_ADDR_HI 9977#define PCIEMSIX_VECT23_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9978//PCIEMSIX_VECT23_MSG_DATA 9979#define PCIEMSIX_VECT23_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9980//PCIEMSIX_VECT23_CONTROL 9981#define PCIEMSIX_VECT23_CONTROL__MASK_BIT__MASK 0x00000001L 9982//PCIEMSIX_VECT24_ADDR_LO 9983#define PCIEMSIX_VECT24_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9984//PCIEMSIX_VECT24_ADDR_HI 9985#define PCIEMSIX_VECT24_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9986//PCIEMSIX_VECT24_MSG_DATA 9987#define PCIEMSIX_VECT24_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9988//PCIEMSIX_VECT24_CONTROL 9989#define PCIEMSIX_VECT24_CONTROL__MASK_BIT__MASK 0x00000001L 9990//PCIEMSIX_VECT25_ADDR_LO 9991#define PCIEMSIX_VECT25_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 9992//PCIEMSIX_VECT25_ADDR_HI 9993#define PCIEMSIX_VECT25_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 9994//PCIEMSIX_VECT25_MSG_DATA 9995#define PCIEMSIX_VECT25_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 9996//PCIEMSIX_VECT25_CONTROL 9997#define PCIEMSIX_VECT25_CONTROL__MASK_BIT__MASK 0x00000001L 9998//PCIEMSIX_VECT26_ADDR_LO 9999#define PCIEMSIX_VECT26_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10000//PCIEMSIX_VECT26_ADDR_HI 10001#define PCIEMSIX_VECT26_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10002//PCIEMSIX_VECT26_MSG_DATA 10003#define PCIEMSIX_VECT26_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10004//PCIEMSIX_VECT26_CONTROL 10005#define PCIEMSIX_VECT26_CONTROL__MASK_BIT__MASK 0x00000001L 10006//PCIEMSIX_VECT27_ADDR_LO 10007#define PCIEMSIX_VECT27_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10008//PCIEMSIX_VECT27_ADDR_HI 10009#define PCIEMSIX_VECT27_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10010//PCIEMSIX_VECT27_MSG_DATA 10011#define PCIEMSIX_VECT27_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10012//PCIEMSIX_VECT27_CONTROL 10013#define PCIEMSIX_VECT27_CONTROL__MASK_BIT__MASK 0x00000001L 10014//PCIEMSIX_VECT28_ADDR_LO 10015#define PCIEMSIX_VECT28_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10016//PCIEMSIX_VECT28_ADDR_HI 10017#define PCIEMSIX_VECT28_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10018//PCIEMSIX_VECT28_MSG_DATA 10019#define PCIEMSIX_VECT28_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10020//PCIEMSIX_VECT28_CONTROL 10021#define PCIEMSIX_VECT28_CONTROL__MASK_BIT__MASK 0x00000001L 10022//PCIEMSIX_VECT29_ADDR_LO 10023#define PCIEMSIX_VECT29_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10024//PCIEMSIX_VECT29_ADDR_HI 10025#define PCIEMSIX_VECT29_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10026//PCIEMSIX_VECT29_MSG_DATA 10027#define PCIEMSIX_VECT29_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10028//PCIEMSIX_VECT29_CONTROL 10029#define PCIEMSIX_VECT29_CONTROL__MASK_BIT__MASK 0x00000001L 10030//PCIEMSIX_VECT30_ADDR_LO 10031#define PCIEMSIX_VECT30_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10032//PCIEMSIX_VECT30_ADDR_HI 10033#define PCIEMSIX_VECT30_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10034//PCIEMSIX_VECT30_MSG_DATA 10035#define PCIEMSIX_VECT30_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10036//PCIEMSIX_VECT30_CONTROL 10037#define PCIEMSIX_VECT30_CONTROL__MASK_BIT__MASK 0x00000001L 10038//PCIEMSIX_VECT31_ADDR_LO 10039#define PCIEMSIX_VECT31_ADDR_LO__MSG_ADDR_LO__MASK 0xFFFFFFFCL 10040//PCIEMSIX_VECT31_ADDR_HI 10041#define PCIEMSIX_VECT31_ADDR_HI__MSG_ADDR_HI__MASK 0xFFFFFFFFL 10042//PCIEMSIX_VECT31_MSG_DATA 10043#define PCIEMSIX_VECT31_MSG_DATA__MSG_DATA__MASK 0xFFFFFFFFL 10044//PCIEMSIX_VECT31_CONTROL 10045#define PCIEMSIX_VECT31_CONTROL__MASK_BIT__MASK 0x00000001L 10046 10047 10048// addressBlock: pciemsix_amdgfx_MSIXPDEC 10049//PCIEMSIX_PBA 10050#define PCIEMSIX_PBA__MSIX_PENDING_BITS__MASK 0xFFFFFFFFL 10051 10052 10053// addressBlock: syshub_mmreg_ind_syshubind 10054//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK 10055#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 10056#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 10057#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 10058#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 10059#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 10060#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 10061#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 10062#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__HST_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 10063#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 10064#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 10065#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 10066#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 10067#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 10068#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 10069#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 10070#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 10071#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 10072#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__MASK 0x80000000L 10073//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK 10074#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__MASK 0x0000FFFFL 10075//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 10076#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_bypass_en__MASK 0x00000001L 10077#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_bypass_en__MASK 0x00000002L 10078#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__MASK 0x00008000L 10079#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__MASK 0x00010000L 10080#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__MASK 0x00020000L 10081//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 10082#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW0_imm_en__MASK 0x00000001L 10083#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_HST_SW1_imm_en__MASK 0x00000002L 10084#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__MASK 0x00008000L 10085#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__MASK 0x00010000L 10086#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__MASK 0x00020000L 10087//SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 10088#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10089#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10090#define SYSHUBMMREGIND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10091//SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 10092#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10093#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10094#define SYSHUBMMREGIND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10095//SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL 10096#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10097#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10098#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10099#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10100#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10101#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10102//SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL 10103#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10104#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10105#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10106#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10107#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10108#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10109//SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL 10110#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10111#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10112#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10113#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10114#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10115#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10116//SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL 10117#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10118#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10119#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10120#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10121#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10122#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10123//SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL 10124#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10125#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10126#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10127#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10128#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10129#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10130//SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL 10131#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10132#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10133#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10134#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10135#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10136#define SYSHUBMMREGIND_DMA_CLK0_SW0_CL5_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10137//SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL 10138#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10139#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10140#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10141#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10142#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10143#define SYSHUBMMREGIND_DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10144//SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL 10145#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10146#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10147#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10148#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10149#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10150#define SYSHUBMMREGIND_DMA_CLK0_SW2_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10151//SYSHUBMMREGIND_SYSHUB_CG_CNTL 10152#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_EN__MASK 0x00000001L 10153#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_IDLE_TIMER__MASK 0x0000FF00L 10154#define SYSHUBMMREGIND_SYSHUB_CG_CNTL__SYSHUB_CG_WAKEUP_TIMER__MASK 0x00FF0000L 10155//SYSHUBMMREGIND_SYSHUB_TRANS_IDLE 10156#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF0__MASK 0x00000001L 10157#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF1__MASK 0x00000002L 10158#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF2__MASK 0x00000004L 10159#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF3__MASK 0x00000008L 10160#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF4__MASK 0x00000010L 10161#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF5__MASK 0x00000020L 10162#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF6__MASK 0x00000040L 10163#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF7__MASK 0x00000080L 10164#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF8__MASK 0x00000100L 10165#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF9__MASK 0x00000200L 10166#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF10__MASK 0x00000400L 10167#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF11__MASK 0x00000800L 10168#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF12__MASK 0x00001000L 10169#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF13__MASK 0x00002000L 10170#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF14__MASK 0x00004000L 10171#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_VF15__MASK 0x00008000L 10172#define SYSHUBMMREGIND_SYSHUB_TRANS_IDLE__SYSHUB_TRANS_IDLE_PF__MASK 0x00010000L 10173//SYSHUBMMREGIND_SYSHUB_HP_TIMER 10174#define SYSHUBMMREGIND_SYSHUB_HP_TIMER__SYSHUB_HP_TIMER__MASK 0xFFFFFFFFL 10175//SYSHUBMMREGIND_SYSHUB_SCRATCH 10176#define SYSHUBMMREGIND_SYSHUB_SCRATCH__SCRATCH__MASK 0xFFFFFFFFL 10177//SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK 10178#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000001L 10179#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000002L 10180#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000004L 10181#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000008L 10182#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000010L 10183#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000020L 10184#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000040L 10185#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__HST_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00000080L 10186#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL0_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00010000L 10187#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL1_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00020000L 10188#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL2_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00040000L 10189#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL3_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00080000L 10190#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL4_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00100000L 10191#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL5_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00200000L 10192#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL6_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00400000L 10193#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__DMA_CL7_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x00800000L 10194#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DEEPSLEEP_ALLOW_ENABLE__MASK 0x10000000L 10195#define SYSHUBMMREGIND_SYSHUB_DS_CTRL_SHUBCLK__SYSHUB_SHUBCLK_DS_EN__MASK 0x80000000L 10196//SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK 10197#define SYSHUBMMREGIND_SYSHUB_DS_CTRL2_SHUBCLK__SYSHUB_SHUBCLK_DS_TIMER__MASK 0x0000FFFFL 10198//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 10199#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_bypass_en__MASK 0x00008000L 10200#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_bypass_en__MASK 0x00010000L 10201//SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 10202#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW0_imm_en__MASK 0x00008000L 10203#define SYSHUBMMREGIND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK__SYSHUB_bgen_shubclk_DMA_SW1_imm_en__MASK 0x00010000L 10204//SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 10205#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10206#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10207#define SYSHUBMMREGIND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10208//SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 10209#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__MASK 0x00000001L 10210#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__MASK 0x0000001EL 10211#define SYSHUBMMREGIND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__MASK 0x000001E0L 10212//SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL 10213#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10214#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10215#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10216#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10217#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10218#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10219//SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL 10220#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10221#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10222#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10223#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10224#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10225#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10226//SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL 10227#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10228#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10229#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10230#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10231#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10232#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10233//SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL 10234#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10235#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10236#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10237#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10238#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10239#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10240//SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL 10241#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10242#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10243#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10244#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10245#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10246#define SYSHUBMMREGIND_DMA_CLK1_SW0_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10247//SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL 10248#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10249#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10250#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10251#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10252#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10253#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10254//SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL 10255#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10256#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10257#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10258#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10259#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10260#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10261//SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL 10262#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10263#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10264#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10265#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10266#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10267#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL2_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10268//SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL 10269#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10270#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10271#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10272#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10273#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10274#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL3_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10275//SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL 10276#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__FLR_ON_RS_RESET_EN__MASK 0x00000001L 10277#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__LKRST_ON_RS_RESET_EN__MASK 0x00000002L 10278#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_EN__MASK 0x00000100L 10279#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__QOS_STATIC_OVERRIDE_VALUE__MASK 0x00001E00L 10280#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__READ_WRR_WEIGHT__MASK 0x00FF0000L 10281#define SYSHUBMMREGIND_DMA_CLK1_SW1_CL4_CNTL__WRITE_WRR_WEIGHT__MASK 0xFF000000L 10282 10283#endif 10284