1/* $NetBSD: gmc_7_1_d.h,v 1.3 2021/12/18 23:45:15 riastradh Exp $ */ 2 3/* 4 * GMC_7_1 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef GMC_7_1_D_H 27#define GMC_7_1_D_H 28 29#define mmMC_CONFIG 0x800 30#define mmMC_ARB_AGE_CNTL 0x9bf 31#define mmMC_ARB_RET_CREDITS2 0x9c0 32#define mmMC_ARB_FED_CNTL 0x9c1 33#define mmMC_ARB_GECC2_STATUS 0x9c2 34#define mmMC_ARB_GECC2_MISC 0x9c3 35#define mmMC_ARB_GECC2_DEBUG 0x9c4 36#define mmMC_ARB_GECC2_DEBUG2 0x9c5 37#define mmMC_ARB_PERF_CID 0x9c6 38#define mmMC_ARB_GECC2 0x9c9 39#define mmMC_ARB_GECC2_CLI 0x9ca 40#define mmMC_ARB_ADDR_SWIZ0 0x9cb 41#define mmMC_ARB_ADDR_SWIZ1 0x9cc 42#define mmMC_ARB_MISC3 0x9cd 43#define mmMC_ARB_WCDR_2 0x9ce 44#define mmMC_ARB_RTT_DATA 0x9cf 45#define mmMC_ARB_RTT_CNTL0 0x9d0 46#define mmMC_ARB_RTT_CNTL1 0x9d1 47#define mmMC_ARB_RTT_CNTL2 0x9d2 48#define mmMC_ARB_RTT_DEBUG 0x9d3 49#define mmMC_ARB_CAC_CNTL 0x9d4 50#define mmMC_ARB_MISC2 0x9d5 51#define mmMC_ARB_MISC 0x9d6 52#define mmMC_ARB_BANKMAP 0x9d7 53#define mmMC_ARB_RAMCFG 0x9d8 54#define mmMC_ARB_POP 0x9d9 55#define mmMC_ARB_MINCLKS 0x9da 56#define mmMC_ARB_SQM_CNTL 0x9db 57#define mmMC_ARB_ADDR_HASH 0x9dc 58#define mmMC_ARB_DRAM_TIMING 0x9dd 59#define mmMC_ARB_DRAM_TIMING2 0x9de 60#define mmMC_ARB_WTM_CNTL_RD 0x9df 61#define mmMC_ARB_WTM_CNTL_WR 0x9e0 62#define mmMC_ARB_WTM_GRPWT_RD 0x9e1 63#define mmMC_ARB_WTM_GRPWT_WR 0x9e2 64#define mmMC_ARB_TM_CNTL_RD 0x9e3 65#define mmMC_ARB_TM_CNTL_WR 0x9e4 66#define mmMC_ARB_LAZY0_RD 0x9e5 67#define mmMC_ARB_LAZY0_WR 0x9e6 68#define mmMC_ARB_LAZY1_RD 0x9e7 69#define mmMC_ARB_LAZY1_WR 0x9e8 70#define mmMC_ARB_AGE_RD 0x9e9 71#define mmMC_ARB_AGE_WR 0x9ea 72#define mmMC_ARB_RFSH_CNTL 0x9eb 73#define mmMC_ARB_RFSH_RATE 0x9ec 74#define mmMC_ARB_PM_CNTL 0x9ed 75#define mmMC_ARB_GDEC_RD_CNTL 0x9ee 76#define mmMC_ARB_GDEC_WR_CNTL 0x9ef 77#define mmMC_ARB_LM_RD 0x9f0 78#define mmMC_ARB_LM_WR 0x9f1 79#define mmMC_ARB_REMREQ 0x9f2 80#define mmMC_ARB_REPLAY 0x9f3 81#define mmMC_ARB_RET_CREDITS_RD 0x9f4 82#define mmMC_ARB_RET_CREDITS_WR 0x9f5 83#define mmMC_ARB_MAX_LAT_CID 0x9f6 84#define mmMC_ARB_MAX_LAT_RSLT0 0x9f7 85#define mmMC_ARB_MAX_LAT_RSLT1 0x9f8 86#define mmMC_ARB_SSM 0x9f9 87#define mmMC_ARB_CG 0x9fa 88#define mmMC_ARB_WCDR 0x9fb 89#define mmMC_ARB_DRAM_TIMING_1 0x9fc 90#define mmMC_ARB_BUSY_STATUS 0x9fd 91#define mmMC_ARB_DRAM_TIMING2_1 0x9ff 92#define mmMC_ARB_BURST_TIME 0xa02 93#define mmMC_CITF_XTRA_ENABLE 0x96d 94#define mmCC_MC_MAX_CHANNEL 0x96e 95#define mmMC_CG_CONFIG 0x96f 96#define mmMC_CITF_CNTL 0x970 97#define mmMC_CITF_CREDITS_VM 0x971 98#define mmMC_CITF_CREDITS_ARB_RD 0x972 99#define mmMC_CITF_CREDITS_ARB_WR 0x973 100#define mmMC_CITF_DAGB_CNTL 0x974 101#define mmMC_CITF_INT_CREDITS 0x975 102#define mmMC_CITF_RET_MODE 0x976 103#define mmMC_CITF_DAGB_DLY 0x977 104#define mmMC_RD_GRP_EXT 0x978 105#define mmMC_WR_GRP_EXT 0x979 106#define mmMC_CITF_REMREQ 0x97a 107#define mmMC_WR_TC0 0x97b 108#define mmMC_WR_TC1 0x97c 109#define mmMC_CITF_INT_CREDITS_WR 0x97d 110#define mmMC_CITF_WTM_RD_CNTL 0x97f 111#define mmMC_CITF_WTM_WR_CNTL 0x980 112#define mmMC_RD_CB 0x981 113#define mmMC_RD_DB 0x982 114#define mmMC_RD_TC0 0x983 115#define mmMC_RD_TC1 0x984 116#define mmMC_RD_HUB 0x985 117#define mmMC_WR_CB 0x986 118#define mmMC_WR_DB 0x987 119#define mmMC_WR_HUB 0x988 120#define mmMC_CITF_CREDITS_XBAR 0x989 121#define mmMC_RD_GRP_LCL 0x98a 122#define mmMC_WR_GRP_LCL 0x98b 123#define mmMC_CITF_PERF_MON_CNTL2 0x98e 124#define mmMC_CITF_PERF_MON_RSLT2 0x991 125#define mmMC_CITF_MISC_RD_CG 0x992 126#define mmMC_CITF_MISC_WR_CG 0x993 127#define mmMC_CITF_MISC_VM_CG 0x994 128#define mmMC_HUB_MISC_POWER 0x82d 129#define mmMC_HUB_MISC_HUB_CG 0x82e 130#define mmMC_HUB_MISC_VM_CG 0x82f 131#define mmMC_HUB_MISC_SIP_CG 0x830 132#define mmMC_HUB_MISC_STATUS 0x832 133#define mmMC_HUB_MISC_OVERRIDE 0x833 134#define mmMC_HUB_MISC_FRAMING 0x834 135#define mmMC_HUB_WDP_CNTL 0x835 136#define mmMC_HUB_WDP_ERR 0x836 137#define mmMC_HUB_WDP_BP 0x837 138#define mmMC_HUB_WDP_STATUS 0x838 139#define mmMC_HUB_RDREQ_STATUS 0x839 140#define mmMC_HUB_WRRET_STATUS 0x83a 141#define mmMC_HUB_RDREQ_CNTL 0x83b 142#define mmMC_HUB_WRRET_CNTL 0x83c 143#define mmMC_HUB_RDREQ_WTM_CNTL 0x83d 144#define mmMC_HUB_WDP_WTM_CNTL 0x83e 145#define mmMC_HUB_WDP_CREDITS 0x83f 146#define mmMC_HUB_WDP_CREDITS2 0x840 147#define mmMC_HUB_WDP_GBL0 0x841 148#define mmMC_HUB_WDP_GBL1 0x842 149#define mmMC_HUB_RDREQ_CREDITS 0x844 150#define mmMC_HUB_RDREQ_CREDITS2 0x845 151#define mmMC_HUB_SHARED_DAGB_DLY 0x846 152#define mmMC_HUB_MISC_IDLE_STATUS 0x847 153#define mmMC_HUB_RDREQ_DMIF_LIMIT 0x848 154#define mmMC_HUB_RDREQ_ACPG_LIMIT 0x849 155#define mmMC_HUB_WDP_BYPASS_GBL0 0x84a 156#define mmMC_HUB_WDP_BYPASS_GBL1 0x84b 157#define mmMC_HUB_RDREQ_BYPASS_GBL0 0x84c 158#define mmMC_HUB_WDP_SH2 0x84d 159#define mmMC_HUB_WDP_SH3 0x84e 160#define mmMC_HUB_RDREQ_IA0 0x84f 161#define mmMC_HUB_RDREQ_IA1 0x850 162#define mmMC_HUB_RDREQ_MCDW 0x851 163#define mmMC_HUB_RDREQ_MCDX 0x852 164#define mmMC_HUB_RDREQ_MCDY 0x853 165#define mmMC_HUB_RDREQ_MCDZ 0x854 166#define mmMC_HUB_RDREQ_SIP 0x855 167#define mmMC_HUB_RDREQ_GBL0 0x856 168#define mmMC_HUB_RDREQ_GBL1 0x857 169#define mmMC_HUB_RDREQ_SMU 0x858 170#define mmMC_HUB_RDREQ_CPG 0x859 171#define mmMC_HUB_RDREQ_SDMA0 0x85a 172#define mmMC_HUB_RDREQ_HDP 0x85b 173#define mmMC_HUB_RDREQ_SDMA1 0x85c 174#define mmMC_HUB_RDREQ_RLC 0x85d 175#define mmMC_HUB_RDREQ_SEM 0x85e 176#define mmMC_HUB_RDREQ_VCE 0x85f 177#define mmMC_HUB_RDREQ_UMC 0x860 178#define mmMC_HUB_RDREQ_UVD 0x861 179#define mmMC_HUB_RDREQ_IA 0x862 180#define mmMC_HUB_RDREQ_DMIF 0x863 181#define mmMC_HUB_RDREQ_MCIF 0x864 182#define mmMC_HUB_RDREQ_VMC 0x865 183#define mmMC_HUB_RDREQ_VCEU 0x866 184#define mmMC_HUB_WDP_MCDW 0x867 185#define mmMC_HUB_WDP_MCDX 0x868 186#define mmMC_HUB_WDP_MCDY 0x869 187#define mmMC_HUB_WDP_MCDZ 0x86a 188#define mmMC_HUB_WDP_SIP 0x86b 189#define mmMC_HUB_WDP_CPG 0x86c 190#define mmMC_HUB_WDP_SDMA1 0x86d 191#define mmMC_HUB_WDP_SH0 0x86e 192#define mmMC_HUB_WDP_MCIF 0x86f 193#define mmMC_HUB_WDP_VCE 0x870 194#define mmMC_HUB_WDP_XDP 0x871 195#define mmMC_HUB_WDP_IH 0x872 196#define mmMC_HUB_WDP_RLC 0x873 197#define mmMC_HUB_WDP_SEM 0x874 198#define mmMC_HUB_WDP_SMU 0x875 199#define mmMC_HUB_WDP_SH1 0x876 200#define mmMC_HUB_WDP_UMC 0x877 201#define mmMC_HUB_WDP_UVD 0x878 202#define mmMC_HUB_WDP_HDP 0x879 203#define mmMC_HUB_WDP_SDMA0 0x87a 204#define mmMC_HUB_WRRET_MCDW 0x87b 205#define mmMC_HUB_WRRET_MCDX 0x87c 206#define mmMC_HUB_WRRET_MCDY 0x87d 207#define mmMC_HUB_WRRET_MCDZ 0x87e 208#define mmMC_HUB_WDP_VCEU 0x87f 209#define mmMC_HUB_WDP_XDMAM 0x880 210#define mmMC_HUB_WDP_XDMA 0x881 211#define mmMC_HUB_RDREQ_XDMAM 0x882 212#define mmMC_HUB_RDREQ_ACPG 0x883 213#define mmMC_HUB_RDREQ_ACPO 0x884 214#define mmMC_HUB_RDREQ_SAM 0x885 215#define mmMC_HUB_WDP_ACPG 0x886 216#define mmMC_HUB_WDP_ACPO 0x887 217#define mmMC_HUB_WDP_SAM 0x888 218#define mmMC_HUB_RDREQ_CPC 0x889 219#define mmMC_HUB_RDREQ_CPF 0x88a 220#define mmMC_HUB_WDP_CPC 0x88b 221#define mmMC_HUB_WDP_CPF 0x88c 222#define mmMC_HUB_RDREQ_ISP_SPM 0xde0 223#define mmMC_HUB_RDREQ_ISP_MPM 0xde1 224#define mmMC_HUB_RDREQ_ISP_CCPU 0xde2 225#define mmMC_HUB_WDP_ISP_SPM 0xde3 226#define mmMC_HUB_WDP_ISP_MPS 0xde4 227#define mmMC_HUB_WDP_ISP_MPM 0xde5 228#define mmMC_HUB_WDP_ISP_CCPU 0xde6 229#define mmMC_HUB_RDREQ_MCDS 0xde7 230#define mmMC_HUB_RDREQ_MCDT 0xde8 231#define mmMC_HUB_RDREQ_MCDU 0xde9 232#define mmMC_HUB_RDREQ_MCDV 0xdea 233#define mmMC_HUB_WDP_MCDS 0xdeb 234#define mmMC_HUB_WDP_MCDT 0xdec 235#define mmMC_HUB_WDP_MCDU 0xded 236#define mmMC_HUB_WDP_MCDV 0xdee 237#define mmMC_HUB_WRRET_MCDS 0xdef 238#define mmMC_HUB_WRRET_MCDT 0xdf0 239#define mmMC_HUB_WRRET_MCDU 0xdf1 240#define mmMC_HUB_WRRET_MCDV 0xdf2 241#define mmMC_HUB_WDP_CREDITS_MCDW 0xdf3 242#define mmMC_HUB_WDP_CREDITS_MCDX 0xdf4 243#define mmMC_HUB_WDP_CREDITS_MCDY 0xdf5 244#define mmMC_HUB_WDP_CREDITS_MCDZ 0xdf6 245#define mmMC_HUB_WDP_CREDITS_MCDS 0xdf7 246#define mmMC_HUB_WDP_CREDITS_MCDT 0xdf8 247#define mmMC_HUB_WDP_CREDITS_MCDU 0xdf9 248#define mmMC_HUB_WDP_CREDITS_MCDV 0xdfa 249#define mmMC_HUB_WDP_BP2 0xdfb 250#define mmMC_RPB_CONF 0x94d 251#define mmMC_RPB_IF_CONF 0x94e 252#define mmMC_RPB_DBG1 0x94f 253#define mmMC_RPB_EFF_CNTL 0x950 254#define mmMC_RPB_ARB_CNTL 0x951 255#define mmMC_RPB_BIF_CNTL 0x952 256#define mmMC_RPB_WR_SWITCH_CNTL 0x953 257#define mmMC_RPB_WR_COMBINE_CNTL 0x954 258#define mmMC_RPB_RD_SWITCH_CNTL 0x955 259#define mmMC_RPB_CID_QUEUE_WR 0x956 260#define mmMC_RPB_CID_QUEUE_RD 0x957 261#define mmMC_RPB_PERF_COUNTER_CNTL 0x958 262#define mmMC_RPB_PERF_COUNTER_STATUS 0x959 263#define mmMC_RPB_CID_QUEUE_EX 0x95a 264#define mmMC_RPB_CID_QUEUE_EX_DATA 0x95b 265#define mmMC_RPB_TCI_CNTL 0x95c 266#define mmMC_SHARED_CHMAP 0x801 267#define mmMC_SHARED_CHREMAP 0x802 268#define mmMC_RD_GRP_GFX 0x803 269#define mmMC_WR_GRP_GFX 0x804 270#define mmMC_RD_GRP_SYS 0x805 271#define mmMC_WR_GRP_SYS 0x806 272#define mmMC_RD_GRP_OTH 0x807 273#define mmMC_WR_GRP_OTH 0x808 274#define mmMC_VM_FB_LOCATION 0x809 275#define mmMC_VM_AGP_TOP 0x80a 276#define mmMC_VM_AGP_BOT 0x80b 277#define mmMC_VM_AGP_BASE 0x80c 278#define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x80d 279#define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x80e 280#define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x80f 281#define mmMC_VM_DC_WRITE_CNTL 0x810 282#define mmMC_VM_DC_WRITE_HIT_REGION_0_LOW_ADDR 0x811 283#define mmMC_VM_DC_WRITE_HIT_REGION_1_LOW_ADDR 0x812 284#define mmMC_VM_DC_WRITE_HIT_REGION_2_LOW_ADDR 0x813 285#define mmMC_VM_DC_WRITE_HIT_REGION_3_LOW_ADDR 0x814 286#define mmMC_VM_DC_WRITE_HIT_REGION_0_HIGH_ADDR 0x815 287#define mmMC_VM_DC_WRITE_HIT_REGION_1_HIGH_ADDR 0x816 288#define mmMC_VM_DC_WRITE_HIT_REGION_2_HIGH_ADDR 0x817 289#define mmMC_VM_DC_WRITE_HIT_REGION_3_HIGH_ADDR 0x818 290#define mmMC_VM_MX_L1_TLB_CNTL 0x819 291#define mmMC_VM_FB_OFFSET 0x81a 292#define mmMC_VM_STEERING 0x81b 293#define mmMC_SHARED_CHREMAP2 0x81c 294#define mmMC_CONFIG_MCD 0x828 295#define mmMC_CG_CONFIG_MCD 0x829 296#define mmMC_MEM_POWER_LS 0x82a 297#define mmMC_SHARED_BLACKOUT_CNTL 0x82b 298#define mmMC_VM_MB_L1_TLB0_DEBUG 0x891 299#define mmMC_VM_MB_L1_TLB2_DEBUG 0x893 300#define mmMC_VM_MB_L1_TLB0_STATUS 0x895 301#define mmMC_VM_MB_L1_TLB1_STATUS 0x896 302#define mmMC_VM_MB_L1_TLB2_STATUS 0x897 303#define mmMC_VM_MB_L2ARBITER_L2_CREDITS 0x8a1 304#define mmMC_VM_MB_L1_TLB3_DEBUG 0x8a5 305#define mmMC_VM_MB_L1_TLB3_STATUS 0x8a6 306#define mmMC_VM_MD_L1_TLB0_DEBUG 0x998 307#define mmMC_VM_MD_L1_TLB1_DEBUG 0x999 308#define mmMC_VM_MD_L1_TLB2_DEBUG 0x99a 309#define mmMC_VM_MD_L1_TLB0_STATUS 0x99b 310#define mmMC_VM_MD_L1_TLB1_STATUS 0x99c 311#define mmMC_VM_MD_L1_TLB2_STATUS 0x99d 312#define mmMC_VM_MD_L2ARBITER_L2_CREDITS 0x9a4 313#define mmMC_VM_MD_L1_TLB3_DEBUG 0x9a7 314#define mmMC_VM_MD_L1_TLB3_STATUS 0x9a8 315#define mmMC_XPB_RTR_SRC_APRTR0 0x8cd 316#define mmMC_XPB_RTR_SRC_APRTR1 0x8ce 317#define mmMC_XPB_RTR_SRC_APRTR2 0x8cf 318#define mmMC_XPB_RTR_SRC_APRTR3 0x8d0 319#define mmMC_XPB_RTR_SRC_APRTR4 0x8d1 320#define mmMC_XPB_RTR_SRC_APRTR5 0x8d2 321#define mmMC_XPB_RTR_SRC_APRTR6 0x8d3 322#define mmMC_XPB_RTR_SRC_APRTR7 0x8d4 323#define mmMC_XPB_RTR_SRC_APRTR8 0x8d5 324#define mmMC_XPB_RTR_SRC_APRTR9 0x8d6 325#define mmMC_XPB_XDMA_RTR_SRC_APRTR0 0x8d7 326#define mmMC_XPB_XDMA_RTR_SRC_APRTR1 0x8d8 327#define mmMC_XPB_XDMA_RTR_SRC_APRTR2 0x8d9 328#define mmMC_XPB_XDMA_RTR_SRC_APRTR3 0x8da 329#define mmMC_XPB_RTR_DEST_MAP0 0x8db 330#define mmMC_XPB_RTR_DEST_MAP1 0x8dc 331#define mmMC_XPB_RTR_DEST_MAP2 0x8dd 332#define mmMC_XPB_RTR_DEST_MAP3 0x8de 333#define mmMC_XPB_RTR_DEST_MAP4 0x8df 334#define mmMC_XPB_RTR_DEST_MAP5 0x8e0 335#define mmMC_XPB_RTR_DEST_MAP6 0x8e1 336#define mmMC_XPB_RTR_DEST_MAP7 0x8e2 337#define mmMC_XPB_RTR_DEST_MAP8 0x8e3 338#define mmMC_XPB_RTR_DEST_MAP9 0x8e4 339#define mmMC_XPB_XDMA_RTR_DEST_MAP0 0x8e5 340#define mmMC_XPB_XDMA_RTR_DEST_MAP1 0x8e6 341#define mmMC_XPB_XDMA_RTR_DEST_MAP2 0x8e7 342#define mmMC_XPB_XDMA_RTR_DEST_MAP3 0x8e8 343#define mmMC_XPB_CLG_CFG0 0x8e9 344#define mmMC_XPB_CLG_CFG1 0x8ea 345#define mmMC_XPB_CLG_CFG2 0x8eb 346#define mmMC_XPB_CLG_CFG3 0x8ec 347#define mmMC_XPB_CLG_CFG4 0x8ed 348#define mmMC_XPB_CLG_CFG5 0x8ee 349#define mmMC_XPB_CLG_CFG6 0x8ef 350#define mmMC_XPB_CLG_CFG7 0x8f0 351#define mmMC_XPB_CLG_CFG8 0x8f1 352#define mmMC_XPB_CLG_CFG9 0x8f2 353#define mmMC_XPB_CLG_CFG10 0x8f3 354#define mmMC_XPB_CLG_CFG11 0x8f4 355#define mmMC_XPB_CLG_CFG12 0x8f5 356#define mmMC_XPB_CLG_CFG13 0x8f6 357#define mmMC_XPB_CLG_CFG14 0x8f7 358#define mmMC_XPB_CLG_CFG15 0x8f8 359#define mmMC_XPB_CLG_CFG16 0x8f9 360#define mmMC_XPB_CLG_CFG17 0x8fa 361#define mmMC_XPB_CLG_CFG18 0x8fb 362#define mmMC_XPB_CLG_CFG19 0x8fc 363#define mmMC_XPB_CLG_EXTRA 0x8fd 364#define mmMC_XPB_LB_ADDR 0x8fe 365#define mmMC_XPB_UNC_THRESH_HST 0x8ff 366#define mmMC_XPB_UNC_THRESH_SID 0x900 367#define mmMC_XPB_WCB_STS 0x901 368#define mmMC_XPB_WCB_CFG 0x902 369#define mmMC_XPB_P2P_BAR_CFG 0x903 370#define mmMC_XPB_P2P_BAR0 0x904 371#define mmMC_XPB_P2P_BAR1 0x905 372#define mmMC_XPB_P2P_BAR2 0x906 373#define mmMC_XPB_P2P_BAR3 0x907 374#define mmMC_XPB_P2P_BAR4 0x908 375#define mmMC_XPB_P2P_BAR5 0x909 376#define mmMC_XPB_P2P_BAR6 0x90a 377#define mmMC_XPB_P2P_BAR7 0x90b 378#define mmMC_XPB_P2P_BAR_SETUP 0x90c 379#define mmMC_XPB_P2P_BAR_DEBUG 0x90d 380#define mmMC_XPB_P2P_BAR_DELTA_ABOVE 0x90e 381#define mmMC_XPB_P2P_BAR_DELTA_BELOW 0x90f 382#define mmMC_XPB_PEER_SYS_BAR0 0x910 383#define mmMC_XPB_PEER_SYS_BAR1 0x911 384#define mmMC_XPB_PEER_SYS_BAR2 0x912 385#define mmMC_XPB_PEER_SYS_BAR3 0x913 386#define mmMC_XPB_PEER_SYS_BAR4 0x914 387#define mmMC_XPB_PEER_SYS_BAR5 0x915 388#define mmMC_XPB_PEER_SYS_BAR6 0x916 389#define mmMC_XPB_PEER_SYS_BAR7 0x917 390#define mmMC_XPB_PEER_SYS_BAR8 0x918 391#define mmMC_XPB_PEER_SYS_BAR9 0x919 392#define mmMC_XPB_XDMA_PEER_SYS_BAR0 0x91a 393#define mmMC_XPB_XDMA_PEER_SYS_BAR1 0x91b 394#define mmMC_XPB_XDMA_PEER_SYS_BAR2 0x91c 395#define mmMC_XPB_XDMA_PEER_SYS_BAR3 0x91d 396#define mmMC_XPB_CLK_GAT 0x91e 397#define mmMC_XPB_INTF_CFG 0x91f 398#define mmMC_XPB_INTF_STS 0x920 399#define mmMC_XPB_PIPE_STS 0x921 400#define mmMC_XPB_SUB_CTRL 0x922 401#define mmMC_XPB_MAP_INVERT_FLUSH_NUM_LSB 0x923 402#define mmMC_XPB_PERF_KNOBS 0x924 403#define mmMC_XPB_STICKY 0x925 404#define mmMC_XPB_STICKY_W1C 0x926 405#define mmMC_XPB_MISC_CFG 0x927 406#define mmMC_XPB_CLG_CFG20 0x928 407#define mmMC_XPB_CLG_CFG21 0x929 408#define mmMC_XPB_CLG_CFG22 0x92a 409#define mmMC_XPB_CLG_CFG23 0x92b 410#define mmMC_XPB_CLG_CFG24 0x92c 411#define mmMC_XPB_CLG_CFG25 0x92d 412#define mmMC_XPB_CLG_CFG26 0x92e 413#define mmMC_XPB_CLG_CFG27 0x92f 414#define mmMC_XPB_CLG_CFG28 0x930 415#define mmMC_XPB_CLG_CFG29 0x931 416#define mmMC_XPB_CLG_CFG30 0x932 417#define mmMC_XPB_CLG_CFG31 0x933 418#define mmMC_XPB_INTF_CFG2 0x934 419#define mmMC_XPB_CLG_EXTRA_RD 0x935 420#define mmMC_XPB_CLG_CFG32 0x936 421#define mmMC_XPB_CLG_CFG33 0x937 422#define mmMC_XPB_CLG_CFG34 0x938 423#define mmMC_XPB_CLG_CFG35 0x939 424#define mmMC_XPB_CLG_CFG36 0x93a 425#define mmMC_XBAR_ADDR_DEC 0xc80 426#define mmMC_XBAR_REMOTE 0xc81 427#define mmMC_XBAR_WRREQ_CREDIT 0xc82 428#define mmMC_XBAR_RDREQ_CREDIT 0xc83 429#define mmMC_XBAR_RDREQ_PRI_CREDIT 0xc84 430#define mmMC_XBAR_WRRET_CREDIT1 0xc85 431#define mmMC_XBAR_WRRET_CREDIT2 0xc86 432#define mmMC_XBAR_RDRET_CREDIT1 0xc87 433#define mmMC_XBAR_RDRET_CREDIT2 0xc88 434#define mmMC_XBAR_RDRET_PRI_CREDIT1 0xc89 435#define mmMC_XBAR_RDRET_PRI_CREDIT2 0xc8a 436#define mmMC_XBAR_CHTRIREMAP 0xc8b 437#define mmMC_XBAR_TWOCHAN 0xc8c 438#define mmMC_XBAR_ARB 0xc8d 439#define mmMC_XBAR_ARB_MAX_BURST 0xc8e 440#define mmMC_XBAR_PERF_MON_CNTL0 0xc8f 441#define mmMC_XBAR_PERF_MON_CNTL1 0xc90 442#define mmMC_XBAR_PERF_MON_CNTL2 0xc91 443#define mmMC_XBAR_PERF_MON_RSLT0 0xc92 444#define mmMC_XBAR_PERF_MON_RSLT1 0xc93 445#define mmMC_XBAR_PERF_MON_RSLT2 0xc94 446#define mmMC_XBAR_PERF_MON_RSLT3 0xc95 447#define mmMC_XBAR_PERF_MON_MAX_THSH 0xc96 448#define mmMC_XBAR_SPARE0 0xc97 449#define mmMC_XBAR_SPARE1 0xc98 450#define mmMC_CITF_PERFCOUNTER_LO 0x7a0 451#define mmMC_HUB_PERFCOUNTER_LO 0x7a1 452#define mmMC_RPB_PERFCOUNTER_LO 0x7a2 453#define mmMC_MCBVM_PERFCOUNTER_LO 0x7a3 454#define mmMC_MCDVM_PERFCOUNTER_LO 0x7a4 455#define mmMC_VM_L2_PERFCOUNTER_LO 0x7a5 456#define mmMC_ARB_PERFCOUNTER_LO 0x7a6 457#define mmATC_PERFCOUNTER_LO 0x7a7 458#define mmMC_CITF_PERFCOUNTER_HI 0x7a8 459#define mmMC_HUB_PERFCOUNTER_HI 0x7a9 460#define mmMC_MCBVM_PERFCOUNTER_HI 0x7aa 461#define mmMC_MCDVM_PERFCOUNTER_HI 0x7ab 462#define mmMC_RPB_PERFCOUNTER_HI 0x7ac 463#define mmMC_VM_L2_PERFCOUNTER_HI 0x7ad 464#define mmMC_ARB_PERFCOUNTER_HI 0x7ae 465#define mmATC_PERFCOUNTER_HI 0x7af 466#define mmMC_CITF_PERFCOUNTER0_CFG 0x7b0 467#define mmMC_CITF_PERFCOUNTER1_CFG 0x7b1 468#define mmMC_CITF_PERFCOUNTER2_CFG 0x7b2 469#define mmMC_CITF_PERFCOUNTER3_CFG 0x7b3 470#define mmMC_HUB_PERFCOUNTER0_CFG 0x7b4 471#define mmMC_HUB_PERFCOUNTER1_CFG 0x7b5 472#define mmMC_HUB_PERFCOUNTER2_CFG 0x7b6 473#define mmMC_HUB_PERFCOUNTER3_CFG 0x7b7 474#define mmMC_RPB_PERFCOUNTER0_CFG 0x7b8 475#define mmMC_RPB_PERFCOUNTER1_CFG 0x7b9 476#define mmMC_RPB_PERFCOUNTER2_CFG 0x7ba 477#define mmMC_RPB_PERFCOUNTER3_CFG 0x7bb 478#define mmMC_ARB_PERFCOUNTER0_CFG 0x7bc 479#define mmMC_ARB_PERFCOUNTER1_CFG 0x7bd 480#define mmMC_ARB_PERFCOUNTER2_CFG 0x7be 481#define mmMC_ARB_PERFCOUNTER3_CFG 0x7bf 482#define mmMC_MCBVM_PERFCOUNTER0_CFG 0x7c0 483#define mmMC_MCBVM_PERFCOUNTER1_CFG 0x7c1 484#define mmMC_MCBVM_PERFCOUNTER2_CFG 0x7c2 485#define mmMC_MCBVM_PERFCOUNTER3_CFG 0x7c3 486#define mmMC_MCDVM_PERFCOUNTER0_CFG 0x7c4 487#define mmMC_MCDVM_PERFCOUNTER1_CFG 0x7c5 488#define mmMC_MCDVM_PERFCOUNTER2_CFG 0x7c6 489#define mmMC_MCDVM_PERFCOUNTER3_CFG 0x7c7 490#define mmATC_PERFCOUNTER0_CFG 0x7c8 491#define mmATC_PERFCOUNTER1_CFG 0x7c9 492#define mmATC_PERFCOUNTER2_CFG 0x7ca 493#define mmATC_PERFCOUNTER3_CFG 0x7cb 494#define mmMC_VM_L2_PERFCOUNTER0_CFG 0x7cc 495#define mmMC_VM_L2_PERFCOUNTER1_CFG 0x7cd 496#define mmMC_CITF_PERFCOUNTER_RSLT_CNTL 0x7ce 497#define mmMC_HUB_PERFCOUNTER_RSLT_CNTL 0x7cf 498#define mmMC_RPB_PERFCOUNTER_RSLT_CNTL 0x7d0 499#define mmMC_MCBVM_PERFCOUNTER_RSLT_CNTL 0x7d1 500#define mmMC_MCDVM_PERFCOUNTER_RSLT_CNTL 0x7d2 501#define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x7d3 502#define mmMC_ARB_PERFCOUNTER_RSLT_CNTL 0x7d4 503#define mmATC_PERFCOUNTER_RSLT_CNTL 0x7d5 504#define mmCHUB_ATC_PERFCOUNTER_LO 0x7d6 505#define mmCHUB_ATC_PERFCOUNTER_HI 0x7d7 506#define mmCHUB_ATC_PERFCOUNTER0_CFG 0x7d8 507#define mmCHUB_ATC_PERFCOUNTER1_CFG 0x7d9 508#define mmCHUB_ATC_PERFCOUNTER_RSLT_CNTL 0x7da 509#define mmMC_ARB_PERF_MON_CNTL0_ECC 0x7db 510#define mmATC_VM_APERTURE0_LOW_ADDR 0xcc0 511#define mmATC_VM_APERTURE1_LOW_ADDR 0xcc1 512#define mmATC_VM_APERTURE0_HIGH_ADDR 0xcc2 513#define mmATC_VM_APERTURE1_HIGH_ADDR 0xcc3 514#define mmATC_VM_APERTURE0_CNTL 0xcc4 515#define mmATC_VM_APERTURE1_CNTL 0xcc5 516#define mmATC_VM_APERTURE0_CNTL2 0xcc6 517#define mmATC_VM_APERTURE1_CNTL2 0xcc7 518#define mmATC_ATS_CNTL 0xcc9 519#define mmATC_ATS_DEBUG 0xcca 520#define mmATC_ATS_FAULT_DEBUG 0xccb 521#define mmATC_ATS_STATUS 0xccc 522#define mmATC_ATS_FAULT_CNTL 0xccd 523#define mmATC_ATS_FAULT_STATUS_INFO 0xcce 524#define mmATC_ATS_FAULT_STATUS_ADDR 0xccf 525#define mmATC_ATS_DEFAULT_PAGE_LOW 0xcd0 526#define mmATC_ATS_DEFAULT_PAGE_CNTL 0xcd1 527#define mmATC_MISC_CG 0xcd4 528#define mmATC_L2_CNTL 0xcd5 529#define mmATC_L2_CNTL2 0xcd6 530#define mmATC_L2_DEBUG 0xcd7 531#define mmATC_L2_DEBUG2 0xcd8 532#define mmATC_L1_CNTL 0xcdc 533#define mmATC_L1_ADDRESS_OFFSET 0xcdd 534#define mmATC_L1RD_DEBUG_TLB 0xcde 535#define mmATC_L1WR_DEBUG_TLB 0xcdf 536#define mmATC_L1RD_STATUS 0xce0 537#define mmATC_L1WR_STATUS 0xce1 538#define mmATC_VMID_PASID_MAPPING_UPDATE_STATUS 0xce6 539#define mmATC_VMID0_PASID_MAPPING 0xce7 540#define mmATC_VMID1_PASID_MAPPING 0xce8 541#define mmATC_VMID2_PASID_MAPPING 0xce9 542#define mmATC_VMID3_PASID_MAPPING 0xcea 543#define mmATC_VMID4_PASID_MAPPING 0xceb 544#define mmATC_VMID5_PASID_MAPPING 0xcec 545#define mmATC_VMID6_PASID_MAPPING 0xced 546#define mmATC_VMID7_PASID_MAPPING 0xcee 547#define mmATC_VMID8_PASID_MAPPING 0xcef 548#define mmATC_VMID9_PASID_MAPPING 0xcf0 549#define mmATC_VMID10_PASID_MAPPING 0xcf1 550#define mmATC_VMID11_PASID_MAPPING 0xcf2 551#define mmATC_VMID12_PASID_MAPPING 0xcf3 552#define mmATC_VMID13_PASID_MAPPING 0xcf4 553#define mmATC_VMID14_PASID_MAPPING 0xcf5 554#define mmATC_VMID15_PASID_MAPPING 0xcf6 555#define mmGMCON_RENG_RAM_INDEX 0xd40 556#define mmGMCON_RENG_RAM_DATA 0xd41 557#define mmGMCON_RENG_EXECUTE 0xd42 558#define mmGMCON_MISC 0xd43 559#define mmGMCON_MISC2 0xd44 560#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE0 0xd45 561#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE1 0xd46 562#define mmGMCON_STCTRL_REGISTER_SAVE_RANGE2 0xd47 563#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET0 0xd48 564#define mmGMCON_STCTRL_REGISTER_SAVE_EXCL_SET1 0xd49 565#define mmGMCON_PERF_MON_CNTL0 0xd4a 566#define mmGMCON_PERF_MON_CNTL1 0xd4b 567#define mmGMCON_PERF_MON_RSLT0 0xd4c 568#define mmGMCON_PERF_MON_RSLT1 0xd4d 569#define mmGMCON_PGFSM_CONFIG 0xd4e 570#define mmGMCON_PGFSM_WRITE 0xd4f 571#define mmGMCON_PGFSM_READ 0xd50 572#define mmGMCON_MISC3 0xd51 573#define mmGMCON_MASK 0xd52 574#define mmGMCON_LPT_TARGET 0xd53 575#define mmGMCON_DEBUG 0xd5f 576#define mmVM_L2_CNTL 0x500 577#define mmVM_L2_CNTL2 0x501 578#define mmVM_L2_CNTL3 0x502 579#define mmVM_L2_STATUS 0x503 580#define mmVM_CONTEXT0_CNTL 0x504 581#define mmVM_CONTEXT1_CNTL 0x505 582#define mmVM_DUMMY_PAGE_FAULT_CNTL 0x506 583#define mmVM_DUMMY_PAGE_FAULT_ADDR 0x507 584#define mmVM_CONTEXT0_CNTL2 0x50c 585#define mmVM_CONTEXT1_CNTL2 0x50d 586#define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x50e 587#define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x50f 588#define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x510 589#define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x511 590#define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x512 591#define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x513 592#define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x514 593#define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x515 594#define mmVM_INVALIDATE_REQUEST 0x51e 595#define mmVM_INVALIDATE_RESPONSE 0x51f 596#define mmVM_PRT_APERTURE0_LOW_ADDR 0x52c 597#define mmVM_PRT_APERTURE1_LOW_ADDR 0x52d 598#define mmVM_PRT_APERTURE2_LOW_ADDR 0x52e 599#define mmVM_PRT_APERTURE3_LOW_ADDR 0x52f 600#define mmVM_PRT_APERTURE0_HIGH_ADDR 0x530 601#define mmVM_PRT_APERTURE1_HIGH_ADDR 0x531 602#define mmVM_PRT_APERTURE2_HIGH_ADDR 0x532 603#define mmVM_PRT_APERTURE3_HIGH_ADDR 0x533 604#define mmVM_PRT_CNTL 0x534 605#define mmVM_CONTEXTS_DISABLE 0x535 606#define mmVM_CONTEXT0_PROTECTION_FAULT_STATUS 0x536 607#define mmVM_CONTEXT1_PROTECTION_FAULT_STATUS 0x537 608#define mmVM_CONTEXT0_PROTECTION_FAULT_MCCLIENT 0x538 609#define mmVM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x539 610#define mmVM_CONTEXT0_PROTECTION_FAULT_ADDR 0x53e 611#define mmVM_CONTEXT1_PROTECTION_FAULT_ADDR 0x53f 612#define mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x546 613#define mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x547 614#define mmVM_FAULT_CLIENT_ID 0x54e 615#define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x54f 616#define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x550 617#define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x551 618#define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x552 619#define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x553 620#define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x554 621#define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x555 622#define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x556 623#define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR 0x557 624#define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR 0x558 625#define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR 0x55f 626#define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR 0x560 627#define mmVM_DEBUG 0x56f 628#define mmVM_L2_CG 0x570 629#define mmVM_L2_BANK_SELECT_MASKA 0x572 630#define mmVM_L2_BANK_SELECT_MASKB 0x573 631#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR 0x575 632#define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR 0x576 633#define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET 0x577 634#define mmMC_SEQ_CNTL 0xa25 635#define mmMC_SEQ_CNTL_2 0xad4 636#define mmMC_SEQ_DRAM 0xa26 637#define mmMC_SEQ_DRAM_2 0xa27 638#define mmMC_SEQ_RAS_TIMING 0xa28 639#define mmMC_SEQ_CAS_TIMING 0xa29 640#define mmMC_SEQ_MISC_TIMING 0xa2a 641#define mmMC_SEQ_MISC_TIMING2 0xa2b 642#define mmMC_SEQ_PMG_TIMING 0xa2c 643#define mmMC_SEQ_RD_CTL_D0 0xa2d 644#define mmMC_SEQ_RD_CTL_D1 0xa2e 645#define mmMC_SEQ_WR_CTL_D0 0xa2f 646#define mmMC_SEQ_WR_CTL_D1 0xa30 647#define mmMC_SEQ_WR_CTL_2 0xad5 648#define mmMC_SEQ_CMD 0xa31 649#define mmMC_PMG_CMD_EMRS 0xa83 650#define mmMC_PMG_CMD_MRS 0xaab 651#define mmMC_PMG_CMD_MRS1 0xad1 652#define mmMC_PMG_CMD_MRS2 0xad7 653#define mmMC_PMG_CFG 0xa84 654#define mmMC_PMG_AUTO_CMD 0xa34 655#define mmMC_PMG_AUTO_CFG 0xa35 656#define mmMC_IMP_CNTL 0xa36 657#define mmMC_IMP_DEBUG 0xa37 658#define mmMC_IMP_STATUS 0xa38 659#define mmMC_IMP_DQ_STATUS 0xabc 660#define mmMC_SEQ_WCDR_CTRL 0xa39 661#define mmMC_SEQ_TRAIN_WAKEUP_CNTL 0xa3a 662#define mmMC_SEQ_TRAIN_EDC_THRESHOLD 0xa3b 663#define mmMC_SEQ_TRAIN_EDC_THRESHOLD2 0xafe 664#define mmMC_SEQ_TRAIN_EDC_THRESHOLD3 0xaff 665#define mmMC_SEQ_TRAIN_WAKEUP_EDGE 0xa3c 666#define mmMC_SEQ_TRAIN_WAKEUP_MASK 0xa3d 667#define mmMC_SEQ_TRAIN_CAPTURE 0xa3e 668#define mmMC_SEQ_TRAIN_WAKEUP_CLEAR 0xa3f 669#define mmMC_SEQ_TRAIN_TIMING 0xa40 670#define mmMC_TRAIN_EDCCDR_R_D0 0xa41 671#define mmMC_TRAIN_EDCCDR_R_D1 0xa42 672#define mmMC_TRAIN_PRBSERR_0_D0 0xa43 673#define mmMC_TRAIN_PRBSERR_1_D0 0xa44 674#define mmMC_TRAIN_PRBSERR_2_D0 0xafb 675#define mmMC_TRAIN_EDC_STATUS_D0 0xa45 676#define mmMC_TRAIN_PRBSERR_0_D1 0xa46 677#define mmMC_TRAIN_PRBSERR_1_D1 0xa47 678#define mmMC_TRAIN_PRBSERR_2_D1 0xafc 679#define mmMC_TRAIN_EDC_STATUS_D1 0xa48 680#define mmMC_IO_TXCNTL_DPHY0_D0 0xa49 681#define mmMC_IO_TXCNTL_DPHY1_D0 0xa4a 682#define mmMC_IO_TXCNTL_APHY_D0 0xa4b 683#define mmMC_IO_RXCNTL_DPHY0_D0 0xa4c 684#define mmMC_IO_RXCNTL1_DPHY0_D0 0xadf 685#define mmMC_IO_RXCNTL_DPHY1_D0 0xa4d 686#define mmMC_IO_RXCNTL1_DPHY1_D0 0xae0 687#define mmMC_IO_DPHY_STR_CNTL_D0 0xa4e 688#define mmMC_IO_APHY_STR_CNTL_D0 0xa97 689#define mmMC_IO_TXCNTL_DPHY0_D1 0xa4f 690#define mmMC_IO_TXCNTL_DPHY1_D1 0xa50 691#define mmMC_IO_TXCNTL_APHY_D1 0xa51 692#define mmMC_IO_RXCNTL_DPHY0_D1 0xa52 693#define mmMC_IO_RXCNTL1_DPHY0_D1 0xae1 694#define mmMC_IO_RXCNTL_DPHY1_D1 0xa53 695#define mmMC_IO_RXCNTL1_DPHY1_D1 0xae2 696#define mmMC_IO_DPHY_STR_CNTL_D1 0xa54 697#define mmMC_IO_APHY_STR_CNTL_D1 0xa98 698#define mmMC_IO_CDRCNTL_D0 0xa55 699#define mmMC_IO_CDRCNTL1_D0 0xadd 700#define mmMC_IO_CDRCNTL2_D0 0xae4 701#define mmMC_IO_CDRCNTL_D1 0xa56 702#define mmMC_IO_CDRCNTL1_D1 0xade 703#define mmMC_IO_CDRCNTL2_D1 0xae5 704#define mmMC_SEQ_FIFO_CTL 0xa57 705#define mmMC_SEQ_TXFRAMING_BYTE0_D0 0xa58 706#define mmMC_SEQ_TXFRAMING_BYTE1_D0 0xa59 707#define mmMC_SEQ_TXFRAMING_BYTE2_D0 0xa5a 708#define mmMC_SEQ_TXFRAMING_BYTE3_D0 0xa5b 709#define mmMC_SEQ_TXFRAMING_DBI_D0 0xa5c 710#define mmMC_SEQ_TXFRAMING_EDC_D0 0xa5d 711#define mmMC_SEQ_TXFRAMING_FCK_D0 0xa5e 712#define mmMC_SEQ_TXFRAMING_BYTE0_D1 0xa60 713#define mmMC_SEQ_TXFRAMING_BYTE1_D1 0xa61 714#define mmMC_SEQ_TXFRAMING_BYTE2_D1 0xa62 715#define mmMC_SEQ_TXFRAMING_BYTE3_D1 0xa63 716#define mmMC_SEQ_TXFRAMING_DBI_D1 0xa64 717#define mmMC_SEQ_TXFRAMING_EDC_D1 0xa65 718#define mmMC_SEQ_TXFRAMING_FCK_D1 0xa66 719#define mmMC_SEQ_RXFRAMING_BYTE0_D0 0xa67 720#define mmMC_SEQ_RXFRAMING_BYTE1_D0 0xa68 721#define mmMC_SEQ_RXFRAMING_BYTE2_D0 0xa69 722#define mmMC_SEQ_RXFRAMING_BYTE3_D0 0xa6a 723#define mmMC_SEQ_RXFRAMING_DBI_D0 0xa6b 724#define mmMC_SEQ_RXFRAMING_EDC_D0 0xa6c 725#define mmMC_SEQ_RXFRAMING_BYTE0_D1 0xa6d 726#define mmMC_SEQ_RXFRAMING_BYTE1_D1 0xa6e 727#define mmMC_SEQ_RXFRAMING_BYTE2_D1 0xa6f 728#define mmMC_SEQ_RXFRAMING_BYTE3_D1 0xa70 729#define mmMC_SEQ_RXFRAMING_DBI_D1 0xa71 730#define mmMC_SEQ_RXFRAMING_EDC_D1 0xa72 731#define mmMC_IO_PAD_CNTL 0xa73 732#define mmMC_IO_PAD_CNTL_D0 0xa74 733#define mmMC_IO_PAD_CNTL_D1 0xa75 734#define mmMC_NPL_STATUS 0xa76 735#define mmMC_BIST_CMD_CNTL 0xa8e 736#define mmMC_BIST_CNTL 0xa05 737#define mmMC_BIST_AUTO_CNTL 0xa06 738#define mmMC_BIST_DIR_CNTL 0xa07 739#define mmMC_BIST_SADDR 0xa08 740#define mmMC_BIST_EADDR 0xa09 741#define mmMC_BIST_CMP_CNTL 0xa8d 742#define mmMC_BIST_CMP_CNTL_2 0xab6 743#define mmMC_BIST_DATA_WORD0 0xa0a 744#define mmMC_BIST_DATA_WORD1 0xa0b 745#define mmMC_BIST_DATA_WORD2 0xa0c 746#define mmMC_BIST_DATA_WORD3 0xa0d 747#define mmMC_BIST_DATA_WORD4 0xa0e 748#define mmMC_BIST_DATA_WORD5 0xa0f 749#define mmMC_BIST_DATA_WORD6 0xa10 750#define mmMC_BIST_DATA_WORD7 0xa11 751#define mmMC_BIST_DATA_MASK 0xa12 752#define mmMC_BIST_MISMATCH_ADDR 0xa13 753#define mmMC_BIST_RDATA_WORD0 0xa14 754#define mmMC_BIST_RDATA_WORD1 0xa15 755#define mmMC_BIST_RDATA_WORD2 0xa16 756#define mmMC_BIST_RDATA_WORD3 0xa17 757#define mmMC_BIST_RDATA_WORD4 0xa18 758#define mmMC_BIST_RDATA_WORD5 0xa19 759#define mmMC_BIST_RDATA_WORD6 0xa1a 760#define mmMC_BIST_RDATA_WORD7 0xa1b 761#define mmMC_BIST_RDATA_MASK 0xa1c 762#define mmMC_BIST_RDATA_EDC 0xa1d 763#define mmMC_SEQ_PERF_CNTL 0xa77 764#define mmMC_SEQ_PERF_CNTL_1 0xafd 765#define mmMC_SEQ_PERF_SEQ_CTL 0xa78 766#define mmMC_SEQ_PERF_SEQ_CNT_A_I0 0xa79 767#define mmMC_SEQ_PERF_SEQ_CNT_A_I1 0xa7a 768#define mmMC_SEQ_PERF_SEQ_CNT_B_I0 0xa7b 769#define mmMC_SEQ_PERF_SEQ_CNT_B_I1 0xa7c 770#define mmMC_SEQ_PERF_SEQ_CNT_C_I0 0xad9 771#define mmMC_SEQ_PERF_SEQ_CNT_C_I1 0xada 772#define mmMC_SEQ_PERF_SEQ_CNT_D_I0 0xadb 773#define mmMC_SEQ_PERF_SEQ_CNT_D_I1 0xadc 774#define mmMC_SEQ_STATUS_M 0xa7d 775#define mmMC_SEQ_STATUS_S 0xa20 776#define mmMC_CG_DATAPORT 0xa21 777#define mmMC_SEQ_VENDOR_ID_I0 0xa7e 778#define mmMC_SEQ_VENDOR_ID_I1 0xa7f 779#define mmMC_SEQ_MISC0 0xa80 780#define mmMC_SEQ_MISC1 0xa81 781#define mmMC_SEQ_RESERVE_0_S 0xa1e 782#define mmMC_SEQ_RESERVE_1_S 0xa1f 783#define mmMC_SEQ_RESERVE_M 0xa82 784#define mmMC_SEQ_IO_RESERVE_D0 0xab7 785#define mmMC_SEQ_IO_RESERVE_D1 0xab8 786#define mmMC_SEQ_SUP_CNTL 0xa32 787#define mmMC_SEQ_SUP_PGM 0xa33 788#define mmMC_SEQ_SUP_GP0_STAT 0xa8f 789#define mmMC_SEQ_SUP_GP1_STAT 0xa90 790#define mmMC_SEQ_SUP_GP2_STAT 0xa85 791#define mmMC_SEQ_SUP_GP3_STAT 0xa86 792#define mmMC_SEQ_SUP_IR_STAT 0xa87 793#define mmMC_SEQ_SUP_DEC_STAT 0xa88 794#define mmMC_SEQ_SUP_PGM_STAT 0xa89 795#define mmMC_SEQ_SUP_R_PGM 0xa8a 796#define mmMC_SEQ_MISC3 0xa8b 797#define mmMC_SEQ_MISC4 0xa8c 798#define mmMC_SEQ_MISC5 0xa95 799#define mmMC_SEQ_MISC6 0xa96 800#define mmMC_SEQ_MISC7 0xa99 801#define mmMC_SEQ_MISC8 0xa5f 802#define mmMC_SEQ_MISC9 0xae7 803#define mmMC_SEQ_CG 0xa9a 804#define mmMC_SEQ_BYTE_REMAP_D0 0xa93 805#define mmMC_SEQ_BYTE_REMAP_D1 0xa94 806#define mmMC_SEQ_BIT_REMAP_B0_D0 0xaa3 807#define mmMC_SEQ_BIT_REMAP_B1_D0 0xaa4 808#define mmMC_SEQ_BIT_REMAP_B2_D0 0xaa5 809#define mmMC_SEQ_BIT_REMAP_B3_D0 0xaa6 810#define mmMC_SEQ_BIT_REMAP_B0_D1 0xaa7 811#define mmMC_SEQ_BIT_REMAP_B1_D1 0xaa8 812#define mmMC_SEQ_BIT_REMAP_B2_D1 0xaa9 813#define mmMC_SEQ_BIT_REMAP_B3_D1 0xaaa 814#define mmMC_SEQ_RAS_TIMING_LP 0xa9b 815#define mmMC_SEQ_CAS_TIMING_LP 0xa9c 816#define mmMC_SEQ_MISC_TIMING_LP 0xa9d 817#define mmMC_SEQ_MISC_TIMING2_LP 0xa9e 818#define mmMC_SEQ_RD_CTL_D0_LP 0xac7 819#define mmMC_SEQ_RD_CTL_D1_LP 0xac8 820#define mmMC_SEQ_WR_CTL_D0_LP 0xa9f 821#define mmMC_SEQ_WR_CTL_D1_LP 0xaa0 822#define mmMC_SEQ_WR_CTL_2_LP 0xad6 823#define mmMC_SEQ_PMG_CMD_EMRS_LP 0xaa1 824#define mmMC_SEQ_PMG_CMD_MRS_LP 0xaa2 825#define mmMC_SEQ_PMG_CMD_MRS1_LP 0xad2 826#define mmMC_SEQ_PMG_CMD_MRS2_LP 0xad8 827#define mmMC_SEQ_PMG_TIMING_LP 0xad3 828#define mmMC_SEQ_IO_RWORD0 0xaac 829#define mmMC_SEQ_IO_RWORD1 0xaad 830#define mmMC_SEQ_IO_RWORD2 0xaae 831#define mmMC_SEQ_IO_RWORD3 0xaaf 832#define mmMC_SEQ_IO_RWORD4 0xab0 833#define mmMC_SEQ_IO_RWORD5 0xab1 834#define mmMC_SEQ_IO_RWORD6 0xab2 835#define mmMC_SEQ_IO_RWORD7 0xab3 836#define mmMC_SEQ_IO_RDBI 0xab4 837#define mmMC_SEQ_IO_REDC 0xab5 838#define mmMC_SEQ_TCG_CNTL 0xabd 839#define mmMC_SEQ_TSM_CTRL 0xabe 840#define mmMC_SEQ_TSM_GCNT 0xabf 841#define mmMC_SEQ_TSM_OCNT 0xac0 842#define mmMC_SEQ_TSM_NCNT 0xac1 843#define mmMC_SEQ_TSM_BCNT 0xac2 844#define mmMC_SEQ_TSM_FLAG 0xac3 845#define mmMC_SEQ_TSM_UPDATE 0xac4 846#define mmMC_SEQ_TSM_EDC 0xac5 847#define mmMC_SEQ_TSM_DBI 0xac6 848#define mmMC_SEQ_TSM_WCDR 0xae3 849#define mmMC_SEQ_TSM_MISC 0xae6 850#define mmMC_SEQ_TIMER_WR 0xac9 851#define mmMC_SEQ_TIMER_RD 0xaca 852#define mmMC_SEQ_DRAM_ERROR_INSERTION 0xacb 853#define mmMC_PHY_TIMING_D0 0xacc 854#define mmMC_PHY_TIMING_D1 0xacd 855#define mmMC_PHY_TIMING_2 0xace 856#define mmMC_SEQ_MPLL_OVERRIDE 0xa22 857#define mmMCLK_PWRMGT_CNTL 0xae8 858#define mmDLL_CNTL 0xae9 859#define mmMPLL_SEQ_UCODE_1 0xaea 860#define mmMPLL_SEQ_UCODE_2 0xaeb 861#define mmMPLL_CNTL_MODE 0xaec 862#define mmMPLL_FUNC_CNTL 0xaed 863#define mmMPLL_FUNC_CNTL_1 0xaee 864#define mmMPLL_FUNC_CNTL_2 0xaef 865#define mmMPLL_AD_FUNC_CNTL 0xaf0 866#define mmMPLL_DQ_FUNC_CNTL 0xaf1 867#define mmMPLL_TIME 0xaf2 868#define mmMPLL_SS1 0xaf3 869#define mmMPLL_SS2 0xaf4 870#define mmMPLL_CONTROL 0xaf5 871#define mmMPLL_AD_STATUS 0xaf6 872#define mmMPLL_DQ_0_0_STATUS 0xaf7 873#define mmMPLL_DQ_0_1_STATUS 0xaf8 874#define mmMPLL_DQ_1_0_STATUS 0xaf9 875#define mmMPLL_DQ_1_1_STATUS 0xafa 876#define mmMC_SEQ_PMG_PG_HWCNTL 0xab9 877#define mmMC_SEQ_PMG_PG_SWCNTL_0 0xaba 878#define mmMC_SEQ_PMG_PG_SWCNTL_1 0xabb 879#define mmMC_SEQ_TSM_DEBUG_INDEX 0xacf 880#define mmMC_SEQ_TSM_DEBUG_DATA 0xad0 881#define ixMC_TSM_DEBUG_GCNT 0x0 882#define ixMC_TSM_DEBUG_FLAG 0x1 883#define ixMC_TSM_DEBUG_MISC 0x2 884#define ixMC_TSM_DEBUG_BCNT0 0x3 885#define ixMC_TSM_DEBUG_BCNT1 0x4 886#define ixMC_TSM_DEBUG_BCNT2 0x5 887#define ixMC_TSM_DEBUG_BCNT3 0x6 888#define ixMC_TSM_DEBUG_BCNT4 0x7 889#define ixMC_TSM_DEBUG_BCNT5 0x8 890#define ixMC_TSM_DEBUG_BCNT6 0x9 891#define ixMC_TSM_DEBUG_BCNT7 0xa 892#define ixMC_TSM_DEBUG_BCNT8 0xb 893#define ixMC_TSM_DEBUG_BCNT9 0xc 894#define ixMC_TSM_DEBUG_BCNT10 0xd 895#define ixMC_TSM_DEBUG_ST01 0x10 896#define ixMC_TSM_DEBUG_ST23 0x11 897#define ixMC_TSM_DEBUG_ST45 0x12 898#define ixMC_TSM_DEBUG_BKPT 0x13 899#define mmMC_SEQ_IO_DEBUG_INDEX 0xa91 900#define mmMC_SEQ_IO_DEBUG_DATA 0xa92 901#define ixMC_IO_DEBUG_UP_0 0x0 902#define ixMC_IO_DEBUG_UP_1 0x1 903#define ixMC_IO_DEBUG_UP_2 0x2 904#define ixMC_IO_DEBUG_UP_3 0x3 905#define ixMC_IO_DEBUG_UP_4 0x4 906#define ixMC_IO_DEBUG_UP_5 0x5 907#define ixMC_IO_DEBUG_UP_6 0x6 908#define ixMC_IO_DEBUG_UP_7 0x7 909#define ixMC_IO_DEBUG_UP_8 0x8 910#define ixMC_IO_DEBUG_UP_9 0x9 911#define ixMC_IO_DEBUG_UP_10 0xa 912#define ixMC_IO_DEBUG_UP_11 0xb 913#define ixMC_IO_DEBUG_UP_12 0xc 914#define ixMC_IO_DEBUG_UP_13 0xd 915#define ixMC_IO_DEBUG_UP_14 0xe 916#define ixMC_IO_DEBUG_UP_15 0xf 917#define ixMC_IO_DEBUG_UP_16 0x10 918#define ixMC_IO_DEBUG_UP_17 0x11 919#define ixMC_IO_DEBUG_UP_18 0x12 920#define ixMC_IO_DEBUG_UP_19 0x13 921#define ixMC_IO_DEBUG_UP_20 0x14 922#define ixMC_IO_DEBUG_UP_21 0x15 923#define ixMC_IO_DEBUG_UP_22 0x16 924#define ixMC_IO_DEBUG_UP_23 0x17 925#define ixMC_IO_DEBUG_UP_24 0x18 926#define ixMC_IO_DEBUG_UP_25 0x19 927#define ixMC_IO_DEBUG_UP_26 0x1a 928#define ixMC_IO_DEBUG_UP_27 0x1b 929#define ixMC_IO_DEBUG_UP_28 0x1c 930#define ixMC_IO_DEBUG_UP_29 0x1d 931#define ixMC_IO_DEBUG_UP_30 0x1e 932#define ixMC_IO_DEBUG_UP_31 0x1f 933#define ixMC_IO_DEBUG_UP_32 0x20 934#define ixMC_IO_DEBUG_UP_33 0x21 935#define ixMC_IO_DEBUG_UP_34 0x22 936#define ixMC_IO_DEBUG_UP_35 0x23 937#define ixMC_IO_DEBUG_UP_36 0x24 938#define ixMC_IO_DEBUG_UP_37 0x25 939#define ixMC_IO_DEBUG_UP_38 0x26 940#define ixMC_IO_DEBUG_UP_39 0x27 941#define ixMC_IO_DEBUG_UP_40 0x28 942#define ixMC_IO_DEBUG_UP_41 0x29 943#define ixMC_IO_DEBUG_UP_42 0x2a 944#define ixMC_IO_DEBUG_UP_43 0x2b 945#define ixMC_IO_DEBUG_UP_44 0x2c 946#define ixMC_IO_DEBUG_UP_45 0x2d 947#define ixMC_IO_DEBUG_UP_46 0x2e 948#define ixMC_IO_DEBUG_UP_47 0x2f 949#define ixMC_IO_DEBUG_UP_48 0x30 950#define ixMC_IO_DEBUG_UP_49 0x31 951#define ixMC_IO_DEBUG_UP_50 0x32 952#define ixMC_IO_DEBUG_UP_51 0x33 953#define ixMC_IO_DEBUG_UP_52 0x34 954#define ixMC_IO_DEBUG_UP_53 0x35 955#define ixMC_IO_DEBUG_UP_54 0x36 956#define ixMC_IO_DEBUG_UP_55 0x37 957#define ixMC_IO_DEBUG_UP_56 0x38 958#define ixMC_IO_DEBUG_UP_57 0x39 959#define ixMC_IO_DEBUG_UP_58 0x3a 960#define ixMC_IO_DEBUG_UP_59 0x3b 961#define ixMC_IO_DEBUG_UP_60 0x3c 962#define ixMC_IO_DEBUG_UP_61 0x3d 963#define ixMC_IO_DEBUG_UP_62 0x3e 964#define ixMC_IO_DEBUG_UP_63 0x3f 965#define ixMC_IO_DEBUG_UP_64 0x40 966#define ixMC_IO_DEBUG_UP_65 0x41 967#define ixMC_IO_DEBUG_UP_66 0x42 968#define ixMC_IO_DEBUG_UP_67 0x43 969#define ixMC_IO_DEBUG_UP_68 0x44 970#define ixMC_IO_DEBUG_UP_69 0x45 971#define ixMC_IO_DEBUG_UP_70 0x46 972#define ixMC_IO_DEBUG_UP_71 0x47 973#define ixMC_IO_DEBUG_UP_72 0x48 974#define ixMC_IO_DEBUG_UP_73 0x49 975#define ixMC_IO_DEBUG_UP_74 0x4a 976#define ixMC_IO_DEBUG_UP_75 0x4b 977#define ixMC_IO_DEBUG_UP_76 0x4c 978#define ixMC_IO_DEBUG_UP_77 0x4d 979#define ixMC_IO_DEBUG_UP_78 0x4e 980#define ixMC_IO_DEBUG_UP_79 0x4f 981#define ixMC_IO_DEBUG_UP_80 0x50 982#define ixMC_IO_DEBUG_UP_81 0x51 983#define ixMC_IO_DEBUG_UP_82 0x52 984#define ixMC_IO_DEBUG_UP_83 0x53 985#define ixMC_IO_DEBUG_UP_84 0x54 986#define ixMC_IO_DEBUG_UP_85 0x55 987#define ixMC_IO_DEBUG_UP_86 0x56 988#define ixMC_IO_DEBUG_UP_87 0x57 989#define ixMC_IO_DEBUG_UP_88 0x58 990#define ixMC_IO_DEBUG_UP_89 0x59 991#define ixMC_IO_DEBUG_UP_90 0x5a 992#define ixMC_IO_DEBUG_UP_91 0x5b 993#define ixMC_IO_DEBUG_UP_92 0x5c 994#define ixMC_IO_DEBUG_UP_93 0x5d 995#define ixMC_IO_DEBUG_UP_94 0x5e 996#define ixMC_IO_DEBUG_UP_95 0x5f 997#define ixMC_IO_DEBUG_UP_96 0x60 998#define ixMC_IO_DEBUG_UP_97 0x61 999#define ixMC_IO_DEBUG_UP_98 0x62 1000#define ixMC_IO_DEBUG_UP_99 0x63 1001#define ixMC_IO_DEBUG_UP_100 0x64 1002#define ixMC_IO_DEBUG_UP_101 0x65 1003#define ixMC_IO_DEBUG_UP_102 0x66 1004#define ixMC_IO_DEBUG_UP_103 0x67 1005#define ixMC_IO_DEBUG_UP_104 0x68 1006#define ixMC_IO_DEBUG_UP_105 0x69 1007#define ixMC_IO_DEBUG_UP_106 0x6a 1008#define ixMC_IO_DEBUG_UP_107 0x6b 1009#define ixMC_IO_DEBUG_UP_108 0x6c 1010#define ixMC_IO_DEBUG_UP_109 0x6d 1011#define ixMC_IO_DEBUG_UP_110 0x6e 1012#define ixMC_IO_DEBUG_UP_111 0x6f 1013#define ixMC_IO_DEBUG_UP_112 0x70 1014#define ixMC_IO_DEBUG_UP_113 0x71 1015#define ixMC_IO_DEBUG_UP_114 0x72 1016#define ixMC_IO_DEBUG_UP_115 0x73 1017#define ixMC_IO_DEBUG_UP_116 0x74 1018#define ixMC_IO_DEBUG_UP_117 0x75 1019#define ixMC_IO_DEBUG_UP_118 0x76 1020#define ixMC_IO_DEBUG_UP_119 0x77 1021#define ixMC_IO_DEBUG_UP_120 0x78 1022#define ixMC_IO_DEBUG_UP_121 0x79 1023#define ixMC_IO_DEBUG_UP_122 0x7a 1024#define ixMC_IO_DEBUG_UP_123 0x7b 1025#define ixMC_IO_DEBUG_UP_124 0x7c 1026#define ixMC_IO_DEBUG_UP_125 0x7d 1027#define ixMC_IO_DEBUG_UP_126 0x7e 1028#define ixMC_IO_DEBUG_UP_127 0x7f 1029#define ixMC_IO_DEBUG_UP_128 0x80 1030#define ixMC_IO_DEBUG_UP_129 0x81 1031#define ixMC_IO_DEBUG_UP_130 0x82 1032#define ixMC_IO_DEBUG_UP_131 0x83 1033#define ixMC_IO_DEBUG_UP_132 0x84 1034#define ixMC_IO_DEBUG_UP_133 0x85 1035#define ixMC_IO_DEBUG_UP_134 0x86 1036#define ixMC_IO_DEBUG_UP_135 0x87 1037#define ixMC_IO_DEBUG_UP_136 0x88 1038#define ixMC_IO_DEBUG_UP_137 0x89 1039#define ixMC_IO_DEBUG_UP_138 0x8a 1040#define ixMC_IO_DEBUG_UP_139 0x8b 1041#define ixMC_IO_DEBUG_UP_140 0x8c 1042#define ixMC_IO_DEBUG_UP_141 0x8d 1043#define ixMC_IO_DEBUG_UP_142 0x8e 1044#define ixMC_IO_DEBUG_UP_143 0x8f 1045#define ixMC_IO_DEBUG_UP_144 0x90 1046#define ixMC_IO_DEBUG_UP_145 0x91 1047#define ixMC_IO_DEBUG_UP_146 0x92 1048#define ixMC_IO_DEBUG_UP_147 0x93 1049#define ixMC_IO_DEBUG_UP_148 0x94 1050#define ixMC_IO_DEBUG_UP_149 0x95 1051#define ixMC_IO_DEBUG_UP_150 0x96 1052#define ixMC_IO_DEBUG_UP_151 0x97 1053#define ixMC_IO_DEBUG_UP_152 0x98 1054#define ixMC_IO_DEBUG_UP_153 0x99 1055#define ixMC_IO_DEBUG_UP_154 0x9a 1056#define ixMC_IO_DEBUG_UP_155 0x9b 1057#define ixMC_IO_DEBUG_UP_156 0x9c 1058#define ixMC_IO_DEBUG_UP_157 0x9d 1059#define ixMC_IO_DEBUG_UP_158 0x9e 1060#define ixMC_IO_DEBUG_UP_159 0x9f 1061#define ixMC_IO_DEBUG_DQB0L_MISC_D0 0xa0 1062#define ixMC_IO_DEBUG_DQB0H_MISC_D0 0xa1 1063#define ixMC_IO_DEBUG_DQB1L_MISC_D0 0xa2 1064#define ixMC_IO_DEBUG_DQB1H_MISC_D0 0xa3 1065#define ixMC_IO_DEBUG_DQB2L_MISC_D0 0xa4 1066#define ixMC_IO_DEBUG_DQB2H_MISC_D0 0xa5 1067#define ixMC_IO_DEBUG_DQB3L_MISC_D0 0xa6 1068#define ixMC_IO_DEBUG_DQB3H_MISC_D0 0xa7 1069#define ixMC_IO_DEBUG_DBI_MISC_D0 0xa8 1070#define ixMC_IO_DEBUG_EDC_MISC_D0 0xa9 1071#define ixMC_IO_DEBUG_WCK_MISC_D0 0xaa 1072#define ixMC_IO_DEBUG_CK_MISC_D0 0xab 1073#define ixMC_IO_DEBUG_ADDRL_MISC_D0 0xac 1074#define ixMC_IO_DEBUG_ADDRH_MISC_D0 0xad 1075#define ixMC_IO_DEBUG_ACMD_MISC_D0 0xae 1076#define ixMC_IO_DEBUG_CMD_MISC_D0 0xaf 1077#define ixMC_IO_DEBUG_DQB0L_MISC_D1 0xb0 1078#define ixMC_IO_DEBUG_DQB0H_MISC_D1 0xb1 1079#define ixMC_IO_DEBUG_DQB1L_MISC_D1 0xb2 1080#define ixMC_IO_DEBUG_DQB1H_MISC_D1 0xb3 1081#define ixMC_IO_DEBUG_DQB2L_MISC_D1 0xb4 1082#define ixMC_IO_DEBUG_DQB2H_MISC_D1 0xb5 1083#define ixMC_IO_DEBUG_DQB3L_MISC_D1 0xb6 1084#define ixMC_IO_DEBUG_DQB3H_MISC_D1 0xb7 1085#define ixMC_IO_DEBUG_DBI_MISC_D1 0xb8 1086#define ixMC_IO_DEBUG_EDC_MISC_D1 0xb9 1087#define ixMC_IO_DEBUG_WCK_MISC_D1 0xba 1088#define ixMC_IO_DEBUG_CK_MISC_D1 0xbb 1089#define ixMC_IO_DEBUG_ADDRL_MISC_D1 0xbc 1090#define ixMC_IO_DEBUG_ADDRH_MISC_D1 0xbd 1091#define ixMC_IO_DEBUG_ACMD_MISC_D1 0xbe 1092#define ixMC_IO_DEBUG_CMD_MISC_D1 0xbf 1093#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D0 0xc0 1094#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D0 0xc1 1095#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D0 0xc2 1096#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D0 0xc3 1097#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D0 0xc4 1098#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D0 0xc5 1099#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D0 0xc6 1100#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D0 0xc7 1101#define ixMC_IO_DEBUG_DBI_CLKSEL_D0 0xc8 1102#define ixMC_IO_DEBUG_EDC_CLKSEL_D0 0xc9 1103#define ixMC_IO_DEBUG_WCK_CLKSEL_D0 0xca 1104#define ixMC_IO_DEBUG_CK_CLKSEL_D0 0xcb 1105#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D0 0xcc 1106#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D0 0xcd 1107#define ixMC_IO_DEBUG_ACMD_CLKSEL_D0 0xce 1108#define ixMC_IO_DEBUG_CMD_CLKSEL_D0 0xcf 1109#define ixMC_IO_DEBUG_DQB0L_CLKSEL_D1 0xd0 1110#define ixMC_IO_DEBUG_DQB0H_CLKSEL_D1 0xd1 1111#define ixMC_IO_DEBUG_DQB1L_CLKSEL_D1 0xd2 1112#define ixMC_IO_DEBUG_DQB1H_CLKSEL_D1 0xd3 1113#define ixMC_IO_DEBUG_DQB2L_CLKSEL_D1 0xd4 1114#define ixMC_IO_DEBUG_DQB2H_CLKSEL_D1 0xd5 1115#define ixMC_IO_DEBUG_DQB3L_CLKSEL_D1 0xd6 1116#define ixMC_IO_DEBUG_DQB3H_CLKSEL_D1 0xd7 1117#define ixMC_IO_DEBUG_DBI_CLKSEL_D1 0xd8 1118#define ixMC_IO_DEBUG_EDC_CLKSEL_D1 0xd9 1119#define ixMC_IO_DEBUG_WCK_CLKSEL_D1 0xda 1120#define ixMC_IO_DEBUG_CK_CLKSEL_D1 0xdb 1121#define ixMC_IO_DEBUG_ADDRL_CLKSEL_D1 0xdc 1122#define ixMC_IO_DEBUG_ADDRH_CLKSEL_D1 0xdd 1123#define ixMC_IO_DEBUG_ACMD_CLKSEL_D1 0xde 1124#define ixMC_IO_DEBUG_CMD_CLKSEL_D1 0xdf 1125#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D0 0xe0 1126#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D0 0xe1 1127#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D0 0xe2 1128#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D0 0xe3 1129#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D0 0xe4 1130#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D0 0xe5 1131#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D0 0xe6 1132#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D0 0xe7 1133#define ixMC_IO_DEBUG_DBI_OFSCAL_D0 0xe8 1134#define ixMC_IO_DEBUG_EDC_OFSCAL_D0 0xe9 1135#define ixMC_IO_DEBUG_WCK_OFSCAL_D0 0xea 1136#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D0 0xeb 1137#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D0 0xec 1138#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D0 0xed 1139#define ixMC_IO_DEBUG_ACMD_OFSCAL_D0 0xee 1140#define ixMC_IO_DEBUG_CMD_OFSCAL_D0 0xef 1141#define ixMC_IO_DEBUG_DQB0L_OFSCAL_D1 0xf0 1142#define ixMC_IO_DEBUG_DQB0H_OFSCAL_D1 0xf1 1143#define ixMC_IO_DEBUG_DQB1L_OFSCAL_D1 0xf2 1144#define ixMC_IO_DEBUG_DQB1H_OFSCAL_D1 0xf3 1145#define ixMC_IO_DEBUG_DQB2L_OFSCAL_D1 0xf4 1146#define ixMC_IO_DEBUG_DQB2H_OFSCAL_D1 0xf5 1147#define ixMC_IO_DEBUG_DQB3L_OFSCAL_D1 0xf6 1148#define ixMC_IO_DEBUG_DQB3H_OFSCAL_D1 0xf7 1149#define ixMC_IO_DEBUG_DBI_OFSCAL_D1 0xf8 1150#define ixMC_IO_DEBUG_EDC_OFSCAL_D1 0xf9 1151#define ixMC_IO_DEBUG_WCK_OFSCAL_D1 0xfa 1152#define ixMC_IO_DEBUG_EDC_RX_EQ_PM_D1 0xfb 1153#define ixMC_IO_DEBUG_EDC_RX_DYN_PM_D1 0xfc 1154#define ixMC_IO_DEBUG_EDC_CDR_PHSIZE_D1 0xfd 1155#define ixMC_IO_DEBUG_ACMD_OFSCAL_D1 0xfe 1156#define ixMC_IO_DEBUG_CMD_OFSCAL_D1 0xff 1157#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D0 0x100 1158#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D0 0x101 1159#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D0 0x102 1160#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D0 0x103 1161#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D0 0x104 1162#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D0 0x105 1163#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D0 0x106 1164#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D0 0x107 1165#define ixMC_IO_DEBUG_DBI_RXPHASE_D0 0x108 1166#define ixMC_IO_DEBUG_EDC_RXPHASE_D0 0x109 1167#define ixMC_IO_DEBUG_WCK_RXPHASE_D0 0x10a 1168#define ixMC_IO_DEBUG_CK_RXPHASE_D0 0x10b 1169#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D0 0x10c 1170#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D0 0x10d 1171#define ixMC_IO_DEBUG_ACMD_RXPHASE_D0 0x10e 1172#define ixMC_IO_DEBUG_CMD_RXPHASE_D0 0x10f 1173#define ixMC_IO_DEBUG_DQB0L_RXPHASE_D1 0x110 1174#define ixMC_IO_DEBUG_DQB0H_RXPHASE_D1 0x111 1175#define ixMC_IO_DEBUG_DQB1L_RXPHASE_D1 0x112 1176#define ixMC_IO_DEBUG_DQB1H_RXPHASE_D1 0x113 1177#define ixMC_IO_DEBUG_DQB2L_RXPHASE_D1 0x114 1178#define ixMC_IO_DEBUG_DQB2H_RXPHASE_D1 0x115 1179#define ixMC_IO_DEBUG_DQB3L_RXPHASE_D1 0x116 1180#define ixMC_IO_DEBUG_DQB3H_RXPHASE_D1 0x117 1181#define ixMC_IO_DEBUG_DBI_RXPHASE_D1 0x118 1182#define ixMC_IO_DEBUG_EDC_RXPHASE_D1 0x119 1183#define ixMC_IO_DEBUG_WCK_RXPHASE_D1 0x11a 1184#define ixMC_IO_DEBUG_CK_RXPHASE_D1 0x11b 1185#define ixMC_IO_DEBUG_ADDRL_RXPHASE_D1 0x11c 1186#define ixMC_IO_DEBUG_ADDRH_RXPHASE_D1 0x11d 1187#define ixMC_IO_DEBUG_ACMD_RXPHASE_D1 0x11e 1188#define ixMC_IO_DEBUG_CMD_RXPHASE_D1 0x11f 1189#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D0 0x120 1190#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D0 0x121 1191#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D0 0x122 1192#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D0 0x123 1193#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D0 0x124 1194#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D0 0x125 1195#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D0 0x126 1196#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D0 0x127 1197#define ixMC_IO_DEBUG_DBI_TXPHASE_D0 0x128 1198#define ixMC_IO_DEBUG_EDC_TXPHASE_D0 0x129 1199#define ixMC_IO_DEBUG_WCK_TXPHASE_D0 0x12a 1200#define ixMC_IO_DEBUG_CK_TXPHASE_D0 0x12b 1201#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D0 0x12c 1202#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D0 0x12d 1203#define ixMC_IO_DEBUG_ACMD_TXPHASE_D0 0x12e 1204#define ixMC_IO_DEBUG_CMD_TXPHASE_D0 0x12f 1205#define ixMC_IO_DEBUG_DQB0L_TXPHASE_D1 0x130 1206#define ixMC_IO_DEBUG_DQB0H_TXPHASE_D1 0x131 1207#define ixMC_IO_DEBUG_DQB1L_TXPHASE_D1 0x132 1208#define ixMC_IO_DEBUG_DQB1H_TXPHASE_D1 0x133 1209#define ixMC_IO_DEBUG_DQB2L_TXPHASE_D1 0x134 1210#define ixMC_IO_DEBUG_DQB2H_TXPHASE_D1 0x135 1211#define ixMC_IO_DEBUG_DQB3L_TXPHASE_D1 0x136 1212#define ixMC_IO_DEBUG_DQB3H_TXPHASE_D1 0x137 1213#define ixMC_IO_DEBUG_DBI_TXPHASE_D1 0x138 1214#define ixMC_IO_DEBUG_EDC_TXPHASE_D1 0x139 1215#define ixMC_IO_DEBUG_WCK_TXPHASE_D1 0x13a 1216#define ixMC_IO_DEBUG_CK_TXPHASE_D1 0x13b 1217#define ixMC_IO_DEBUG_ADDRL_TXPHASE_D1 0x13c 1218#define ixMC_IO_DEBUG_ADDRH_TXPHASE_D1 0x13d 1219#define ixMC_IO_DEBUG_ACMD_TXPHASE_D1 0x13e 1220#define ixMC_IO_DEBUG_CMD_TXPHASE_D1 0x13f 1221#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D0 0x140 1222#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D0 0x141 1223#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D0 0x142 1224#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D0 0x143 1225#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D0 0x144 1226#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D0 0x145 1227#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D0 0x146 1228#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D0 0x147 1229#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D0 0x148 1230#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D0 0x149 1231#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D0 0x14a 1232#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D0 0x14b 1233#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D0 0x14c 1234#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D0 0x14d 1235#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D0 0x14e 1236#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D0 0x14f 1237#define ixMC_IO_DEBUG_DQB0L_RX_VREF_CAL_D1 0x150 1238#define ixMC_IO_DEBUG_DQB0H_RX_VREF_CAL_D1 0x151 1239#define ixMC_IO_DEBUG_DQB1L_RX_VREF_CAL_D1 0x152 1240#define ixMC_IO_DEBUG_DQB1H_RX_VREF_CAL_D1 0x153 1241#define ixMC_IO_DEBUG_DQB2L_RX_VREF_CAL_D1 0x154 1242#define ixMC_IO_DEBUG_DQB2H_RX_VREF_CAL_D1 0x155 1243#define ixMC_IO_DEBUG_DQB3L_RX_VREF_CAL_D1 0x156 1244#define ixMC_IO_DEBUG_DQB3H_RX_VREF_CAL_D1 0x157 1245#define ixMC_IO_DEBUG_DBI_RX_VREF_CAL_D1 0x158 1246#define ixMC_IO_DEBUG_EDC_RX_VREF_CAL_D1 0x159 1247#define ixMC_IO_DEBUG_WCK_RX_VREF_CAL_D1 0x15a 1248#define ixMC_IO_DEBUG_DQB0_CDR_PHSIZE_D1 0x15b 1249#define ixMC_IO_DEBUG_DQB1_CDR_PHSIZE_D1 0x15c 1250#define ixMC_IO_DEBUG_DQB2_CDR_PHSIZE_D1 0x15d 1251#define ixMC_IO_DEBUG_DQB3_CDR_PHSIZE_D1 0x15e 1252#define ixMC_IO_DEBUG_DBI_CDR_PHSIZE_D1 0x15f 1253#define ixMC_IO_DEBUG_DQB0L_TXSLF_D0 0x160 1254#define ixMC_IO_DEBUG_DQB0H_TXSLF_D0 0x161 1255#define ixMC_IO_DEBUG_DQB1L_TXSLF_D0 0x162 1256#define ixMC_IO_DEBUG_DQB1H_TXSLF_D0 0x163 1257#define ixMC_IO_DEBUG_DQB2L_TXSLF_D0 0x164 1258#define ixMC_IO_DEBUG_DQB2H_TXSLF_D0 0x165 1259#define ixMC_IO_DEBUG_DQB3L_TXSLF_D0 0x166 1260#define ixMC_IO_DEBUG_DQB3H_TXSLF_D0 0x167 1261#define ixMC_IO_DEBUG_DBI_TXSLF_D0 0x168 1262#define ixMC_IO_DEBUG_EDC_TXSLF_D0 0x169 1263#define ixMC_IO_DEBUG_WCK_TXSLF_D0 0x16a 1264#define ixMC_IO_DEBUG_CK_TXSLF_D0 0x16b 1265#define ixMC_IO_DEBUG_ADDRL_TXSLF_D0 0x16c 1266#define ixMC_IO_DEBUG_ADDRH_TXSLF_D0 0x16d 1267#define ixMC_IO_DEBUG_ACMD_TXSLF_D0 0x16e 1268#define ixMC_IO_DEBUG_CMD_TXSLF_D0 0x16f 1269#define ixMC_IO_DEBUG_DQB0L_TXSLF_D1 0x170 1270#define ixMC_IO_DEBUG_DQB0H_TXSLF_D1 0x171 1271#define ixMC_IO_DEBUG_DQB1L_TXSLF_D1 0x172 1272#define ixMC_IO_DEBUG_DQB1H_TXSLF_D1 0x173 1273#define ixMC_IO_DEBUG_DQB2L_TXSLF_D1 0x174 1274#define ixMC_IO_DEBUG_DQB2H_TXSLF_D1 0x175 1275#define ixMC_IO_DEBUG_DQB3L_TXSLF_D1 0x176 1276#define ixMC_IO_DEBUG_DQB3H_TXSLF_D1 0x177 1277#define ixMC_IO_DEBUG_DBI_TXSLF_D1 0x178 1278#define ixMC_IO_DEBUG_EDC_TXSLF_D1 0x179 1279#define ixMC_IO_DEBUG_WCK_TXSLF_D1 0x17a 1280#define ixMC_IO_DEBUG_CK_TXSLF_D1 0x17b 1281#define ixMC_IO_DEBUG_ADDRL_TXSLF_D1 0x17c 1282#define ixMC_IO_DEBUG_ADDRH_TXSLF_D1 0x17d 1283#define ixMC_IO_DEBUG_ACMD_TXSLF_D1 0x17e 1284#define ixMC_IO_DEBUG_CMD_TXSLF_D1 0x17f 1285#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D0 0x180 1286#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D0 0x181 1287#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D0 0x182 1288#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D0 0x183 1289#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D0 0x184 1290#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D0 0x185 1291#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D0 0x186 1292#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D0 0x187 1293#define ixMC_IO_DEBUG_DBI_TXBST_PD_D0 0x188 1294#define ixMC_IO_DEBUG_EDC_TXBST_PD_D0 0x189 1295#define ixMC_IO_DEBUG_WCK_TXBST_PD_D0 0x18a 1296#define ixMC_IO_DEBUG_CK_TXBST_PD_D0 0x18b 1297#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D0 0x18c 1298#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D0 0x18d 1299#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D0 0x18e 1300#define ixMC_IO_DEBUG_CMD_TXBST_PD_D0 0x18f 1301#define ixMC_IO_DEBUG_DQB0L_TXBST_PD_D1 0x190 1302#define ixMC_IO_DEBUG_DQB0H_TXBST_PD_D1 0x191 1303#define ixMC_IO_DEBUG_DQB1L_TXBST_PD_D1 0x192 1304#define ixMC_IO_DEBUG_DQB1H_TXBST_PD_D1 0x193 1305#define ixMC_IO_DEBUG_DQB2L_TXBST_PD_D1 0x194 1306#define ixMC_IO_DEBUG_DQB2H_TXBST_PD_D1 0x195 1307#define ixMC_IO_DEBUG_DQB3L_TXBST_PD_D1 0x196 1308#define ixMC_IO_DEBUG_DQB3H_TXBST_PD_D1 0x197 1309#define ixMC_IO_DEBUG_DBI_TXBST_PD_D1 0x198 1310#define ixMC_IO_DEBUG_EDC_TXBST_PD_D1 0x199 1311#define ixMC_IO_DEBUG_WCK_TXBST_PD_D1 0x19a 1312#define ixMC_IO_DEBUG_CK_TXBST_PD_D1 0x19b 1313#define ixMC_IO_DEBUG_ADDRL_TXBST_PD_D1 0x19c 1314#define ixMC_IO_DEBUG_ADDRH_TXBST_PD_D1 0x19d 1315#define ixMC_IO_DEBUG_ACMD_TXBST_PD_D1 0x19e 1316#define ixMC_IO_DEBUG_CMD_TXBST_PD_D1 0x19f 1317#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D0 0x1a0 1318#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D0 0x1a1 1319#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D0 0x1a2 1320#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D0 0x1a3 1321#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D0 0x1a4 1322#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D0 0x1a5 1323#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D0 0x1a6 1324#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D0 0x1a7 1325#define ixMC_IO_DEBUG_DBI_TXBST_PU_D0 0x1a8 1326#define ixMC_IO_DEBUG_EDC_TXBST_PU_D0 0x1a9 1327#define ixMC_IO_DEBUG_WCK_TXBST_PU_D0 0x1aa 1328#define ixMC_IO_DEBUG_CK_TXBST_PU_D0 0x1ab 1329#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D0 0x1ac 1330#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D0 0x1ad 1331#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D0 0x1ae 1332#define ixMC_IO_DEBUG_CMD_TXBST_PU_D0 0x1af 1333#define ixMC_IO_DEBUG_DQB0L_TXBST_PU_D1 0x1b0 1334#define ixMC_IO_DEBUG_DQB0H_TXBST_PU_D1 0x1b1 1335#define ixMC_IO_DEBUG_DQB1L_TXBST_PU_D1 0x1b2 1336#define ixMC_IO_DEBUG_DQB1H_TXBST_PU_D1 0x1b3 1337#define ixMC_IO_DEBUG_DQB2L_TXBST_PU_D1 0x1b4 1338#define ixMC_IO_DEBUG_DQB2H_TXBST_PU_D1 0x1b5 1339#define ixMC_IO_DEBUG_DQB3L_TXBST_PU_D1 0x1b6 1340#define ixMC_IO_DEBUG_DQB3H_TXBST_PU_D1 0x1b7 1341#define ixMC_IO_DEBUG_DBI_TXBST_PU_D1 0x1b8 1342#define ixMC_IO_DEBUG_EDC_TXBST_PU_D1 0x1b9 1343#define ixMC_IO_DEBUG_WCK_TXBST_PU_D1 0x1ba 1344#define ixMC_IO_DEBUG_CK_TXBST_PU_D1 0x1bb 1345#define ixMC_IO_DEBUG_ADDRL_TXBST_PU_D1 0x1bc 1346#define ixMC_IO_DEBUG_ADDRH_TXBST_PU_D1 0x1bd 1347#define ixMC_IO_DEBUG_ACMD_TXBST_PU_D1 0x1be 1348#define ixMC_IO_DEBUG_CMD_TXBST_PU_D1 0x1bf 1349#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D0 0x1c0 1350#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D0 0x1c1 1351#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D0 0x1c2 1352#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D0 0x1c3 1353#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D0 0x1c4 1354#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D0 0x1c5 1355#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D0 0x1c6 1356#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D0 0x1c7 1357#define ixMC_IO_DEBUG_DBI_RX_EQ_D0 0x1c8 1358#define ixMC_IO_DEBUG_EDC_RX_EQ_D0 0x1c9 1359#define ixMC_IO_DEBUG_WCK_RX_EQ_D0 0x1ca 1360#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D0 0x1cb 1361#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D0 0x1cc 1362#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D0 0x1cd 1363#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D0 0x1ce 1364#define ixMC_IO_DEBUG_CMD_RX_EQ_D0 0x1cf 1365#define ixMC_IO_DEBUG_DQB0L_RX_EQ_D1 0x1d0 1366#define ixMC_IO_DEBUG_DQB0H_RX_EQ_D1 0x1d1 1367#define ixMC_IO_DEBUG_DQB1L_RX_EQ_D1 0x1d2 1368#define ixMC_IO_DEBUG_DQB1H_RX_EQ_D1 0x1d3 1369#define ixMC_IO_DEBUG_DQB2L_RX_EQ_D1 0x1d4 1370#define ixMC_IO_DEBUG_DQB2H_RX_EQ_D1 0x1d5 1371#define ixMC_IO_DEBUG_DQB3L_RX_EQ_D1 0x1d6 1372#define ixMC_IO_DEBUG_DQB3H_RX_EQ_D1 0x1d7 1373#define ixMC_IO_DEBUG_DBI_RX_EQ_D1 0x1d8 1374#define ixMC_IO_DEBUG_EDC_RX_EQ_D1 0x1d9 1375#define ixMC_IO_DEBUG_WCK_RX_EQ_D1 0x1da 1376#define ixMC_IO_DEBUG_DQ0_RX_EQ_PM_D1 0x1db 1377#define ixMC_IO_DEBUG_DQ1_RX_EQ_PM_D1 0x1dc 1378#define ixMC_IO_DEBUG_DQ0_RX_DYN_PM_D1 0x1dd 1379#define ixMC_IO_DEBUG_DQ1_RX_DYN_PM_D1 0x1de 1380#define ixMC_IO_DEBUG_CMD_RX_EQ_D1 0x1df 1381#define ixMC_IO_DEBUG_WCDR_MISC_D0 0x1e0 1382#define ixMC_IO_DEBUG_WCDR_CLKSEL_D0 0x1e1 1383#define ixMC_IO_DEBUG_WCDR_OFSCAL_D0 0x1e2 1384#define ixMC_IO_DEBUG_WCDR_RXPHASE_D0 0x1e3 1385#define ixMC_IO_DEBUG_WCDR_TXPHASE_D0 0x1e4 1386#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D0 0x1e5 1387#define ixMC_IO_DEBUG_WCDR_TXSLF_D0 0x1e6 1388#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D0 0x1e7 1389#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D0 0x1e8 1390#define ixMC_IO_DEBUG_WCDR_RX_EQ_D0 0x1e9 1391#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D0 0x1ea 1392#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D0 0x1eb 1393#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D0 0x1ec 1394#define ixMC_IO_DEBUG_WCDR_MISC_D1 0x1f0 1395#define ixMC_IO_DEBUG_WCDR_CLKSEL_D1 0x1f1 1396#define ixMC_IO_DEBUG_WCDR_OFSCAL_D1 0x1f2 1397#define ixMC_IO_DEBUG_WCDR_RXPHASE_D1 0x1f3 1398#define ixMC_IO_DEBUG_WCDR_TXPHASE_D1 0x1f4 1399#define ixMC_IO_DEBUG_WCDR_RX_VREF_CAL_D1 0x1f5 1400#define ixMC_IO_DEBUG_WCDR_TXSLF_D1 0x1f6 1401#define ixMC_IO_DEBUG_WCDR_TXBST_PD_D1 0x1f7 1402#define ixMC_IO_DEBUG_WCDR_TXBST_PU_D1 0x1f8 1403#define ixMC_IO_DEBUG_WCDR_RX_EQ_D1 0x1f9 1404#define ixMC_IO_DEBUG_WCDR_CDR_PHSIZE_D1 0x1fa 1405#define ixMC_IO_DEBUG_WCDR_RX_EQ_PM_D1 0x1fb 1406#define ixMC_IO_DEBUG_WCDR_RX_DYN_PM_D1 0x1fc 1407#define mmMC_SEQ_CNTL_3 0xd80 1408#define mmMC_SEQ_G5PDX_CTRL 0xd81 1409#define mmMC_SEQ_G5PDX_CTRL_LP 0xd82 1410#define mmMC_SEQ_G5PDX_CMD0 0xd83 1411#define mmMC_SEQ_G5PDX_CMD0_LP 0xd84 1412#define mmMC_SEQ_G5PDX_CMD1 0xd85 1413#define mmMC_SEQ_G5PDX_CMD1_LP 0xd86 1414#define mmMC_SEQ_SREG_READ 0xd87 1415#define mmMC_SEQ_SREG_STATUS 0xd88 1416#define mmMC_SEQ_PHYREG_BCAST 0xd89 1417#define mmMC_SEQ_PMG_DVS_CTL 0xd8a 1418#define mmMC_SEQ_PMG_DVS_CTL_LP 0xd8b 1419#define mmMC_SEQ_PMG_DVS_CMD 0xd8c 1420#define mmMC_SEQ_PMG_DVS_CMD_LP 0xd8d 1421#define mmMC_SEQ_DLL_STBY 0xd8e 1422#define mmMC_SEQ_DLL_STBY_LP 0xd8f 1423#define mmMC_DLB_MISCCTRL0 0xd90 1424#define mmMC_DLB_MISCCTRL1 0xd91 1425#define mmMC_DLB_MISCCTRL2 0xd92 1426#define mmMC_DLB_CONFIG0 0xd93 1427#define mmMC_DLB_CONFIG1 0xd94 1428#define mmMC_DLB_SETUP 0xd95 1429#define mmMC_DLB_SETUPSWEEP 0xd96 1430#define mmMC_DLB_SETUPFIFO 0xd97 1431#define mmMC_DLB_WRITE_MASK 0xd98 1432#define mmMC_DLB_STATUS 0xd99 1433#define mmMC_DLB_STATUS_MISC0 0xd9a 1434#define mmMC_DLB_STATUS_MISC1 0xd9b 1435#define mmMC_DLB_STATUS_MISC2 0xd9c 1436#define mmMC_DLB_STATUS_MISC3 0xd9d 1437#define mmMC_DLB_STATUS_MISC4 0xd9e 1438#define mmMC_DLB_STATUS_MISC5 0xd9f 1439#define mmMC_DLB_STATUS_MISC6 0xda0 1440#define mmMC_DLB_STATUS_MISC7 0xda1 1441#define mmMC_ARB_HARSH_EN_RD 0xdc0 1442#define mmMC_ARB_HARSH_EN_WR 0xdc1 1443#define mmMC_ARB_HARSH_TX_HI0_RD 0xdc2 1444#define mmMC_ARB_HARSH_TX_HI0_WR 0xdc3 1445#define mmMC_ARB_HARSH_TX_HI1_RD 0xdc4 1446#define mmMC_ARB_HARSH_TX_HI1_WR 0xdc5 1447#define mmMC_ARB_HARSH_TX_LO0_RD 0xdc6 1448#define mmMC_ARB_HARSH_TX_LO0_WR 0xdc7 1449#define mmMC_ARB_HARSH_TX_LO1_RD 0xdc8 1450#define mmMC_ARB_HARSH_TX_LO1_WR 0xdc9 1451#define mmMC_ARB_HARSH_BWPERIOD0_RD 0xdca 1452#define mmMC_ARB_HARSH_BWPERIOD0_WR 0xdcb 1453#define mmMC_ARB_HARSH_BWPERIOD1_RD 0xdcc 1454#define mmMC_ARB_HARSH_BWPERIOD1_WR 0xdcd 1455#define mmMC_ARB_HARSH_BWCNT0_RD 0xdce 1456#define mmMC_ARB_HARSH_BWCNT0_WR 0xdcf 1457#define mmMC_ARB_HARSH_BWCNT1_RD 0xdd0 1458#define mmMC_ARB_HARSH_BWCNT1_WR 0xdd1 1459#define mmMC_ARB_HARSH_SAT0_RD 0xdd2 1460#define mmMC_ARB_HARSH_SAT0_WR 0xdd3 1461#define mmMC_ARB_HARSH_SAT1_RD 0xdd4 1462#define mmMC_ARB_HARSH_SAT1_WR 0xdd5 1463#define mmMC_ARB_HARSH_CTL_RD 0xdd6 1464#define mmMC_ARB_HARSH_CTL_WR 0xdd7 1465 1466#endif /* GMC_7_1_D_H */ 1467