gfx_7_2_d.h revision 1.1
1/* $NetBSD: gfx_7_2_d.h,v 1.1 2018/08/27 01:34:50 riastradh Exp $ */ 2 3/* 4 * GFX_7_2 Register documentation 5 * 6 * Copyright (C) 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included 16 * in all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26#ifndef GFX_7_2_D_H 27#define GFX_7_2_D_H 28 29#define mmCB_BLEND_RED 0xa105 30#define mmCB_BLEND_GREEN 0xa106 31#define mmCB_BLEND_BLUE 0xa107 32#define mmCB_BLEND_ALPHA 0xa108 33#define mmCB_COLOR_CONTROL 0xa202 34#define mmCB_BLEND0_CONTROL 0xa1e0 35#define mmCB_BLEND1_CONTROL 0xa1e1 36#define mmCB_BLEND2_CONTROL 0xa1e2 37#define mmCB_BLEND3_CONTROL 0xa1e3 38#define mmCB_BLEND4_CONTROL 0xa1e4 39#define mmCB_BLEND5_CONTROL 0xa1e5 40#define mmCB_BLEND6_CONTROL 0xa1e6 41#define mmCB_BLEND7_CONTROL 0xa1e7 42#define mmCB_COLOR0_BASE 0xa318 43#define mmCB_COLOR1_BASE 0xa327 44#define mmCB_COLOR2_BASE 0xa336 45#define mmCB_COLOR3_BASE 0xa345 46#define mmCB_COLOR4_BASE 0xa354 47#define mmCB_COLOR5_BASE 0xa363 48#define mmCB_COLOR6_BASE 0xa372 49#define mmCB_COLOR7_BASE 0xa381 50#define mmCB_COLOR0_PITCH 0xa319 51#define mmCB_COLOR1_PITCH 0xa328 52#define mmCB_COLOR2_PITCH 0xa337 53#define mmCB_COLOR3_PITCH 0xa346 54#define mmCB_COLOR4_PITCH 0xa355 55#define mmCB_COLOR5_PITCH 0xa364 56#define mmCB_COLOR6_PITCH 0xa373 57#define mmCB_COLOR7_PITCH 0xa382 58#define mmCB_COLOR0_SLICE 0xa31a 59#define mmCB_COLOR1_SLICE 0xa329 60#define mmCB_COLOR2_SLICE 0xa338 61#define mmCB_COLOR3_SLICE 0xa347 62#define mmCB_COLOR4_SLICE 0xa356 63#define mmCB_COLOR5_SLICE 0xa365 64#define mmCB_COLOR6_SLICE 0xa374 65#define mmCB_COLOR7_SLICE 0xa383 66#define mmCB_COLOR0_VIEW 0xa31b 67#define mmCB_COLOR1_VIEW 0xa32a 68#define mmCB_COLOR2_VIEW 0xa339 69#define mmCB_COLOR3_VIEW 0xa348 70#define mmCB_COLOR4_VIEW 0xa357 71#define mmCB_COLOR5_VIEW 0xa366 72#define mmCB_COLOR6_VIEW 0xa375 73#define mmCB_COLOR7_VIEW 0xa384 74#define mmCB_COLOR0_INFO 0xa31c 75#define mmCB_COLOR1_INFO 0xa32b 76#define mmCB_COLOR2_INFO 0xa33a 77#define mmCB_COLOR3_INFO 0xa349 78#define mmCB_COLOR4_INFO 0xa358 79#define mmCB_COLOR5_INFO 0xa367 80#define mmCB_COLOR6_INFO 0xa376 81#define mmCB_COLOR7_INFO 0xa385 82#define mmCB_COLOR0_ATTRIB 0xa31d 83#define mmCB_COLOR1_ATTRIB 0xa32c 84#define mmCB_COLOR2_ATTRIB 0xa33b 85#define mmCB_COLOR3_ATTRIB 0xa34a 86#define mmCB_COLOR4_ATTRIB 0xa359 87#define mmCB_COLOR5_ATTRIB 0xa368 88#define mmCB_COLOR6_ATTRIB 0xa377 89#define mmCB_COLOR7_ATTRIB 0xa386 90#define mmCB_COLOR0_CMASK 0xa31f 91#define mmCB_COLOR1_CMASK 0xa32e 92#define mmCB_COLOR2_CMASK 0xa33d 93#define mmCB_COLOR3_CMASK 0xa34c 94#define mmCB_COLOR4_CMASK 0xa35b 95#define mmCB_COLOR5_CMASK 0xa36a 96#define mmCB_COLOR6_CMASK 0xa379 97#define mmCB_COLOR7_CMASK 0xa388 98#define mmCB_COLOR0_CMASK_SLICE 0xa320 99#define mmCB_COLOR1_CMASK_SLICE 0xa32f 100#define mmCB_COLOR2_CMASK_SLICE 0xa33e 101#define mmCB_COLOR3_CMASK_SLICE 0xa34d 102#define mmCB_COLOR4_CMASK_SLICE 0xa35c 103#define mmCB_COLOR5_CMASK_SLICE 0xa36b 104#define mmCB_COLOR6_CMASK_SLICE 0xa37a 105#define mmCB_COLOR7_CMASK_SLICE 0xa389 106#define mmCB_COLOR0_FMASK 0xa321 107#define mmCB_COLOR1_FMASK 0xa330 108#define mmCB_COLOR2_FMASK 0xa33f 109#define mmCB_COLOR3_FMASK 0xa34e 110#define mmCB_COLOR4_FMASK 0xa35d 111#define mmCB_COLOR5_FMASK 0xa36c 112#define mmCB_COLOR6_FMASK 0xa37b 113#define mmCB_COLOR7_FMASK 0xa38a 114#define mmCB_COLOR0_FMASK_SLICE 0xa322 115#define mmCB_COLOR1_FMASK_SLICE 0xa331 116#define mmCB_COLOR2_FMASK_SLICE 0xa340 117#define mmCB_COLOR3_FMASK_SLICE 0xa34f 118#define mmCB_COLOR4_FMASK_SLICE 0xa35e 119#define mmCB_COLOR5_FMASK_SLICE 0xa36d 120#define mmCB_COLOR6_FMASK_SLICE 0xa37c 121#define mmCB_COLOR7_FMASK_SLICE 0xa38b 122#define mmCB_COLOR0_CLEAR_WORD0 0xa323 123#define mmCB_COLOR1_CLEAR_WORD0 0xa332 124#define mmCB_COLOR2_CLEAR_WORD0 0xa341 125#define mmCB_COLOR3_CLEAR_WORD0 0xa350 126#define mmCB_COLOR4_CLEAR_WORD0 0xa35f 127#define mmCB_COLOR5_CLEAR_WORD0 0xa36e 128#define mmCB_COLOR6_CLEAR_WORD0 0xa37d 129#define mmCB_COLOR7_CLEAR_WORD0 0xa38c 130#define mmCB_COLOR0_CLEAR_WORD1 0xa324 131#define mmCB_COLOR1_CLEAR_WORD1 0xa333 132#define mmCB_COLOR2_CLEAR_WORD1 0xa342 133#define mmCB_COLOR3_CLEAR_WORD1 0xa351 134#define mmCB_COLOR4_CLEAR_WORD1 0xa360 135#define mmCB_COLOR5_CLEAR_WORD1 0xa36f 136#define mmCB_COLOR6_CLEAR_WORD1 0xa37e 137#define mmCB_COLOR7_CLEAR_WORD1 0xa38d 138#define mmCB_TARGET_MASK 0xa08e 139#define mmCB_SHADER_MASK 0xa08f 140#define mmCB_HW_CONTROL 0x2684 141#define mmCB_HW_CONTROL_1 0x2685 142#define mmCB_HW_CONTROL_2 0x2686 143#define mmCB_HW_CONTROL_3 0x2683 144#define mmCB_PERFCOUNTER_FILTER 0xdc00 145#define mmCB_PERFCOUNTER0_SELECT 0xdc01 146#define mmCB_PERFCOUNTER0_SELECT1 0xdc02 147#define mmCB_PERFCOUNTER1_SELECT 0xdc03 148#define mmCB_PERFCOUNTER2_SELECT 0xdc04 149#define mmCB_PERFCOUNTER3_SELECT 0xdc05 150#define mmCB_PERFCOUNTER0_LO 0xd406 151#define mmCB_PERFCOUNTER1_LO 0xd408 152#define mmCB_PERFCOUNTER2_LO 0xd40a 153#define mmCB_PERFCOUNTER3_LO 0xd40c 154#define mmCB_PERFCOUNTER0_HI 0xd407 155#define mmCB_PERFCOUNTER1_HI 0xd409 156#define mmCB_PERFCOUNTER2_HI 0xd40b 157#define mmCB_PERFCOUNTER3_HI 0xd40d 158#define mmCB_CGTT_SCLK_CTRL 0xf0a8 159#define mmCB_DEBUG_BUS_1 0x2699 160#define mmCB_DEBUG_BUS_2 0x269a 161#define mmCB_DEBUG_BUS_3 0x269b 162#define mmCB_DEBUG_BUS_4 0x269c 163#define mmCB_DEBUG_BUS_5 0x269d 164#define mmCB_DEBUG_BUS_6 0x269e 165#define mmCB_DEBUG_BUS_7 0x269f 166#define mmCB_DEBUG_BUS_8 0x26a0 167#define mmCB_DEBUG_BUS_9 0x26a1 168#define mmCB_DEBUG_BUS_10 0x26a2 169#define mmCB_DEBUG_BUS_11 0x26a3 170#define mmCB_DEBUG_BUS_12 0x26a4 171#define mmCB_DEBUG_BUS_13 0x26a5 172#define mmCB_DEBUG_BUS_14 0x26a6 173#define mmCB_DEBUG_BUS_15 0x26a7 174#define mmCB_DEBUG_BUS_16 0x26a8 175#define mmCB_DEBUG_BUS_17 0x26a9 176#define mmCB_DEBUG_BUS_18 0x26aa 177#define mmCP_DFY_CNTL 0x3020 178#define mmCP_DFY_STAT 0x3021 179#define mmCP_DFY_ADDR_HI 0x3022 180#define mmCP_DFY_ADDR_LO 0x3023 181#define mmCP_DFY_DATA_0 0x3024 182#define mmCP_DFY_DATA_1 0x3025 183#define mmCP_DFY_DATA_2 0x3026 184#define mmCP_DFY_DATA_3 0x3027 185#define mmCP_DFY_DATA_4 0x3028 186#define mmCP_DFY_DATA_5 0x3029 187#define mmCP_DFY_DATA_6 0x302a 188#define mmCP_DFY_DATA_7 0x302b 189#define mmCP_DFY_DATA_8 0x302c 190#define mmCP_DFY_DATA_9 0x302d 191#define mmCP_DFY_DATA_10 0x302e 192#define mmCP_DFY_DATA_11 0x302f 193#define mmCP_DFY_DATA_12 0x3030 194#define mmCP_DFY_DATA_13 0x3031 195#define mmCP_DFY_DATA_14 0x3032 196#define mmCP_DFY_DATA_15 0x3033 197#define mmCP_RB0_BASE 0x3040 198#define mmCP_RB0_BASE_HI 0x30b1 199#define mmCP_RB_BASE 0x3040 200#define mmCP_RB1_BASE 0x3060 201#define mmCP_RB1_BASE_HI 0x30b2 202#define mmCP_RB2_BASE 0x3065 203#define mmCP_RB0_CNTL 0x3041 204#define mmCP_RB_CNTL 0x3041 205#define mmCP_RB1_CNTL 0x3061 206#define mmCP_RB2_CNTL 0x3066 207#define mmCP_RB_RPTR_WR 0x3042 208#define mmCP_RB0_RPTR_ADDR 0x3043 209#define mmCP_RB_RPTR_ADDR 0x3043 210#define mmCP_RB1_RPTR_ADDR 0x3062 211#define mmCP_RB2_RPTR_ADDR 0x3067 212#define mmCP_RB0_RPTR_ADDR_HI 0x3044 213#define mmCP_RB_RPTR_ADDR_HI 0x3044 214#define mmCP_RB1_RPTR_ADDR_HI 0x3063 215#define mmCP_RB2_RPTR_ADDR_HI 0x3068 216#define mmCP_RB0_WPTR 0x3045 217#define mmCP_RB_WPTR 0x3045 218#define mmCP_RB1_WPTR 0x3064 219#define mmCP_RB2_WPTR 0x3069 220#define mmCP_RB_WPTR_POLL_ADDR_LO 0x3046 221#define mmCP_RB_WPTR_POLL_ADDR_HI 0x3047 222#define mmGC_PRIV_MODE 0x3048 223#define mmCP_INT_CNTL 0x3049 224#define mmCP_INT_CNTL_RING0 0x306a 225#define mmCP_INT_CNTL_RING1 0x306b 226#define mmCP_INT_CNTL_RING2 0x306c 227#define mmCP_INT_STATUS 0x304a 228#define mmCP_INT_STATUS_RING0 0x306d 229#define mmCP_INT_STATUS_RING1 0x306e 230#define mmCP_INT_STATUS_RING2 0x306f 231#define mmCP_DEVICE_ID 0x304b 232#define mmCP_RING_PRIORITY_CNTS 0x304c 233#define mmCP_ME0_PIPE_PRIORITY_CNTS 0x304c 234#define mmCP_RING0_PRIORITY 0x304d 235#define mmCP_ME0_PIPE0_PRIORITY 0x304d 236#define mmCP_RING1_PRIORITY 0x304e 237#define mmCP_ME0_PIPE1_PRIORITY 0x304e 238#define mmCP_RING2_PRIORITY 0x304f 239#define mmCP_ME0_PIPE2_PRIORITY 0x304f 240#define mmCP_ENDIAN_SWAP 0x3050 241#define mmCP_RB_VMID 0x3051 242#define mmCP_ME0_PIPE0_VMID 0x3052 243#define mmCP_ME0_PIPE1_VMID 0x3053 244#define mmCP_PFP_UCODE_ADDR 0x3054 245#define mmCP_PFP_UCODE_DATA 0x3055 246#define mmCP_ME_RAM_RADDR 0x3056 247#define mmCP_ME_RAM_WADDR 0x3057 248#define mmCP_ME_RAM_DATA 0x3058 249#define mmCGTT_CPC_CLK_CTRL 0xf0b2 250#define mmCGTT_CPF_CLK_CTRL 0xf0b1 251#define mmCGTT_CP_CLK_CTRL 0xf0b0 252#define mmCP_CE_UCODE_ADDR 0x305a 253#define mmCP_CE_UCODE_DATA 0x305b 254#define mmCP_MEC_ME1_UCODE_ADDR 0x305c 255#define mmCP_MEC_ME1_UCODE_DATA 0x305d 256#define mmCP_MEC_ME2_UCODE_ADDR 0x305e 257#define mmCP_MEC_ME2_UCODE_DATA 0x305f 258#define mmCP_PWR_CNTL 0x3078 259#define mmCP_MEM_SLP_CNTL 0x3079 260#define mmCP_ECC_FIRSTOCCURRENCE 0x307a 261#define mmCP_ECC_FIRSTOCCURRENCE_RING0 0x307b 262#define mmCP_ECC_FIRSTOCCURRENCE_RING1 0x307c 263#define mmCP_ECC_FIRSTOCCURRENCE_RING2 0x307d 264#define mmCP_CPF_DEBUG 0x3080 265#define mmCP_FETCHER_SOURCE 0x3082 266#define mmCP_PQ_WPTR_POLL_CNTL 0x3083 267#define mmCP_PQ_WPTR_POLL_CNTL1 0x3084 268#define mmCPC_INT_CNTL 0x30b4 269#define mmCP_ME1_PIPE0_INT_CNTL 0x3085 270#define mmCP_ME1_PIPE1_INT_CNTL 0x3086 271#define mmCP_ME1_PIPE2_INT_CNTL 0x3087 272#define mmCP_ME1_PIPE3_INT_CNTL 0x3088 273#define mmCP_ME2_PIPE0_INT_CNTL 0x3089 274#define mmCP_ME2_PIPE1_INT_CNTL 0x308a 275#define mmCP_ME2_PIPE2_INT_CNTL 0x308b 276#define mmCP_ME2_PIPE3_INT_CNTL 0x308c 277#define mmCPC_INT_STATUS 0x30b5 278#define mmCP_ME1_PIPE0_INT_STATUS 0x308d 279#define mmCP_ME1_PIPE1_INT_STATUS 0x308e 280#define mmCP_ME1_PIPE2_INT_STATUS 0x308f 281#define mmCP_ME1_PIPE3_INT_STATUS 0x3090 282#define mmCP_ME2_PIPE0_INT_STATUS 0x3091 283#define mmCP_ME2_PIPE1_INT_STATUS 0x3092 284#define mmCP_ME2_PIPE2_INT_STATUS 0x3093 285#define mmCP_ME2_PIPE3_INT_STATUS 0x3094 286#define mmCP_ME1_INT_STAT_DEBUG 0x3095 287#define mmCP_ME2_INT_STAT_DEBUG 0x3096 288#define mmCP_ME1_PIPE_PRIORITY_CNTS 0x3099 289#define mmCP_ME1_PIPE0_PRIORITY 0x309a 290#define mmCP_ME1_PIPE1_PRIORITY 0x309b 291#define mmCP_ME1_PIPE2_PRIORITY 0x309c 292#define mmCP_ME1_PIPE3_PRIORITY 0x309d 293#define mmCP_ME2_PIPE_PRIORITY_CNTS 0x309e 294#define mmCP_ME2_PIPE0_PRIORITY 0x309f 295#define mmCP_ME2_PIPE1_PRIORITY 0x30a0 296#define mmCP_ME2_PIPE2_PRIORITY 0x30a1 297#define mmCP_ME2_PIPE3_PRIORITY 0x30a2 298#define mmCP_CE_PRGRM_CNTR_START 0x30a3 299#define mmCP_PFP_PRGRM_CNTR_START 0x30a4 300#define mmCP_ME_PRGRM_CNTR_START 0x30a5 301#define mmCP_MEC1_PRGRM_CNTR_START 0x30a6 302#define mmCP_MEC2_PRGRM_CNTR_START 0x30a7 303#define mmCP_CE_INTR_ROUTINE_START 0x30a8 304#define mmCP_PFP_INTR_ROUTINE_START 0x30a9 305#define mmCP_ME_INTR_ROUTINE_START 0x30aa 306#define mmCP_MEC1_INTR_ROUTINE_START 0x30ab 307#define mmCP_MEC2_INTR_ROUTINE_START 0x30ac 308#define mmCP_CONTEXT_CNTL 0x30ad 309#define mmCP_MAX_CONTEXT 0x30ae 310#define mmCP_IQ_WAIT_TIME1 0x30af 311#define mmCP_IQ_WAIT_TIME2 0x30b0 312#define mmCP_VMID_RESET 0x30b3 313#define mmCP_VMID_PREEMPT 0x30b6 314#define mmCPC_INT_CNTX_ID 0x30b7 315#define mmCP_PQ_STATUS 0x30b8 316#define mmCP_CPC_STATUS 0x2084 317#define mmCP_CPC_BUSY_STAT 0x2085 318#define mmCP_CPC_STALLED_STAT1 0x2086 319#define mmCP_CPF_STATUS 0x2087 320#define mmCP_CPF_BUSY_STAT 0x2088 321#define mmCP_CPF_STALLED_STAT1 0x2089 322#define mmCP_CPC_MC_CNTL 0x208a 323#define mmCP_CPC_GRBM_FREE_COUNT 0x208b 324#define mmCP_MEC_CNTL 0x208d 325#define mmCP_MEC_ME1_HEADER_DUMP 0x208e 326#define mmCP_MEC_ME2_HEADER_DUMP 0x208f 327#define mmCP_CPC_SCRATCH_INDEX 0x2090 328#define mmCP_CPC_SCRATCH_DATA 0x2091 329#define mmCPG_PERFCOUNTER1_SELECT 0xd800 330#define mmCPG_PERFCOUNTER1_LO 0xd000 331#define mmCPG_PERFCOUNTER1_HI 0xd001 332#define mmCPG_PERFCOUNTER0_SELECT1 0xd801 333#define mmCPG_PERFCOUNTER0_SELECT 0xd802 334#define mmCPG_PERFCOUNTER0_LO 0xd002 335#define mmCPG_PERFCOUNTER0_HI 0xd003 336#define mmCPC_PERFCOUNTER1_SELECT 0xd803 337#define mmCPC_PERFCOUNTER1_LO 0xd004 338#define mmCPC_PERFCOUNTER1_HI 0xd005 339#define mmCPC_PERFCOUNTER0_SELECT1 0xd804 340#define mmCPC_PERFCOUNTER0_SELECT 0xd809 341#define mmCPC_PERFCOUNTER0_LO 0xd006 342#define mmCPC_PERFCOUNTER0_HI 0xd007 343#define mmCPF_PERFCOUNTER1_SELECT 0xd805 344#define mmCPF_PERFCOUNTER1_LO 0xd008 345#define mmCPF_PERFCOUNTER1_HI 0xd009 346#define mmCPF_PERFCOUNTER0_SELECT1 0xd806 347#define mmCPF_PERFCOUNTER0_SELECT 0xd807 348#define mmCPF_PERFCOUNTER0_LO 0xd00a 349#define mmCPF_PERFCOUNTER0_HI 0xd00b 350#define mmCP_CPC_HALT_HYST_COUNT 0x20a7 351#define mmCP_DRAW_OBJECT 0xd810 352#define mmCP_DRAW_OBJECT_COUNTER 0xd811 353#define mmCP_DRAW_WINDOW_MASK_HI 0xd812 354#define mmCP_DRAW_WINDOW_HI 0xd813 355#define mmCP_DRAW_WINDOW_LO 0xd814 356#define mmCP_DRAW_WINDOW_CNTL 0xd815 357#define mmCP_PRT_LOD_STATS_CNTL0 0x20ad 358#define mmCP_PRT_LOD_STATS_CNTL1 0x20ae 359#define mmCP_PRT_LOD_STATS_CNTL2 0x20af 360#define mmCP_CE_COMPARE_COUNT 0x20c0 361#define mmCP_CE_DE_COUNT 0x20c1 362#define mmCP_DE_CE_COUNT 0x20c2 363#define mmCP_DE_LAST_INVAL_COUNT 0x20c3 364#define mmCP_DE_DE_COUNT 0x20c4 365#define mmCP_EOP_DONE_EVENT_CNTL 0xc0d5 366#define mmCP_EOP_DONE_DATA_CNTL 0xc0d6 367#define mmCP_EOP_DONE_ADDR_LO 0xc000 368#define mmCP_EOP_DONE_ADDR_HI 0xc001 369#define mmCP_EOP_DONE_DATA_LO 0xc002 370#define mmCP_EOP_DONE_DATA_HI 0xc003 371#define mmCP_EOP_LAST_FENCE_LO 0xc004 372#define mmCP_EOP_LAST_FENCE_HI 0xc005 373#define mmCP_STREAM_OUT_ADDR_LO 0xc006 374#define mmCP_STREAM_OUT_ADDR_HI 0xc007 375#define mmCP_NUM_PRIM_WRITTEN_COUNT0_LO 0xc008 376#define mmCP_NUM_PRIM_WRITTEN_COUNT0_HI 0xc009 377#define mmCP_NUM_PRIM_NEEDED_COUNT0_LO 0xc00a 378#define mmCP_NUM_PRIM_NEEDED_COUNT0_HI 0xc00b 379#define mmCP_NUM_PRIM_WRITTEN_COUNT1_LO 0xc00c 380#define mmCP_NUM_PRIM_WRITTEN_COUNT1_HI 0xc00d 381#define mmCP_NUM_PRIM_NEEDED_COUNT1_LO 0xc00e 382#define mmCP_NUM_PRIM_NEEDED_COUNT1_HI 0xc00f 383#define mmCP_NUM_PRIM_WRITTEN_COUNT2_LO 0xc010 384#define mmCP_NUM_PRIM_WRITTEN_COUNT2_HI 0xc011 385#define mmCP_NUM_PRIM_NEEDED_COUNT2_LO 0xc012 386#define mmCP_NUM_PRIM_NEEDED_COUNT2_HI 0xc013 387#define mmCP_NUM_PRIM_WRITTEN_COUNT3_LO 0xc014 388#define mmCP_NUM_PRIM_WRITTEN_COUNT3_HI 0xc015 389#define mmCP_NUM_PRIM_NEEDED_COUNT3_LO 0xc016 390#define mmCP_NUM_PRIM_NEEDED_COUNT3_HI 0xc017 391#define mmCP_PIPE_STATS_ADDR_LO 0xc018 392#define mmCP_PIPE_STATS_ADDR_HI 0xc019 393#define mmCP_VGT_IAVERT_COUNT_LO 0xc01a 394#define mmCP_VGT_IAVERT_COUNT_HI 0xc01b 395#define mmCP_VGT_IAPRIM_COUNT_LO 0xc01c 396#define mmCP_VGT_IAPRIM_COUNT_HI 0xc01d 397#define mmCP_VGT_GSPRIM_COUNT_LO 0xc01e 398#define mmCP_VGT_GSPRIM_COUNT_HI 0xc01f 399#define mmCP_VGT_VSINVOC_COUNT_LO 0xc020 400#define mmCP_VGT_VSINVOC_COUNT_HI 0xc021 401#define mmCP_VGT_GSINVOC_COUNT_LO 0xc022 402#define mmCP_VGT_GSINVOC_COUNT_HI 0xc023 403#define mmCP_VGT_HSINVOC_COUNT_LO 0xc024 404#define mmCP_VGT_HSINVOC_COUNT_HI 0xc025 405#define mmCP_VGT_DSINVOC_COUNT_LO 0xc026 406#define mmCP_VGT_DSINVOC_COUNT_HI 0xc027 407#define mmCP_PA_CINVOC_COUNT_LO 0xc028 408#define mmCP_PA_CINVOC_COUNT_HI 0xc029 409#define mmCP_PA_CPRIM_COUNT_LO 0xc02a 410#define mmCP_PA_CPRIM_COUNT_HI 0xc02b 411#define mmCP_SC_PSINVOC_COUNT0_LO 0xc02c 412#define mmCP_SC_PSINVOC_COUNT0_HI 0xc02d 413#define mmCP_SC_PSINVOC_COUNT1_LO 0xc02e 414#define mmCP_SC_PSINVOC_COUNT1_HI 0xc02f 415#define mmCP_VGT_CSINVOC_COUNT_LO 0xc030 416#define mmCP_VGT_CSINVOC_COUNT_HI 0xc031 417#define mmCP_STRMOUT_CNTL 0xc03f 418#define mmSCRATCH_REG0 0xc040 419#define mmSCRATCH_REG1 0xc041 420#define mmSCRATCH_REG2 0xc042 421#define mmSCRATCH_REG3 0xc043 422#define mmSCRATCH_REG4 0xc044 423#define mmSCRATCH_REG5 0xc045 424#define mmSCRATCH_REG6 0xc046 425#define mmSCRATCH_REG7 0xc047 426#define mmSCRATCH_UMSK 0xc050 427#define mmSCRATCH_ADDR 0xc051 428#define mmCP_PFP_ATOMIC_PREOP_LO 0xc052 429#define mmCP_PFP_ATOMIC_PREOP_HI 0xc053 430#define mmCP_PFP_GDS_ATOMIC0_PREOP_LO 0xc054 431#define mmCP_PFP_GDS_ATOMIC0_PREOP_HI 0xc055 432#define mmCP_PFP_GDS_ATOMIC1_PREOP_LO 0xc056 433#define mmCP_PFP_GDS_ATOMIC1_PREOP_HI 0xc057 434#define mmCP_APPEND_ADDR_LO 0xc058 435#define mmCP_APPEND_ADDR_HI 0xc059 436#define mmCP_APPEND_DATA 0xc05a 437#define mmCP_APPEND_LAST_CS_FENCE 0xc05b 438#define mmCP_APPEND_LAST_PS_FENCE 0xc05c 439#define mmCP_ATOMIC_PREOP_LO 0xc05d 440#define mmCP_ME_ATOMIC_PREOP_LO 0xc05d 441#define mmCP_ATOMIC_PREOP_HI 0xc05e 442#define mmCP_ME_ATOMIC_PREOP_HI 0xc05e 443#define mmCP_GDS_ATOMIC0_PREOP_LO 0xc05f 444#define mmCP_ME_GDS_ATOMIC0_PREOP_LO 0xc05f 445#define mmCP_GDS_ATOMIC0_PREOP_HI 0xc060 446#define mmCP_ME_GDS_ATOMIC0_PREOP_HI 0xc060 447#define mmCP_GDS_ATOMIC1_PREOP_LO 0xc061 448#define mmCP_ME_GDS_ATOMIC1_PREOP_LO 0xc061 449#define mmCP_GDS_ATOMIC1_PREOP_HI 0xc062 450#define mmCP_ME_GDS_ATOMIC1_PREOP_HI 0xc062 451#define mmCP_ME_MC_WADDR_LO 0xc069 452#define mmCP_ME_MC_WADDR_HI 0xc06a 453#define mmCP_ME_MC_WDATA_LO 0xc06b 454#define mmCP_ME_MC_WDATA_HI 0xc06c 455#define mmCP_ME_MC_RADDR_LO 0xc06d 456#define mmCP_ME_MC_RADDR_HI 0xc06e 457#define mmCP_SEM_WAIT_TIMER 0xc06f 458#define mmCP_SIG_SEM_ADDR_LO 0xc070 459#define mmCP_SIG_SEM_ADDR_HI 0xc071 460#define mmCP_WAIT_SEM_ADDR_LO 0xc075 461#define mmCP_WAIT_SEM_ADDR_HI 0xc076 462#define mmCP_WAIT_REG_MEM_TIMEOUT 0xc074 463#define mmCP_COHER_START_DELAY 0xc07b 464#define mmCP_COHER_CNTL 0xc07c 465#define mmCP_COHER_SIZE 0xc07d 466#define mmCP_COHER_SIZE_HI 0xc08c 467#define mmCP_COHER_BASE 0xc07e 468#define mmCP_COHER_BASE_HI 0xc079 469#define mmCP_COHER_STATUS 0xc07f 470#define mmCOHER_DEST_BASE_0 0xa092 471#define mmCOHER_DEST_BASE_1 0xa093 472#define mmCOHER_DEST_BASE_2 0xa07e 473#define mmCOHER_DEST_BASE_3 0xa07f 474#define mmCOHER_DEST_BASE_HI_0 0xa07a 475#define mmCOHER_DEST_BASE_HI_1 0xa07b 476#define mmCOHER_DEST_BASE_HI_2 0xa07c 477#define mmCOHER_DEST_BASE_HI_3 0xa07d 478#define mmCP_DMA_ME_SRC_ADDR 0xc080 479#define mmCP_DMA_ME_SRC_ADDR_HI 0xc081 480#define mmCP_DMA_ME_DST_ADDR 0xc082 481#define mmCP_DMA_ME_DST_ADDR_HI 0xc083 482#define mmCP_DMA_ME_CONTROL 0xc078 483#define mmCP_DMA_ME_COMMAND 0xc084 484#define mmCP_DMA_PFP_SRC_ADDR 0xc085 485#define mmCP_DMA_PFP_SRC_ADDR_HI 0xc086 486#define mmCP_DMA_PFP_DST_ADDR 0xc087 487#define mmCP_DMA_PFP_DST_ADDR_HI 0xc088 488#define mmCP_DMA_PFP_CONTROL 0xc077 489#define mmCP_DMA_PFP_COMMAND 0xc089 490#define mmCP_DMA_CNTL 0xc08a 491#define mmCP_DMA_READ_TAGS 0xc08b 492#define mmCP_PFP_IB_CONTROL 0xc08d 493#define mmCP_PFP_LOAD_CONTROL 0xc08e 494#define mmCP_SCRATCH_INDEX 0xc08f 495#define mmCP_SCRATCH_DATA 0xc090 496#define mmCP_RB_OFFSET 0xc091 497#define mmCP_IB1_OFFSET 0xc092 498#define mmCP_IB2_OFFSET 0xc093 499#define mmCP_IB1_PREAMBLE_BEGIN 0xc094 500#define mmCP_IB1_PREAMBLE_END 0xc095 501#define mmCP_IB2_PREAMBLE_BEGIN 0xc096 502#define mmCP_IB2_PREAMBLE_END 0xc097 503#define mmCP_CE_IB1_OFFSET 0xc098 504#define mmCP_CE_IB2_OFFSET 0xc099 505#define mmCP_CE_COUNTER 0xc09a 506#define mmCP_STALLED_STAT1 0x219d 507#define mmCP_STALLED_STAT2 0x219e 508#define mmCP_STALLED_STAT3 0x219c 509#define mmCP_BUSY_STAT 0x219f 510#define mmCP_STAT 0x21a0 511#define mmCP_ME_HEADER_DUMP 0x21a1 512#define mmCP_PFP_HEADER_DUMP 0x21a2 513#define mmCP_GRBM_FREE_COUNT 0x21a3 514#define mmCP_CE_HEADER_DUMP 0x21a4 515#define mmCP_MC_PACK_DELAY_CNT 0x21a7 516#define mmCP_MC_TAG_CNTL 0x21a8 517#define mmCP_MC_TAG_DATA 0x21a9 518#define mmCP_CSF_STAT 0x21b4 519#define mmCP_CSF_CNTL 0x21b5 520#define mmCP_ME_CNTL 0x21b6 521#define mmCP_CNTX_STAT 0x21b8 522#define mmCP_ME_PREEMPTION 0x21b9 523#define mmCP_RB0_RPTR 0x21c0 524#define mmCP_RB_RPTR 0x21c0 525#define mmCP_RB1_RPTR 0x21bf 526#define mmCP_RB2_RPTR 0x21be 527#define mmCP_RB_WPTR_DELAY 0x21c1 528#define mmCP_RB_WPTR_POLL_CNTL 0x21c2 529#define mmCP_CE_INIT_BASE_LO 0xc0c3 530#define mmCP_CE_INIT_BASE_HI 0xc0c4 531#define mmCP_CE_INIT_BUFSZ 0xc0c5 532#define mmCP_CE_IB1_BASE_LO 0xc0c6 533#define mmCP_CE_IB1_BASE_HI 0xc0c7 534#define mmCP_CE_IB1_BUFSZ 0xc0c8 535#define mmCP_CE_IB2_BASE_LO 0xc0c9 536#define mmCP_CE_IB2_BASE_HI 0xc0ca 537#define mmCP_CE_IB2_BUFSZ 0xc0cb 538#define mmCP_IB1_BASE_LO 0xc0cc 539#define mmCP_IB1_BASE_HI 0xc0cd 540#define mmCP_IB1_BUFSZ 0xc0ce 541#define mmCP_IB2_BASE_LO 0xc0cf 542#define mmCP_IB2_BASE_HI 0xc0d0 543#define mmCP_IB2_BUFSZ 0xc0d1 544#define mmCP_ST_BASE_LO 0xc0d2 545#define mmCP_ST_BASE_HI 0xc0d3 546#define mmCP_ST_BUFSZ 0xc0d4 547#define mmCP_ROQ_THRESHOLDS 0x21bc 548#define mmCP_MEQ_STQ_THRESHOLD 0x21bd 549#define mmCP_ROQ1_THRESHOLDS 0x21d5 550#define mmCP_ROQ2_THRESHOLDS 0x21d6 551#define mmCP_STQ_THRESHOLDS 0x21d7 552#define mmCP_QUEUE_THRESHOLDS 0x21d8 553#define mmCP_MEQ_THRESHOLDS 0x21d9 554#define mmCP_ROQ_AVAIL 0x21da 555#define mmCP_STQ_AVAIL 0x21db 556#define mmCP_ROQ2_AVAIL 0x21dc 557#define mmCP_MEQ_AVAIL 0x21dd 558#define mmCP_CMD_INDEX 0x21de 559#define mmCP_CMD_DATA 0x21df 560#define mmCP_ROQ_RB_STAT 0x21e0 561#define mmCP_ROQ_IB1_STAT 0x21e1 562#define mmCP_ROQ_IB2_STAT 0x21e2 563#define mmCP_STQ_STAT 0x21e3 564#define mmCP_STQ_WR_STAT 0x21e4 565#define mmCP_MEQ_STAT 0x21e5 566#define mmCP_CEQ1_AVAIL 0x21e6 567#define mmCP_CEQ2_AVAIL 0x21e7 568#define mmCP_CE_ROQ_RB_STAT 0x21e8 569#define mmCP_CE_ROQ_IB1_STAT 0x21e9 570#define mmCP_CE_ROQ_IB2_STAT 0x21ea 571#define mmCP_INT_STAT_DEBUG 0x21f7 572#define mmCP_PERFMON_CNTL 0xd808 573#define mmCP_PERFMON_CNTX_CNTL 0xa0d8 574#define mmCP_RINGID 0xa0d9 575#define mmCP_PIPEID 0xa0d9 576#define mmCP_VMID 0xa0da 577#define mmCP_HPD_ROQ_OFFSETS 0x3240 578#define mmCP_HPD_EOP_BASE_ADDR 0x3241 579#define mmCP_HPD_EOP_BASE_ADDR_HI 0x3242 580#define mmCP_HPD_EOP_VMID 0x3243 581#define mmCP_HPD_EOP_CONTROL 0x3244 582#define mmCP_MQD_BASE_ADDR 0x3245 583#define mmCP_MQD_BASE_ADDR_HI 0x3246 584#define mmCP_HQD_ACTIVE 0x3247 585#define mmCP_HQD_VMID 0x3248 586#define mmCP_HQD_PERSISTENT_STATE 0x3249 587#define mmCP_HQD_PIPE_PRIORITY 0x324a 588#define mmCP_HQD_QUEUE_PRIORITY 0x324b 589#define mmCP_HQD_QUANTUM 0x324c 590#define mmCP_HQD_PQ_BASE 0x324d 591#define mmCP_HQD_PQ_BASE_HI 0x324e 592#define mmCP_HQD_PQ_RPTR 0x324f 593#define mmCP_HQD_PQ_RPTR_REPORT_ADDR 0x3250 594#define mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI 0x3251 595#define mmCP_HQD_PQ_WPTR_POLL_ADDR 0x3252 596#define mmCP_HQD_PQ_WPTR_POLL_ADDR_HI 0x3253 597#define mmCP_HQD_PQ_DOORBELL_CONTROL 0x3254 598#define mmCP_HQD_PQ_WPTR 0x3255 599#define mmCP_HQD_PQ_CONTROL 0x3256 600#define mmCP_HQD_IB_BASE_ADDR 0x3257 601#define mmCP_HQD_IB_BASE_ADDR_HI 0x3258 602#define mmCP_HQD_IB_RPTR 0x3259 603#define mmCP_HQD_IB_CONTROL 0x325a 604#define mmCP_HQD_IQ_TIMER 0x325b 605#define mmCP_HQD_IQ_RPTR 0x325c 606#define mmCP_HQD_DEQUEUE_REQUEST 0x325d 607#define mmCP_HQD_DMA_OFFLOAD 0x325e 608#define mmCP_HQD_SEMA_CMD 0x325f 609#define mmCP_HQD_MSG_TYPE 0x3260 610#define mmCP_HQD_ATOMIC0_PREOP_LO 0x3261 611#define mmCP_HQD_ATOMIC0_PREOP_HI 0x3262 612#define mmCP_HQD_ATOMIC1_PREOP_LO 0x3263 613#define mmCP_HQD_ATOMIC1_PREOP_HI 0x3264 614#define mmCP_HQD_HQ_SCHEDULER0 0x3265 615#define mmCP_HQD_HQ_SCHEDULER1 0x3266 616#define mmCP_MQD_CONTROL 0x3267 617#define mmDB_Z_READ_BASE 0xa012 618#define mmDB_STENCIL_READ_BASE 0xa013 619#define mmDB_Z_WRITE_BASE 0xa014 620#define mmDB_STENCIL_WRITE_BASE 0xa015 621#define mmDB_DEPTH_INFO 0xa00f 622#define mmDB_Z_INFO 0xa010 623#define mmDB_STENCIL_INFO 0xa011 624#define mmDB_DEPTH_SIZE 0xa016 625#define mmDB_DEPTH_SLICE 0xa017 626#define mmDB_DEPTH_VIEW 0xa002 627#define mmDB_RENDER_CONTROL 0xa000 628#define mmDB_COUNT_CONTROL 0xa001 629#define mmDB_RENDER_OVERRIDE 0xa003 630#define mmDB_RENDER_OVERRIDE2 0xa004 631#define mmDB_EQAA 0xa201 632#define mmDB_SHADER_CONTROL 0xa203 633#define mmDB_DEPTH_BOUNDS_MIN 0xa008 634#define mmDB_DEPTH_BOUNDS_MAX 0xa009 635#define mmDB_STENCIL_CLEAR 0xa00a 636#define mmDB_DEPTH_CLEAR 0xa00b 637#define mmDB_HTILE_DATA_BASE 0xa005 638#define mmDB_HTILE_SURFACE 0xa2af 639#define mmDB_PRELOAD_CONTROL 0xa2b2 640#define mmDB_STENCILREFMASK 0xa10c 641#define mmDB_STENCILREFMASK_BF 0xa10d 642#define mmDB_SRESULTS_COMPARE_STATE0 0xa2b0 643#define mmDB_SRESULTS_COMPARE_STATE1 0xa2b1 644#define mmDB_DEPTH_CONTROL 0xa200 645#define mmDB_STENCIL_CONTROL 0xa10b 646#define mmDB_ALPHA_TO_MASK 0xa2dc 647#define mmDB_PERFCOUNTER0_SELECT 0xdc40 648#define mmDB_PERFCOUNTER1_SELECT 0xdc42 649#define mmDB_PERFCOUNTER2_SELECT 0xdc44 650#define mmDB_PERFCOUNTER3_SELECT 0xdc46 651#define mmDB_PERFCOUNTER0_SELECT1 0xdc41 652#define mmDB_PERFCOUNTER1_SELECT1 0xdc43 653#define mmDB_PERFCOUNTER0_LO 0xd440 654#define mmDB_PERFCOUNTER1_LO 0xd442 655#define mmDB_PERFCOUNTER2_LO 0xd444 656#define mmDB_PERFCOUNTER3_LO 0xd446 657#define mmDB_PERFCOUNTER0_HI 0xd441 658#define mmDB_PERFCOUNTER1_HI 0xd443 659#define mmDB_PERFCOUNTER2_HI 0xd445 660#define mmDB_PERFCOUNTER3_HI 0xd447 661#define mmDB_DEBUG 0x260c 662#define mmDB_DEBUG2 0x260d 663#define mmDB_DEBUG3 0x260e 664#define mmDB_DEBUG4 0x260f 665#define mmDB_CREDIT_LIMIT 0x2614 666#define mmDB_WATERMARKS 0x2615 667#define mmDB_SUBTILE_CONTROL 0x2616 668#define mmDB_FREE_CACHELINES 0x2617 669#define mmDB_FIFO_DEPTH1 0x2618 670#define mmDB_FIFO_DEPTH2 0x2619 671#define mmDB_CGTT_CLK_CTRL_0 0xf0a4 672#define mmDB_ZPASS_COUNT_LOW 0xc3fe 673#define mmDB_ZPASS_COUNT_HI 0xc3ff 674#define mmDB_RING_CONTROL 0x261b 675#define mmDB_READ_DEBUG_0 0x2620 676#define mmDB_READ_DEBUG_1 0x2621 677#define mmDB_READ_DEBUG_2 0x2622 678#define mmDB_READ_DEBUG_3 0x2623 679#define mmDB_READ_DEBUG_4 0x2624 680#define mmDB_READ_DEBUG_5 0x2625 681#define mmDB_READ_DEBUG_6 0x2626 682#define mmDB_READ_DEBUG_7 0x2627 683#define mmDB_READ_DEBUG_8 0x2628 684#define mmDB_READ_DEBUG_9 0x2629 685#define mmDB_READ_DEBUG_A 0x262a 686#define mmDB_READ_DEBUG_B 0x262b 687#define mmDB_READ_DEBUG_C 0x262c 688#define mmDB_READ_DEBUG_D 0x262d 689#define mmDB_READ_DEBUG_E 0x262e 690#define mmDB_READ_DEBUG_F 0x262f 691#define mmDB_OCCLUSION_COUNT0_LOW 0xc3c0 692#define mmDB_OCCLUSION_COUNT0_HI 0xc3c1 693#define mmDB_OCCLUSION_COUNT1_LOW 0xc3c2 694#define mmDB_OCCLUSION_COUNT1_HI 0xc3c3 695#define mmDB_OCCLUSION_COUNT2_LOW 0xc3c4 696#define mmDB_OCCLUSION_COUNT2_HI 0xc3c5 697#define mmDB_OCCLUSION_COUNT3_LOW 0xc3c6 698#define mmDB_OCCLUSION_COUNT3_HI 0xc3c7 699#define mmCC_RB_REDUNDANCY 0x263c 700#define mmCC_RB_BACKEND_DISABLE 0x263d 701#define mmGC_USER_RB_REDUNDANCY 0x26de 702#define mmGC_USER_RB_BACKEND_DISABLE 0x26df 703#define mmGB_ADDR_CONFIG 0x263e 704#define mmGB_BACKEND_MAP 0x263f 705#define mmGB_GPU_ID 0x2640 706#define mmCC_RB_DAISY_CHAIN 0x2641 707#define mmGB_TILE_MODE0 0x2644 708#define mmGB_TILE_MODE1 0x2645 709#define mmGB_TILE_MODE2 0x2646 710#define mmGB_TILE_MODE3 0x2647 711#define mmGB_TILE_MODE4 0x2648 712#define mmGB_TILE_MODE5 0x2649 713#define mmGB_TILE_MODE6 0x264a 714#define mmGB_TILE_MODE7 0x264b 715#define mmGB_TILE_MODE8 0x264c 716#define mmGB_TILE_MODE9 0x264d 717#define mmGB_TILE_MODE10 0x264e 718#define mmGB_TILE_MODE11 0x264f 719#define mmGB_TILE_MODE12 0x2650 720#define mmGB_TILE_MODE13 0x2651 721#define mmGB_TILE_MODE14 0x2652 722#define mmGB_TILE_MODE15 0x2653 723#define mmGB_TILE_MODE16 0x2654 724#define mmGB_TILE_MODE17 0x2655 725#define mmGB_TILE_MODE18 0x2656 726#define mmGB_TILE_MODE19 0x2657 727#define mmGB_TILE_MODE20 0x2658 728#define mmGB_TILE_MODE21 0x2659 729#define mmGB_TILE_MODE22 0x265a 730#define mmGB_TILE_MODE23 0x265b 731#define mmGB_TILE_MODE24 0x265c 732#define mmGB_TILE_MODE25 0x265d 733#define mmGB_TILE_MODE26 0x265e 734#define mmGB_TILE_MODE27 0x265f 735#define mmGB_TILE_MODE28 0x2660 736#define mmGB_TILE_MODE29 0x2661 737#define mmGB_TILE_MODE30 0x2662 738#define mmGB_TILE_MODE31 0x2663 739#define mmGB_MACROTILE_MODE0 0x2664 740#define mmGB_MACROTILE_MODE1 0x2665 741#define mmGB_MACROTILE_MODE2 0x2666 742#define mmGB_MACROTILE_MODE3 0x2667 743#define mmGB_MACROTILE_MODE4 0x2668 744#define mmGB_MACROTILE_MODE5 0x2669 745#define mmGB_MACROTILE_MODE6 0x266a 746#define mmGB_MACROTILE_MODE7 0x266b 747#define mmGB_MACROTILE_MODE8 0x266c 748#define mmGB_MACROTILE_MODE9 0x266d 749#define mmGB_MACROTILE_MODE10 0x266e 750#define mmGB_MACROTILE_MODE11 0x266f 751#define mmGB_MACROTILE_MODE12 0x2670 752#define mmGB_MACROTILE_MODE13 0x2671 753#define mmGB_MACROTILE_MODE14 0x2672 754#define mmGB_MACROTILE_MODE15 0x2673 755#define mmGB_EDC_MODE 0x307e 756#define mmCC_GC_EDC_CONFIG 0x3098 757#define mmRAS_SIGNATURE_CONTROL 0x3380 758#define mmRAS_SIGNATURE_MASK 0x3381 759#define mmRAS_SX_SIGNATURE0 0x3382 760#define mmRAS_SX_SIGNATURE1 0x3383 761#define mmRAS_SX_SIGNATURE2 0x3384 762#define mmRAS_SX_SIGNATURE3 0x3385 763#define mmRAS_DB_SIGNATURE0 0x338b 764#define mmRAS_PA_SIGNATURE0 0x338c 765#define mmRAS_VGT_SIGNATURE0 0x338d 766#define mmRAS_SQ_SIGNATURE0 0x338e 767#define mmRAS_SC_SIGNATURE0 0x338f 768#define mmRAS_SC_SIGNATURE1 0x3390 769#define mmRAS_SC_SIGNATURE2 0x3391 770#define mmRAS_SC_SIGNATURE3 0x3392 771#define mmRAS_SC_SIGNATURE4 0x3393 772#define mmRAS_SC_SIGNATURE5 0x3394 773#define mmRAS_SC_SIGNATURE6 0x3395 774#define mmRAS_SC_SIGNATURE7 0x3396 775#define mmRAS_IA_SIGNATURE0 0x3397 776#define mmRAS_IA_SIGNATURE1 0x3398 777#define mmRAS_SPI_SIGNATURE0 0x3399 778#define mmRAS_SPI_SIGNATURE1 0x339a 779#define mmRAS_TA_SIGNATURE0 0x339b 780#define mmRAS_TD_SIGNATURE0 0x339c 781#define mmRAS_CB_SIGNATURE0 0x339d 782#define mmRAS_BCI_SIGNATURE0 0x339e 783#define mmRAS_BCI_SIGNATURE1 0x339f 784#define mmGRBM_CAM_INDEX 0x3000 785#define mmGRBM_CAM_DATA 0x3001 786#define mmGRBM_CNTL 0x2000 787#define mmGRBM_SKEW_CNTL 0x2001 788#define mmGRBM_PWR_CNTL 0x2003 789#define mmGRBM_STATUS 0x2004 790#define mmGRBM_STATUS2 0x2002 791#define mmGRBM_STATUS_SE0 0x2005 792#define mmGRBM_STATUS_SE1 0x2006 793#define mmGRBM_STATUS_SE2 0x200e 794#define mmGRBM_STATUS_SE3 0x200f 795#define mmGRBM_SOFT_RESET 0x2008 796#define mmGRBM_DEBUG_CNTL 0x2009 797#define mmGRBM_DEBUG_DATA 0x200a 798#define mmGRBM_GFX_INDEX 0xc200 799#define mmGRBM_GFX_CLKEN_CNTL 0x200c 800#define mmGRBM_WAIT_IDLE_CLOCKS 0x200d 801#define mmGRBM_DEBUG 0x2014 802#define mmGRBM_DEBUG_SNAPSHOT 0x2015 803#define mmGRBM_READ_ERROR 0x2016 804#define mmGRBM_READ_ERROR2 0x2017 805#define mmGRBM_INT_CNTL 0x2018 806#define mmGRBM_PERFCOUNTER0_SELECT 0xd840 807#define mmGRBM_PERFCOUNTER1_SELECT 0xd841 808#define mmGRBM_SE0_PERFCOUNTER_SELECT 0xd842 809#define mmGRBM_SE1_PERFCOUNTER_SELECT 0xd843 810#define mmGRBM_SE2_PERFCOUNTER_SELECT 0xd844 811#define mmGRBM_SE3_PERFCOUNTER_SELECT 0xd845 812#define mmGRBM_PERFCOUNTER0_LO 0xd040 813#define mmGRBM_PERFCOUNTER0_HI 0xd041 814#define mmGRBM_PERFCOUNTER1_LO 0xd043 815#define mmGRBM_PERFCOUNTER1_HI 0xd044 816#define mmGRBM_SE0_PERFCOUNTER_LO 0xd045 817#define mmGRBM_SE0_PERFCOUNTER_HI 0xd046 818#define mmGRBM_SE1_PERFCOUNTER_LO 0xd047 819#define mmGRBM_SE1_PERFCOUNTER_HI 0xd048 820#define mmGRBM_SE2_PERFCOUNTER_LO 0xd049 821#define mmGRBM_SE2_PERFCOUNTER_HI 0xd04a 822#define mmGRBM_SE3_PERFCOUNTER_LO 0xd04b 823#define mmGRBM_SE3_PERFCOUNTER_HI 0xd04c 824#define mmGRBM_SCRATCH_REG0 0x2040 825#define mmGRBM_SCRATCH_REG1 0x2041 826#define mmGRBM_SCRATCH_REG2 0x2042 827#define mmGRBM_SCRATCH_REG3 0x2043 828#define mmGRBM_SCRATCH_REG4 0x2044 829#define mmGRBM_SCRATCH_REG5 0x2045 830#define mmGRBM_SCRATCH_REG6 0x2046 831#define mmGRBM_SCRATCH_REG7 0x2047 832#define mmDEBUG_INDEX 0x203c 833#define mmDEBUG_DATA 0x203d 834#define mmGRBM_NOWHERE 0x203f 835#define mmPA_CL_VPORT_XSCALE 0xa10f 836#define mmPA_CL_VPORT_XOFFSET 0xa110 837#define mmPA_CL_VPORT_YSCALE 0xa111 838#define mmPA_CL_VPORT_YOFFSET 0xa112 839#define mmPA_CL_VPORT_ZSCALE 0xa113 840#define mmPA_CL_VPORT_ZOFFSET 0xa114 841#define mmPA_CL_VPORT_XSCALE_1 0xa115 842#define mmPA_CL_VPORT_XSCALE_2 0xa11b 843#define mmPA_CL_VPORT_XSCALE_3 0xa121 844#define mmPA_CL_VPORT_XSCALE_4 0xa127 845#define mmPA_CL_VPORT_XSCALE_5 0xa12d 846#define mmPA_CL_VPORT_XSCALE_6 0xa133 847#define mmPA_CL_VPORT_XSCALE_7 0xa139 848#define mmPA_CL_VPORT_XSCALE_8 0xa13f 849#define mmPA_CL_VPORT_XSCALE_9 0xa145 850#define mmPA_CL_VPORT_XSCALE_10 0xa14b 851#define mmPA_CL_VPORT_XSCALE_11 0xa151 852#define mmPA_CL_VPORT_XSCALE_12 0xa157 853#define mmPA_CL_VPORT_XSCALE_13 0xa15d 854#define mmPA_CL_VPORT_XSCALE_14 0xa163 855#define mmPA_CL_VPORT_XSCALE_15 0xa169 856#define mmPA_CL_VPORT_XOFFSET_1 0xa116 857#define mmPA_CL_VPORT_XOFFSET_2 0xa11c 858#define mmPA_CL_VPORT_XOFFSET_3 0xa122 859#define mmPA_CL_VPORT_XOFFSET_4 0xa128 860#define mmPA_CL_VPORT_XOFFSET_5 0xa12e 861#define mmPA_CL_VPORT_XOFFSET_6 0xa134 862#define mmPA_CL_VPORT_XOFFSET_7 0xa13a 863#define mmPA_CL_VPORT_XOFFSET_8 0xa140 864#define mmPA_CL_VPORT_XOFFSET_9 0xa146 865#define mmPA_CL_VPORT_XOFFSET_10 0xa14c 866#define mmPA_CL_VPORT_XOFFSET_11 0xa152 867#define mmPA_CL_VPORT_XOFFSET_12 0xa158 868#define mmPA_CL_VPORT_XOFFSET_13 0xa15e 869#define mmPA_CL_VPORT_XOFFSET_14 0xa164 870#define mmPA_CL_VPORT_XOFFSET_15 0xa16a 871#define mmPA_CL_VPORT_YSCALE_1 0xa117 872#define mmPA_CL_VPORT_YSCALE_2 0xa11d 873#define mmPA_CL_VPORT_YSCALE_3 0xa123 874#define mmPA_CL_VPORT_YSCALE_4 0xa129 875#define mmPA_CL_VPORT_YSCALE_5 0xa12f 876#define mmPA_CL_VPORT_YSCALE_6 0xa135 877#define mmPA_CL_VPORT_YSCALE_7 0xa13b 878#define mmPA_CL_VPORT_YSCALE_8 0xa141 879#define mmPA_CL_VPORT_YSCALE_9 0xa147 880#define mmPA_CL_VPORT_YSCALE_10 0xa14d 881#define mmPA_CL_VPORT_YSCALE_11 0xa153 882#define mmPA_CL_VPORT_YSCALE_12 0xa159 883#define mmPA_CL_VPORT_YSCALE_13 0xa15f 884#define mmPA_CL_VPORT_YSCALE_14 0xa165 885#define mmPA_CL_VPORT_YSCALE_15 0xa16b 886#define mmPA_CL_VPORT_YOFFSET_1 0xa118 887#define mmPA_CL_VPORT_YOFFSET_2 0xa11e 888#define mmPA_CL_VPORT_YOFFSET_3 0xa124 889#define mmPA_CL_VPORT_YOFFSET_4 0xa12a 890#define mmPA_CL_VPORT_YOFFSET_5 0xa130 891#define mmPA_CL_VPORT_YOFFSET_6 0xa136 892#define mmPA_CL_VPORT_YOFFSET_7 0xa13c 893#define mmPA_CL_VPORT_YOFFSET_8 0xa142 894#define mmPA_CL_VPORT_YOFFSET_9 0xa148 895#define mmPA_CL_VPORT_YOFFSET_10 0xa14e 896#define mmPA_CL_VPORT_YOFFSET_11 0xa154 897#define mmPA_CL_VPORT_YOFFSET_12 0xa15a 898#define mmPA_CL_VPORT_YOFFSET_13 0xa160 899#define mmPA_CL_VPORT_YOFFSET_14 0xa166 900#define mmPA_CL_VPORT_YOFFSET_15 0xa16c 901#define mmPA_CL_VPORT_ZSCALE_1 0xa119 902#define mmPA_CL_VPORT_ZSCALE_2 0xa11f 903#define mmPA_CL_VPORT_ZSCALE_3 0xa125 904#define mmPA_CL_VPORT_ZSCALE_4 0xa12b 905#define mmPA_CL_VPORT_ZSCALE_5 0xa131 906#define mmPA_CL_VPORT_ZSCALE_6 0xa137 907#define mmPA_CL_VPORT_ZSCALE_7 0xa13d 908#define mmPA_CL_VPORT_ZSCALE_8 0xa143 909#define mmPA_CL_VPORT_ZSCALE_9 0xa149 910#define mmPA_CL_VPORT_ZSCALE_10 0xa14f 911#define mmPA_CL_VPORT_ZSCALE_11 0xa155 912#define mmPA_CL_VPORT_ZSCALE_12 0xa15b 913#define mmPA_CL_VPORT_ZSCALE_13 0xa161 914#define mmPA_CL_VPORT_ZSCALE_14 0xa167 915#define mmPA_CL_VPORT_ZSCALE_15 0xa16d 916#define mmPA_CL_VPORT_ZOFFSET_1 0xa11a 917#define mmPA_CL_VPORT_ZOFFSET_2 0xa120 918#define mmPA_CL_VPORT_ZOFFSET_3 0xa126 919#define mmPA_CL_VPORT_ZOFFSET_4 0xa12c 920#define mmPA_CL_VPORT_ZOFFSET_5 0xa132 921#define mmPA_CL_VPORT_ZOFFSET_6 0xa138 922#define mmPA_CL_VPORT_ZOFFSET_7 0xa13e 923#define mmPA_CL_VPORT_ZOFFSET_8 0xa144 924#define mmPA_CL_VPORT_ZOFFSET_9 0xa14a 925#define mmPA_CL_VPORT_ZOFFSET_10 0xa150 926#define mmPA_CL_VPORT_ZOFFSET_11 0xa156 927#define mmPA_CL_VPORT_ZOFFSET_12 0xa15c 928#define mmPA_CL_VPORT_ZOFFSET_13 0xa162 929#define mmPA_CL_VPORT_ZOFFSET_14 0xa168 930#define mmPA_CL_VPORT_ZOFFSET_15 0xa16e 931#define mmPA_CL_VTE_CNTL 0xa206 932#define mmPA_CL_VS_OUT_CNTL 0xa207 933#define mmPA_CL_NANINF_CNTL 0xa208 934#define mmPA_CL_CLIP_CNTL 0xa204 935#define mmPA_CL_GB_VERT_CLIP_ADJ 0xa2fa 936#define mmPA_CL_GB_VERT_DISC_ADJ 0xa2fb 937#define mmPA_CL_GB_HORZ_CLIP_ADJ 0xa2fc 938#define mmPA_CL_GB_HORZ_DISC_ADJ 0xa2fd 939#define mmPA_CL_UCP_0_X 0xa16f 940#define mmPA_CL_UCP_0_Y 0xa170 941#define mmPA_CL_UCP_0_Z 0xa171 942#define mmPA_CL_UCP_0_W 0xa172 943#define mmPA_CL_UCP_1_X 0xa173 944#define mmPA_CL_UCP_1_Y 0xa174 945#define mmPA_CL_UCP_1_Z 0xa175 946#define mmPA_CL_UCP_1_W 0xa176 947#define mmPA_CL_UCP_2_X 0xa177 948#define mmPA_CL_UCP_2_Y 0xa178 949#define mmPA_CL_UCP_2_Z 0xa179 950#define mmPA_CL_UCP_2_W 0xa17a 951#define mmPA_CL_UCP_3_X 0xa17b 952#define mmPA_CL_UCP_3_Y 0xa17c 953#define mmPA_CL_UCP_3_Z 0xa17d 954#define mmPA_CL_UCP_3_W 0xa17e 955#define mmPA_CL_UCP_4_X 0xa17f 956#define mmPA_CL_UCP_4_Y 0xa180 957#define mmPA_CL_UCP_4_Z 0xa181 958#define mmPA_CL_UCP_4_W 0xa182 959#define mmPA_CL_UCP_5_X 0xa183 960#define mmPA_CL_UCP_5_Y 0xa184 961#define mmPA_CL_UCP_5_Z 0xa185 962#define mmPA_CL_UCP_5_W 0xa186 963#define mmPA_CL_POINT_X_RAD 0xa1f5 964#define mmPA_CL_POINT_Y_RAD 0xa1f6 965#define mmPA_CL_POINT_SIZE 0xa1f7 966#define mmPA_CL_POINT_CULL_RAD 0xa1f8 967#define mmPA_CL_ENHANCE 0x2285 968#define mmPA_CL_RESET_DEBUG 0x2286 969#define mmPA_SU_VTX_CNTL 0xa2f9 970#define mmPA_SU_POINT_SIZE 0xa280 971#define mmPA_SU_POINT_MINMAX 0xa281 972#define mmPA_SU_LINE_CNTL 0xa282 973#define mmPA_SU_LINE_STIPPLE_CNTL 0xa209 974#define mmPA_SU_LINE_STIPPLE_SCALE 0xa20a 975#define mmPA_SU_PRIM_FILTER_CNTL 0xa20b 976#define mmPA_SU_SC_MODE_CNTL 0xa205 977#define mmPA_SU_POLY_OFFSET_DB_FMT_CNTL 0xa2de 978#define mmPA_SU_POLY_OFFSET_CLAMP 0xa2df 979#define mmPA_SU_POLY_OFFSET_FRONT_SCALE 0xa2e0 980#define mmPA_SU_POLY_OFFSET_FRONT_OFFSET 0xa2e1 981#define mmPA_SU_POLY_OFFSET_BACK_SCALE 0xa2e2 982#define mmPA_SU_POLY_OFFSET_BACK_OFFSET 0xa2e3 983#define mmPA_SU_HARDWARE_SCREEN_OFFSET 0xa08d 984#define mmPA_SU_LINE_STIPPLE_VALUE 0xc280 985#define mmPA_SU_PERFCOUNTER0_SELECT 0xd900 986#define mmPA_SU_PERFCOUNTER0_SELECT1 0xd901 987#define mmPA_SU_PERFCOUNTER1_SELECT 0xd902 988#define mmPA_SU_PERFCOUNTER1_SELECT1 0xd903 989#define mmPA_SU_PERFCOUNTER2_SELECT 0xd904 990#define mmPA_SU_PERFCOUNTER3_SELECT 0xd905 991#define mmPA_SU_PERFCOUNTER0_LO 0xd100 992#define mmPA_SU_PERFCOUNTER0_HI 0xd101 993#define mmPA_SU_PERFCOUNTER1_LO 0xd102 994#define mmPA_SU_PERFCOUNTER1_HI 0xd103 995#define mmPA_SU_PERFCOUNTER2_LO 0xd104 996#define mmPA_SU_PERFCOUNTER2_HI 0xd105 997#define mmPA_SU_PERFCOUNTER3_LO 0xd106 998#define mmPA_SU_PERFCOUNTER3_HI 0xd107 999#define mmPA_SC_AA_CONFIG 0xa2f8 1000#define mmPA_SC_AA_MASK_X0Y0_X1Y0 0xa30e 1001#define mmPA_SC_AA_MASK_X0Y1_X1Y1 0xa30f 1002#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0xa2fe 1003#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1 0xa2ff 1004#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2 0xa300 1005#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3 0xa301 1006#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0xa302 1007#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1 0xa303 1008#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2 0xa304 1009#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3 0xa305 1010#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0xa306 1011#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1 0xa307 1012#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2 0xa308 1013#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3 0xa309 1014#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0xa30a 1015#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1 0xa30b 1016#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2 0xa30c 1017#define mmPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3 0xa30d 1018#define mmPA_SC_CENTROID_PRIORITY_0 0xa2f5 1019#define mmPA_SC_CENTROID_PRIORITY_1 0xa2f6 1020#define mmPA_SC_CLIPRECT_0_TL 0xa084 1021#define mmPA_SC_CLIPRECT_0_BR 0xa085 1022#define mmPA_SC_CLIPRECT_1_TL 0xa086 1023#define mmPA_SC_CLIPRECT_1_BR 0xa087 1024#define mmPA_SC_CLIPRECT_2_TL 0xa088 1025#define mmPA_SC_CLIPRECT_2_BR 0xa089 1026#define mmPA_SC_CLIPRECT_3_TL 0xa08a 1027#define mmPA_SC_CLIPRECT_3_BR 0xa08b 1028#define mmPA_SC_CLIPRECT_RULE 0xa083 1029#define mmPA_SC_EDGERULE 0xa08c 1030#define mmPA_SC_LINE_CNTL 0xa2f7 1031#define mmPA_SC_LINE_STIPPLE 0xa283 1032#define mmPA_SC_MODE_CNTL_0 0xa292 1033#define mmPA_SC_MODE_CNTL_1 0xa293 1034#define mmPA_SC_RASTER_CONFIG 0xa0d4 1035#define mmPA_SC_RASTER_CONFIG_1 0xa0d5 1036#define mmPA_SC_SCREEN_EXTENT_CONTROL 0xa0d6 1037#define mmPA_SC_GENERIC_SCISSOR_TL 0xa090 1038#define mmPA_SC_GENERIC_SCISSOR_BR 0xa091 1039#define mmPA_SC_SCREEN_SCISSOR_TL 0xa00c 1040#define mmPA_SC_SCREEN_SCISSOR_BR 0xa00d 1041#define mmPA_SC_WINDOW_OFFSET 0xa080 1042#define mmPA_SC_WINDOW_SCISSOR_TL 0xa081 1043#define mmPA_SC_WINDOW_SCISSOR_BR 0xa082 1044#define mmPA_SC_VPORT_SCISSOR_0_TL 0xa094 1045#define mmPA_SC_VPORT_SCISSOR_1_TL 0xa096 1046#define mmPA_SC_VPORT_SCISSOR_2_TL 0xa098 1047#define mmPA_SC_VPORT_SCISSOR_3_TL 0xa09a 1048#define mmPA_SC_VPORT_SCISSOR_4_TL 0xa09c 1049#define mmPA_SC_VPORT_SCISSOR_5_TL 0xa09e 1050#define mmPA_SC_VPORT_SCISSOR_6_TL 0xa0a0 1051#define mmPA_SC_VPORT_SCISSOR_7_TL 0xa0a2 1052#define mmPA_SC_VPORT_SCISSOR_8_TL 0xa0a4 1053#define mmPA_SC_VPORT_SCISSOR_9_TL 0xa0a6 1054#define mmPA_SC_VPORT_SCISSOR_10_TL 0xa0a8 1055#define mmPA_SC_VPORT_SCISSOR_11_TL 0xa0aa 1056#define mmPA_SC_VPORT_SCISSOR_12_TL 0xa0ac 1057#define mmPA_SC_VPORT_SCISSOR_13_TL 0xa0ae 1058#define mmPA_SC_VPORT_SCISSOR_14_TL 0xa0b0 1059#define mmPA_SC_VPORT_SCISSOR_15_TL 0xa0b2 1060#define mmPA_SC_VPORT_SCISSOR_0_BR 0xa095 1061#define mmPA_SC_VPORT_SCISSOR_1_BR 0xa097 1062#define mmPA_SC_VPORT_SCISSOR_2_BR 0xa099 1063#define mmPA_SC_VPORT_SCISSOR_3_BR 0xa09b 1064#define mmPA_SC_VPORT_SCISSOR_4_BR 0xa09d 1065#define mmPA_SC_VPORT_SCISSOR_5_BR 0xa09f 1066#define mmPA_SC_VPORT_SCISSOR_6_BR 0xa0a1 1067#define mmPA_SC_VPORT_SCISSOR_7_BR 0xa0a3 1068#define mmPA_SC_VPORT_SCISSOR_8_BR 0xa0a5 1069#define mmPA_SC_VPORT_SCISSOR_9_BR 0xa0a7 1070#define mmPA_SC_VPORT_SCISSOR_10_BR 0xa0a9 1071#define mmPA_SC_VPORT_SCISSOR_11_BR 0xa0ab 1072#define mmPA_SC_VPORT_SCISSOR_12_BR 0xa0ad 1073#define mmPA_SC_VPORT_SCISSOR_13_BR 0xa0af 1074#define mmPA_SC_VPORT_SCISSOR_14_BR 0xa0b1 1075#define mmPA_SC_VPORT_SCISSOR_15_BR 0xa0b3 1076#define mmPA_SC_VPORT_ZMIN_0 0xa0b4 1077#define mmPA_SC_VPORT_ZMIN_1 0xa0b6 1078#define mmPA_SC_VPORT_ZMIN_2 0xa0b8 1079#define mmPA_SC_VPORT_ZMIN_3 0xa0ba 1080#define mmPA_SC_VPORT_ZMIN_4 0xa0bc 1081#define mmPA_SC_VPORT_ZMIN_5 0xa0be 1082#define mmPA_SC_VPORT_ZMIN_6 0xa0c0 1083#define mmPA_SC_VPORT_ZMIN_7 0xa0c2 1084#define mmPA_SC_VPORT_ZMIN_8 0xa0c4 1085#define mmPA_SC_VPORT_ZMIN_9 0xa0c6 1086#define mmPA_SC_VPORT_ZMIN_10 0xa0c8 1087#define mmPA_SC_VPORT_ZMIN_11 0xa0ca 1088#define mmPA_SC_VPORT_ZMIN_12 0xa0cc 1089#define mmPA_SC_VPORT_ZMIN_13 0xa0ce 1090#define mmPA_SC_VPORT_ZMIN_14 0xa0d0 1091#define mmPA_SC_VPORT_ZMIN_15 0xa0d2 1092#define mmPA_SC_VPORT_ZMAX_0 0xa0b5 1093#define mmPA_SC_VPORT_ZMAX_1 0xa0b7 1094#define mmPA_SC_VPORT_ZMAX_2 0xa0b9 1095#define mmPA_SC_VPORT_ZMAX_3 0xa0bb 1096#define mmPA_SC_VPORT_ZMAX_4 0xa0bd 1097#define mmPA_SC_VPORT_ZMAX_5 0xa0bf 1098#define mmPA_SC_VPORT_ZMAX_6 0xa0c1 1099#define mmPA_SC_VPORT_ZMAX_7 0xa0c3 1100#define mmPA_SC_VPORT_ZMAX_8 0xa0c5 1101#define mmPA_SC_VPORT_ZMAX_9 0xa0c7 1102#define mmPA_SC_VPORT_ZMAX_10 0xa0c9 1103#define mmPA_SC_VPORT_ZMAX_11 0xa0cb 1104#define mmPA_SC_VPORT_ZMAX_12 0xa0cd 1105#define mmPA_SC_VPORT_ZMAX_13 0xa0cf 1106#define mmPA_SC_VPORT_ZMAX_14 0xa0d1 1107#define mmPA_SC_VPORT_ZMAX_15 0xa0d3 1108#define mmPA_SC_ENHANCE 0x22fc 1109#define mmPA_SC_FIFO_SIZE 0x22f3 1110#define mmPA_SC_IF_FIFO_SIZE 0x22f5 1111#define mmPA_SC_FORCE_EOV_MAX_CNTS 0x22c9 1112#define mmPA_SC_LINE_STIPPLE_STATE 0xc281 1113#define mmPA_SC_SCREEN_EXTENT_MIN_0 0xc284 1114#define mmPA_SC_SCREEN_EXTENT_MAX_0 0xc285 1115#define mmPA_SC_SCREEN_EXTENT_MIN_1 0xc286 1116#define mmPA_SC_SCREEN_EXTENT_MAX_1 0xc28b 1117#define mmPA_SC_PERFCOUNTER0_SELECT 0xd940 1118#define mmPA_SC_PERFCOUNTER0_SELECT1 0xd941 1119#define mmPA_SC_PERFCOUNTER1_SELECT 0xd942 1120#define mmPA_SC_PERFCOUNTER2_SELECT 0xd943 1121#define mmPA_SC_PERFCOUNTER3_SELECT 0xd944 1122#define mmPA_SC_PERFCOUNTER4_SELECT 0xd945 1123#define mmPA_SC_PERFCOUNTER5_SELECT 0xd946 1124#define mmPA_SC_PERFCOUNTER6_SELECT 0xd947 1125#define mmPA_SC_PERFCOUNTER7_SELECT 0xd948 1126#define mmPA_SC_PERFCOUNTER0_LO 0xd140 1127#define mmPA_SC_PERFCOUNTER0_HI 0xd141 1128#define mmPA_SC_PERFCOUNTER1_LO 0xd142 1129#define mmPA_SC_PERFCOUNTER1_HI 0xd143 1130#define mmPA_SC_PERFCOUNTER2_LO 0xd144 1131#define mmPA_SC_PERFCOUNTER2_HI 0xd145 1132#define mmPA_SC_PERFCOUNTER3_LO 0xd146 1133#define mmPA_SC_PERFCOUNTER3_HI 0xd147 1134#define mmPA_SC_PERFCOUNTER4_LO 0xd148 1135#define mmPA_SC_PERFCOUNTER4_HI 0xd149 1136#define mmPA_SC_PERFCOUNTER5_LO 0xd14a 1137#define mmPA_SC_PERFCOUNTER5_HI 0xd14b 1138#define mmPA_SC_PERFCOUNTER6_LO 0xd14c 1139#define mmPA_SC_PERFCOUNTER6_HI 0xd14d 1140#define mmPA_SC_PERFCOUNTER7_LO 0xd14e 1141#define mmPA_SC_PERFCOUNTER7_HI 0xd14f 1142#define mmPA_SC_P3D_TRAP_SCREEN_HV_EN 0xc2a0 1143#define mmPA_SC_P3D_TRAP_SCREEN_H 0xc2a1 1144#define mmPA_SC_P3D_TRAP_SCREEN_V 0xc2a2 1145#define mmPA_SC_P3D_TRAP_SCREEN_OCCURRENCE 0xc2a3 1146#define mmPA_SC_P3D_TRAP_SCREEN_COUNT 0xc2a4 1147#define mmPA_SC_HP3D_TRAP_SCREEN_HV_EN 0xc2a8 1148#define mmPA_SC_HP3D_TRAP_SCREEN_H 0xc2a9 1149#define mmPA_SC_HP3D_TRAP_SCREEN_V 0xc2aa 1150#define mmPA_SC_HP3D_TRAP_SCREEN_OCCURRENCE 0xc2ab 1151#define mmPA_SC_HP3D_TRAP_SCREEN_COUNT 0xc2ac 1152#define mmPA_SC_TRAP_SCREEN_HV_EN 0xc2b0 1153#define mmPA_SC_TRAP_SCREEN_H 0xc2b1 1154#define mmPA_SC_TRAP_SCREEN_V 0xc2b2 1155#define mmPA_SC_TRAP_SCREEN_OCCURRENCE 0xc2b3 1156#define mmPA_SC_TRAP_SCREEN_COUNT 0xc2b4 1157#define mmPA_SC_P3D_TRAP_SCREEN_HV_LOCK 0x22c0 1158#define mmPA_SC_HP3D_TRAP_SCREEN_HV_LOCK 0x22c1 1159#define mmPA_SC_TRAP_SCREEN_HV_LOCK 0x22c2 1160#define mmPA_CL_CNTL_STATUS 0x2284 1161#define mmPA_SU_CNTL_STATUS 0x2294 1162#define mmPA_SC_FIFO_DEPTH_CNTL 0x2295 1163#define mmCGTT_PA_CLK_CTRL 0xf088 1164#define mmCGTT_SC_CLK_CTRL 0xf089 1165#define mmPA_SU_DEBUG_CNTL 0x2280 1166#define mmPA_SU_DEBUG_DATA 0x2281 1167#define mmPA_SC_DEBUG_CNTL 0x22f6 1168#define mmPA_SC_DEBUG_DATA 0x22f7 1169#define ixCLIPPER_DEBUG_REG00 0x0 1170#define ixCLIPPER_DEBUG_REG01 0x1 1171#define ixCLIPPER_DEBUG_REG02 0x2 1172#define ixCLIPPER_DEBUG_REG03 0x3 1173#define ixCLIPPER_DEBUG_REG04 0x4 1174#define ixCLIPPER_DEBUG_REG05 0x5 1175#define ixCLIPPER_DEBUG_REG06 0x6 1176#define ixCLIPPER_DEBUG_REG07 0x7 1177#define ixCLIPPER_DEBUG_REG08 0x8 1178#define ixCLIPPER_DEBUG_REG09 0x9 1179#define ixCLIPPER_DEBUG_REG10 0xa 1180#define ixCLIPPER_DEBUG_REG11 0xb 1181#define ixCLIPPER_DEBUG_REG12 0xc 1182#define ixCLIPPER_DEBUG_REG13 0xd 1183#define ixCLIPPER_DEBUG_REG14 0xe 1184#define ixCLIPPER_DEBUG_REG15 0xf 1185#define ixCLIPPER_DEBUG_REG16 0x10 1186#define ixCLIPPER_DEBUG_REG17 0x11 1187#define ixCLIPPER_DEBUG_REG18 0x12 1188#define ixCLIPPER_DEBUG_REG19 0x13 1189#define ixSXIFCCG_DEBUG_REG0 0x14 1190#define ixSXIFCCG_DEBUG_REG1 0x15 1191#define ixSXIFCCG_DEBUG_REG2 0x16 1192#define ixSXIFCCG_DEBUG_REG3 0x17 1193#define ixSETUP_DEBUG_REG0 0x18 1194#define ixSETUP_DEBUG_REG1 0x19 1195#define ixSETUP_DEBUG_REG2 0x1a 1196#define ixSETUP_DEBUG_REG3 0x1b 1197#define ixSETUP_DEBUG_REG4 0x1c 1198#define ixSETUP_DEBUG_REG5 0x1d 1199#define ixPA_SC_DEBUG_REG0 0x0 1200#define ixPA_SC_DEBUG_REG1 0x1 1201#define mmCOMPUTE_DISPATCH_INITIATOR 0x2e00 1202#define mmCOMPUTE_DIM_X 0x2e01 1203#define mmCOMPUTE_DIM_Y 0x2e02 1204#define mmCOMPUTE_DIM_Z 0x2e03 1205#define mmCOMPUTE_START_X 0x2e04 1206#define mmCOMPUTE_START_Y 0x2e05 1207#define mmCOMPUTE_START_Z 0x2e06 1208#define mmCOMPUTE_NUM_THREAD_X 0x2e07 1209#define mmCOMPUTE_NUM_THREAD_Y 0x2e08 1210#define mmCOMPUTE_NUM_THREAD_Z 0x2e09 1211#define mmCOMPUTE_PIPELINESTAT_ENABLE 0x2e0a 1212#define mmCOMPUTE_PERFCOUNT_ENABLE 0x2e0b 1213#define mmCOMPUTE_PGM_LO 0x2e0c 1214#define mmCOMPUTE_PGM_HI 0x2e0d 1215#define mmCOMPUTE_TBA_LO 0x2e0e 1216#define mmCOMPUTE_TBA_HI 0x2e0f 1217#define mmCOMPUTE_TMA_LO 0x2e10 1218#define mmCOMPUTE_TMA_HI 0x2e11 1219#define mmCOMPUTE_PGM_RSRC1 0x2e12 1220#define mmCOMPUTE_PGM_RSRC2 0x2e13 1221#define mmCOMPUTE_VMID 0x2e14 1222#define mmCOMPUTE_RESOURCE_LIMITS 0x2e15 1223#define mmCOMPUTE_STATIC_THREAD_MGMT_SE0 0x2e16 1224#define mmCOMPUTE_STATIC_THREAD_MGMT_SE1 0x2e17 1225#define mmCOMPUTE_TMPRING_SIZE 0x2e18 1226#define mmCOMPUTE_STATIC_THREAD_MGMT_SE2 0x2e19 1227#define mmCOMPUTE_STATIC_THREAD_MGMT_SE3 0x2e1a 1228#define mmCOMPUTE_RESTART_X 0x2e1b 1229#define mmCOMPUTE_RESTART_Y 0x2e1c 1230#define mmCOMPUTE_RESTART_Z 0x2e1d 1231#define mmCOMPUTE_THREAD_TRACE_ENABLE 0x2e1e 1232#define mmCOMPUTE_MISC_RESERVED 0x2e1f 1233#define mmCOMPUTE_USER_DATA_0 0x2e40 1234#define mmCOMPUTE_USER_DATA_1 0x2e41 1235#define mmCOMPUTE_USER_DATA_2 0x2e42 1236#define mmCOMPUTE_USER_DATA_3 0x2e43 1237#define mmCOMPUTE_USER_DATA_4 0x2e44 1238#define mmCOMPUTE_USER_DATA_5 0x2e45 1239#define mmCOMPUTE_USER_DATA_6 0x2e46 1240#define mmCOMPUTE_USER_DATA_7 0x2e47 1241#define mmCOMPUTE_USER_DATA_8 0x2e48 1242#define mmCOMPUTE_USER_DATA_9 0x2e49 1243#define mmCOMPUTE_USER_DATA_10 0x2e4a 1244#define mmCOMPUTE_USER_DATA_11 0x2e4b 1245#define mmCOMPUTE_USER_DATA_12 0x2e4c 1246#define mmCOMPUTE_USER_DATA_13 0x2e4d 1247#define mmCOMPUTE_USER_DATA_14 0x2e4e 1248#define mmCOMPUTE_USER_DATA_15 0x2e4f 1249#define mmCSPRIV_CONNECT 0x0 1250#define mmCSPRIV_THREAD_TRACE_TG0 0x1e 1251#define mmCSPRIV_THREAD_TRACE_TG1 0x1e 1252#define mmCSPRIV_THREAD_TRACE_TG2 0x1e 1253#define mmCSPRIV_THREAD_TRACE_TG3 0x1e 1254#define mmCSPRIV_THREAD_TRACE_EVENT 0x1f 1255#define mmRLC_CNTL 0x30c0 1256#define mmRLC_DEBUG_SELECT 0x30c1 1257#define mmRLC_DEBUG 0x30c2 1258#define mmRLC_MC_CNTL 0x30c3 1259#define mmRLC_STAT 0x30c4 1260#define mmRLC_SAFE_MODE 0x313a 1261#define mmRLC_SOFT_RESET_GPU 0x30c5 1262#define mmRLC_MEM_SLP_CNTL 0x30c6 1263#define mmRLC_PERFMON_CNTL 0xdcc0 1264#define mmRLC_PERFCOUNTER0_SELECT 0xdcc1 1265#define mmRLC_PERFCOUNTER1_SELECT 0xdcc2 1266#define mmRLC_PERFCOUNTER0_LO 0xd480 1267#define mmRLC_PERFCOUNTER1_LO 0xd482 1268#define mmRLC_PERFCOUNTER0_HI 0xd481 1269#define mmRLC_PERFCOUNTER1_HI 0xd483 1270#define mmCGTT_RLC_CLK_CTRL 0xf0b8 1271#define mmRLC_LB_CNTL 0x30d9 1272#define mmRLC_LB_CNTR_MAX 0x30d2 1273#define mmRLC_LB_CNTR_INIT 0x30db 1274#define mmRLC_LOAD_BALANCE_CNTR 0x30dc 1275#define mmRLC_SAVE_AND_RESTORE_BASE 0x30dd 1276#define mmRLC_JUMP_TABLE_RESTORE 0x30de 1277#define mmRLC_DRIVER_CPDMA_STATUS 0x30de 1278#define mmRLC_PG_DELAY_2 0x30df 1279#define mmRLC_GPM_DEBUG_SELECT 0x30e0 1280#define mmRLC_GPM_DEBUG 0x30e1 1281#define mmRLC_GPM_UCODE_ADDR 0x30e2 1282#define mmRLC_GPM_UCODE_DATA 0x30e3 1283#define mmRLC_GPU_CLOCK_COUNT_LSB 0x30e4 1284#define mmRLC_GPU_CLOCK_COUNT_MSB 0x30e5 1285#define mmRLC_CAPTURE_GPU_CLOCK_COUNT 0x30e6 1286#define mmRLC_UCODE_CNTL 0x30e7 1287#define mmRLC_GPM_STAT 0x3100 1288#define mmRLC_GPU_CLOCK_32_RES_SEL 0x3101 1289#define mmRLC_GPU_CLOCK_32 0x3102 1290#define mmRLC_PG_CNTL 0x3103 1291#define mmRLC_GPM_THREAD_PRIORITY 0x3104 1292#define mmRLC_GPM_THREAD_ENABLE 0x3105 1293#define mmRLC_GPM_VMID_THREAD0 0x3106 1294#define mmRLC_GPM_VMID_THREAD1 0x3107 1295#define mmRLC_CGTT_MGCG_OVERRIDE 0x3108 1296#define mmRLC_CGCG_CGLS_CTRL 0x3109 1297#define mmRLC_CGCG_RAMP_CTRL 0x310a 1298#define mmRLC_DYN_PG_STATUS 0x310b 1299#define mmRLC_DYN_PG_REQUEST 0x310c 1300#define mmRLC_PG_DELAY 0x310d 1301#define mmRLC_CU_STATUS 0x310e 1302#define mmRLC_LB_INIT_CU_MASK 0x310f 1303#define mmRLC_LB_ALWAYS_ACTIVE_CU_MASK 0x3110 1304#define mmRLC_LB_PARAMS 0x3111 1305#define mmRLC_THREAD1_DELAY 0x3112 1306#define mmRLC_PG_ALWAYS_ON_CU_MASK 0x3113 1307#define mmRLC_MAX_PG_CU 0x3114 1308#define mmRLC_AUTO_PG_CTRL 0x3115 1309#define mmRLC_SMU_GRBM_REG_SAVE_CTRL 0x3116 1310#define mmRLC_SMU_PG_CTRL 0x3117 1311#define mmRLC_SMU_PG_WAKE_UP_CTRL 0x3118 1312#define mmRLC_SERDES_RD_MASTER_INDEX 0x3119 1313#define mmRLC_SERDES_RD_DATA_0 0x311a 1314#define mmRLC_SERDES_RD_DATA_1 0x311b 1315#define mmRLC_SERDES_RD_DATA_2 0x311c 1316#define mmRLC_SERDES_WR_CU_MASTER_MASK 0x311d 1317#define mmRLC_SERDES_WR_NONCU_MASTER_MASK 0x311e 1318#define mmRLC_SERDES_WR_CTRL 0x311f 1319#define mmRLC_SERDES_WR_DATA 0x3120 1320#define mmRLC_SERDES_CU_MASTER_BUSY 0x3121 1321#define mmRLC_SERDES_NONCU_MASTER_BUSY 0x3122 1322#define mmRLC_GPM_GENERAL_0 0x3123 1323#define mmRLC_GPM_GENERAL_1 0x3124 1324#define mmRLC_GPM_GENERAL_2 0x3125 1325#define mmRLC_GPM_GENERAL_3 0x3126 1326#define mmRLC_GPM_GENERAL_4 0x3127 1327#define mmRLC_GPM_GENERAL_5 0x3128 1328#define mmRLC_GPM_GENERAL_6 0x3129 1329#define mmRLC_GPM_GENERAL_7 0x312a 1330#define mmRLC_GPM_CU_PD_TIMEOUT 0x312b 1331#define mmRLC_GPM_SCRATCH_ADDR 0x312c 1332#define mmRLC_GPM_SCRATCH_DATA 0x312d 1333#define mmRLC_STATIC_PG_STATUS 0x312e 1334#define mmRLC_GPM_PERF_COUNT_0 0x312f 1335#define mmRLC_GPM_PERF_COUNT_1 0x3130 1336#define mmRLC_GPR_REG1 0x3139 1337#define mmRLC_GPR_REG2 0x313a 1338#define mmRLC_SPM_VMID 0x3131 1339#define mmRLC_SPM_INT_CNTL 0x3132 1340#define mmRLC_SPM_INT_STATUS 0x3133 1341#define mmRLC_SPM_DEBUG_SELECT 0x3134 1342#define mmRLC_SPM_DEBUG 0x3135 1343#define mmRLC_GPM_LOG_ADDR 0x3136 1344#define mmRLC_GPM_LOG_SIZE 0x3137 1345#define mmRLC_GPM_LOG_CONT 0x3138 1346#define mmRLC_SPM_PERFMON_CNTL 0xdc80 1347#define mmRLC_SPM_PERFMON_RING_BASE_LO 0xdc81 1348#define mmRLC_SPM_PERFMON_RING_BASE_HI 0xdc82 1349#define mmRLC_SPM_PERFMON_RING_SIZE 0xdc83 1350#define mmRLC_SPM_PERFMON_SEGMENT_SIZE 0xdc84 1351#define mmRLC_SPM_SE_MUXSEL_ADDR 0xdc85 1352#define mmRLC_SPM_SE_MUXSEL_DATA 0xdc86 1353#define mmRLC_SPM_CPG_PERFMON_SAMPLE_DELAY 0xdc87 1354#define mmRLC_SPM_CPC_PERFMON_SAMPLE_DELAY 0xdc88 1355#define mmRLC_SPM_CPF_PERFMON_SAMPLE_DELAY 0xdc89 1356#define mmRLC_SPM_CB_PERFMON_SAMPLE_DELAY 0xdc8a 1357#define mmRLC_SPM_DB_PERFMON_SAMPLE_DELAY 0xdc8b 1358#define mmRLC_SPM_PA_PERFMON_SAMPLE_DELAY 0xdc8c 1359#define mmRLC_SPM_GDS_PERFMON_SAMPLE_DELAY 0xdc8d 1360#define mmRLC_SPM_IA_PERFMON_SAMPLE_DELAY 0xdc8e 1361#define mmRLC_SPM_SC_PERFMON_SAMPLE_DELAY 0xdc90 1362#define mmRLC_SPM_TCC_PERFMON_SAMPLE_DELAY 0xdc91 1363#define mmRLC_SPM_TCA_PERFMON_SAMPLE_DELAY 0xdc92 1364#define mmRLC_SPM_TCP_PERFMON_SAMPLE_DELAY 0xdc93 1365#define mmRLC_SPM_TA_PERFMON_SAMPLE_DELAY 0xdc94 1366#define mmRLC_SPM_TD_PERFMON_SAMPLE_DELAY 0xdc95 1367#define mmRLC_SPM_VGT_PERFMON_SAMPLE_DELAY 0xdc96 1368#define mmRLC_SPM_SPI_PERFMON_SAMPLE_DELAY 0xdc97 1369#define mmRLC_SPM_SQG_PERFMON_SAMPLE_DELAY 0xdc98 1370#define mmRLC_SPM_TCS_PERFMON_SAMPLE_DELAY 0xdc99 1371#define mmRLC_SPM_SX_PERFMON_SAMPLE_DELAY 0xdc9a 1372#define mmRLC_SPM_GLOBAL_MUXSEL_ADDR 0xdc9b 1373#define mmRLC_SPM_GLOBAL_MUXSEL_DATA 0xdc9c 1374#define mmRLC_SPM_RING_RDPTR 0xdc9d 1375#define mmRLC_SPM_SEGMENT_THRESHOLD 0xdc9e 1376#define mmRLC_SPM_DBR0_PERFMON_SAMPLE_DELAY 0xdc9f 1377#define mmRLC_SPM_DBR1_PERFMON_SAMPLE_DELAY 0xdca0 1378#define mmRLC_SPM_CBR0_PERFMON_SAMPLE_DELAY 0xdca1 1379#define mmRLC_SPM_CBR1_PERFMON_SAMPLE_DELAY 0xdca2 1380#define mmSPI_PS_INPUT_CNTL_0 0xa191 1381#define mmSPI_PS_INPUT_CNTL_1 0xa192 1382#define mmSPI_PS_INPUT_CNTL_2 0xa193 1383#define mmSPI_PS_INPUT_CNTL_3 0xa194 1384#define mmSPI_PS_INPUT_CNTL_4 0xa195 1385#define mmSPI_PS_INPUT_CNTL_5 0xa196 1386#define mmSPI_PS_INPUT_CNTL_6 0xa197 1387#define mmSPI_PS_INPUT_CNTL_7 0xa198 1388#define mmSPI_PS_INPUT_CNTL_8 0xa199 1389#define mmSPI_PS_INPUT_CNTL_9 0xa19a 1390#define mmSPI_PS_INPUT_CNTL_10 0xa19b 1391#define mmSPI_PS_INPUT_CNTL_11 0xa19c 1392#define mmSPI_PS_INPUT_CNTL_12 0xa19d 1393#define mmSPI_PS_INPUT_CNTL_13 0xa19e 1394#define mmSPI_PS_INPUT_CNTL_14 0xa19f 1395#define mmSPI_PS_INPUT_CNTL_15 0xa1a0 1396#define mmSPI_PS_INPUT_CNTL_16 0xa1a1 1397#define mmSPI_PS_INPUT_CNTL_17 0xa1a2 1398#define mmSPI_PS_INPUT_CNTL_18 0xa1a3 1399#define mmSPI_PS_INPUT_CNTL_19 0xa1a4 1400#define mmSPI_PS_INPUT_CNTL_20 0xa1a5 1401#define mmSPI_PS_INPUT_CNTL_21 0xa1a6 1402#define mmSPI_PS_INPUT_CNTL_22 0xa1a7 1403#define mmSPI_PS_INPUT_CNTL_23 0xa1a8 1404#define mmSPI_PS_INPUT_CNTL_24 0xa1a9 1405#define mmSPI_PS_INPUT_CNTL_25 0xa1aa 1406#define mmSPI_PS_INPUT_CNTL_26 0xa1ab 1407#define mmSPI_PS_INPUT_CNTL_27 0xa1ac 1408#define mmSPI_PS_INPUT_CNTL_28 0xa1ad 1409#define mmSPI_PS_INPUT_CNTL_29 0xa1ae 1410#define mmSPI_PS_INPUT_CNTL_30 0xa1af 1411#define mmSPI_PS_INPUT_CNTL_31 0xa1b0 1412#define mmSPI_VS_OUT_CONFIG 0xa1b1 1413#define mmSPI_PS_INPUT_ENA 0xa1b3 1414#define mmSPI_PS_INPUT_ADDR 0xa1b4 1415#define mmSPI_INTERP_CONTROL_0 0xa1b5 1416#define mmSPI_PS_IN_CONTROL 0xa1b6 1417#define mmSPI_BARYC_CNTL 0xa1b8 1418#define mmSPI_TMPRING_SIZE 0xa1ba 1419#define mmSPI_SHADER_POS_FORMAT 0xa1c3 1420#define mmSPI_SHADER_Z_FORMAT 0xa1c4 1421#define mmSPI_SHADER_COL_FORMAT 0xa1c5 1422#define mmSPI_ARB_PRIORITY 0x31c0 1423#define mmSPI_ARB_CYCLES_0 0x31c1 1424#define mmSPI_ARB_CYCLES_1 0x31c2 1425#define mmSPI_CDBG_SYS_GFX 0x31c3 1426#define mmSPI_CDBG_SYS_HP3D 0x31c4 1427#define mmSPI_CDBG_SYS_CS0 0x31c5 1428#define mmSPI_CDBG_SYS_CS1 0x31c6 1429#define mmSPI_WCL_PIPE_PERCENT_GFX 0x31c7 1430#define mmSPI_WCL_PIPE_PERCENT_HP3D 0x31c8 1431#define mmSPI_WCL_PIPE_PERCENT_CS0 0x31c9 1432#define mmSPI_WCL_PIPE_PERCENT_CS1 0x31ca 1433#define mmSPI_WCL_PIPE_PERCENT_CS2 0x31cb 1434#define mmSPI_WCL_PIPE_PERCENT_CS3 0x31cc 1435#define mmSPI_WCL_PIPE_PERCENT_CS4 0x31cd 1436#define mmSPI_WCL_PIPE_PERCENT_CS5 0x31ce 1437#define mmSPI_WCL_PIPE_PERCENT_CS6 0x31cf 1438#define mmSPI_WCL_PIPE_PERCENT_CS7 0x31d0 1439#define mmSPI_GDBG_WAVE_CNTL 0x31d1 1440#define mmSPI_GDBG_TRAP_CONFIG 0x31d2 1441#define mmSPI_GDBG_TRAP_MASK 0x31d3 1442#define mmSPI_GDBG_TBA_LO 0x31d4 1443#define mmSPI_GDBG_TBA_HI 0x31d5 1444#define mmSPI_GDBG_TMA_LO 0x31d6 1445#define mmSPI_GDBG_TMA_HI 0x31d7 1446#define mmSPI_GDBG_TRAP_DATA0 0x31d8 1447#define mmSPI_GDBG_TRAP_DATA1 0x31d9 1448#define mmSPI_RESET_DEBUG 0x31da 1449#define mmSPI_COMPUTE_QUEUE_RESET 0x31db 1450#define mmSPI_RESOURCE_RESERVE_CU_0 0x31dc 1451#define mmSPI_RESOURCE_RESERVE_CU_1 0x31dd 1452#define mmSPI_RESOURCE_RESERVE_CU_2 0x31de 1453#define mmSPI_RESOURCE_RESERVE_CU_3 0x31df 1454#define mmSPI_RESOURCE_RESERVE_CU_4 0x31e0 1455#define mmSPI_RESOURCE_RESERVE_CU_5 0x31e1 1456#define mmSPI_RESOURCE_RESERVE_CU_6 0x31e2 1457#define mmSPI_RESOURCE_RESERVE_CU_7 0x31e3 1458#define mmSPI_RESOURCE_RESERVE_CU_8 0x31e4 1459#define mmSPI_RESOURCE_RESERVE_CU_9 0x31e5 1460#define mmSPI_RESOURCE_RESERVE_CU_10 0x31f0 1461#define mmSPI_RESOURCE_RESERVE_CU_11 0x31f1 1462#define mmSPI_RESOURCE_RESERVE_EN_CU_0 0x31e6 1463#define mmSPI_RESOURCE_RESERVE_EN_CU_1 0x31e7 1464#define mmSPI_RESOURCE_RESERVE_EN_CU_2 0x31e8 1465#define mmSPI_RESOURCE_RESERVE_EN_CU_3 0x31e9 1466#define mmSPI_RESOURCE_RESERVE_EN_CU_4 0x31ea 1467#define mmSPI_RESOURCE_RESERVE_EN_CU_5 0x31eb 1468#define mmSPI_RESOURCE_RESERVE_EN_CU_6 0x31ec 1469#define mmSPI_RESOURCE_RESERVE_EN_CU_7 0x31ed 1470#define mmSPI_RESOURCE_RESERVE_EN_CU_8 0x31ee 1471#define mmSPI_RESOURCE_RESERVE_EN_CU_9 0x31ef 1472#define mmSPI_RESOURCE_RESERVE_EN_CU_10 0x31f2 1473#define mmSPI_RESOURCE_RESERVE_EN_CU_11 0x31f3 1474#define mmSPI_PS_MAX_WAVE_ID 0x243a 1475#define mmSPI_CONFIG_CNTL 0x2440 1476#define mmSPI_DEBUG_CNTL 0x2441 1477#define mmSPI_DEBUG_READ 0x2442 1478#define mmSPI_PERFCOUNTER0_SELECT 0xd980 1479#define mmSPI_PERFCOUNTER1_SELECT 0xd981 1480#define mmSPI_PERFCOUNTER2_SELECT 0xd982 1481#define mmSPI_PERFCOUNTER3_SELECT 0xd983 1482#define mmSPI_PERFCOUNTER0_SELECT1 0xd984 1483#define mmSPI_PERFCOUNTER1_SELECT1 0xd985 1484#define mmSPI_PERFCOUNTER2_SELECT1 0xd986 1485#define mmSPI_PERFCOUNTER3_SELECT1 0xd987 1486#define mmSPI_PERFCOUNTER4_SELECT 0xd988 1487#define mmSPI_PERFCOUNTER5_SELECT 0xd989 1488#define mmSPI_PERFCOUNTER_BINS 0xd98a 1489#define mmSPI_PERFCOUNTER0_HI 0xd180 1490#define mmSPI_PERFCOUNTER0_LO 0xd181 1491#define mmSPI_PERFCOUNTER1_HI 0xd182 1492#define mmSPI_PERFCOUNTER1_LO 0xd183 1493#define mmSPI_PERFCOUNTER2_HI 0xd184 1494#define mmSPI_PERFCOUNTER2_LO 0xd185 1495#define mmSPI_PERFCOUNTER3_HI 0xd186 1496#define mmSPI_PERFCOUNTER3_LO 0xd187 1497#define mmSPI_PERFCOUNTER4_HI 0xd188 1498#define mmSPI_PERFCOUNTER4_LO 0xd189 1499#define mmSPI_PERFCOUNTER5_HI 0xd18a 1500#define mmSPI_PERFCOUNTER5_LO 0xd18b 1501#define mmSPI_CONFIG_CNTL_1 0x244f 1502#define mmSPI_DEBUG_BUSY 0x2450 1503#define mmCGTS_SM_CTRL_REG 0xf000 1504#define mmCGTS_RD_CTRL_REG 0xf001 1505#define mmCGTS_RD_REG 0xf002 1506#define mmCGTS_TCC_DISABLE 0xf003 1507#define mmCGTS_USER_TCC_DISABLE 0xf004 1508#define mmCGTS_CU0_SP0_CTRL_REG 0xf008 1509#define mmCGTS_CU0_LDS_SQ_CTRL_REG 0xf009 1510#define mmCGTS_CU0_TA_SQC_CTRL_REG 0xf00a 1511#define mmCGTS_CU0_SP1_CTRL_REG 0xf00b 1512#define mmCGTS_CU0_TD_TCP_CTRL_REG 0xf00c 1513#define mmCGTS_CU1_SP0_CTRL_REG 0xf00d 1514#define mmCGTS_CU1_LDS_SQ_CTRL_REG 0xf00e 1515#define mmCGTS_CU1_TA_CTRL_REG 0xf00f 1516#define mmCGTS_CU1_SP1_CTRL_REG 0xf010 1517#define mmCGTS_CU1_TD_TCP_CTRL_REG 0xf011 1518#define mmCGTS_CU2_SP0_CTRL_REG 0xf012 1519#define mmCGTS_CU2_LDS_SQ_CTRL_REG 0xf013 1520#define mmCGTS_CU2_TA_CTRL_REG 0xf014 1521#define mmCGTS_CU2_SP1_CTRL_REG 0xf015 1522#define mmCGTS_CU2_TD_TCP_CTRL_REG 0xf016 1523#define mmCGTS_CU3_SP0_CTRL_REG 0xf017 1524#define mmCGTS_CU3_LDS_SQ_CTRL_REG 0xf018 1525#define mmCGTS_CU3_TA_CTRL_REG 0xf019 1526#define mmCGTS_CU3_SP1_CTRL_REG 0xf01a 1527#define mmCGTS_CU3_TD_TCP_CTRL_REG 0xf01b 1528#define mmCGTS_CU4_SP0_CTRL_REG 0xf01c 1529#define mmCGTS_CU4_LDS_SQ_CTRL_REG 0xf01d 1530#define mmCGTS_CU4_TA_SQC_CTRL_REG 0xf01e 1531#define mmCGTS_CU4_SP1_CTRL_REG 0xf01f 1532#define mmCGTS_CU4_TD_TCP_CTRL_REG 0xf020 1533#define mmCGTS_CU5_SP0_CTRL_REG 0xf021 1534#define mmCGTS_CU5_LDS_SQ_CTRL_REG 0xf022 1535#define mmCGTS_CU5_TA_CTRL_REG 0xf023 1536#define mmCGTS_CU5_SP1_CTRL_REG 0xf024 1537#define mmCGTS_CU5_TD_TCP_CTRL_REG 0xf025 1538#define mmCGTS_CU6_SP0_CTRL_REG 0xf026 1539#define mmCGTS_CU6_LDS_SQ_CTRL_REG 0xf027 1540#define mmCGTS_CU6_TA_CTRL_REG 0xf028 1541#define mmCGTS_CU6_SP1_CTRL_REG 0xf029 1542#define mmCGTS_CU6_TD_TCP_CTRL_REG 0xf02a 1543#define mmCGTS_CU7_SP0_CTRL_REG 0xf02b 1544#define mmCGTS_CU7_LDS_SQ_CTRL_REG 0xf02c 1545#define mmCGTS_CU7_TA_CTRL_REG 0xf02d 1546#define mmCGTS_CU7_SP1_CTRL_REG 0xf02e 1547#define mmCGTS_CU7_TD_TCP_CTRL_REG 0xf02f 1548#define mmCGTS_CU8_SP0_CTRL_REG 0xf030 1549#define mmCGTS_CU8_LDS_SQ_CTRL_REG 0xf031 1550#define mmCGTS_CU8_TA_SQC_CTRL_REG 0xf032 1551#define mmCGTS_CU8_SP1_CTRL_REG 0xf033 1552#define mmCGTS_CU8_TD_TCP_CTRL_REG 0xf034 1553#define mmCGTS_CU9_SP0_CTRL_REG 0xf035 1554#define mmCGTS_CU9_LDS_SQ_CTRL_REG 0xf036 1555#define mmCGTS_CU9_TA_CTRL_REG 0xf037 1556#define mmCGTS_CU9_SP1_CTRL_REG 0xf038 1557#define mmCGTS_CU9_TD_TCP_CTRL_REG 0xf039 1558#define mmCGTS_CU10_SP0_CTRL_REG 0xf03a 1559#define mmCGTS_CU10_LDS_SQ_CTRL_REG 0xf03b 1560#define mmCGTS_CU10_TA_CTRL_REG 0xf03c 1561#define mmCGTS_CU10_SP1_CTRL_REG 0xf03d 1562#define mmCGTS_CU10_TD_TCP_CTRL_REG 0xf03e 1563#define mmCGTS_CU11_SP0_CTRL_REG 0xf03f 1564#define mmCGTS_CU11_LDS_SQ_CTRL_REG 0xf040 1565#define mmCGTS_CU11_TA_CTRL_REG 0xf041 1566#define mmCGTS_CU11_SP1_CTRL_REG 0xf042 1567#define mmCGTS_CU11_TD_TCP_CTRL_REG 0xf043 1568#define mmCGTS_CU12_SP0_CTRL_REG 0xf044 1569#define mmCGTS_CU12_LDS_SQ_CTRL_REG 0xf045 1570#define mmCGTS_CU12_TA_SQC_CTRL_REG 0xf046 1571#define mmCGTS_CU12_SP1_CTRL_REG 0xf047 1572#define mmCGTS_CU12_TD_TCP_CTRL_REG 0xf048 1573#define mmCGTS_CU13_SP0_CTRL_REG 0xf049 1574#define mmCGTS_CU13_LDS_SQ_CTRL_REG 0xf04a 1575#define mmCGTS_CU13_TA_CTRL_REG 0xf04b 1576#define mmCGTS_CU13_SP1_CTRL_REG 0xf04c 1577#define mmCGTS_CU13_TD_TCP_CTRL_REG 0xf04d 1578#define mmCGTS_CU14_SP0_CTRL_REG 0xf04e 1579#define mmCGTS_CU14_LDS_SQ_CTRL_REG 0xf04f 1580#define mmCGTS_CU14_TA_CTRL_REG 0xf050 1581#define mmCGTS_CU14_SP1_CTRL_REG 0xf051 1582#define mmCGTS_CU14_TD_TCP_CTRL_REG 0xf052 1583#define mmCGTS_CU15_SP0_CTRL_REG 0xf053 1584#define mmCGTS_CU15_LDS_SQ_CTRL_REG 0xf054 1585#define mmCGTS_CU15_TA_CTRL_REG 0xf055 1586#define mmCGTS_CU15_SP1_CTRL_REG 0xf056 1587#define mmCGTS_CU15_TD_TCP_CTRL_REG 0xf057 1588#define mmCGTT_SPI_CLK_CTRL 0xf080 1589#define mmCGTT_PC_CLK_CTRL 0xf081 1590#define mmCGTT_BCI_CLK_CTRL 0xf082 1591#define mmSPI_WF_LIFETIME_CNTL 0x24aa 1592#define mmSPI_WF_LIFETIME_LIMIT_0 0x24ab 1593#define mmSPI_WF_LIFETIME_LIMIT_1 0x24ac 1594#define mmSPI_WF_LIFETIME_LIMIT_2 0x24ad 1595#define mmSPI_WF_LIFETIME_LIMIT_3 0x24ae 1596#define mmSPI_WF_LIFETIME_LIMIT_4 0x24af 1597#define mmSPI_WF_LIFETIME_LIMIT_5 0x24b0 1598#define mmSPI_WF_LIFETIME_LIMIT_6 0x24b1 1599#define mmSPI_WF_LIFETIME_LIMIT_7 0x24b2 1600#define mmSPI_WF_LIFETIME_LIMIT_8 0x24b3 1601#define mmSPI_WF_LIFETIME_LIMIT_9 0x24b4 1602#define mmSPI_WF_LIFETIME_STATUS_0 0x24b5 1603#define mmSPI_WF_LIFETIME_STATUS_1 0x24b6 1604#define mmSPI_WF_LIFETIME_STATUS_2 0x24b7 1605#define mmSPI_WF_LIFETIME_STATUS_3 0x24b8 1606#define mmSPI_WF_LIFETIME_STATUS_4 0x24b9 1607#define mmSPI_WF_LIFETIME_STATUS_5 0x24ba 1608#define mmSPI_WF_LIFETIME_STATUS_6 0x24bb 1609#define mmSPI_WF_LIFETIME_STATUS_7 0x24bc 1610#define mmSPI_WF_LIFETIME_STATUS_8 0x24bd 1611#define mmSPI_WF_LIFETIME_STATUS_9 0x24be 1612#define mmSPI_WF_LIFETIME_STATUS_10 0x24bf 1613#define mmSPI_WF_LIFETIME_STATUS_11 0x24c0 1614#define mmSPI_WF_LIFETIME_STATUS_12 0x24c1 1615#define mmSPI_WF_LIFETIME_STATUS_13 0x24c2 1616#define mmSPI_WF_LIFETIME_STATUS_14 0x24c3 1617#define mmSPI_WF_LIFETIME_STATUS_15 0x24c4 1618#define mmSPI_WF_LIFETIME_STATUS_16 0x24c5 1619#define mmSPI_WF_LIFETIME_STATUS_17 0x24c6 1620#define mmSPI_WF_LIFETIME_STATUS_18 0x24c7 1621#define mmSPI_WF_LIFETIME_STATUS_19 0x24c8 1622#define mmSPI_WF_LIFETIME_STATUS_20 0x24c9 1623#define mmSPI_WF_LIFETIME_DEBUG 0x24ca 1624#define mmSPI_SLAVE_DEBUG_BUSY 0x24d3 1625#define mmSPI_LB_CTR_CTRL 0x24d4 1626#define mmSPI_LB_CU_MASK 0x24d5 1627#define mmSPI_LB_DATA_REG 0x24d6 1628#define mmSPI_PG_ENABLE_STATIC_CU_MASK 0x24d7 1629#define mmSPI_GDS_CREDITS 0x24d8 1630#define mmSPI_SX_EXPORT_BUFFER_SIZES 0x24d9 1631#define mmSPI_SX_SCOREBOARD_BUFFER_SIZES 0x24da 1632#define mmSPI_CSQ_WF_ACTIVE_STATUS 0x24db 1633#define mmSPI_CSQ_WF_ACTIVE_COUNT_0 0x24dc 1634#define mmSPI_CSQ_WF_ACTIVE_COUNT_1 0x24dd 1635#define mmSPI_CSQ_WF_ACTIVE_COUNT_2 0x24de 1636#define mmSPI_CSQ_WF_ACTIVE_COUNT_3 0x24df 1637#define mmSPI_CSQ_WF_ACTIVE_COUNT_4 0x24e0 1638#define mmSPI_CSQ_WF_ACTIVE_COUNT_5 0x24e1 1639#define mmSPI_CSQ_WF_ACTIVE_COUNT_6 0x24e2 1640#define mmSPI_CSQ_WF_ACTIVE_COUNT_7 0x24e3 1641#define mmBCI_DEBUG_READ 0x24eb 1642#define mmSPI_P0_TRAP_SCREEN_PSBA_LO 0x24ec 1643#define mmSPI_P0_TRAP_SCREEN_PSBA_HI 0x24ed 1644#define mmSPI_P0_TRAP_SCREEN_PSMA_LO 0x24ee 1645#define mmSPI_P0_TRAP_SCREEN_PSMA_HI 0x24ef 1646#define mmSPI_P0_TRAP_SCREEN_GPR_MIN 0x24f0 1647#define mmSPI_P1_TRAP_SCREEN_PSBA_LO 0x24f1 1648#define mmSPI_P1_TRAP_SCREEN_PSBA_HI 0x24f2 1649#define mmSPI_P1_TRAP_SCREEN_PSMA_LO 0x24f3 1650#define mmSPI_P1_TRAP_SCREEN_PSMA_HI 0x24f4 1651#define mmSPI_P1_TRAP_SCREEN_GPR_MIN 0x24f5 1652#define mmSPI_SHADER_TBA_LO_PS 0x2c00 1653#define mmSPI_SHADER_TBA_HI_PS 0x2c01 1654#define mmSPI_SHADER_TMA_LO_PS 0x2c02 1655#define mmSPI_SHADER_TMA_HI_PS 0x2c03 1656#define mmSPI_SHADER_PGM_LO_PS 0x2c08 1657#define mmSPI_SHADER_PGM_HI_PS 0x2c09 1658#define mmSPI_SHADER_PGM_RSRC1_PS 0x2c0a 1659#define mmSPI_SHADER_PGM_RSRC2_PS 0x2c0b 1660#define mmSPI_SHADER_PGM_RSRC3_PS 0x2c07 1661#define mmSPI_SHADER_USER_DATA_PS_0 0x2c0c 1662#define mmSPI_SHADER_USER_DATA_PS_1 0x2c0d 1663#define mmSPI_SHADER_USER_DATA_PS_2 0x2c0e 1664#define mmSPI_SHADER_USER_DATA_PS_3 0x2c0f 1665#define mmSPI_SHADER_USER_DATA_PS_4 0x2c10 1666#define mmSPI_SHADER_USER_DATA_PS_5 0x2c11 1667#define mmSPI_SHADER_USER_DATA_PS_6 0x2c12 1668#define mmSPI_SHADER_USER_DATA_PS_7 0x2c13 1669#define mmSPI_SHADER_USER_DATA_PS_8 0x2c14 1670#define mmSPI_SHADER_USER_DATA_PS_9 0x2c15 1671#define mmSPI_SHADER_USER_DATA_PS_10 0x2c16 1672#define mmSPI_SHADER_USER_DATA_PS_11 0x2c17 1673#define mmSPI_SHADER_USER_DATA_PS_12 0x2c18 1674#define mmSPI_SHADER_USER_DATA_PS_13 0x2c19 1675#define mmSPI_SHADER_USER_DATA_PS_14 0x2c1a 1676#define mmSPI_SHADER_USER_DATA_PS_15 0x2c1b 1677#define mmSPI_SHADER_TBA_LO_VS 0x2c40 1678#define mmSPI_SHADER_TBA_HI_VS 0x2c41 1679#define mmSPI_SHADER_TMA_LO_VS 0x2c42 1680#define mmSPI_SHADER_TMA_HI_VS 0x2c43 1681#define mmSPI_SHADER_PGM_LO_VS 0x2c48 1682#define mmSPI_SHADER_PGM_HI_VS 0x2c49 1683#define mmSPI_SHADER_PGM_RSRC1_VS 0x2c4a 1684#define mmSPI_SHADER_PGM_RSRC2_VS 0x2c4b 1685#define mmSPI_SHADER_PGM_RSRC3_VS 0x2c46 1686#define mmSPI_SHADER_LATE_ALLOC_VS 0x2c47 1687#define mmSPI_SHADER_USER_DATA_VS_0 0x2c4c 1688#define mmSPI_SHADER_USER_DATA_VS_1 0x2c4d 1689#define mmSPI_SHADER_USER_DATA_VS_2 0x2c4e 1690#define mmSPI_SHADER_USER_DATA_VS_3 0x2c4f 1691#define mmSPI_SHADER_USER_DATA_VS_4 0x2c50 1692#define mmSPI_SHADER_USER_DATA_VS_5 0x2c51 1693#define mmSPI_SHADER_USER_DATA_VS_6 0x2c52 1694#define mmSPI_SHADER_USER_DATA_VS_7 0x2c53 1695#define mmSPI_SHADER_USER_DATA_VS_8 0x2c54 1696#define mmSPI_SHADER_USER_DATA_VS_9 0x2c55 1697#define mmSPI_SHADER_USER_DATA_VS_10 0x2c56 1698#define mmSPI_SHADER_USER_DATA_VS_11 0x2c57 1699#define mmSPI_SHADER_USER_DATA_VS_12 0x2c58 1700#define mmSPI_SHADER_USER_DATA_VS_13 0x2c59 1701#define mmSPI_SHADER_USER_DATA_VS_14 0x2c5a 1702#define mmSPI_SHADER_USER_DATA_VS_15 0x2c5b 1703#define mmSPI_SHADER_PGM_RSRC2_ES_VS 0x2c7c 1704#define mmSPI_SHADER_PGM_RSRC2_LS_VS 0x2c7d 1705#define mmSPI_SHADER_TBA_LO_GS 0x2c80 1706#define mmSPI_SHADER_TBA_HI_GS 0x2c81 1707#define mmSPI_SHADER_TMA_LO_GS 0x2c82 1708#define mmSPI_SHADER_TMA_HI_GS 0x2c83 1709#define mmSPI_SHADER_PGM_LO_GS 0x2c88 1710#define mmSPI_SHADER_PGM_HI_GS 0x2c89 1711#define mmSPI_SHADER_PGM_RSRC1_GS 0x2c8a 1712#define mmSPI_SHADER_PGM_RSRC2_GS 0x2c8b 1713#define mmSPI_SHADER_PGM_RSRC3_GS 0x2c87 1714#define mmSPI_SHADER_USER_DATA_GS_0 0x2c8c 1715#define mmSPI_SHADER_USER_DATA_GS_1 0x2c8d 1716#define mmSPI_SHADER_USER_DATA_GS_2 0x2c8e 1717#define mmSPI_SHADER_USER_DATA_GS_3 0x2c8f 1718#define mmSPI_SHADER_USER_DATA_GS_4 0x2c90 1719#define mmSPI_SHADER_USER_DATA_GS_5 0x2c91 1720#define mmSPI_SHADER_USER_DATA_GS_6 0x2c92 1721#define mmSPI_SHADER_USER_DATA_GS_7 0x2c93 1722#define mmSPI_SHADER_USER_DATA_GS_8 0x2c94 1723#define mmSPI_SHADER_USER_DATA_GS_9 0x2c95 1724#define mmSPI_SHADER_USER_DATA_GS_10 0x2c96 1725#define mmSPI_SHADER_USER_DATA_GS_11 0x2c97 1726#define mmSPI_SHADER_USER_DATA_GS_12 0x2c98 1727#define mmSPI_SHADER_USER_DATA_GS_13 0x2c99 1728#define mmSPI_SHADER_USER_DATA_GS_14 0x2c9a 1729#define mmSPI_SHADER_USER_DATA_GS_15 0x2c9b 1730#define mmSPI_SHADER_PGM_RSRC2_ES_GS 0x2cbc 1731#define mmSPI_SHADER_TBA_LO_ES 0x2cc0 1732#define mmSPI_SHADER_TBA_HI_ES 0x2cc1 1733#define mmSPI_SHADER_TMA_LO_ES 0x2cc2 1734#define mmSPI_SHADER_TMA_HI_ES 0x2cc3 1735#define mmSPI_SHADER_PGM_LO_ES 0x2cc8 1736#define mmSPI_SHADER_PGM_HI_ES 0x2cc9 1737#define mmSPI_SHADER_PGM_RSRC1_ES 0x2cca 1738#define mmSPI_SHADER_PGM_RSRC2_ES 0x2ccb 1739#define mmSPI_SHADER_PGM_RSRC3_ES 0x2cc7 1740#define mmSPI_SHADER_USER_DATA_ES_0 0x2ccc 1741#define mmSPI_SHADER_USER_DATA_ES_1 0x2ccd 1742#define mmSPI_SHADER_USER_DATA_ES_2 0x2cce 1743#define mmSPI_SHADER_USER_DATA_ES_3 0x2ccf 1744#define mmSPI_SHADER_USER_DATA_ES_4 0x2cd0 1745#define mmSPI_SHADER_USER_DATA_ES_5 0x2cd1 1746#define mmSPI_SHADER_USER_DATA_ES_6 0x2cd2 1747#define mmSPI_SHADER_USER_DATA_ES_7 0x2cd3 1748#define mmSPI_SHADER_USER_DATA_ES_8 0x2cd4 1749#define mmSPI_SHADER_USER_DATA_ES_9 0x2cd5 1750#define mmSPI_SHADER_USER_DATA_ES_10 0x2cd6 1751#define mmSPI_SHADER_USER_DATA_ES_11 0x2cd7 1752#define mmSPI_SHADER_USER_DATA_ES_12 0x2cd8 1753#define mmSPI_SHADER_USER_DATA_ES_13 0x2cd9 1754#define mmSPI_SHADER_USER_DATA_ES_14 0x2cda 1755#define mmSPI_SHADER_USER_DATA_ES_15 0x2cdb 1756#define mmSPI_SHADER_PGM_RSRC2_LS_ES 0x2cfd 1757#define mmSPI_SHADER_TBA_LO_HS 0x2d00 1758#define mmSPI_SHADER_TBA_HI_HS 0x2d01 1759#define mmSPI_SHADER_TMA_LO_HS 0x2d02 1760#define mmSPI_SHADER_TMA_HI_HS 0x2d03 1761#define mmSPI_SHADER_PGM_LO_HS 0x2d08 1762#define mmSPI_SHADER_PGM_HI_HS 0x2d09 1763#define mmSPI_SHADER_PGM_RSRC1_HS 0x2d0a 1764#define mmSPI_SHADER_PGM_RSRC2_HS 0x2d0b 1765#define mmSPI_SHADER_PGM_RSRC3_HS 0x2d07 1766#define mmSPI_SHADER_USER_DATA_HS_0 0x2d0c 1767#define mmSPI_SHADER_USER_DATA_HS_1 0x2d0d 1768#define mmSPI_SHADER_USER_DATA_HS_2 0x2d0e 1769#define mmSPI_SHADER_USER_DATA_HS_3 0x2d0f 1770#define mmSPI_SHADER_USER_DATA_HS_4 0x2d10 1771#define mmSPI_SHADER_USER_DATA_HS_5 0x2d11 1772#define mmSPI_SHADER_USER_DATA_HS_6 0x2d12 1773#define mmSPI_SHADER_USER_DATA_HS_7 0x2d13 1774#define mmSPI_SHADER_USER_DATA_HS_8 0x2d14 1775#define mmSPI_SHADER_USER_DATA_HS_9 0x2d15 1776#define mmSPI_SHADER_USER_DATA_HS_10 0x2d16 1777#define mmSPI_SHADER_USER_DATA_HS_11 0x2d17 1778#define mmSPI_SHADER_USER_DATA_HS_12 0x2d18 1779#define mmSPI_SHADER_USER_DATA_HS_13 0x2d19 1780#define mmSPI_SHADER_USER_DATA_HS_14 0x2d1a 1781#define mmSPI_SHADER_USER_DATA_HS_15 0x2d1b 1782#define mmSPI_SHADER_PGM_RSRC2_LS_HS 0x2d3d 1783#define mmSPI_SHADER_TBA_LO_LS 0x2d40 1784#define mmSPI_SHADER_TBA_HI_LS 0x2d41 1785#define mmSPI_SHADER_TMA_LO_LS 0x2d42 1786#define mmSPI_SHADER_TMA_HI_LS 0x2d43 1787#define mmSPI_SHADER_PGM_LO_LS 0x2d48 1788#define mmSPI_SHADER_PGM_HI_LS 0x2d49 1789#define mmSPI_SHADER_PGM_RSRC1_LS 0x2d4a 1790#define mmSPI_SHADER_PGM_RSRC2_LS 0x2d4b 1791#define mmSPI_SHADER_PGM_RSRC3_LS 0x2d47 1792#define mmSPI_SHADER_USER_DATA_LS_0 0x2d4c 1793#define mmSPI_SHADER_USER_DATA_LS_1 0x2d4d 1794#define mmSPI_SHADER_USER_DATA_LS_2 0x2d4e 1795#define mmSPI_SHADER_USER_DATA_LS_3 0x2d4f 1796#define mmSPI_SHADER_USER_DATA_LS_4 0x2d50 1797#define mmSPI_SHADER_USER_DATA_LS_5 0x2d51 1798#define mmSPI_SHADER_USER_DATA_LS_6 0x2d52 1799#define mmSPI_SHADER_USER_DATA_LS_7 0x2d53 1800#define mmSPI_SHADER_USER_DATA_LS_8 0x2d54 1801#define mmSPI_SHADER_USER_DATA_LS_9 0x2d55 1802#define mmSPI_SHADER_USER_DATA_LS_10 0x2d56 1803#define mmSPI_SHADER_USER_DATA_LS_11 0x2d57 1804#define mmSPI_SHADER_USER_DATA_LS_12 0x2d58 1805#define mmSPI_SHADER_USER_DATA_LS_13 0x2d59 1806#define mmSPI_SHADER_USER_DATA_LS_14 0x2d5a 1807#define mmSPI_SHADER_USER_DATA_LS_15 0x2d5b 1808#define mmSQ_CONFIG 0x2300 1809#define mmSQC_CONFIG 0x2301 1810#define mmSQC_CACHES 0xc348 1811#define mmSQ_RANDOM_WAVE_PRI 0x2303 1812#define mmSQ_REG_CREDITS 0x2304 1813#define mmSQ_FIFO_SIZES 0x2305 1814#define mmSQ_INTERRUPT_AUTO_MASK 0x2314 1815#define mmSQ_INTERRUPT_MSG_CTRL 0x2315 1816#define mmSQ_PERFCOUNTER_CTRL 0xd9e0 1817#define mmSQ_PERFCOUNTER_MASK 0xd9e1 1818#define mmSQ_PERFCOUNTER_CTRL2 0xd9e2 1819#define mmCC_SQC_BANK_DISABLE 0x2307 1820#define mmUSER_SQC_BANK_DISABLE 0x2308 1821#define mmSQ_PERFCOUNTER0_LO 0xd1c0 1822#define mmSQ_PERFCOUNTER1_LO 0xd1c2 1823#define mmSQ_PERFCOUNTER2_LO 0xd1c4 1824#define mmSQ_PERFCOUNTER3_LO 0xd1c6 1825#define mmSQ_PERFCOUNTER4_LO 0xd1c8 1826#define mmSQ_PERFCOUNTER5_LO 0xd1ca 1827#define mmSQ_PERFCOUNTER6_LO 0xd1cc 1828#define mmSQ_PERFCOUNTER7_LO 0xd1ce 1829#define mmSQ_PERFCOUNTER8_LO 0xd1d0 1830#define mmSQ_PERFCOUNTER9_LO 0xd1d2 1831#define mmSQ_PERFCOUNTER10_LO 0xd1d4 1832#define mmSQ_PERFCOUNTER11_LO 0xd1d6 1833#define mmSQ_PERFCOUNTER12_LO 0xd1d8 1834#define mmSQ_PERFCOUNTER13_LO 0xd1da 1835#define mmSQ_PERFCOUNTER14_LO 0xd1dc 1836#define mmSQ_PERFCOUNTER15_LO 0xd1de 1837#define mmSQ_PERFCOUNTER0_HI 0xd1c1 1838#define mmSQ_PERFCOUNTER1_HI 0xd1c3 1839#define mmSQ_PERFCOUNTER2_HI 0xd1c5 1840#define mmSQ_PERFCOUNTER3_HI 0xd1c7 1841#define mmSQ_PERFCOUNTER4_HI 0xd1c9 1842#define mmSQ_PERFCOUNTER5_HI 0xd1cb 1843#define mmSQ_PERFCOUNTER6_HI 0xd1cd 1844#define mmSQ_PERFCOUNTER7_HI 0xd1cf 1845#define mmSQ_PERFCOUNTER8_HI 0xd1d1 1846#define mmSQ_PERFCOUNTER9_HI 0xd1d3 1847#define mmSQ_PERFCOUNTER10_HI 0xd1d5 1848#define mmSQ_PERFCOUNTER11_HI 0xd1d7 1849#define mmSQ_PERFCOUNTER12_HI 0xd1d9 1850#define mmSQ_PERFCOUNTER13_HI 0xd1db 1851#define mmSQ_PERFCOUNTER14_HI 0xd1dd 1852#define mmSQ_PERFCOUNTER15_HI 0xd1df 1853#define mmSQ_PERFCOUNTER0_SELECT 0xd9c0 1854#define mmSQ_PERFCOUNTER1_SELECT 0xd9c1 1855#define mmSQ_PERFCOUNTER2_SELECT 0xd9c2 1856#define mmSQ_PERFCOUNTER3_SELECT 0xd9c3 1857#define mmSQ_PERFCOUNTER4_SELECT 0xd9c4 1858#define mmSQ_PERFCOUNTER5_SELECT 0xd9c5 1859#define mmSQ_PERFCOUNTER6_SELECT 0xd9c6 1860#define mmSQ_PERFCOUNTER7_SELECT 0xd9c7 1861#define mmSQ_PERFCOUNTER8_SELECT 0xd9c8 1862#define mmSQ_PERFCOUNTER9_SELECT 0xd9c9 1863#define mmSQ_PERFCOUNTER10_SELECT 0xd9ca 1864#define mmSQ_PERFCOUNTER11_SELECT 0xd9cb 1865#define mmSQ_PERFCOUNTER12_SELECT 0xd9cc 1866#define mmSQ_PERFCOUNTER13_SELECT 0xd9cd 1867#define mmSQ_PERFCOUNTER14_SELECT 0xd9ce 1868#define mmSQ_PERFCOUNTER15_SELECT 0xd9cf 1869#define mmCGTT_SQ_CLK_CTRL 0xf08c 1870#define mmCGTT_SQG_CLK_CTRL 0xf08d 1871#define mmSQ_ALU_CLK_CTRL 0xf08e 1872#define mmSQ_TEX_CLK_CTRL 0xf08f 1873#define mmSQ_LDS_CLK_CTRL 0xf090 1874#define mmSQ_POWER_THROTTLE 0xf091 1875#define mmSQ_POWER_THROTTLE2 0xf092 1876#define mmSQ_TIME_HI 0x237c 1877#define mmSQ_TIME_LO 0x237d 1878#define mmSQ_THREAD_TRACE_BASE 0x2380 1879#define mmSQ_THREAD_TRACE_BASE2 0x2385 1880#define mmSQ_THREAD_TRACE_SIZE 0x2381 1881#define mmSQ_THREAD_TRACE_MASK 0x2382 1882#define mmSQ_THREAD_TRACE_USERDATA_0 0xc340 1883#define mmSQ_THREAD_TRACE_USERDATA_1 0xc341 1884#define mmSQ_THREAD_TRACE_USERDATA_2 0xc342 1885#define mmSQ_THREAD_TRACE_USERDATA_3 0xc343 1886#define mmSQ_THREAD_TRACE_MODE 0x238e 1887#define mmSQ_THREAD_TRACE_CTRL 0x238f 1888#define mmSQ_THREAD_TRACE_TOKEN_MASK 0x2383 1889#define mmSQ_THREAD_TRACE_TOKEN_MASK2 0x2386 1890#define mmSQ_THREAD_TRACE_PERF_MASK 0x2384 1891#define mmSQ_THREAD_TRACE_WPTR 0x238c 1892#define mmSQ_THREAD_TRACE_STATUS 0x238d 1893#define mmSQ_THREAD_TRACE_CNTR 0x2390 1894#define mmSQ_THREAD_TRACE_HIWATER 0x2392 1895#define mmSQ_LB_CTR_CTRL 0x2398 1896#define mmSQ_LB_DATA_ALU_CYCLES 0x2399 1897#define mmSQ_LB_DATA_TEX_CYCLES 0x239a 1898#define mmSQ_LB_DATA_ALU_STALLS 0x239b 1899#define mmSQ_LB_DATA_TEX_STALLS 0x239c 1900#define mmSQC_SECDED_CNT 0x23a0 1901#define mmSQ_SEC_CNT 0x23a1 1902#define mmSQ_DED_CNT 0x23a2 1903#define mmSQ_DED_INFO 0x23a3 1904#define mmSQ_BUF_RSRC_WORD0 0x23c0 1905#define mmSQ_BUF_RSRC_WORD1 0x23c1 1906#define mmSQ_BUF_RSRC_WORD2 0x23c2 1907#define mmSQ_BUF_RSRC_WORD3 0x23c3 1908#define mmSQ_IMG_RSRC_WORD0 0x23c4 1909#define mmSQ_IMG_RSRC_WORD1 0x23c5 1910#define mmSQ_IMG_RSRC_WORD2 0x23c6 1911#define mmSQ_IMG_RSRC_WORD3 0x23c7 1912#define mmSQ_IMG_RSRC_WORD4 0x23c8 1913#define mmSQ_IMG_RSRC_WORD5 0x23c9 1914#define mmSQ_IMG_RSRC_WORD6 0x23ca 1915#define mmSQ_IMG_RSRC_WORD7 0x23cb 1916#define mmSQ_IMG_SAMP_WORD0 0x23cc 1917#define mmSQ_IMG_SAMP_WORD1 0x23cd 1918#define mmSQ_IMG_SAMP_WORD2 0x23ce 1919#define mmSQ_IMG_SAMP_WORD3 0x23cf 1920#define mmSQ_FLAT_SCRATCH_WORD0 0x23d0 1921#define mmSQ_FLAT_SCRATCH_WORD1 0x23d1 1922#define mmSQ_IND_INDEX 0x2378 1923#define mmSQ_IND_CMD 0x237a 1924#define mmSQ_CMD 0x237b 1925#define mmSQ_IND_DATA 0x2379 1926#define mmSQ_REG_TIMESTAMP 0x2374 1927#define mmSQ_CMD_TIMESTAMP 0x2375 1928#define mmSQ_HV_VMID_CTRL 0xf840 1929#define ixSQ_WAVE_INST_DW0 0x1a 1930#define ixSQ_WAVE_INST_DW1 0x1b 1931#define ixSQ_WAVE_PC_LO 0x18 1932#define ixSQ_WAVE_PC_HI 0x19 1933#define ixSQ_WAVE_IB_DBG0 0x1c 1934#define ixSQ_WAVE_EXEC_LO 0x27e 1935#define ixSQ_WAVE_EXEC_HI 0x27f 1936#define ixSQ_WAVE_STATUS 0x12 1937#define ixSQ_WAVE_MODE 0x11 1938#define ixSQ_WAVE_TRAPSTS 0x13 1939#define ixSQ_WAVE_HW_ID 0x14 1940#define ixSQ_WAVE_GPR_ALLOC 0x15 1941#define ixSQ_WAVE_LDS_ALLOC 0x16 1942#define ixSQ_WAVE_IB_STS 0x17 1943#define ixSQ_WAVE_M0 0x27c 1944#define ixSQ_WAVE_TBA_LO 0x26c 1945#define ixSQ_WAVE_TBA_HI 0x26d 1946#define ixSQ_WAVE_TMA_LO 0x26e 1947#define ixSQ_WAVE_TMA_HI 0x26f 1948#define ixSQ_WAVE_TTMP0 0x270 1949#define ixSQ_WAVE_TTMP1 0x271 1950#define ixSQ_WAVE_TTMP2 0x272 1951#define ixSQ_WAVE_TTMP3 0x273 1952#define ixSQ_WAVE_TTMP4 0x274 1953#define ixSQ_WAVE_TTMP5 0x275 1954#define ixSQ_WAVE_TTMP6 0x276 1955#define ixSQ_WAVE_TTMP7 0x277 1956#define ixSQ_WAVE_TTMP8 0x278 1957#define ixSQ_WAVE_TTMP9 0x279 1958#define ixSQ_WAVE_TTMP10 0x27a 1959#define ixSQ_WAVE_TTMP11 0x27b 1960#define mmSQ_DEBUG_STS_GLOBAL 0x2309 1961#define mmSQ_DEBUG_STS_GLOBAL2 0x2310 1962#define mmSQ_DEBUG_STS_GLOBAL3 0x2311 1963#define ixSQ_DEBUG_STS_LOCAL 0x8 1964#define ixSQ_DEBUG_CTRL_LOCAL 0x9 1965#define mmSH_MEM_BASES 0x230a 1966#define mmSH_MEM_APE1_BASE 0x230b 1967#define mmSH_MEM_APE1_LIMIT 0x230c 1968#define mmSH_MEM_CONFIG 0x230d 1969#define mmSQC_POLICY 0x230e 1970#define mmSQC_VOLATILE 0x230f 1971#define mmSQ_THREAD_TRACE_WORD_CMN 0x23b0 1972#define mmSQ_THREAD_TRACE_WORD_INST 0x23b0 1973#define mmSQ_THREAD_TRACE_WORD_INST_PC_1_OF_2 0x23b0 1974#define mmSQ_THREAD_TRACE_WORD_INST_PC_2_OF_2 0x23b1 1975#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_1_OF_2 0x23b0 1976#define mmSQ_THREAD_TRACE_WORD_INST_USERDATA_2_OF_2 0x23b1 1977#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_1_OF_2 0x23b0 1978#define mmSQ_THREAD_TRACE_WORD_TIMESTAMP_2_OF_2 0x23b1 1979#define mmSQ_THREAD_TRACE_WORD_WAVE 0x23b0 1980#define mmSQ_THREAD_TRACE_WORD_MISC 0x23b0 1981#define mmSQ_THREAD_TRACE_WORD_WAVE_START 0x23b0 1982#define mmSQ_THREAD_TRACE_WORD_REG_1_OF_2 0x23b0 1983#define mmSQ_THREAD_TRACE_WORD_REG_2_OF_2 0x23b0 1984#define mmSQ_THREAD_TRACE_WORD_REG_CS_1_OF_2 0x23b0 1985#define mmSQ_THREAD_TRACE_WORD_REG_CS_2_OF_2 0x23b0 1986#define mmSQ_THREAD_TRACE_WORD_EVENT 0x23b0 1987#define mmSQ_THREAD_TRACE_WORD_ISSUE 0x23b0 1988#define mmSQ_THREAD_TRACE_WORD_PERF_1_OF_2 0x23b0 1989#define mmSQ_THREAD_TRACE_WORD_PERF_2_OF_2 0x23b1 1990#define ixSQ_INTERRUPT_WORD_CMN 0x20c0 1991#define ixSQ_INTERRUPT_WORD_AUTO 0x20c0 1992#define ixSQ_INTERRUPT_WORD_WAVE 0x20c0 1993#define mmSQ_SOP2 0x237f 1994#define mmSQ_VOP1 0x237f 1995#define mmSQ_MTBUF_1 0x237f 1996#define mmSQ_EXP_1 0x237f 1997#define mmSQ_MUBUF_1 0x237f 1998#define mmSQ_INST 0x237f 1999#define mmSQ_EXP_0 0x237f 2000#define mmSQ_MUBUF_0 0x237f 2001#define mmSQ_VOP3_0 0x237f 2002#define mmSQ_VOP2 0x237f 2003#define mmSQ_MTBUF_0 0x237f 2004#define mmSQ_SOPP 0x237f 2005#define mmSQ_FLAT_0 0x237f 2006#define mmSQ_VOP3_0_SDST_ENC 0x237f 2007#define mmSQ_MIMG_1 0x237f 2008#define mmSQ_SMRD 0x237f 2009#define mmSQ_SOP1 0x237f 2010#define mmSQ_SOPC 0x237f 2011#define mmSQ_FLAT_1 0x237f 2012#define mmSQ_DS_1 0x237f 2013#define mmSQ_VOP3_1 0x237f 2014#define mmSQ_MIMG_0 0x237f 2015#define mmSQ_SOPK 0x237f 2016#define mmSQ_DS_0 0x237f 2017#define mmSQ_VOPC 0x237f 2018#define mmSQ_VINTRP 0x237f 2019#define mmCGTT_SX_CLK_CTRL0 0xf094 2020#define mmCGTT_SX_CLK_CTRL1 0xf095 2021#define mmCGTT_SX_CLK_CTRL2 0xf096 2022#define mmCGTT_SX_CLK_CTRL3 0xf097 2023#define mmCGTT_SX_CLK_CTRL4 0xf098 2024#define mmSX_DEBUG_BUSY 0x2414 2025#define mmSX_DEBUG_BUSY_2 0x2415 2026#define mmSX_DEBUG_BUSY_3 0x2416 2027#define mmSX_DEBUG_BUSY_4 0x2417 2028#define mmSX_DEBUG_1 0x2418 2029#define mmSX_PERFCOUNTER0_SELECT 0xda40 2030#define mmSX_PERFCOUNTER1_SELECT 0xda41 2031#define mmSX_PERFCOUNTER2_SELECT 0xda42 2032#define mmSX_PERFCOUNTER3_SELECT 0xda43 2033#define mmSX_PERFCOUNTER0_SELECT1 0xda44 2034#define mmSX_PERFCOUNTER1_SELECT1 0xda45 2035#define mmSX_PERFCOUNTER0_LO 0xd240 2036#define mmSX_PERFCOUNTER0_HI 0xd241 2037#define mmSX_PERFCOUNTER1_LO 0xd242 2038#define mmSX_PERFCOUNTER1_HI 0xd243 2039#define mmSX_PERFCOUNTER2_LO 0xd244 2040#define mmSX_PERFCOUNTER2_HI 0xd245 2041#define mmSX_PERFCOUNTER3_LO 0xd246 2042#define mmSX_PERFCOUNTER3_HI 0xd247 2043#define mmTCC_CTRL 0x2b80 2044#define mmTCC_EDC_COUNTER 0x2b82 2045#define mmTCC_REDUNDANCY 0x2b83 2046#define mmTCC_CGTT_SCLK_CTRL 0xf0ac 2047#define mmTCA_CGTT_SCLK_CTRL 0xf0ad 2048#define mmTCS_CGTT_SCLK_CTRL 0xf0ae 2049#define mmTCC_PERFCOUNTER0_SELECT 0xdb80 2050#define mmTCC_PERFCOUNTER1_SELECT 0xdb82 2051#define mmTCC_PERFCOUNTER0_SELECT1 0xdb81 2052#define mmTCC_PERFCOUNTER1_SELECT1 0xdb83 2053#define mmTCC_PERFCOUNTER2_SELECT 0xdb84 2054#define mmTCC_PERFCOUNTER3_SELECT 0xdb85 2055#define mmTCC_PERFCOUNTER0_LO 0xd380 2056#define mmTCC_PERFCOUNTER1_LO 0xd382 2057#define mmTCC_PERFCOUNTER2_LO 0xd384 2058#define mmTCC_PERFCOUNTER3_LO 0xd386 2059#define mmTCC_PERFCOUNTER0_HI 0xd381 2060#define mmTCC_PERFCOUNTER1_HI 0xd383 2061#define mmTCC_PERFCOUNTER2_HI 0xd385 2062#define mmTCC_PERFCOUNTER3_HI 0xd387 2063#define mmTCA_CTRL 0x2bc0 2064#define mmTCA_PERFCOUNTER0_SELECT 0xdb90 2065#define mmTCA_PERFCOUNTER1_SELECT 0xdb92 2066#define mmTCA_PERFCOUNTER0_SELECT1 0xdb91 2067#define mmTCA_PERFCOUNTER1_SELECT1 0xdb93 2068#define mmTCA_PERFCOUNTER2_SELECT 0xdb94 2069#define mmTCA_PERFCOUNTER3_SELECT 0xdb95 2070#define mmTCA_PERFCOUNTER0_LO 0xd390 2071#define mmTCA_PERFCOUNTER1_LO 0xd392 2072#define mmTCA_PERFCOUNTER2_LO 0xd394 2073#define mmTCA_PERFCOUNTER3_LO 0xd396 2074#define mmTCA_PERFCOUNTER0_HI 0xd391 2075#define mmTCA_PERFCOUNTER1_HI 0xd393 2076#define mmTCA_PERFCOUNTER2_HI 0xd395 2077#define mmTCA_PERFCOUNTER3_HI 0xd397 2078#define mmTCS_CTRL 0x2be0 2079#define mmTCS_PERFCOUNTER0_SELECT 0xdba0 2080#define mmTCS_PERFCOUNTER0_SELECT1 0xdba1 2081#define mmTCS_PERFCOUNTER1_SELECT 0xdba2 2082#define mmTCS_PERFCOUNTER2_SELECT 0xdba3 2083#define mmTCS_PERFCOUNTER3_SELECT 0xdba4 2084#define mmTCS_PERFCOUNTER0_LO 0xd3a0 2085#define mmTCS_PERFCOUNTER1_LO 0xd3a2 2086#define mmTCS_PERFCOUNTER2_LO 0xd3a4 2087#define mmTCS_PERFCOUNTER3_LO 0xd3a6 2088#define mmTCS_PERFCOUNTER0_HI 0xd3a1 2089#define mmTCS_PERFCOUNTER1_HI 0xd3a3 2090#define mmTCS_PERFCOUNTER2_HI 0xd3a5 2091#define mmTCS_PERFCOUNTER3_HI 0xd3a7 2092#define mmTA_BC_BASE_ADDR 0xa020 2093#define mmTA_BC_BASE_ADDR_HI 0xa021 2094#define mmTD_CNTL 0x2525 2095#define mmTD_STATUS 0x2526 2096#define mmTD_DEBUG_INDEX 0x2528 2097#define mmTD_DEBUG_DATA 0x2529 2098#define mmTD_PERFCOUNTER0_SELECT 0xdb00 2099#define mmTD_PERFCOUNTER1_SELECT 0xdb02 2100#define mmTD_PERFCOUNTER0_SELECT1 0xdb01 2101#define mmTD_PERFCOUNTER0_LO 0xd300 2102#define mmTD_PERFCOUNTER1_LO 0xd302 2103#define mmTD_PERFCOUNTER0_HI 0xd301 2104#define mmTD_PERFCOUNTER1_HI 0xd303 2105#define mmTD_SCRATCH 0x2533 2106#define mmTA_CNTL 0x2541 2107#define mmTA_CNTL_AUX 0x2542 2108#define mmTA_RESERVED_010C 0x2543 2109#define mmTA_CS_BC_BASE_ADDR 0xc380 2110#define mmTA_CS_BC_BASE_ADDR_HI 0xc381 2111#define mmTA_STATUS 0x2548 2112#define mmTA_DEBUG_INDEX 0x254c 2113#define mmTA_DEBUG_DATA 0x254d 2114#define mmTA_PERFCOUNTER0_SELECT 0xdac0 2115#define mmTA_PERFCOUNTER1_SELECT 0xdac2 2116#define mmTA_PERFCOUNTER0_SELECT1 0xdac1 2117#define mmTA_PERFCOUNTER0_LO 0xd2c0 2118#define mmTA_PERFCOUNTER1_LO 0xd2c2 2119#define mmTA_PERFCOUNTER0_HI 0xd2c1 2120#define mmTA_PERFCOUNTER1_HI 0xd2c3 2121#define mmTA_SCRATCH 0x2564 2122#define mmSH_HIDDEN_PRIVATE_BASE_VMID 0x2580 2123#define mmSH_STATIC_MEM_CONFIG 0x2581 2124#define mmTCP_INVALIDATE 0x2b00 2125#define mmTCP_STATUS 0x2b01 2126#define mmTCP_CNTL 0x2b02 2127#define mmTCP_CHAN_STEER_LO 0x2b03 2128#define mmTCP_CHAN_STEER_HI 0x2b04 2129#define mmTCP_ADDR_CONFIG 0x2b05 2130#define mmTCP_CREDIT 0x2b06 2131#define mmTCP_PERFCOUNTER0_SELECT 0xdb40 2132#define mmTCP_PERFCOUNTER1_SELECT 0xdb42 2133#define mmTCP_PERFCOUNTER0_SELECT1 0xdb41 2134#define mmTCP_PERFCOUNTER1_SELECT1 0xdb43 2135#define mmTCP_PERFCOUNTER2_SELECT 0xdb44 2136#define mmTCP_PERFCOUNTER3_SELECT 0xdb45 2137#define mmTCP_PERFCOUNTER0_LO 0xd340 2138#define mmTCP_PERFCOUNTER1_LO 0xd342 2139#define mmTCP_PERFCOUNTER2_LO 0xd344 2140#define mmTCP_PERFCOUNTER3_LO 0xd346 2141#define mmTCP_PERFCOUNTER0_HI 0xd341 2142#define mmTCP_PERFCOUNTER1_HI 0xd343 2143#define mmTCP_PERFCOUNTER2_HI 0xd345 2144#define mmTCP_PERFCOUNTER3_HI 0xd347 2145#define mmTCP_BUFFER_ADDR_HASH_CNTL 0x2b16 2146#define mmTCP_EDC_COUNTER 0x2b17 2147#define mmTC_CFG_L1_LOAD_POLICY0 0x2b1a 2148#define mmTC_CFG_L1_LOAD_POLICY1 0x2b1b 2149#define mmTC_CFG_L1_STORE_POLICY 0x2b1c 2150#define mmTC_CFG_L2_LOAD_POLICY0 0x2b1d 2151#define mmTC_CFG_L2_LOAD_POLICY1 0x2b1e 2152#define mmTC_CFG_L2_STORE_POLICY0 0x2b1f 2153#define mmTC_CFG_L2_STORE_POLICY1 0x2b20 2154#define mmTC_CFG_L2_ATOMIC_POLICY 0x2b21 2155#define mmTC_CFG_L1_VOLATILE 0x2b22 2156#define mmTC_CFG_L2_VOLATILE 0x2b23 2157#define mmTCP_WATCH0_ADDR_H 0x32a0 2158#define mmTCP_WATCH1_ADDR_H 0x32a3 2159#define mmTCP_WATCH2_ADDR_H 0x32a6 2160#define mmTCP_WATCH3_ADDR_H 0x32a9 2161#define mmTCP_WATCH0_ADDR_L 0x32a1 2162#define mmTCP_WATCH1_ADDR_L 0x32a4 2163#define mmTCP_WATCH2_ADDR_L 0x32a7 2164#define mmTCP_WATCH3_ADDR_L 0x32aa 2165#define mmTCP_WATCH0_CNTL 0x32a2 2166#define mmTCP_WATCH1_CNTL 0x32a5 2167#define mmTCP_WATCH2_CNTL 0x32a8 2168#define mmTCP_WATCH3_CNTL 0x32ab 2169#define mmTD_CGTT_CTRL 0xf09c 2170#define mmTA_CGTT_CTRL 0xf09d 2171#define mmCGTT_TCP_CLK_CTRL 0xf09e 2172#define mmCGTT_TCI_CLK_CTRL 0xf09f 2173#define mmTCI_STATUS 0x2b61 2174#define mmTCI_CNTL_1 0x2b62 2175#define mmTCI_CNTL_2 0x2b63 2176#define mmGDS_CONFIG 0x25c0 2177#define mmGDS_CNTL_STATUS 0x25c1 2178#define mmGDS_ENHANCE2 0x25c2 2179#define mmGDS_PROTECTION_FAULT 0x25c3 2180#define mmGDS_VM_PROTECTION_FAULT 0x25c4 2181#define mmGDS_SECDED_CNT 0x25c5 2182#define mmGDS_GRBM_SECDED_CNT 0x25c6 2183#define mmGDS_OA_DED 0x25c7 2184#define mmGDS_DEBUG_CNTL 0x25c8 2185#define mmGDS_DEBUG_DATA 0x25c9 2186#define mmCGTT_GDS_CLK_CTRL 0xf0a0 2187#define mmGDS_RD_ADDR 0xc400 2188#define mmGDS_RD_DATA 0xc401 2189#define mmGDS_RD_BURST_ADDR 0xc402 2190#define mmGDS_RD_BURST_COUNT 0xc403 2191#define mmGDS_RD_BURST_DATA 0xc404 2192#define mmGDS_WR_ADDR 0xc405 2193#define mmGDS_WR_DATA 0xc406 2194#define mmGDS_WR_BURST_ADDR 0xc407 2195#define mmGDS_WR_BURST_DATA 0xc408 2196#define mmGDS_WRITE_COMPLETE 0xc409 2197#define mmGDS_ATOM_CNTL 0xc40a 2198#define mmGDS_ATOM_COMPLETE 0xc40b 2199#define mmGDS_ATOM_BASE 0xc40c 2200#define mmGDS_ATOM_SIZE 0xc40d 2201#define mmGDS_ATOM_OFFSET0 0xc40e 2202#define mmGDS_ATOM_OFFSET1 0xc40f 2203#define mmGDS_ATOM_DST 0xc410 2204#define mmGDS_ATOM_OP 0xc411 2205#define mmGDS_ATOM_SRC0 0xc412 2206#define mmGDS_ATOM_SRC0_U 0xc413 2207#define mmGDS_ATOM_SRC1 0xc414 2208#define mmGDS_ATOM_SRC1_U 0xc415 2209#define mmGDS_ATOM_READ0 0xc416 2210#define mmGDS_ATOM_READ0_U 0xc417 2211#define mmGDS_ATOM_READ1 0xc418 2212#define mmGDS_ATOM_READ1_U 0xc419 2213#define mmGDS_GWS_RESOURCE_CNTL 0xc41a 2214#define mmGDS_GWS_RESOURCE 0xc41b 2215#define mmGDS_GWS_RESOURCE_CNT 0xc41c 2216#define mmGDS_OA_CNTL 0xc41d 2217#define mmGDS_OA_COUNTER 0xc41e 2218#define mmGDS_OA_ADDRESS 0xc41f 2219#define mmGDS_OA_INCDEC 0xc420 2220#define mmGDS_OA_RING_SIZE 0xc421 2221#define ixGDS_DEBUG_REG0 0x0 2222#define ixGDS_DEBUG_REG1 0x1 2223#define ixGDS_DEBUG_REG2 0x2 2224#define ixGDS_DEBUG_REG3 0x3 2225#define ixGDS_DEBUG_REG4 0x4 2226#define ixGDS_DEBUG_REG5 0x5 2227#define ixGDS_DEBUG_REG6 0x6 2228#define mmGDS_PERFCOUNTER0_SELECT 0xda80 2229#define mmGDS_PERFCOUNTER1_SELECT 0xda81 2230#define mmGDS_PERFCOUNTER2_SELECT 0xda82 2231#define mmGDS_PERFCOUNTER3_SELECT 0xda83 2232#define mmGDS_PERFCOUNTER0_LO 0xd280 2233#define mmGDS_PERFCOUNTER1_LO 0xd282 2234#define mmGDS_PERFCOUNTER2_LO 0xd284 2235#define mmGDS_PERFCOUNTER3_LO 0xd286 2236#define mmGDS_PERFCOUNTER0_HI 0xd281 2237#define mmGDS_PERFCOUNTER1_HI 0xd283 2238#define mmGDS_PERFCOUNTER2_HI 0xd285 2239#define mmGDS_PERFCOUNTER3_HI 0xd287 2240#define mmGDS_PERFCOUNTER0_SELECT1 0xda84 2241#define mmGDS_VMID0_BASE 0x3300 2242#define mmGDS_VMID1_BASE 0x3302 2243#define mmGDS_VMID2_BASE 0x3304 2244#define mmGDS_VMID3_BASE 0x3306 2245#define mmGDS_VMID4_BASE 0x3308 2246#define mmGDS_VMID5_BASE 0x330a 2247#define mmGDS_VMID6_BASE 0x330c 2248#define mmGDS_VMID7_BASE 0x330e 2249#define mmGDS_VMID8_BASE 0x3310 2250#define mmGDS_VMID9_BASE 0x3312 2251#define mmGDS_VMID10_BASE 0x3314 2252#define mmGDS_VMID11_BASE 0x3316 2253#define mmGDS_VMID12_BASE 0x3318 2254#define mmGDS_VMID13_BASE 0x331a 2255#define mmGDS_VMID14_BASE 0x331c 2256#define mmGDS_VMID15_BASE 0x331e 2257#define mmGDS_VMID0_SIZE 0x3301 2258#define mmGDS_VMID1_SIZE 0x3303 2259#define mmGDS_VMID2_SIZE 0x3305 2260#define mmGDS_VMID3_SIZE 0x3307 2261#define mmGDS_VMID4_SIZE 0x3309 2262#define mmGDS_VMID5_SIZE 0x330b 2263#define mmGDS_VMID6_SIZE 0x330d 2264#define mmGDS_VMID7_SIZE 0x330f 2265#define mmGDS_VMID8_SIZE 0x3311 2266#define mmGDS_VMID9_SIZE 0x3313 2267#define mmGDS_VMID10_SIZE 0x3315 2268#define mmGDS_VMID11_SIZE 0x3317 2269#define mmGDS_VMID12_SIZE 0x3319 2270#define mmGDS_VMID13_SIZE 0x331b 2271#define mmGDS_VMID14_SIZE 0x331d 2272#define mmGDS_VMID15_SIZE 0x331f 2273#define mmGDS_GWS_VMID0 0x3320 2274#define mmGDS_GWS_VMID1 0x3321 2275#define mmGDS_GWS_VMID2 0x3322 2276#define mmGDS_GWS_VMID3 0x3323 2277#define mmGDS_GWS_VMID4 0x3324 2278#define mmGDS_GWS_VMID5 0x3325 2279#define mmGDS_GWS_VMID6 0x3326 2280#define mmGDS_GWS_VMID7 0x3327 2281#define mmGDS_GWS_VMID8 0x3328 2282#define mmGDS_GWS_VMID9 0x3329 2283#define mmGDS_GWS_VMID10 0x332a 2284#define mmGDS_GWS_VMID11 0x332b 2285#define mmGDS_GWS_VMID12 0x332c 2286#define mmGDS_GWS_VMID13 0x332d 2287#define mmGDS_GWS_VMID14 0x332e 2288#define mmGDS_GWS_VMID15 0x332f 2289#define mmGDS_OA_VMID0 0x3330 2290#define mmGDS_OA_VMID1 0x3331 2291#define mmGDS_OA_VMID2 0x3332 2292#define mmGDS_OA_VMID3 0x3333 2293#define mmGDS_OA_VMID4 0x3334 2294#define mmGDS_OA_VMID5 0x3335 2295#define mmGDS_OA_VMID6 0x3336 2296#define mmGDS_OA_VMID7 0x3337 2297#define mmGDS_OA_VMID8 0x3338 2298#define mmGDS_OA_VMID9 0x3339 2299#define mmGDS_OA_VMID10 0x333a 2300#define mmGDS_OA_VMID11 0x333b 2301#define mmGDS_OA_VMID12 0x333c 2302#define mmGDS_OA_VMID13 0x333d 2303#define mmGDS_OA_VMID14 0x333e 2304#define mmGDS_OA_VMID15 0x333f 2305#define mmGDS_GWS_RESET0 0x3344 2306#define mmGDS_GWS_RESET1 0x3345 2307#define mmGDS_GWS_RESOURCE_RESET 0x3346 2308#define mmGDS_COMPUTE_MAX_WAVE_ID 0x3348 2309#define mmGDS_OA_RESET_MASK 0x3349 2310#define mmGDS_OA_RESET 0x334a 2311#define mmGDS_ENHANCE 0x334b 2312#define mmGDS_OA_CGPG_RESTORE 0x334c 2313#define mmCS_COPY_STATE 0xa1f3 2314#define mmGFX_COPY_STATE 0xa1f4 2315#define mmVGT_DRAW_INITIATOR 0xa1fc 2316#define mmVGT_EVENT_INITIATOR 0xa2a4 2317#define mmVGT_EVENT_ADDRESS_REG 0xa1fe 2318#define mmVGT_DMA_BASE_HI 0xa1f9 2319#define mmVGT_DMA_BASE 0xa1fa 2320#define mmVGT_DMA_INDEX_TYPE 0xa29f 2321#define mmVGT_DMA_NUM_INSTANCES 0xa2a2 2322#define mmIA_ENHANCE 0xa29c 2323#define mmVGT_DMA_SIZE 0xa29d 2324#define mmVGT_DMA_MAX_SIZE 0xa29e 2325#define mmVGT_DMA_PRIMITIVE_TYPE 0x2271 2326#define mmVGT_DMA_CONTROL 0x2272 2327#define mmVGT_IMMED_DATA 0xa1fd 2328#define mmVGT_INDEX_TYPE 0xc243 2329#define mmVGT_NUM_INDICES 0xc24c 2330#define mmVGT_NUM_INSTANCES 0xc24d 2331#define mmVGT_PRIMITIVE_TYPE 0xc242 2332#define mmVGT_PRIMITIVEID_EN 0xa2a1 2333#define mmVGT_PRIMITIVEID_RESET 0xa2a3 2334#define mmVGT_VTX_CNT_EN 0xa2ae 2335#define mmVGT_REUSE_OFF 0xa2ad 2336#define mmVGT_INSTANCE_STEP_RATE_0 0xa2a8 2337#define mmVGT_INSTANCE_STEP_RATE_1 0xa2a9 2338#define mmVGT_MAX_VTX_INDX 0xa100 2339#define mmVGT_MIN_VTX_INDX 0xa101 2340#define mmVGT_INDX_OFFSET 0xa102 2341#define mmVGT_VERTEX_REUSE_BLOCK_CNTL 0xa316 2342#define mmVGT_OUT_DEALLOC_CNTL 0xa317 2343#define mmVGT_MULTI_PRIM_IB_RESET_INDX 0xa103 2344#define mmVGT_MULTI_PRIM_IB_RESET_EN 0xa2a5 2345#define mmVGT_ENHANCE 0xa294 2346#define mmVGT_OUTPUT_PATH_CNTL 0xa284 2347#define mmVGT_HOS_CNTL 0xa285 2348#define mmVGT_HOS_MAX_TESS_LEVEL 0xa286 2349#define mmVGT_HOS_MIN_TESS_LEVEL 0xa287 2350#define mmVGT_HOS_REUSE_DEPTH 0xa288 2351#define mmVGT_GROUP_PRIM_TYPE 0xa289 2352#define mmVGT_GROUP_FIRST_DECR 0xa28a 2353#define mmVGT_GROUP_DECR 0xa28b 2354#define mmVGT_GROUP_VECT_0_CNTL 0xa28c 2355#define mmVGT_GROUP_VECT_1_CNTL 0xa28d 2356#define mmVGT_GROUP_VECT_0_FMT_CNTL 0xa28e 2357#define mmVGT_GROUP_VECT_1_FMT_CNTL 0xa28f 2358#define mmVGT_VTX_VECT_EJECT_REG 0x222c 2359#define mmVGT_DMA_DATA_FIFO_DEPTH 0x222d 2360#define mmVGT_DMA_REQ_FIFO_DEPTH 0x222e 2361#define mmVGT_DRAW_INIT_FIFO_DEPTH 0x222f 2362#define mmVGT_LAST_COPY_STATE 0x2230 2363#define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f 2364#define mmGC_USER_SHADER_ARRAY_CONFIG 0x2270 2365#define mmVGT_GS_MODE 0xa290 2366#define mmVGT_GS_ONCHIP_CNTL 0xa291 2367#define mmVGT_GS_OUT_PRIM_TYPE 0xa29b 2368#define mmVGT_CACHE_INVALIDATION 0x2231 2369#define mmVGT_RESET_DEBUG 0x2232 2370#define mmVGT_STRMOUT_DELAY 0x2233 2371#define mmVGT_FIFO_DEPTHS 0x2234 2372#define mmVGT_GS_PER_ES 0xa295 2373#define mmVGT_ES_PER_GS 0xa296 2374#define mmVGT_GS_PER_VS 0xa297 2375#define mmVGT_GS_VERTEX_REUSE 0x2235 2376#define mmVGT_MC_LAT_CNTL 0x2236 2377#define mmIA_CNTL_STATUS 0x2237 2378#define mmVGT_STRMOUT_CONFIG 0xa2e5 2379#define mmVGT_STRMOUT_BUFFER_SIZE_0 0xa2b4 2380#define mmVGT_STRMOUT_BUFFER_SIZE_1 0xa2b8 2381#define mmVGT_STRMOUT_BUFFER_SIZE_2 0xa2bc 2382#define mmVGT_STRMOUT_BUFFER_SIZE_3 0xa2c0 2383#define mmVGT_STRMOUT_BUFFER_OFFSET_0 0xa2b7 2384#define mmVGT_STRMOUT_BUFFER_OFFSET_1 0xa2bb 2385#define mmVGT_STRMOUT_BUFFER_OFFSET_2 0xa2bf 2386#define mmVGT_STRMOUT_BUFFER_OFFSET_3 0xa2c3 2387#define mmVGT_STRMOUT_VTX_STRIDE_0 0xa2b5 2388#define mmVGT_STRMOUT_VTX_STRIDE_1 0xa2b9 2389#define mmVGT_STRMOUT_VTX_STRIDE_2 0xa2bd 2390#define mmVGT_STRMOUT_VTX_STRIDE_3 0xa2c1 2391#define mmVGT_STRMOUT_BUFFER_CONFIG 0xa2e6 2392#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_0 0xc244 2393#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_1 0xc245 2394#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_2 0xc246 2395#define mmVGT_STRMOUT_BUFFER_FILLED_SIZE_3 0xc247 2396#define mmVGT_STRMOUT_DRAW_OPAQUE_OFFSET 0xa2ca 2397#define mmVGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE 0xa2cb 2398#define mmVGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE 0xa2cc 2399#define mmVGT_GS_MAX_VERT_OUT 0xa2ce 2400#define mmIA_VMID_OVERRIDE 0x2260 2401#define mmVGT_SHADER_STAGES_EN 0xa2d5 2402#define mmVGT_DISPATCH_DRAW_INDEX 0xa2dd 2403#define mmVGT_LS_HS_CONFIG 0xa2d6 2404#define mmVGT_DMA_LS_HS_CONFIG 0x2273 2405#define mmVGT_TF_PARAM 0xa2db 2406#define mmVGT_TF_RING_SIZE 0xc24e 2407#define mmVGT_SYS_CONFIG 0x2263 2408#define mmVGT_HS_OFFCHIP_PARAM 0xc24f 2409#define mmVGT_TF_MEMORY_BASE 0xc250 2410#define mmVGT_GS_INSTANCE_CNT 0xa2e4 2411#define mmIA_MULTI_VGT_PARAM 0xa2aa 2412#define mmVGT_VS_MAX_WAVE_ID 0x2268 2413#define mmVGT_ESGS_RING_SIZE 0xc240 2414#define mmVGT_GSVS_RING_SIZE 0xc241 2415#define mmVGT_GSVS_RING_OFFSET_1 0xa298 2416#define mmVGT_GSVS_RING_OFFSET_2 0xa299 2417#define mmVGT_GSVS_RING_OFFSET_3 0xa29a 2418#define mmVGT_ESGS_RING_ITEMSIZE 0xa2ab 2419#define mmVGT_GSVS_RING_ITEMSIZE 0xa2ac 2420#define mmVGT_GS_VERT_ITEMSIZE 0xa2d7 2421#define mmVGT_GS_VERT_ITEMSIZE_1 0xa2d8 2422#define mmVGT_GS_VERT_ITEMSIZE_2 0xa2d9 2423#define mmVGT_GS_VERT_ITEMSIZE_3 0xa2da 2424#define mmWD_CNTL_STATUS 0x223f 2425#define mmWD_ENHANCE 0xa2a0 2426#define mmGFX_PIPE_CONTROL 0x226d 2427#define mmGFX_PIPE_PRIORITY 0xf87f 2428#define mmCGTT_VGT_CLK_CTRL 0xf084 2429#define mmCGTT_IA_CLK_CTRL 0xf085 2430#define mmCGTT_WD_CLK_CTRL 0xf086 2431#define mmVGT_DEBUG_CNTL 0x2238 2432#define mmVGT_DEBUG_DATA 0x2239 2433#define mmIA_DEBUG_CNTL 0x223a 2434#define mmIA_DEBUG_DATA 0x223b 2435#define mmVGT_CNTL_STATUS 0x223c 2436#define mmWD_DEBUG_CNTL 0x223d 2437#define mmWD_DEBUG_DATA 0x223e 2438#define mmCC_GC_PRIM_CONFIG 0x2240 2439#define mmGC_USER_PRIM_CONFIG 0x2241 2440#define ixWD_DEBUG_REG0 0x0 2441#define ixWD_DEBUG_REG1 0x1 2442#define ixWD_DEBUG_REG2 0x2 2443#define ixWD_DEBUG_REG3 0x3 2444#define ixWD_DEBUG_REG4 0x4 2445#define ixWD_DEBUG_REG5 0x5 2446#define ixIA_DEBUG_REG0 0x0 2447#define ixIA_DEBUG_REG1 0x1 2448#define ixIA_DEBUG_REG2 0x2 2449#define ixIA_DEBUG_REG3 0x3 2450#define ixIA_DEBUG_REG4 0x4 2451#define ixIA_DEBUG_REG5 0x5 2452#define ixIA_DEBUG_REG6 0x6 2453#define ixIA_DEBUG_REG7 0x7 2454#define ixIA_DEBUG_REG8 0x8 2455#define ixIA_DEBUG_REG9 0x9 2456#define ixVGT_DEBUG_REG0 0x0 2457#define ixVGT_DEBUG_REG1 0x1 2458#define ixVGT_DEBUG_REG2 0x1e 2459#define ixVGT_DEBUG_REG3 0x1f 2460#define ixVGT_DEBUG_REG4 0x20 2461#define ixVGT_DEBUG_REG5 0x21 2462#define ixVGT_DEBUG_REG6 0x22 2463#define ixVGT_DEBUG_REG7 0x23 2464#define ixVGT_DEBUG_REG8 0x8 2465#define ixVGT_DEBUG_REG9 0x9 2466#define ixVGT_DEBUG_REG10 0xa 2467#define ixVGT_DEBUG_REG11 0xb 2468#define ixVGT_DEBUG_REG12 0xc 2469#define ixVGT_DEBUG_REG13 0xd 2470#define ixVGT_DEBUG_REG14 0xe 2471#define ixVGT_DEBUG_REG15 0xf 2472#define ixVGT_DEBUG_REG16 0x10 2473#define ixVGT_DEBUG_REG17 0x11 2474#define ixVGT_DEBUG_REG18 0x7 2475#define ixVGT_DEBUG_REG19 0x13 2476#define ixVGT_DEBUG_REG20 0x14 2477#define ixVGT_DEBUG_REG21 0x15 2478#define ixVGT_DEBUG_REG22 0x16 2479#define ixVGT_DEBUG_REG23 0x17 2480#define ixVGT_DEBUG_REG24 0x18 2481#define ixVGT_DEBUG_REG25 0x19 2482#define ixVGT_DEBUG_REG26 0x24 2483#define ixVGT_DEBUG_REG27 0x1b 2484#define ixVGT_DEBUG_REG28 0x1c 2485#define ixVGT_DEBUG_REG29 0x1d 2486#define ixVGT_DEBUG_REG30 0x25 2487#define ixVGT_DEBUG_REG31 0x26 2488#define ixVGT_DEBUG_REG32 0x27 2489#define ixVGT_DEBUG_REG33 0x28 2490#define ixVGT_DEBUG_REG34 0x29 2491#define ixVGT_DEBUG_REG35 0x2a 2492#define mmVGT_PERFCOUNTER_SEID_MASK 0xd894 2493#define mmVGT_PERFCOUNTER0_SELECT 0xd88c 2494#define mmVGT_PERFCOUNTER1_SELECT 0xd88d 2495#define mmVGT_PERFCOUNTER2_SELECT 0xd88e 2496#define mmVGT_PERFCOUNTER3_SELECT 0xd88f 2497#define mmVGT_PERFCOUNTER0_SELECT1 0xd890 2498#define mmVGT_PERFCOUNTER1_SELECT1 0xd891 2499#define mmVGT_PERFCOUNTER0_LO 0xd090 2500#define mmVGT_PERFCOUNTER1_LO 0xd092 2501#define mmVGT_PERFCOUNTER2_LO 0xd094 2502#define mmVGT_PERFCOUNTER3_LO 0xd096 2503#define mmVGT_PERFCOUNTER0_HI 0xd091 2504#define mmVGT_PERFCOUNTER1_HI 0xd093 2505#define mmVGT_PERFCOUNTER2_HI 0xd095 2506#define mmVGT_PERFCOUNTER3_HI 0xd097 2507#define mmIA_PERFCOUNTER0_SELECT 0xd884 2508#define mmIA_PERFCOUNTER1_SELECT 0xd885 2509#define mmIA_PERFCOUNTER2_SELECT 0xd886 2510#define mmIA_PERFCOUNTER3_SELECT 0xd887 2511#define mmIA_PERFCOUNTER0_SELECT1 0xd888 2512#define mmIA_PERFCOUNTER0_LO 0xd088 2513#define mmIA_PERFCOUNTER1_LO 0xd08a 2514#define mmIA_PERFCOUNTER2_LO 0xd08c 2515#define mmIA_PERFCOUNTER3_LO 0xd08e 2516#define mmIA_PERFCOUNTER0_HI 0xd089 2517#define mmIA_PERFCOUNTER1_HI 0xd08b 2518#define mmIA_PERFCOUNTER2_HI 0xd08d 2519#define mmIA_PERFCOUNTER3_HI 0xd08f 2520#define mmWD_PERFCOUNTER0_SELECT 0xd880 2521#define mmWD_PERFCOUNTER1_SELECT 0xd881 2522#define mmWD_PERFCOUNTER2_SELECT 0xd882 2523#define mmWD_PERFCOUNTER3_SELECT 0xd883 2524#define mmWD_PERFCOUNTER0_LO 0xd080 2525#define mmWD_PERFCOUNTER1_LO 0xd082 2526#define mmWD_PERFCOUNTER2_LO 0xd084 2527#define mmWD_PERFCOUNTER3_LO 0xd086 2528#define mmWD_PERFCOUNTER0_HI 0xd081 2529#define mmWD_PERFCOUNTER1_HI 0xd083 2530#define mmWD_PERFCOUNTER2_HI 0xd085 2531#define mmWD_PERFCOUNTER3_HI 0xd087 2532#define mmDIDT_IND_INDEX 0x3280 2533#define mmDIDT_IND_DATA 0x3281 2534#define ixDIDT_SQ_CTRL0 0x0 2535#define ixDIDT_SQ_CTRL1 0x1 2536#define ixDIDT_SQ_CTRL2 0x2 2537#define ixDIDT_SQ_WEIGHT0_3 0x10 2538#define ixDIDT_SQ_WEIGHT4_7 0x11 2539#define ixDIDT_SQ_WEIGHT8_11 0x12 2540#define ixDIDT_DB_CTRL0 0x20 2541#define ixDIDT_DB_CTRL1 0x21 2542#define ixDIDT_DB_CTRL2 0x22 2543#define ixDIDT_DB_WEIGHT0_3 0x30 2544#define ixDIDT_DB_WEIGHT4_7 0x31 2545#define ixDIDT_DB_WEIGHT8_11 0x32 2546#define ixDIDT_TD_CTRL0 0x40 2547#define ixDIDT_TD_CTRL1 0x41 2548#define ixDIDT_TD_CTRL2 0x42 2549#define ixDIDT_TD_WEIGHT0_3 0x50 2550#define ixDIDT_TD_WEIGHT4_7 0x51 2551#define ixDIDT_TD_WEIGHT8_11 0x52 2552#define ixDIDT_TCP_CTRL0 0x60 2553#define ixDIDT_TCP_CTRL1 0x61 2554#define ixDIDT_TCP_CTRL2 0x62 2555#define ixDIDT_TCP_WEIGHT0_3 0x70 2556#define ixDIDT_TCP_WEIGHT4_7 0x71 2557#define ixDIDT_TCP_WEIGHT8_11 0x72 2558 2559#endif /* GFX_7_2_D_H */ 2560