dce_11_0_enum.h revision 1.1 
1/*	$NetBSD: dce_11_0_enum.h,v 1.1 2018/08/27 01:34:49 riastradh Exp $	*/
2
3/*
4 * DCE_11_0 Register documentation
5 *
6 * Copyright (C) 2014  Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included
16 * in all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
22 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef DCE_11_0_ENUM_H
27#define DCE_11_0_ENUM_H
28
29typedef enum CRTC_CONTROL_CRTC_START_POINT_CNTL {
30	CRTC_CONTROL_CRTC_START_POINT_CNTL_NORMAL        = 0x0,
31	CRTC_CONTROL_CRTC_START_POINT_CNTL_DP            = 0x1,
32} CRTC_CONTROL_CRTC_START_POINT_CNTL;
33typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL {
34	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_NORMAL       = 0x0,
35	CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL_DP           = 0x1,
36} CRTC_CONTROL_CRTC_FIELD_NUMBER_CNTL;
37typedef enum CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL {
38	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE     = 0x0,
39	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_CURRENT= 0x1,
40	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_RESERVED    = 0x2,
41	CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL_DISABLE_FIRST= 0x3,
42} CRTC_CONTROL_CRTC_DISABLE_POINT_CNTL;
43typedef enum CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY {
44	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_FALSE    = 0x0,
45	CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY_TRUE     = 0x1,
46} CRTC_CONTROL_CRTC_FIELD_NUMBER_POLARITY;
47typedef enum CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE {
48	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_FALSE= 0x0,
49	CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE_TRUE = 0x1,
50} CRTC_CONTROL_CRTC_DISP_READ_REQUEST_DISABLE;
51typedef enum CRTC_CONTROL_CRTC_SOF_PULL_EN {
52	CRTC_CONTROL_CRTC_SOF_PULL_EN_FALSE              = 0x0,
53	CRTC_CONTROL_CRTC_SOF_PULL_EN_TRUE               = 0x1,
54} CRTC_CONTROL_CRTC_SOF_PULL_EN;
55typedef enum CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL {
56	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_FALSE       = 0x0,
57	CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL_TRUE        = 0x1,
58} CRTC_H_SYNC_B_CNTL_CRTC_H_SYNC_B_POL;
59typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL {
60	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_FALSE  = 0x0,
61	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL_TRUE   = 0x1,
62} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MAX_SEL;
63typedef enum CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL {
64	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_FALSE  = 0x0,
65	CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL_TRUE   = 0x1,
66} CRTC_V_TOTAL_CONTROL_CRTC_V_TOTAL_MIN_SEL;
67typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN {
68	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_FALSE= 0x0,
69	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN_TRUE= 0x1,
70} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_EN;
71typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC {
72	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE= 0x0,
73	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE= 0x1,
74} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_TO_MASTER_VSYNC;
75typedef enum CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT {
76	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_DISABLE= 0x0,
77	CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT_ENABLE= 0x1,
78} CRTC_V_TOTAL_CONTROL_CRTC_FORCE_LOCK_ON_EVENT;
79typedef enum CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK {
80	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_FRAME_START= 0x0,
81	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_A= 0x1,
82	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CRTC_TRIG_B= 0x2,
83	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_CURSOR_CHANGE= 0x3,
84	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_OTHER_CLIENT= 0x4,
85	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION0= 0x5,
86	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION1= 0x6,
87	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION2= 0x7,
88	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_MC_DC_REGION3= 0x8,
89	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_GRAPHIC_UPDATE_PENDING= 0x9,
90	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED2= 0xa,
91	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_INVALID= 0xb,
92	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_DOUBLE_BUFFER= 0xc,
93	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT_NOM= 0xd,
94	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_D1CRTC_VERT_COUNT= 0xe,
95	CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK_RESERVED= 0xf,
96} CRTC_V_TOTAL_CONTROL_CRTC_SET_V_TOTAL_MIN_MASK;
97typedef enum CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
98	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE= 0x0,
99	CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE= 0x1,
100} CRTC_V_TOTAL_INT_STATUS_CRTC_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
101typedef enum CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR {
102	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_FALSE= 0x0,
103	CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR_TRUE= 0x1,
104} CRTC_VSYNC_NOM_INT_STATUS_CRTC_VSYNC_NOM_INT_CLEAR;
105typedef enum CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL {
106	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_FALSE       = 0x0,
107	CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL_TRUE        = 0x1,
108} CRTC_V_SYNC_B_CNTL_CRTC_V_SYNC_B_POL;
109typedef enum CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN {
110	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_FALSE     = 0x0,
111	CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN_TRUE      = 0x1,
112} CRTC_DTMTEST_CNTL_CRTC_DTMTEST_CRTC_EN;
113typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT {
114	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
115	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
116	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICF= 0x5,
117	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICE= 0x6,
118	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCA  = 0x7,
119	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCA  = 0x8,
120	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VSYNCB  = 0x9,
121	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HSYNCB  = 0xa,
122	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD1    = 0xb,
123	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_HPD2    = 0xc,
124	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICD= 0xd,
125	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICC= 0xe,
126	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_VIDEO   = 0xf,
127	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL0   = 0x10,
128	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL1   = 0x11,
129	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL2   = 0x12,
130	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IBLON   = 0x13,
131	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICA= 0x14,
132	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_GENERICB= 0x15,
133	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_IGSL_ALLOW= 0x16,
134	CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT_MANUAL_FLOW= 0x17,
135} CRTC_TRIGA_CNTL_CRTC_TRIGA_SOURCE_SELECT;
136typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT {
137	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_INTERLACE= 0x1,
138	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICA= 0x2,
139	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICB= 0x3,
140	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCA= 0x4,
141	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_HSYNCB= 0x5,
142	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_VIDEO = 0x6,
143	CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT_GENERICC= 0x7,
144} CRTC_TRIGA_CNTL_CRTC_TRIGA_POLARITY_SELECT;
145typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN {
146	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_FALSE= 0x0,
147	CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x1,
148} CRTC_TRIGA_CNTL_CRTC_TRIGA_RESYNC_BYPASS_EN;
149typedef enum CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR {
150	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_FALSE           = 0x0,
151	CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR_TRUE            = 0x1,
152} CRTC_TRIGA_CNTL_CRTC_TRIGA_CLEAR;
153typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT {
154	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA_OTHER= 0x1,
155	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA_OTHER= 0x2,
156	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICF= 0x5,
157	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICE= 0x6,
158	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCA  = 0x7,
159	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCA  = 0x8,
160	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VSYNCB  = 0x9,
161	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HSYNCB  = 0xa,
162	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD1    = 0xb,
163	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_HPD2    = 0xc,
164	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICD= 0xd,
165	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICC= 0xe,
166	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_VIDEO   = 0xf,
167	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL0   = 0x10,
168	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL1   = 0x11,
169	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL2   = 0x12,
170	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IBLON   = 0x13,
171	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICA= 0x14,
172	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_GENERICB= 0x15,
173	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_IGSL_ALLOW= 0x16,
174	CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT_MANUAL_FLOW= 0x17,
175} CRTC_TRIGB_CNTL_CRTC_TRIGB_SOURCE_SELECT;
176typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT {
177	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_INTERLACE= 0x1,
178	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICA= 0x2,
179	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICB= 0x3,
180	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCA= 0x4,
181	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_HSYNCB= 0x5,
182	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_VIDEO = 0x6,
183	CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT_GENERICC= 0x7,
184} CRTC_TRIGB_CNTL_CRTC_TRIGB_POLARITY_SELECT;
185typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN {
186	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_FALSE= 0x0,
187	CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x1,
188} CRTC_TRIGB_CNTL_CRTC_TRIGB_RESYNC_BYPASS_EN;
189typedef enum CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR {
190	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_FALSE           = 0x0,
191	CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR_TRUE            = 0x1,
192} CRTC_TRIGB_CNTL_CRTC_TRIGB_CLEAR;
193typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE {
194	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_DISABLE= 0x0,
195	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT= 0x1,
196	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT= 0x2,
197	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE_RESERVED= 0x3,
198} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_MODE;
199typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK {
200	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_FALSE= 0x0,
201	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK_TRUE= 0x1,
202} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CHECK;
203typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL {
204	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_FALSE= 0x0,
205	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL_TRUE= 0x1,
206} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_TRIG_SEL;
207typedef enum CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR {
208	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_FALSE= 0x0,
209	CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR_TRUE= 0x1,
210} CRTC_FORCE_COUNT_NOW_CNTL_CRTC_FORCE_COUNT_NOW_CLEAR;
211typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT {
212	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC0= 0x0,
213	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICF= 0x1,
214	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICE= 0x2,
215	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD1= 0x3,
216	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_HPD2= 0x4,
217	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA= 0x5,
218	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK= 0x6,
219	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA= 0x7,
220	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK= 0x8,
221	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_DVOCLK= 0x9,
222	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_MANUAL= 0xa,
223	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_LOGIC1= 0xb,
224	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICB= 0xc,
225	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICA= 0xd,
226	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICD= 0xe,
227	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GENERICC= 0xf,
228	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT_GPIO= 0x10,
229} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_SOURCE_SELECT;
230typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY {
231	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_FALSE= 0x0,
232	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY_TRUE= 0x1,
233} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_POLARITY;
234typedef enum CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY {
235	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_FALSE= 0x0,
236	CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY_TRUE= 0x1,
237} CRTC_FLOW_CONTROL_CRTC_FLOW_CONTROL_GRANULARITY;
238typedef enum CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE {
239	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_NO= 0x0,
240	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RIGHT= 0x1,
241	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_LEFT= 0x2,
242	CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE_RESERVED= 0x3,
243} CRTC_STEREO_FORCE_NEXT_EYE_CRTC_STEREO_FORCE_NEXT_EYE;
244typedef enum CRTC_CONTROL_CRTC_MASTER_EN {
245	CRTC_CONTROL_CRTC_MASTER_EN_FALSE                = 0x0,
246	CRTC_CONTROL_CRTC_MASTER_EN_TRUE                 = 0x1,
247} CRTC_CONTROL_CRTC_MASTER_EN;
248typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN {
249	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_FALSE      = 0x0,
250	CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN_TRUE       = 0x1,
251} CRTC_BLANK_CONTROL_CRTC_BLANK_DATA_EN;
252typedef enum CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE {
253	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_FALSE      = 0x0,
254	CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE_TRUE       = 0x1,
255} CRTC_BLANK_CONTROL_CRTC_BLANK_DE_MODE;
256typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE {
257	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_FALSE= 0x0,
258	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE_TRUE= 0x1,
259} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_ENABLE;
260typedef enum CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD {
261	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT= 0x0,
262	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_ODD= 0x1,
263	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_EVEN= 0x2,
264	CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD_NOT2= 0x3,
265} CRTC_INTERLACE_CONTROL_CRTC_INTERLACE_FORCE_NEXT_FIELD;
266typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY {
267	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_FALSE= 0x0,
268	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY_TRUE= 0x1,
269} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_INDICATION_OUTPUT_POLARITY;
270typedef enum CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT {
271	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_FALSE= 0x0,
272	CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT_TRUE= 0x1,
273} CRTC_FIELD_INDICATION_CONTROL_CRTC_FIELD_ALIGNMENT;
274typedef enum CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN {
275	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_FALSE  = 0x0,
276	CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN_TRUE   = 0x1,
277} CRTC_COUNT_CONTROL_CRTC_HORZ_COUNT_BY2_EN;
278typedef enum CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE {
279	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE= 0x0,
280	CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE= 0x1,
281} CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE;
282typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR {
283	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE= 0x0,
284	CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE= 0x1,
285} CRTC_VERT_SYNC_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_CLEAR;
286typedef enum CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE {
287	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_DISABLE= 0x0,
288	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERA= 0x1,
289	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_TRIGGERB= 0x2,
290	CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE_RESERVED= 0x3,
291} CRTC_VERT_SYNC_CONTROL_CRTC_AUTO_FORCE_VSYNC_MODE;
292typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY {
293	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_FALSE= 0x0,
294	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY_TRUE= 0x1,
295} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_OUTPUT_POLARITY;
296typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY {
297	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_FALSE= 0x0,
298	CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY_TRUE= 0x1,
299} CRTC_STEREO_CONTROL_CRTC_STEREO_SYNC_SELECT_POLARITY;
300typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY {
301	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_FALSE= 0x0,
302	CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY_TRUE= 0x1,
303} CRTC_STEREO_CONTROL_CRTC_STEREO_EYE_FLAG_POLARITY;
304typedef enum CRTC_STEREO_CONTROL_CRTC_STEREO_EN {
305	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_FALSE         = 0x0,
306	CRTC_STEREO_CONTROL_CRTC_STEREO_EN_TRUE          = 0x1,
307} CRTC_STEREO_CONTROL_CRTC_STEREO_EN;
308typedef enum CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR {
309	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_FALSE   = 0x0,
310	CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR_TRUE    = 0x1,
311} CRTC_SNAPSHOT_STATUS_CRTC_SNAPSHOT_CLEAR;
312typedef enum CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL {
313	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_DISABLE= 0x0,
314	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA= 0x1,
315	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB= 0x2,
316	CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL_RESERVED= 0x3,
317} CRTC_SNAPSHOT_CONTROL_CRTC_AUTO_SNAPSHOT_TRIG_SEL;
318typedef enum CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY {
319	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_FALSE= 0x0,
320	CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY_TRUE= 0x1,
321} CRTC_START_LINE_CONTROL_CRTC_PROGRESSIVE_START_LINE_EARLY;
322typedef enum CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY {
323	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_FALSE= 0x0,
324	CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY_TRUE= 0x1,
325} CRTC_START_LINE_CONTROL_CRTC_INTERLACE_START_LINE_EARLY;
326typedef enum CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN {
327	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_FALSE= 0x0,
328	CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN_TRUE= 0x1,
329} CRTC_START_LINE_CONTROL_CRTC_LEGACY_REQUESTOR_EN;
330typedef enum CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN {
331	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_FALSE   = 0x0,
332	CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN_TRUE    = 0x1,
333} CRTC_START_LINE_CONTROL_CRTC_PREFETCH_EN;
334typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK {
335	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_FALSE= 0x0,
336	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK_TRUE= 0x1,
337} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_MSK;
338typedef enum CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE {
339	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_FALSE= 0x0,
340	CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE_TRUE= 0x1,
341} CRTC_INTERRUPT_CONTROL_CRTC_SNAPSHOT_INT_TYPE;
342typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK {
343	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_FALSE= 0x0,
344	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK_TRUE= 0x1,
345} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_MSK;
346typedef enum CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE {
347	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_FALSE= 0x0,
348	CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE_TRUE= 0x1,
349} CRTC_INTERRUPT_CONTROL_CRTC_V_UPDATE_INT_TYPE;
350typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK {
351	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_FALSE= 0x0,
352	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK_TRUE= 0x1,
353} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_MSK;
354typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE {
355	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_FALSE= 0x0,
356	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE_TRUE= 0x1,
357} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_COUNT_NOW_INT_TYPE;
358typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK {
359	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE= 0x0,
360	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE= 0x1,
361} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_MSK;
362typedef enum CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
363	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE= 0x0,
364	CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE= 0x1,
365} CRTC_INTERRUPT_CONTROL_CRTC_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
366typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK {
367	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_FALSE  = 0x0,
368	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK_TRUE   = 0x1,
369} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_MSK;
370typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE {
371	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_FALSE = 0x0,
372	CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE_TRUE  = 0x1,
373} CRTC_INTERRUPT_CONTROL_CRTC_TRIGA_INT_TYPE;
374typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK {
375	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_FALSE  = 0x0,
376	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK_TRUE   = 0x1,
377} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_MSK;
378typedef enum CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE {
379	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_FALSE = 0x0,
380	CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE_TRUE  = 0x1,
381} CRTC_INTERRUPT_CONTROL_CRTC_TRIGB_INT_TYPE;
382typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK {
383	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_FALSE= 0x0,
384	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK_TRUE= 0x1,
385} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_MSK;
386typedef enum CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE {
387	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_FALSE= 0x0,
388	CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE_TRUE= 0x1,
389} CRTC_INTERRUPT_CONTROL_CRTC_VSYNC_NOM_INT_TYPE;
390typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK {
391	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_FALSE= 0x0,
392	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK_TRUE= 0x1,
393} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_MSK;
394typedef enum CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE {
395	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_FALSE= 0x0,
396	CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE_TRUE= 0x1,
397} CRTC_INTERRUPT_CONTROL_CRTC_GSL_VSYNC_GAP_INT_TYPE;
398typedef enum CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK {
399	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_FALSE          = 0x0,
400	CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK_TRUE           = 0x1,
401} CRTC_UPDATE_LOCK_CRTC_UPDATE_LOCK;
402typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY {
403	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_FALSE= 0x0,
404	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY_TRUE= 0x1,
405} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_UPDATE_INSTANTLY;
406typedef enum CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN {
407	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE= 0x0,
408	CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE= 0x1,
409} CRTC_DOUBLE_BUFFER_CONTROL_CRTC_BLANK_DATA_DOUBLE_BUFFER_EN;
410typedef enum CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE {
411	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_FALSE= 0x0,
412	CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE_TRUE= 0x1,
413} CRTC_VGA_PARAMETER_CAPTURE_MODE_CRTC_VGA_PARAMETER_CAPTURE_MODE;
414typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN {
415	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_FALSE= 0x0,
416	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN_TRUE= 0x1,
417} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_EN;
418typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE {
419	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_RGB= 0x0,
420	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR601= 0x1,
421	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_YCBCR709= 0x2,
422	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_VBARS= 0x3,
423	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_HBARS= 0x4,
424	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_SRRGB= 0x5,
425	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_DRRGB= 0x6,
426	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE_XRBIAS= 0x7,
427} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_MODE;
428typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE {
429	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_FALSE= 0x0,
430	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE_TRUE= 0x1,
431} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_DYNAMIC_RANGE;
432typedef enum CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT {
433	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_6BPC= 0x0,
434	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_8BPC= 0x1,
435	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_10BPC= 0x2,
436	CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT_RESERVED= 0x3,
437} CRTC_TEST_PATTERN_CONTROL_CRTC_TEST_PATTERN_COLOR_FORMAT;
438typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
439	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE      = 0x0,
440	MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE       = 0x1,
441} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
442typedef enum MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK {
443	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_FALSE= 0x0,
444	MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK_TRUE= 0x1,
445} MASTER_UPDATE_LOCK_GSL_CONTROL_MASTER_UPDATE_LOCK;
446typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
447	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE   = 0x0,
448	MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE    = 0x1,
449} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
450typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_MODE {
451	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BETWEEN    = 0x0,
452	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_HSYNCA     = 0x1,
453	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_VSYNCA     = 0x2,
454	MASTER_UPDATE_MODE_MASTER_UPDATE_MODE_BEFORE     = 0x3,
455} MASTER_UPDATE_MODE_MASTER_UPDATE_MODE;
456typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
457	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH= 0x0,
458	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_EVEN= 0x1,
459	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_ODD= 0x2,
460	MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED= 0x3,
461} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
462typedef enum CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE {
463	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DISABLE= 0x0,
464	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_DEBUG= 0x1,
465	CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE_NORMAL= 0x2,
466} CRTC_MVP_INBAND_CNTL_INSERT_CRTC_MVP_INBAND_OUT_MODE;
467typedef enum CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR {
468	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_FALSE        = 0x0,
469	CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR_TRUE         = 0x1,
470} CRTC_MVP_STATUS_CRTC_FLIP_NOW_CLEAR;
471typedef enum CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR {
472	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE= 0x0,
473	CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE= 0x1,
474} CRTC_MVP_STATUS_CRTC_AFR_HSYNC_SWITCH_DONE_CLEAR;
475typedef enum CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR {
476	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_FALSE= 0x0,
477	CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR_TRUE= 0x1,
478} CRTC_V_UPDATE_INT_STATUS_CRTC_V_UPDATE_INT_CLEAR;
479typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
480	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE= 0x0,
481	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE= 0x1,
482} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
483typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE {
484	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE= 0x0,
485	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE= 0x1,
486} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_ENABLE;
487typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR {
488	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_FALSE= 0x0,
489	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR_TRUE= 0x1,
490} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_CLEAR;
491typedef enum CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE {
492	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_FALSE= 0x0,
493	CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE_TRUE= 0x1,
494} CRTC_VERTICAL_INTERRUPT0_CONTROL_CRTC_VERTICAL_INTERRUPT0_INT_TYPE;
495typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR {
496	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE= 0x0,
497	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR_TRUE= 0x1,
498} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_CLEAR;
499typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE {
500	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE= 0x0,
501	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE= 0x1,
502} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_ENABLE;
503typedef enum CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE {
504	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_FALSE= 0x0,
505	CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE_TRUE= 0x1,
506} CRTC_VERTICAL_INTERRUPT1_CONTROL_CRTC_VERTICAL_INTERRUPT1_INT_TYPE;
507typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR {
508	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE= 0x0,
509	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR_TRUE= 0x1,
510} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_CLEAR;
511typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE {
512	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE= 0x0,
513	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE= 0x1,
514} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_ENABLE;
515typedef enum CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE {
516	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_FALSE= 0x0,
517	CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE_TRUE= 0x1,
518} CRTC_VERTICAL_INTERRUPT2_CONTROL_CRTC_VERTICAL_INTERRUPT2_INT_TYPE;
519typedef enum CRTC_CRC_CNTL_CRTC_CRC_EN {
520	CRTC_CRC_CNTL_CRTC_CRC_EN_FALSE                  = 0x0,
521	CRTC_CRC_CNTL_CRTC_CRC_EN_TRUE                   = 0x1,
522} CRTC_CRC_CNTL_CRTC_CRC_EN;
523typedef enum CRTC_CRC_CNTL_CRTC_CRC_CONT_EN {
524	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_FALSE             = 0x0,
525	CRTC_CRC_CNTL_CRTC_CRC_CONT_EN_TRUE              = 0x1,
526} CRTC_CRC_CNTL_CRTC_CRC_CONT_EN;
527typedef enum CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE {
528	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_LEFT          = 0x0,
529	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_RIGHT         = 0x1,
530	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_EYES     = 0x2,
531	CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE_BOTH_FIELDS   = 0x3,
532} CRTC_CRC_CNTL_CRTC_CRC_STEREO_MODE;
533typedef enum CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE {
534	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_TOP        = 0x0,
535	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTTOM     = 0x1,
536	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_BOTTOM= 0x2,
537	CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE_BOTH_FIELD = 0x3,
538} CRTC_CRC_CNTL_CRTC_CRC_INTERLACE_MODE;
539typedef enum CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS {
540	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE= 0x0,
541	CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE= 0x1,
542} CRTC_CRC_CNTL_CRTC_CRC_USE_NEW_AND_REPEATED_PIXELS;
543typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT {
544	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UAB          = 0x0,
545	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_UA_B         = 0x1,
546	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_AB         = 0x2,
547	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_U_A_B        = 0x3,
548	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IAB          = 0x4,
549	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_IA_B         = 0x5,
550	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_AB         = 0x6,
551	CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT_I_A_B        = 0x7,
552} CRTC_CRC_CNTL_CRTC_CRTC_CRC0_SELECT;
553typedef enum CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT {
554	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UAB          = 0x0,
555	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_UA_B         = 0x1,
556	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_AB         = 0x2,
557	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_U_A_B        = 0x3,
558	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IAB          = 0x4,
559	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_IA_B         = 0x5,
560	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_AB         = 0x6,
561	CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT_I_A_B        = 0x7,
562} CRTC_CRC_CNTL_CRTC_CRTC_CRC1_SELECT;
563typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE {
564	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_FALSE= 0x0,
565	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE_TRUE= 0x1,
566} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_ENABLE;
567typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR {
568	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_FALSE= 0x0,
569	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR_TRUE= 0x1,
570} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_CLEAR;
571typedef enum CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE {
572	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_FALSE= 0x0,
573	CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE_TRUE= 0x1,
574} CRTC_STATIC_SCREEN_CONTROL_CRTC_CPU_SS_INT_TYPE;
575typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN {
576	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_FALSE= 0x0,
577	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_TRUE= 0x1,
578} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN;
579typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB {
580	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_FALSE= 0x0,
581	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB_TRUE= 0x1,
582} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_EN_DB;
583typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE {
584	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH= 0x0,
585	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE= 0x1,
586	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE= 0x2,
587	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE_RESERVED= 0x3,
588} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_V_UPDATE_MODE;
589typedef enum CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR {
590	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_FALSE= 0x0,
591	CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR_TRUE= 0x1,
592} CRTC_3D_STRUCTURE_CONTROL_CRTC_3D_STRUCTURE_STEREO_SEL_OVR;
593typedef enum CRTC_V_SYNC_A_POL {
594	CRTC_V_SYNC_A_POL_HIGH                           = 0x0,
595	CRTC_V_SYNC_A_POL_LOW                            = 0x1,
596} CRTC_V_SYNC_A_POL;
597typedef enum CRTC_H_SYNC_A_POL {
598	CRTC_H_SYNC_A_POL_HIGH                           = 0x0,
599	CRTC_H_SYNC_A_POL_LOW                            = 0x1,
600} CRTC_H_SYNC_A_POL;
601typedef enum CRTC_HORZ_REPETITION_COUNT {
602	CRTC_HORZ_REPETITION_COUNT_0                     = 0x0,
603	CRTC_HORZ_REPETITION_COUNT_1                     = 0x1,
604	CRTC_HORZ_REPETITION_COUNT_2                     = 0x2,
605	CRTC_HORZ_REPETITION_COUNT_3                     = 0x3,
606	CRTC_HORZ_REPETITION_COUNT_4                     = 0x4,
607	CRTC_HORZ_REPETITION_COUNT_5                     = 0x5,
608	CRTC_HORZ_REPETITION_COUNT_6                     = 0x6,
609	CRTC_HORZ_REPETITION_COUNT_7                     = 0x7,
610	CRTC_HORZ_REPETITION_COUNT_8                     = 0x8,
611	CRTC_HORZ_REPETITION_COUNT_9                     = 0x9,
612	CRTC_HORZ_REPETITION_COUNT_10                    = 0xa,
613	CRTC_HORZ_REPETITION_COUNT_11                    = 0xb,
614	CRTC_HORZ_REPETITION_COUNT_12                    = 0xc,
615	CRTC_HORZ_REPETITION_COUNT_13                    = 0xd,
616	CRTC_HORZ_REPETITION_COUNT_14                    = 0xe,
617	CRTC_HORZ_REPETITION_COUNT_15                    = 0xf,
618} CRTC_HORZ_REPETITION_COUNT;
619typedef enum PERFCOUNTER_CVALUE_SEL {
620	PERFCOUNTER_CVALUE_SEL_47_0                      = 0x0,
621	PERFCOUNTER_CVALUE_SEL_15_0                      = 0x1,
622	PERFCOUNTER_CVALUE_SEL_31_16                     = 0x2,
623	PERFCOUNTER_CVALUE_SEL_47_32                     = 0x3,
624	PERFCOUNTER_CVALUE_SEL_11_0                      = 0x4,
625	PERFCOUNTER_CVALUE_SEL_23_12                     = 0x5,
626	PERFCOUNTER_CVALUE_SEL_35_24                     = 0x6,
627	PERFCOUNTER_CVALUE_SEL_47_36                     = 0x7,
628} PERFCOUNTER_CVALUE_SEL;
629typedef enum PERFCOUNTER_INC_MODE {
630	PERFCOUNTER_INC_MODE_MULTI_BIT                   = 0x0,
631	PERFCOUNTER_INC_MODE_BOTH_EDGE                   = 0x1,
632	PERFCOUNTER_INC_MODE_LSB                         = 0x2,
633	PERFCOUNTER_INC_MODE_POS_EDGE                    = 0x3,
634} PERFCOUNTER_INC_MODE;
635typedef enum PERFCOUNTER_HW_CNTL_SEL {
636	PERFCOUNTER_HW_CNTL_SEL_RUNEN                    = 0x0,
637	PERFCOUNTER_HW_CNTL_SEL_CNTOFF                   = 0x1,
638} PERFCOUNTER_HW_CNTL_SEL;
639typedef enum PERFCOUNTER_RUNEN_MODE {
640	PERFCOUNTER_RUNEN_MODE_LEVEL                     = 0x0,
641	PERFCOUNTER_RUNEN_MODE_EDGE                      = 0x1,
642} PERFCOUNTER_RUNEN_MODE;
643typedef enum PERFCOUNTER_CNTOFF_START_DIS {
644	PERFCOUNTER_CNTOFF_START_ENABLE                  = 0x0,
645	PERFCOUNTER_CNTOFF_START_DISABLE                 = 0x1,
646} PERFCOUNTER_CNTOFF_START_DIS;
647typedef enum PERFCOUNTER_RESTART_EN {
648	PERFCOUNTER_RESTART_DISABLE                      = 0x0,
649	PERFCOUNTER_RESTART_ENABLE                       = 0x1,
650} PERFCOUNTER_RESTART_EN;
651typedef enum PERFCOUNTER_INT_EN {
652	PERFCOUNTER_INT_DISABLE                          = 0x0,
653	PERFCOUNTER_INT_ENABLE                           = 0x1,
654} PERFCOUNTER_INT_EN;
655typedef enum PERFCOUNTER_OFF_MASK {
656	PERFCOUNTER_OFF_MASK_DISABLE                     = 0x0,
657	PERFCOUNTER_OFF_MASK_ENABLE                      = 0x1,
658} PERFCOUNTER_OFF_MASK;
659typedef enum PERFCOUNTER_ACTIVE {
660	PERFCOUNTER_IS_IDLE                              = 0x0,
661	PERFCOUNTER_IS_ACTIVE                            = 0x1,
662} PERFCOUNTER_ACTIVE;
663typedef enum PERFCOUNTER_INT_TYPE {
664	PERFCOUNTER_INT_TYPE_LEVEL                       = 0x0,
665	PERFCOUNTER_INT_TYPE_PULSE                       = 0x1,
666} PERFCOUNTER_INT_TYPE;
667typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
668	PERFCOUNTER_COUNTED_VALUE_TYPE_ACC               = 0x0,
669	PERFCOUNTER_COUNTED_VALUE_TYPE_MAX               = 0x1,
670} PERFCOUNTER_COUNTED_VALUE_TYPE;
671typedef enum PERFCOUNTER_CNTL_SEL {
672	PERFCOUNTER_CNTL_SEL_0                           = 0x0,
673	PERFCOUNTER_CNTL_SEL_1                           = 0x1,
674	PERFCOUNTER_CNTL_SEL_2                           = 0x2,
675	PERFCOUNTER_CNTL_SEL_3                           = 0x3,
676	PERFCOUNTER_CNTL_SEL_4                           = 0x4,
677	PERFCOUNTER_CNTL_SEL_5                           = 0x5,
678	PERFCOUNTER_CNTL_SEL_6                           = 0x6,
679	PERFCOUNTER_CNTL_SEL_7                           = 0x7,
680} PERFCOUNTER_CNTL_SEL;
681typedef enum PERFCOUNTER_CNT0_STATE {
682	PERFCOUNTER_CNT0_STATE_RESET                     = 0x0,
683	PERFCOUNTER_CNT0_STATE_START                     = 0x1,
684	PERFCOUNTER_CNT0_STATE_FREEZE                    = 0x2,
685	PERFCOUNTER_CNT0_STATE_HW                        = 0x3,
686} PERFCOUNTER_CNT0_STATE;
687typedef enum PERFCOUNTER_STATE_SEL0 {
688	PERFCOUNTER_STATE_SEL0_GLOBAL                    = 0x0,
689	PERFCOUNTER_STATE_SEL0_LOCAL                     = 0x1,
690} PERFCOUNTER_STATE_SEL0;
691typedef enum PERFCOUNTER_CNT1_STATE {
692	PERFCOUNTER_CNT1_STATE_RESET                     = 0x0,
693	PERFCOUNTER_CNT1_STATE_START                     = 0x1,
694	PERFCOUNTER_CNT1_STATE_FREEZE                    = 0x2,
695	PERFCOUNTER_CNT1_STATE_HW                        = 0x3,
696} PERFCOUNTER_CNT1_STATE;
697typedef enum PERFCOUNTER_STATE_SEL1 {
698	PERFCOUNTER_STATE_SEL1_GLOBAL                    = 0x0,
699	PERFCOUNTER_STATE_SEL1_LOCAL                     = 0x1,
700} PERFCOUNTER_STATE_SEL1;
701typedef enum PERFCOUNTER_CNT2_STATE {
702	PERFCOUNTER_CNT2_STATE_RESET                     = 0x0,
703	PERFCOUNTER_CNT2_STATE_START                     = 0x1,
704	PERFCOUNTER_CNT2_STATE_FREEZE                    = 0x2,
705	PERFCOUNTER_CNT2_STATE_HW                        = 0x3,
706} PERFCOUNTER_CNT2_STATE;
707typedef enum PERFCOUNTER_STATE_SEL2 {
708	PERFCOUNTER_STATE_SEL2_GLOBAL                    = 0x0,
709	PERFCOUNTER_STATE_SEL2_LOCAL                     = 0x1,
710} PERFCOUNTER_STATE_SEL2;
711typedef enum PERFCOUNTER_CNT3_STATE {
712	PERFCOUNTER_CNT3_STATE_RESET                     = 0x0,
713	PERFCOUNTER_CNT3_STATE_START                     = 0x1,
714	PERFCOUNTER_CNT3_STATE_FREEZE                    = 0x2,
715	PERFCOUNTER_CNT3_STATE_HW                        = 0x3,
716} PERFCOUNTER_CNT3_STATE;
717typedef enum PERFCOUNTER_STATE_SEL3 {
718	PERFCOUNTER_STATE_SEL3_GLOBAL                    = 0x0,
719	PERFCOUNTER_STATE_SEL3_LOCAL                     = 0x1,
720} PERFCOUNTER_STATE_SEL3;
721typedef enum PERFCOUNTER_CNT4_STATE {
722	PERFCOUNTER_CNT4_STATE_RESET                     = 0x0,
723	PERFCOUNTER_CNT4_STATE_START                     = 0x1,
724	PERFCOUNTER_CNT4_STATE_FREEZE                    = 0x2,
725	PERFCOUNTER_CNT4_STATE_HW                        = 0x3,
726} PERFCOUNTER_CNT4_STATE;
727typedef enum PERFCOUNTER_STATE_SEL4 {
728	PERFCOUNTER_STATE_SEL4_GLOBAL                    = 0x0,
729	PERFCOUNTER_STATE_SEL4_LOCAL                     = 0x1,
730} PERFCOUNTER_STATE_SEL4;
731typedef enum PERFCOUNTER_CNT5_STATE {
732	PERFCOUNTER_CNT5_STATE_RESET                     = 0x0,
733	PERFCOUNTER_CNT5_STATE_START                     = 0x1,
734	PERFCOUNTER_CNT5_STATE_FREEZE                    = 0x2,
735	PERFCOUNTER_CNT5_STATE_HW                        = 0x3,
736} PERFCOUNTER_CNT5_STATE;
737typedef enum PERFCOUNTER_STATE_SEL5 {
738	PERFCOUNTER_STATE_SEL5_GLOBAL                    = 0x0,
739	PERFCOUNTER_STATE_SEL5_LOCAL                     = 0x1,
740} PERFCOUNTER_STATE_SEL5;
741typedef enum PERFCOUNTER_CNT6_STATE {
742	PERFCOUNTER_CNT6_STATE_RESET                     = 0x0,
743	PERFCOUNTER_CNT6_STATE_START                     = 0x1,
744	PERFCOUNTER_CNT6_STATE_FREEZE                    = 0x2,
745	PERFCOUNTER_CNT6_STATE_HW                        = 0x3,
746} PERFCOUNTER_CNT6_STATE;
747typedef enum PERFCOUNTER_STATE_SEL6 {
748	PERFCOUNTER_STATE_SEL6_GLOBAL                    = 0x0,
749	PERFCOUNTER_STATE_SEL6_LOCAL                     = 0x1,
750} PERFCOUNTER_STATE_SEL6;
751typedef enum PERFCOUNTER_CNT7_STATE {
752	PERFCOUNTER_CNT7_STATE_RESET                     = 0x0,
753	PERFCOUNTER_CNT7_STATE_START                     = 0x1,
754	PERFCOUNTER_CNT7_STATE_FREEZE                    = 0x2,
755	PERFCOUNTER_CNT7_STATE_HW                        = 0x3,
756} PERFCOUNTER_CNT7_STATE;
757typedef enum PERFCOUNTER_STATE_SEL7 {
758	PERFCOUNTER_STATE_SEL7_GLOBAL                    = 0x0,
759	PERFCOUNTER_STATE_SEL7_LOCAL                     = 0x1,
760} PERFCOUNTER_STATE_SEL7;
761typedef enum PERFMON_STATE {
762	PERFMON_STATE_RESET                              = 0x0,
763	PERFMON_STATE_START                              = 0x1,
764	PERFMON_STATE_FREEZE                             = 0x2,
765	PERFMON_STATE_HW                                 = 0x3,
766} PERFMON_STATE;
767typedef enum PERFMON_CNTOFF_AND_OR {
768	PERFMON_CNTOFF_OR                                = 0x0,
769	PERFMON_CNTOFF_AND                               = 0x1,
770} PERFMON_CNTOFF_AND_OR;
771typedef enum PERFMON_CNTOFF_INT_EN {
772	PERFMON_CNTOFF_INT_DISABLE                       = 0x0,
773	PERFMON_CNTOFF_INT_ENABLE                        = 0x1,
774} PERFMON_CNTOFF_INT_EN;
775typedef enum PERFMON_CNTOFF_INT_TYPE {
776	PERFMON_CNTOFF_INT_TYPE_LEVEL                    = 0x0,
777	PERFMON_CNTOFF_INT_TYPE_PULSE                    = 0x1,
778} PERFMON_CNTOFF_INT_TYPE;
779typedef enum LptNumBanks {
780	LPT_NUM_BANKS_2BANK                              = 0x0,
781	LPT_NUM_BANKS_4BANK                              = 0x1,
782	LPT_NUM_BANKS_8BANK                              = 0x2,
783	LPT_NUM_BANKS_16BANK                             = 0x3,
784	LPT_NUM_BANKS_32BANK                             = 0x4,
785} LptNumBanks;
786typedef enum DCIO_DC_GENERICA_SEL {
787	DCIO_GENERICA_SEL_DACA_STEREOSYNC                = 0x0,
788	DCIO_GENERICA_SEL_STEREOSYNC                     = 0x1,
789	DCIO_GENERICA_SEL_DACA_PIXCLK                    = 0x2,
790	DCIO_GENERICA_SEL_DACB_PIXCLK                    = 0x3,
791	DCIO_GENERICA_SEL_DVOA_CTL3                      = 0x4,
792	DCIO_GENERICA_SEL_P1_PLLCLK                      = 0x5,
793	DCIO_GENERICA_SEL_P2_PLLCLK                      = 0x6,
794	DCIO_GENERICA_SEL_DVOA_STEREOSYNC                = 0x7,
795	DCIO_GENERICA_SEL_DACA_FIELD_NUMBER              = 0x8,
796	DCIO_GENERICA_SEL_DACB_FIELD_NUMBER              = 0x9,
797	DCIO_GENERICA_SEL_GENERICA_DCCG                  = 0xa,
798	DCIO_GENERICA_SEL_SYNCEN                         = 0xb,
799	DCIO_GENERICA_SEL_GENERICA_SCG                   = 0xc,
800	DCIO_GENERICA_SEL_RESERVED_VALUE13               = 0xd,
801	DCIO_GENERICA_SEL_RESERVED_VALUE14               = 0xe,
802	DCIO_GENERICA_SEL_RESERVED_VALUE15               = 0xf,
803	DCIO_GENERICA_SEL_GENERICA_DPRX                  = 0x10,
804	DCIO_GENERICA_SEL_GENERICB_DPRX                  = 0x11,
805} DCIO_DC_GENERICA_SEL;
806typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
807	DCIO_UNIPHYA_TEST_REFDIV_CLK                     = 0x0,
808	DCIO_UNIPHYB_TEST_REFDIV_CLK                     = 0x1,
809	DCIO_UNIPHYC_TEST_REFDIV_CLK                     = 0x2,
810	DCIO_UNIPHYD_TEST_REFDIV_CLK                     = 0x3,
811	DCIO_UNIPHYE_TEST_REFDIV_CLK                     = 0x4,
812	DCIO_UNIPHYF_TEST_REFDIV_CLK                     = 0x5,
813	DCIO_UNIPHYG_TEST_REFDIV_CLK                     = 0x6,
814	DCIO_UNIPHYLPA_TEST_REFDIV_CLK                   = 0x7,
815	DCIO_UNIPHYLPB_TEST_REFDIV_CLK                   = 0x8,
816} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
817typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
818	DCIO_UNIPHYA_FBDIV_CLK                           = 0x0,
819	DCIO_UNIPHYB_FBDIV_CLK                           = 0x1,
820	DCIO_UNIPHYC_FBDIV_CLK                           = 0x2,
821	DCIO_UNIPHYD_FBDIV_CLK                           = 0x3,
822	DCIO_UNIPHYE_FBDIV_CLK                           = 0x4,
823	DCIO_UNIPHYF_FBDIV_CLK                           = 0x5,
824	DCIO_UNIPHYG_FBDIV_CLK                           = 0x6,
825	DCIO_UNIPHYLPA_FBDIV_CLK                         = 0x7,
826	DCIO_UNIPHYLPB_FBDIV_CLK                         = 0x8,
827} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
828typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
829	DCIO_UNIPHYA_FBDIV_SSC_CLK                       = 0x0,
830	DCIO_UNIPHYB_FBDIV_SSC_CLK                       = 0x1,
831	DCIO_UNIPHYC_FBDIV_SSC_CLK                       = 0x2,
832	DCIO_UNIPHYD_FBDIV_SSC_CLK                       = 0x3,
833	DCIO_UNIPHYE_FBDIV_SSC_CLK                       = 0x4,
834	DCIO_UNIPHYF_FBDIV_SSC_CLK                       = 0x5,
835	DCIO_UNIPHYG_FBDIV_SSC_CLK                       = 0x6,
836	DCIO_UNIPHYLPA_FBDIV_SSC_CLK                     = 0x7,
837	DCIO_UNIPHYLPB_FBDIV_SSC_CLK                     = 0x8,
838} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
839typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
840	DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2                 = 0x0,
841	DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2                 = 0x1,
842	DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2                 = 0x2,
843	DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2                 = 0x3,
844	DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2                 = 0x4,
845	DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2                 = 0x5,
846	DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2                 = 0x6,
847	DCIO_UNIPHYLPA_TEST_FBDIV_CLK_DIV2               = 0x7,
848	DCIO_UNIPHYLPB_TEST_FBDIV_CLK_DIV2               = 0x8,
849} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
850typedef enum DCIO_DC_GENERICB_SEL {
851	DCIO_GENERICB_SEL_DACA_STEREOSYNC                = 0x0,
852	DCIO_GENERICB_SEL_STEREOSYNC                     = 0x1,
853	DCIO_GENERICB_SEL_DACA_PIXCLK                    = 0x2,
854	DCIO_GENERICB_SEL_DACB_PIXCLK                    = 0x3,
855	DCIO_GENERICB_SEL_DVOA_CTL3                      = 0x4,
856	DCIO_GENERICB_SEL_P1_PLLCLK                      = 0x5,
857	DCIO_GENERICB_SEL_P2_PLLCLK                      = 0x6,
858	DCIO_GENERICB_SEL_DVOA_STEREOSYNC                = 0x7,
859	DCIO_GENERICB_SEL_DACA_FIELD_NUMBER              = 0x8,
860	DCIO_GENERICB_SEL_DACB_FIELD_NUMBER              = 0x9,
861	DCIO_GENERICB_SEL_GENERICB_DCCG                  = 0xa,
862	DCIO_GENERICB_SEL_SYNCEN                         = 0xb,
863	DCIO_GENERICB_SEL_GENERICA_SCG                   = 0xc,
864	DCIO_GENERICB_SEL_RESERVED_VALUE13               = 0xd,
865	DCIO_GENERICB_SEL_RESERVED_VALUE14               = 0xe,
866	DCIO_GENERICB_SEL_RESERVED_VALUE15               = 0xf,
867} DCIO_DC_GENERICB_SEL;
868typedef enum DCIO_DC_PAD_EXTERN_SIG_SEL {
869	DCIO_DC_PAD_EXTERN_SIG_SEL_MVP                   = 0x0,
870	DCIO_DC_PAD_EXTERN_SIG_SEL_VSYNCA                = 0x1,
871	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_CLK             = 0x2,
872	DCIO_DC_PAD_EXTERN_SIG_SEL_GENLK_VSYNC           = 0x3,
873	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICA              = 0x4,
874	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICB              = 0x5,
875	DCIO_DC_PAD_EXTERN_SIG_SEL_GENERICC              = 0x6,
876	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD1                  = 0x7,
877	DCIO_DC_PAD_EXTERN_SIG_SEL_HPD2                  = 0x8,
878	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1CLK               = 0x9,
879	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC1DATA              = 0xa,
880	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2CLK               = 0xb,
881	DCIO_DC_PAD_EXTERN_SIG_SEL_DDC2DATA              = 0xc,
882	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD1                 = 0xd,
883	DCIO_DC_PAD_EXTERN_SIG_SEL_VHAD0                 = 0xe,
884	DCIO_DC_PAD_EXTERN_SIG_SEL_VPHCTL                = 0xf,
885} DCIO_DC_PAD_EXTERN_SIG_SEL;
886typedef enum DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS {
887	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA                 = 0x0,
888	DCIO_MVP_PIXEL_SRC_STATUS_HSYNCA_DUPLICATE       = 0x1,
889	DCIO_MVP_PIXEL_SRC_STATUS_CRTC                   = 0x2,
890	DCIO_MVP_PIXEL_SRC_STATUS_LB                     = 0x3,
891} DCIO_DC_PAD_EXTERN_SIG_MVP_PIXEL_SRC_STATUS;
892typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
893	DCIO_HSYNCA_OUTPUT_SEL_DISABLE                   = 0x0,
894	DCIO_HSYNCA_OUTPUT_SEL_PPLL1                     = 0x1,
895	DCIO_HSYNCA_OUTPUT_SEL_PPLL2                     = 0x2,
896	DCIO_HSYNCA_OUTPUT_SEL_RESERVED                  = 0x3,
897} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
898typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
899	DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE                = 0x0,
900	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1                  = 0x1,
901	DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2                  = 0x2,
902	DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3        = 0x3,
903} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
904typedef enum DCIO_DC_GPIO_VIP_DEBUG {
905	DCIO_DC_GPIO_VIP_DEBUG_NORMAL                    = 0x0,
906	DCIO_DC_GPIO_VIP_DEBUG_CG_BIG                    = 0x1,
907} DCIO_DC_GPIO_VIP_DEBUG;
908typedef enum DCIO_DC_GPIO_MACRO_DEBUG {
909	DCIO_DC_GPIO_MACRO_DEBUG_NORMAL                  = 0x0,
910	DCIO_DC_GPIO_MACRO_DEBUG_CHIP_BIF                = 0x1,
911	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE2         = 0x2,
912	DCIO_DC_GPIO_MACRO_DEBUG_RESERVED_VALUE3         = 0x3,
913} DCIO_DC_GPIO_MACRO_DEBUG;
914typedef enum DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL {
915	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_NORMAL       = 0x0,
916	DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL_SWAP         = 0x1,
917} DCIO_DC_GPIO_CHIP_DEBUG_OUT_PIN_SEL;
918typedef enum DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN {
919	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_BYPASS            = 0x0,
920	DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN_ENABLE            = 0x1,
921} DCIO_DC_GPIO_DEBUG_BUS_FLOP_EN;
922typedef enum DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE {
923	DCIO_DPRX_LOOPBACK_ENABLE_NORMAL                 = 0x0,
924	DCIO_DPRX_LOOPBACK_ENABLE_LOOP                   = 0x1,
925} DCIO_DC_GPIO_DEBUG_DPRX_LOOPBACK_ENABLE;
926typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
927	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x0,
928	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x1,
929	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS= 0x2,
930	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS= 0x3,
931	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS= 0x4,
932	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS= 0x5,
933	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS= 0x6,
934	DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS= 0x7,
935} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
936typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
937	DCIO_UNIPHY_CHANNEL_NO_INVERSION                 = 0x0,
938	DCIO_UNIPHY_CHANNEL_INVERTED                     = 0x1,
939} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
940typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
941	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW        = 0x0,
942	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW           = 0x1,
943	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x2,
944	DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED= 0x3,
945} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
946typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
947	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0              = 0x0,
948	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1              = 0x1,
949	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2              = 0x2,
950	DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3              = 0x3,
951} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
952typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
953	DCIO_VIP_MUX_EN_DVO                              = 0x0,
954	DCIO_VIP_MUX_EN_VIP                              = 0x1,
955} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
956typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
957	DCIO_VIP_ALTER_MAPPING_EN_DEFAULT                = 0x0,
958	DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
959} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
960typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
961	DCIO_DVO_ALTER_MAPPING_EN_DEFAULT                = 0x0,
962	DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE            = 0x1,
963} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
964typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
965	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE= 0x0,
966	DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE= 0x1,
967} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
968typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
969	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF           = 0x0,
970	DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON            = 0x1,
971} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
972typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
973	DCIO_LVTMA_SYNCEN_POL_NON_INVERT                 = 0x0,
974	DCIO_LVTMA_SYNCEN_POL_INVERT                     = 0x1,
975} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
976typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
977	DCIO_LVTMA_DIGON_OFF                             = 0x0,
978	DCIO_LVTMA_DIGON_ON                              = 0x1,
979} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
980typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
981	DCIO_LVTMA_DIGON_POL_NON_INVERT                  = 0x0,
982	DCIO_LVTMA_DIGON_POL_INVERT                      = 0x1,
983} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
984typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
985	DCIO_LVTMA_BLON_OFF                              = 0x0,
986	DCIO_LVTMA_BLON_ON                               = 0x1,
987} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
988typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
989	DCIO_LVTMA_BLON_POL_NON_INVERT                   = 0x0,
990	DCIO_LVTMA_BLON_POL_INVERT                       = 0x1,
991} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
992typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
993	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON              = 0x0,
994	DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE          = 0x1,
995} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
996typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
997	DCIO_BL_PWM_FRACTIONAL_DISABLE                   = 0x0,
998	DCIO_BL_PWM_FRACTIONAL_ENABLE                    = 0x1,
999} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
1000typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
1001	DCIO_BL_PWM_DISABLE                              = 0x0,
1002	DCIO_BL_PWM_ENABLE                               = 0x1,
1003} DCIO_BL_PWM_CNTL_BL_PWM_EN;
1004typedef enum DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT {
1005	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_NORMAL       = 0x0,
1006	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG1       = 0x1,
1007	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG2       = 0x2,
1008	DCIO_DBG_BL_PWM_INPUT_REFCLK_SELECT_DEBUG3       = 0x3,
1009} DCIO_BL_PWM_CNTL2_DBG_BL_PWM_INPUT_REFCLK_SELECT;
1010typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
1011	DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE              = 0x0,
1012	DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE               = 0x1,
1013} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
1014typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
1015	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL      = 0x0,
1016	DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM         = 0x1,
1017} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
1018typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
1019	DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE                = 0x0,
1020	DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE                 = 0x1,
1021} DCIO_BL_PWM_GRP1_REG_LOCK;
1022typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
1023	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE   = 0x0,
1024	DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE    = 0x1,
1025} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
1026typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
1027	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1= 0x0,
1028	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2= 0x1,
1029	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3= 0x2,
1030	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4= 0x3,
1031	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5= 0x4,
1032	DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6= 0x5,
1033} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
1034typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
1035	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x0,
1036	DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM= 0x1,
1037} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
1038typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
1039	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE       = 0x0,
1040	DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE      = 0x1,
1041} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
1042typedef enum DCIO_GSL_SEL {
1043	DCIO_GSL_SEL_GROUP_0                             = 0x0,
1044	DCIO_GSL_SEL_GROUP_1                             = 0x1,
1045	DCIO_GSL_SEL_GROUP_2                             = 0x2,
1046} DCIO_GSL_SEL;
1047typedef enum DCIO_GENLK_CLK_GSL_MASK {
1048	DCIO_GENLK_CLK_GSL_MASK_NO                       = 0x0,
1049	DCIO_GENLK_CLK_GSL_MASK_TIMING                   = 0x1,
1050	DCIO_GENLK_CLK_GSL_MASK_STEREO                   = 0x2,
1051} DCIO_GENLK_CLK_GSL_MASK;
1052typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
1053	DCIO_GENLK_VSYNC_GSL_MASK_NO                     = 0x0,
1054	DCIO_GENLK_VSYNC_GSL_MASK_TIMING                 = 0x1,
1055	DCIO_GENLK_VSYNC_GSL_MASK_STEREO                 = 0x2,
1056} DCIO_GENLK_VSYNC_GSL_MASK;
1057typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
1058	DCIO_SWAPLOCK_A_GSL_MASK_NO                      = 0x0,
1059	DCIO_SWAPLOCK_A_GSL_MASK_TIMING                  = 0x1,
1060	DCIO_SWAPLOCK_A_GSL_MASK_STEREO                  = 0x2,
1061} DCIO_SWAPLOCK_A_GSL_MASK;
1062typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
1063	DCIO_SWAPLOCK_B_GSL_MASK_NO                      = 0x0,
1064	DCIO_SWAPLOCK_B_GSL_MASK_TIMING                  = 0x1,
1065	DCIO_SWAPLOCK_B_GSL_MASK_STEREO                  = 0x2,
1066} DCIO_SWAPLOCK_B_GSL_MASK;
1067typedef enum DCIO_GSL_VSYNC_SEL {
1068	DCIO_GSL_VSYNC_SEL_PIPE0                         = 0x0,
1069	DCIO_GSL_VSYNC_SEL_PIPE1                         = 0x1,
1070	DCIO_GSL_VSYNC_SEL_PIPE2                         = 0x2,
1071	DCIO_GSL_VSYNC_SEL_PIPE3                         = 0x3,
1072	DCIO_GSL_VSYNC_SEL_PIPE4                         = 0x4,
1073	DCIO_GSL_VSYNC_SEL_PIPE5                         = 0x5,
1074} DCIO_GSL_VSYNC_SEL;
1075typedef enum DCIO_GSL0_TIMING_SYNC_SEL {
1076	DCIO_GSL0_TIMING_SYNC_SEL_PIPE                   = 0x0,
1077	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1078	DCIO_GSL0_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1079	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1080	DCIO_GSL0_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1081} DCIO_GSL0_TIMING_SYNC_SEL;
1082typedef enum DCIO_GSL0_GLOBAL_UNLOCK_SEL {
1083	DCIO_GSL0_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1084	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1085	DCIO_GSL0_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1086	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1087	DCIO_GSL0_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1088} DCIO_GSL0_GLOBAL_UNLOCK_SEL;
1089typedef enum DCIO_GSL1_TIMING_SYNC_SEL {
1090	DCIO_GSL1_TIMING_SYNC_SEL_PIPE                   = 0x0,
1091	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1092	DCIO_GSL1_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1093	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1094	DCIO_GSL1_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1095} DCIO_GSL1_TIMING_SYNC_SEL;
1096typedef enum DCIO_GSL1_GLOBAL_UNLOCK_SEL {
1097	DCIO_GSL1_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1098	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1099	DCIO_GSL1_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1100	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1101	DCIO_GSL1_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1102} DCIO_GSL1_GLOBAL_UNLOCK_SEL;
1103typedef enum DCIO_GSL2_TIMING_SYNC_SEL {
1104	DCIO_GSL2_TIMING_SYNC_SEL_PIPE                   = 0x0,
1105	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_VSYNC           = 0x1,
1106	DCIO_GSL2_TIMING_SYNC_SEL_GENCLK_CLK             = 0x2,
1107	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_A             = 0x3,
1108	DCIO_GSL2_TIMING_SYNC_SEL_SWAPLOCK_B             = 0x4,
1109} DCIO_GSL2_TIMING_SYNC_SEL;
1110typedef enum DCIO_GSL2_GLOBAL_UNLOCK_SEL {
1111	DCIO_GSL2_GLOBAL_UNLOCK_SEL_INVERSION            = 0x0,
1112	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENCLK_VSYNC         = 0x1,
1113	DCIO_GSL2_GLOBAL_UNLOCK_SEL_GENLK_CLK            = 0x2,
1114	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_A           = 0x3,
1115	DCIO_GSL2_GLOBAL_UNLOCK_SEL_SWAPLOCK_B           = 0x4,
1116} DCIO_GSL2_GLOBAL_UNLOCK_SEL;
1117typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
1118	DCIO_GPU_TIMER_START_0_END_27                    = 0x0,
1119	DCIO_GPU_TIMER_START_1_END_28                    = 0x1,
1120	DCIO_GPU_TIMER_START_2_END_29                    = 0x2,
1121	DCIO_GPU_TIMER_START_3_END_30                    = 0x3,
1122	DCIO_GPU_TIMER_START_4_END_31                    = 0x4,
1123	DCIO_GPU_TIMER_START_6_END_33                    = 0x5,
1124	DCIO_GPU_TIMER_START_8_END_35                    = 0x6,
1125	DCIO_GPU_TIMER_START_10_END_37                   = 0x7,
1126} DCIO_DC_GPU_TIMER_START_POSITION;
1127typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
1128	DCIO_TEST_CLK_SEL_DISPCLK                        = 0x0,
1129	DCIO_TEST_CLK_SEL_GATED_DISPCLK                  = 0x1,
1130	DCIO_TEST_CLK_SEL_SCLK                           = 0x2,
1131} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
1132typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
1133	DCIO_DISPCLK_R_DCIO_GATE_DISABLE                 = 0x0,
1134	DCIO_DISPCLK_R_DCIO_GATE_ENABLE                  = 0x1,
1135} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
1136typedef enum DCIO_DCO_DCFE_EXT_VSYNC_MUX {
1137	DCIO_EXT_VSYNC_MUX_SWAPLOCKB                     = 0x0,
1138	DCIO_EXT_VSYNC_MUX_CRTC0                         = 0x1,
1139	DCIO_EXT_VSYNC_MUX_CRTC1                         = 0x2,
1140	DCIO_EXT_VSYNC_MUX_CRTC2                         = 0x3,
1141	DCIO_EXT_VSYNC_MUX_CRTC3                         = 0x4,
1142	DCIO_EXT_VSYNC_MUX_CRTC4                         = 0x5,
1143	DCIO_EXT_VSYNC_MUX_CRTC5                         = 0x6,
1144	DCIO_EXT_VSYNC_MUX_GENERICB                      = 0x7,
1145} DCIO_DCO_DCFE_EXT_VSYNC_MUX;
1146typedef enum DCIO_DCO_EXT_VSYNC_MASK {
1147	DCIO_EXT_VSYNC_MASK_NONE                         = 0x0,
1148	DCIO_EXT_VSYNC_MASK_PIPE0                        = 0x1,
1149	DCIO_EXT_VSYNC_MASK_PIPE1                        = 0x2,
1150	DCIO_EXT_VSYNC_MASK_PIPE2                        = 0x3,
1151	DCIO_EXT_VSYNC_MASK_PIPE3                        = 0x4,
1152	DCIO_EXT_VSYNC_MASK_PIPE4                        = 0x5,
1153	DCIO_EXT_VSYNC_MASK_PIPE5                        = 0x6,
1154	DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE               = 0x7,
1155} DCIO_DCO_EXT_VSYNC_MASK;
1156typedef enum DCIO_DBG_OUT_PIN_SEL {
1157	DCIO_DBG_OUT_PIN_SEL_LOW_12BIT                   = 0x0,
1158	DCIO_DBG_OUT_PIN_SEL_HIGH_12BIT                  = 0x1,
1159} DCIO_DBG_OUT_PIN_SEL;
1160typedef enum DCIO_DBG_OUT_12BIT_SEL {
1161	DCIO_DBG_OUT_12BIT_SEL_LOW_12BIT                 = 0x0,
1162	DCIO_DBG_OUT_12BIT_SEL_MID_12BIT                 = 0x1,
1163	DCIO_DBG_OUT_12BIT_SEL_HIGH_12BIT                = 0x2,
1164	DCIO_DBG_OUT_12BIT_SEL_OVERRIDE                  = 0x3,
1165} DCIO_DBG_OUT_12BIT_SEL;
1166typedef enum DCIO_DSYNC_SOFT_RESET {
1167	DCIO_DSYNC_SOFT_RESET_DEASSERT                   = 0x0,
1168	DCIO_DSYNC_SOFT_RESET_ASSERT                     = 0x1,
1169} DCIO_DSYNC_SOFT_RESET;
1170typedef enum DCIO_DACA_SOFT_RESET {
1171	DCIO_DACA_SOFT_RESET_DEASSERT                    = 0x0,
1172	DCIO_DACA_SOFT_RESET_ASSERT                      = 0x1,
1173} DCIO_DACA_SOFT_RESET;
1174typedef enum DCIO_DCRXPHY_SOFT_RESET {
1175	DCIO_DCRXPHY_SOFT_RESET_DEASSERT                 = 0x0,
1176	DCIO_DCRXPHY_SOFT_RESET_ASSERT                   = 0x1,
1177} DCIO_DCRXPHY_SOFT_RESET;
1178typedef enum DCIO_DPHY_LANE_SEL {
1179	DCIO_DPHY_LANE_SEL_LANE0                         = 0x0,
1180	DCIO_DPHY_LANE_SEL_LANE1                         = 0x1,
1181	DCIO_DPHY_LANE_SEL_LANE2                         = 0x2,
1182	DCIO_DPHY_LANE_SEL_LANE3                         = 0x3,
1183} DCIO_DPHY_LANE_SEL;
1184typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
1185	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE     = 0x0,
1186	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE     = 0x1,
1187	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE     = 0x2,
1188	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE     = 0x3,
1189	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE     = 0x4,
1190	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE     = 0x5,
1191	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP       = 0xc,
1192	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP       = 0xd,
1193	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_P_FLIP       = 0xe,
1194	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_P_FLIP       = 0xf,
1195	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_P_FLIP       = 0x10,
1196	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_P_FLIP       = 0x11,
1197	DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM    = 0x18,
1198	DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM    = 0x19,
1199	DCIO_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM    = 0x1a,
1200	DCIO_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM    = 0x1b,
1201	DCIO_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM    = 0x1c,
1202	DCIO_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM    = 0x1d,
1203	DCIO_GPU_TIMER_READ_SELECT_LOWER_DCFEV_P_FLIP    = 0x24,
1204	DCIO_GPU_TIMER_READ_SELECT_UPPER_DCFEV_P_FLIP    = 0x25,
1205} DCIO_DC_GPU_TIMER_READ_SELECT;
1206typedef enum DCIO_IMPCAL_STEP_DELAY {
1207	DCIO_IMPCAL_STEP_DELAY_1us                       = 0x0,
1208	DCIO_IMPCAL_STEP_DELAY_2us                       = 0x1,
1209	DCIO_IMPCAL_STEP_DELAY_3us                       = 0x2,
1210	DCIO_IMPCAL_STEP_DELAY_4us                       = 0x3,
1211	DCIO_IMPCAL_STEP_DELAY_5us                       = 0x4,
1212	DCIO_IMPCAL_STEP_DELAY_6us                       = 0x5,
1213	DCIO_IMPCAL_STEP_DELAY_7us                       = 0x6,
1214	DCIO_IMPCAL_STEP_DELAY_8us                       = 0x7,
1215	DCIO_IMPCAL_STEP_DELAY_9us                       = 0x8,
1216	DCIO_IMPCAL_STEP_DELAY_10us                      = 0x9,
1217	DCIO_IMPCAL_STEP_DELAY_11us                      = 0xa,
1218	DCIO_IMPCAL_STEP_DELAY_12us                      = 0xb,
1219	DCIO_IMPCAL_STEP_DELAY_13us                      = 0xc,
1220	DCIO_IMPCAL_STEP_DELAY_14us                      = 0xd,
1221	DCIO_IMPCAL_STEP_DELAY_15us                      = 0xe,
1222	DCIO_IMPCAL_STEP_DELAY_16us                      = 0xf,
1223} DCIO_IMPCAL_STEP_DELAY;
1224typedef enum DCIO_UNIPHY_IMPCAL_SEL {
1225	DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE               = 0x0,
1226	DCIO_UNIPHY_IMPCAL_SEL_BINARY                    = 0x1,
1227} DCIO_UNIPHY_IMPCAL_SEL;
1228typedef enum DCIOCHIP_HPD_SEL {
1229	DCIOCHIP_HPD_SEL_ASYNC                           = 0x0,
1230	DCIOCHIP_HPD_SEL_CLOCKED                         = 0x1,
1231} DCIOCHIP_HPD_SEL;
1232typedef enum DCIOCHIP_PAD_MODE {
1233	DCIOCHIP_PAD_MODE_DDC                            = 0x0,
1234	DCIOCHIP_PAD_MODE_DP                             = 0x1,
1235} DCIOCHIP_PAD_MODE;
1236typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
1237	DCIOCHIP_AUXSLAVE_PAD_MODE_I2C                   = 0x0,
1238	DCIOCHIP_AUXSLAVE_PAD_MODE_AUX                   = 0x1,
1239} DCIOCHIP_AUXSLAVE_PAD_MODE;
1240typedef enum DCIOCHIP_INVERT {
1241	DCIOCHIP_POL_NON_INVERT                          = 0x0,
1242	DCIOCHIP_POL_INVERT                              = 0x1,
1243} DCIOCHIP_INVERT;
1244typedef enum DCIOCHIP_PD_EN {
1245	DCIOCHIP_PD_EN_NOTALLOW                          = 0x0,
1246	DCIOCHIP_PD_EN_ALLOW                             = 0x1,
1247} DCIOCHIP_PD_EN;
1248typedef enum DCIOCHIP_GPIO_MASK_EN {
1249	DCIOCHIP_GPIO_MASK_EN_HARDWARE                   = 0x0,
1250	DCIOCHIP_GPIO_MASK_EN_SOFTWARE                   = 0x1,
1251} DCIOCHIP_GPIO_MASK_EN;
1252typedef enum DCIOCHIP_MASK {
1253	DCIOCHIP_MASK_DISABLE                            = 0x0,
1254	DCIOCHIP_MASK_ENABLE                             = 0x1,
1255} DCIOCHIP_MASK;
1256typedef enum DCIOCHIP_GPIO_I2C_MASK {
1257	DCIOCHIP_GPIO_I2C_MASK_DISABLE                   = 0x0,
1258	DCIOCHIP_GPIO_I2C_MASK_ENABLE                    = 0x1,
1259} DCIOCHIP_GPIO_I2C_MASK;
1260typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
1261	DCIOCHIP_GPIO_I2C_DRIVE_LOW                      = 0x0,
1262	DCIOCHIP_GPIO_I2C_DRIVE_HIGH                     = 0x1,
1263} DCIOCHIP_GPIO_I2C_DRIVE;
1264typedef enum DCIOCHIP_GPIO_I2C_EN {
1265	DCIOCHIP_GPIO_I2C_DISABLE                        = 0x0,
1266	DCIOCHIP_GPIO_I2C_ENABLE                         = 0x1,
1267} DCIOCHIP_GPIO_I2C_EN;
1268typedef enum DCIOCHIP_MASK_4BIT {
1269	DCIOCHIP_MASK_4BIT_DISABLE                       = 0x0,
1270	DCIOCHIP_MASK_4BIT_ENABLE                        = 0xf,
1271} DCIOCHIP_MASK_4BIT;
1272typedef enum DCIOCHIP_ENABLE_4BIT {
1273	DCIOCHIP_4BIT_DISABLE                            = 0x0,
1274	DCIOCHIP_4BIT_ENABLE                             = 0xf,
1275} DCIOCHIP_ENABLE_4BIT;
1276typedef enum DCIOCHIP_MASK_5BIT {
1277	DCIOCHIP_MASIK_5BIT_DISABLE                      = 0x0,
1278	DCIOCHIP_MASIK_5BIT_ENABLE                       = 0x1f,
1279} DCIOCHIP_MASK_5BIT;
1280typedef enum DCIOCHIP_ENABLE_5BIT {
1281	DCIOCHIP_5BIT_DISABLE                            = 0x0,
1282	DCIOCHIP_5BIT_ENABLE                             = 0x1f,
1283} DCIOCHIP_ENABLE_5BIT;
1284typedef enum DCIOCHIP_MASK_2BIT {
1285	DCIOCHIP_MASK_2BIT_DISABLE                       = 0x0,
1286	DCIOCHIP_MASK_2BIT_ENABLE                        = 0x3,
1287} DCIOCHIP_MASK_2BIT;
1288typedef enum DCIOCHIP_ENABLE_2BIT {
1289	DCIOCHIP_2BIT_DISABLE                            = 0x0,
1290	DCIOCHIP_2BIT_ENABLE                             = 0x3,
1291} DCIOCHIP_ENABLE_2BIT;
1292typedef enum DCIOCHIP_REF_27_SRC_SEL {
1293	DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER             = 0x0,
1294	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER      = 0x1,
1295	DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS              = 0x2,
1296	DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS       = 0x3,
1297} DCIOCHIP_REF_27_SRC_SEL;
1298typedef enum DCIOCHIP_DVO_VREFPON {
1299	DCIOCHIP_DVO_VREFPON_DISABLE                     = 0x0,
1300	DCIOCHIP_DVO_VREFPON_ENABLE                      = 0x1,
1301} DCIOCHIP_DVO_VREFPON;
1302typedef enum DCIOCHIP_DVO_VREFSEL {
1303	DCIOCHIP_DVO_VREFSEL_ONCHIP                      = 0x0,
1304	DCIOCHIP_DVO_VREFSEL_EXTERNAL                    = 0x1,
1305} DCIOCHIP_DVO_VREFSEL;
1306typedef enum DCP_GRPH_ENABLE {
1307	DCP_GRPH_ENABLE_FALSE                            = 0x0,
1308	DCP_GRPH_ENABLE_TRUE                             = 0x1,
1309} DCP_GRPH_ENABLE;
1310typedef enum DCP_GRPH_KEYER_ALPHA_SEL {
1311	DCP_GRPH_KEYER_ALPHA_SEL_FALSE                   = 0x0,
1312	DCP_GRPH_KEYER_ALPHA_SEL_TRUE                    = 0x1,
1313} DCP_GRPH_KEYER_ALPHA_SEL;
1314typedef enum DCP_GRPH_DEPTH {
1315	DCP_GRPH_DEPTH_8BPP                              = 0x0,
1316	DCP_GRPH_DEPTH_16BPP                             = 0x1,
1317	DCP_GRPH_DEPTH_32BPP                             = 0x2,
1318	DCP_GRPH_DEPTH_64BPP                             = 0x3,
1319} DCP_GRPH_DEPTH;
1320typedef enum DCP_GRPH_NUM_BANKS {
1321	DCP_GRPH_NUM_BANKS_2BANK                         = 0x0,
1322	DCP_GRPH_NUM_BANKS_4BANK                         = 0x1,
1323	DCP_GRPH_NUM_BANKS_8BANK                         = 0x2,
1324	DCP_GRPH_NUM_BANKS_16BANK                        = 0x3,
1325} DCP_GRPH_NUM_BANKS;
1326typedef enum DCP_GRPH_BANK_WIDTH {
1327	DCP_GRPH_BANK_WIDTH_1                            = 0x0,
1328	DCP_GRPH_BANK_WIDTH_2                            = 0x1,
1329	DCP_GRPH_BANK_WIDTH_4                            = 0x2,
1330	DCP_GRPH_BANK_WIDTH_8                            = 0x3,
1331} DCP_GRPH_BANK_WIDTH;
1332typedef enum DCP_GRPH_FORMAT {
1333	DCP_GRPH_FORMAT_8BPP                             = 0x0,
1334	DCP_GRPH_FORMAT_16BPP                            = 0x1,
1335	DCP_GRPH_FORMAT_32BPP                            = 0x2,
1336	DCP_GRPH_FORMAT_64BPP                            = 0x3,
1337} DCP_GRPH_FORMAT;
1338typedef enum DCP_GRPH_BANK_HEIGHT {
1339	DCP_GRPH_BANK_HEIGHT_1                           = 0x0,
1340	DCP_GRPH_BANK_HEIGHT_2                           = 0x1,
1341	DCP_GRPH_BANK_HEIGHT_4                           = 0x2,
1342	DCP_GRPH_BANK_HEIGHT_8                           = 0x3,
1343} DCP_GRPH_BANK_HEIGHT;
1344typedef enum DCP_GRPH_TILE_SPLIT {
1345	DCP_GRPH_TILE_SPLIT_64B                          = 0x0,
1346	DCP_GRPH_TILE_SPLIT_128B                         = 0x1,
1347	DCP_GRPH_TILE_SPLIT_256B                         = 0x2,
1348	DCP_GRPH_TILE_SPLIT_512B                         = 0x3,
1349	DCP_GRPH_TILE_SPLIT_1B                           = 0x4,
1350	DCP_GRPH_TILE_SPLIT_2B                           = 0x5,
1351	DCP_GRPH_TILE_SPLIT_4B                           = 0x6,
1352} DCP_GRPH_TILE_SPLIT;
1353typedef enum DCP_GRPH_ADDRESS_TRANSLATION_ENABLE {
1354	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_FALSE        = 0x0,
1355	DCP_GRPH_ADDRESS_TRANSLATION_ENABLE_TRUE         = 0x1,
1356} DCP_GRPH_ADDRESS_TRANSLATION_ENABLE;
1357typedef enum DCP_GRPH_PRIVILEGED_ACCESS_ENABLE {
1358	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_FALSE          = 0x0,
1359	DCP_GRPH_PRIVILEGED_ACCESS_ENABLE_TRUE           = 0x1,
1360} DCP_GRPH_PRIVILEGED_ACCESS_ENABLE;
1361typedef enum DCP_GRPH_MACRO_TILE_ASPECT {
1362	DCP_GRPH_MACRO_TILE_ASPECT_1                     = 0x0,
1363	DCP_GRPH_MACRO_TILE_ASPECT_2                     = 0x1,
1364	DCP_GRPH_MACRO_TILE_ASPECT_4                     = 0x2,
1365	DCP_GRPH_MACRO_TILE_ASPECT_8                     = 0x3,
1366} DCP_GRPH_MACRO_TILE_ASPECT;
1367typedef enum DCP_GRPH_ARRAY_MODE {
1368	DCP_GRPH_ARRAY_MODE_0                            = 0x0,
1369	DCP_GRPH_ARRAY_MODE_1                            = 0x1,
1370	DCP_GRPH_ARRAY_MODE_2                            = 0x2,
1371	DCP_GRPH_ARRAY_MODE_3                            = 0x3,
1372	DCP_GRPH_ARRAY_MODE_4                            = 0x4,
1373	DCP_GRPH_ARRAY_MODE_7                            = 0x7,
1374	DCP_GRPH_ARRAY_MODE_12                           = 0xc,
1375	DCP_GRPH_ARRAY_MODE_13                           = 0xd,
1376} DCP_GRPH_ARRAY_MODE;
1377typedef enum DCP_GRPH_MICRO_TILE_MODE {
1378	DCP_GRPH_MICRO_TILE_MODE_0                       = 0x0,
1379	DCP_GRPH_MICRO_TILE_MODE_1                       = 0x1,
1380	DCP_GRPH_MICRO_TILE_MODE_2                       = 0x2,
1381	DCP_GRPH_MICRO_TILE_MODE_3                       = 0x3,
1382} DCP_GRPH_MICRO_TILE_MODE;
1383typedef enum DCP_GRPH_COLOR_EXPANSION_MODE {
1384	DCP_GRPH_COLOR_EXPANSION_MODE_DEXP               = 0x0,
1385	DCP_GRPH_COLOR_EXPANSION_MODE_ZEXP               = 0x1,
1386} DCP_GRPH_COLOR_EXPANSION_MODE;
1387typedef enum DCP_GRPH_LUT_10BIT_BYPASS_EN {
1388	DCP_GRPH_LUT_10BIT_BYPASS_EN_FALSE               = 0x0,
1389	DCP_GRPH_LUT_10BIT_BYPASS_EN_TRUE                = 0x1,
1390} DCP_GRPH_LUT_10BIT_BYPASS_EN;
1391typedef enum DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN {
1392	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_FALSE       = 0x0,
1393	DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN_TRUE        = 0x1,
1394} DCP_GRPH_LUT_10BIT_BYPASS_DBL_BUF_EN;
1395typedef enum DCP_GRPH_ENDIAN_SWAP {
1396	DCP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
1397	DCP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
1398	DCP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
1399	DCP_GRPH_ENDIAN_SWAP_8IN64                       = 0x3,
1400} DCP_GRPH_ENDIAN_SWAP;
1401typedef enum DCP_GRPH_RED_CROSSBAR {
1402	DCP_GRPH_RED_CROSSBAR_FROM_R                     = 0x0,
1403	DCP_GRPH_RED_CROSSBAR_FROM_G                     = 0x1,
1404	DCP_GRPH_RED_CROSSBAR_FROM_B                     = 0x2,
1405	DCP_GRPH_RED_CROSSBAR_FROM_A                     = 0x3,
1406} DCP_GRPH_RED_CROSSBAR;
1407typedef enum DCP_GRPH_GREEN_CROSSBAR {
1408	DCP_GRPH_GREEN_CROSSBAR_FROM_G                   = 0x0,
1409	DCP_GRPH_GREEN_CROSSBAR_FROM_B                   = 0x1,
1410	DCP_GRPH_GREEN_CROSSBAR_FROM_A                   = 0x2,
1411	DCP_GRPH_GREEN_CROSSBAR_FROM_R                   = 0x3,
1412} DCP_GRPH_GREEN_CROSSBAR;
1413typedef enum DCP_GRPH_BLUE_CROSSBAR {
1414	DCP_GRPH_BLUE_CROSSBAR_FROM_B                    = 0x0,
1415	DCP_GRPH_BLUE_CROSSBAR_FROM_A                    = 0x1,
1416	DCP_GRPH_BLUE_CROSSBAR_FROM_R                    = 0x2,
1417	DCP_GRPH_BLUE_CROSSBAR_FROM_G                    = 0x3,
1418} DCP_GRPH_BLUE_CROSSBAR;
1419typedef enum DCP_GRPH_ALPHA_CROSSBAR {
1420	DCP_GRPH_ALPHA_CROSSBAR_FROM_A                   = 0x0,
1421	DCP_GRPH_ALPHA_CROSSBAR_FROM_R                   = 0x1,
1422	DCP_GRPH_ALPHA_CROSSBAR_FROM_G                   = 0x2,
1423	DCP_GRPH_ALPHA_CROSSBAR_FROM_B                   = 0x3,
1424} DCP_GRPH_ALPHA_CROSSBAR;
1425typedef enum DCP_GRPH_PRIMARY_DFQ_ENABLE {
1426	DCP_GRPH_PRIMARY_DFQ_ENABLE_FALSE                = 0x0,
1427	DCP_GRPH_PRIMARY_DFQ_ENABLE_TRUE                 = 0x1,
1428} DCP_GRPH_PRIMARY_DFQ_ENABLE;
1429typedef enum DCP_GRPH_SECONDARY_DFQ_ENABLE {
1430	DCP_GRPH_SECONDARY_DFQ_ENABLE_FALSE              = 0x0,
1431	DCP_GRPH_SECONDARY_DFQ_ENABLE_TRUE               = 0x1,
1432} DCP_GRPH_SECONDARY_DFQ_ENABLE;
1433typedef enum DCP_GRPH_INPUT_GAMMA_MODE {
1434	DCP_GRPH_INPUT_GAMMA_MODE_LUT                    = 0x0,
1435	DCP_GRPH_INPUT_GAMMA_MODE_BYPASS                 = 0x1,
1436} DCP_GRPH_INPUT_GAMMA_MODE;
1437typedef enum DCP_GRPH_MODE_UPDATE_PENDING {
1438	DCP_GRPH_MODE_UPDATE_PENDING_FALSE               = 0x0,
1439	DCP_GRPH_MODE_UPDATE_PENDING_TRUE                = 0x1,
1440} DCP_GRPH_MODE_UPDATE_PENDING;
1441typedef enum DCP_GRPH_MODE_UPDATE_TAKEN {
1442	DCP_GRPH_MODE_UPDATE_TAKEN_FALSE                 = 0x0,
1443	DCP_GRPH_MODE_UPDATE_TAKEN_TRUE                  = 0x1,
1444} DCP_GRPH_MODE_UPDATE_TAKEN;
1445typedef enum DCP_GRPH_SURFACE_UPDATE_PENDING {
1446	DCP_GRPH_SURFACE_UPDATE_PENDING_FALSE            = 0x0,
1447	DCP_GRPH_SURFACE_UPDATE_PENDING_TRUE             = 0x1,
1448} DCP_GRPH_SURFACE_UPDATE_PENDING;
1449typedef enum DCP_GRPH_SURFACE_UPDATE_TAKEN {
1450	DCP_GRPH_SURFACE_UPDATE_TAKEN_FALSE              = 0x0,
1451	DCP_GRPH_SURFACE_UPDATE_TAKEN_TRUE               = 0x1,
1452} DCP_GRPH_SURFACE_UPDATE_TAKEN;
1453typedef enum DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE {
1454	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_FALSE       = 0x0,
1455	DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE_TRUE        = 0x1,
1456} DCP_GRPH_SURFACE_XDMA_PENDING_ENABLE;
1457typedef enum DCP_GRPH_UPDATE_LOCK {
1458	DCP_GRPH_UPDATE_LOCK_FALSE                       = 0x0,
1459	DCP_GRPH_UPDATE_LOCK_TRUE                        = 0x1,
1460} DCP_GRPH_UPDATE_LOCK;
1461typedef enum DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
1462	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_FALSE        = 0x0,
1463	DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_TRUE         = 0x1,
1464} DCP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
1465typedef enum DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
1466	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_FALSE      = 0x0,
1467	DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_TRUE       = 0x1,
1468} DCP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
1469typedef enum DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
1470	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_FALSE   = 0x0,
1471	DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_TRUE    = 0x1,
1472} DCP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
1473typedef enum DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN {
1474	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_FALSE       = 0x0,
1475	DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN_TRUE        = 0x1,
1476} DCP_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1477typedef enum DCP_GRPH_XDMA_SUPER_AA_EN {
1478	DCP_GRPH_XDMA_SUPER_AA_EN_FALSE                  = 0x0,
1479	DCP_GRPH_XDMA_SUPER_AA_EN_TRUE                   = 0x1,
1480} DCP_GRPH_XDMA_SUPER_AA_EN;
1481typedef enum DCP_GRPH_DFQ_RESET {
1482	DCP_GRPH_DFQ_RESET_FALSE                         = 0x0,
1483	DCP_GRPH_DFQ_RESET_TRUE                          = 0x1,
1484} DCP_GRPH_DFQ_RESET;
1485typedef enum DCP_GRPH_DFQ_SIZE {
1486	DCP_GRPH_DFQ_SIZE_DEEP1                          = 0x0,
1487	DCP_GRPH_DFQ_SIZE_DEEP2                          = 0x1,
1488	DCP_GRPH_DFQ_SIZE_DEEP3                          = 0x2,
1489	DCP_GRPH_DFQ_SIZE_DEEP4                          = 0x3,
1490	DCP_GRPH_DFQ_SIZE_DEEP5                          = 0x4,
1491	DCP_GRPH_DFQ_SIZE_DEEP6                          = 0x5,
1492	DCP_GRPH_DFQ_SIZE_DEEP7                          = 0x6,
1493	DCP_GRPH_DFQ_SIZE_DEEP8                          = 0x7,
1494} DCP_GRPH_DFQ_SIZE;
1495typedef enum DCP_GRPH_DFQ_MIN_FREE_ENTRIES {
1496	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_1                  = 0x0,
1497	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_2                  = 0x1,
1498	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_3                  = 0x2,
1499	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_4                  = 0x3,
1500	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_5                  = 0x4,
1501	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_6                  = 0x5,
1502	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_7                  = 0x6,
1503	DCP_GRPH_DFQ_MIN_FREE_ENTRIES_8                  = 0x7,
1504} DCP_GRPH_DFQ_MIN_FREE_ENTRIES;
1505typedef enum DCP_GRPH_DFQ_RESET_ACK {
1506	DCP_GRPH_DFQ_RESET_ACK_FALSE                     = 0x0,
1507	DCP_GRPH_DFQ_RESET_ACK_TRUE                      = 0x1,
1508} DCP_GRPH_DFQ_RESET_ACK;
1509typedef enum DCP_GRPH_PFLIP_INT_CLEAR {
1510	DCP_GRPH_PFLIP_INT_CLEAR_FALSE                   = 0x0,
1511	DCP_GRPH_PFLIP_INT_CLEAR_TRUE                    = 0x1,
1512} DCP_GRPH_PFLIP_INT_CLEAR;
1513typedef enum DCP_GRPH_PFLIP_INT_MASK {
1514	DCP_GRPH_PFLIP_INT_MASK_FALSE                    = 0x0,
1515	DCP_GRPH_PFLIP_INT_MASK_TRUE                     = 0x1,
1516} DCP_GRPH_PFLIP_INT_MASK;
1517typedef enum DCP_GRPH_PFLIP_INT_TYPE {
1518	DCP_GRPH_PFLIP_INT_TYPE_LEGACY_LEVEL             = 0x0,
1519	DCP_GRPH_PFLIP_INT_TYPE_PULSE                    = 0x1,
1520} DCP_GRPH_PFLIP_INT_TYPE;
1521typedef enum DCP_GRPH_PRESCALE_SELECT {
1522	DCP_GRPH_PRESCALE_SELECT_FIXED                   = 0x0,
1523	DCP_GRPH_PRESCALE_SELECT_FLOATING                = 0x1,
1524} DCP_GRPH_PRESCALE_SELECT;
1525typedef enum DCP_GRPH_PRESCALE_R_SIGN {
1526	DCP_GRPH_PRESCALE_R_SIGN_UNSIGNED                = 0x0,
1527	DCP_GRPH_PRESCALE_R_SIGN_SIGNED                  = 0x1,
1528} DCP_GRPH_PRESCALE_R_SIGN;
1529typedef enum DCP_GRPH_PRESCALE_G_SIGN {
1530	DCP_GRPH_PRESCALE_G_SIGN_UNSIGNED                = 0x0,
1531	DCP_GRPH_PRESCALE_G_SIGN_SIGNED                  = 0x1,
1532} DCP_GRPH_PRESCALE_G_SIGN;
1533typedef enum DCP_GRPH_PRESCALE_B_SIGN {
1534	DCP_GRPH_PRESCALE_B_SIGN_UNSIGNED                = 0x0,
1535	DCP_GRPH_PRESCALE_B_SIGN_SIGNED                  = 0x1,
1536} DCP_GRPH_PRESCALE_B_SIGN;
1537typedef enum DCP_GRPH_PRESCALE_BYPASS {
1538	DCP_GRPH_PRESCALE_BYPASS_FALSE                   = 0x0,
1539	DCP_GRPH_PRESCALE_BYPASS_TRUE                    = 0x1,
1540} DCP_GRPH_PRESCALE_BYPASS;
1541typedef enum DCP_INPUT_CSC_GRPH_MODE {
1542	DCP_INPUT_CSC_GRPH_MODE_BYPASS                   = 0x0,
1543	DCP_INPUT_CSC_GRPH_MODE_INPUT_CSC_COEF           = 0x1,
1544	DCP_INPUT_CSC_GRPH_MODE_SHARED_COEF              = 0x2,
1545	DCP_INPUT_CSC_GRPH_MODE_RESERVED                 = 0x3,
1546} DCP_INPUT_CSC_GRPH_MODE;
1547typedef enum DCP_OUTPUT_CSC_GRPH_MODE {
1548	DCP_OUTPUT_CSC_GRPH_MODE_BYPASS                  = 0x0,
1549	DCP_OUTPUT_CSC_GRPH_MODE_RGB                     = 0x1,
1550	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR601                = 0x2,
1551	DCP_OUTPUT_CSC_GRPH_MODE_YCBCR709                = 0x3,
1552	DCP_OUTPUT_CSC_GRPH_MODE_OUTPUT_CSC_COEF         = 0x4,
1553	DCP_OUTPUT_CSC_GRPH_MODE_SHARED_COEF             = 0x5,
1554	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED0               = 0x6,
1555	DCP_OUTPUT_CSC_GRPH_MODE_RESERVED1               = 0x7,
1556} DCP_OUTPUT_CSC_GRPH_MODE;
1557typedef enum DCP_DENORM_MODE {
1558	DCP_DENORM_MODE_UNITY                            = 0x0,
1559	DCP_DENORM_MODE_6BIT                             = 0x1,
1560	DCP_DENORM_MODE_8BIT                             = 0x2,
1561	DCP_DENORM_MODE_10BIT                            = 0x3,
1562	DCP_DENORM_MODE_11BIT                            = 0x4,
1563	DCP_DENORM_MODE_12BIT                            = 0x5,
1564	DCP_DENORM_MODE_RESERVED0                        = 0x6,
1565	DCP_DENORM_MODE_RESERVED1                        = 0x7,
1566} DCP_DENORM_MODE;
1567typedef enum DCP_DENORM_14BIT_OUT {
1568	DCP_DENORM_14BIT_OUT_FALSE                       = 0x0,
1569	DCP_DENORM_14BIT_OUT_TRUE                        = 0x1,
1570} DCP_DENORM_14BIT_OUT;
1571typedef enum DCP_OUT_ROUND_TRUNC_MODE {
1572	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_12             = 0x0,
1573	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_11             = 0x1,
1574	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_10             = 0x2,
1575	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_9              = 0x3,
1576	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_8              = 0x4,
1577	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_RESERVED       = 0x5,
1578	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_14             = 0x6,
1579	DCP_OUT_ROUND_TRUNC_MODE_TRUNCATE_13             = 0x7,
1580	DCP_OUT_ROUND_TRUNC_MODE_ROUND_12                = 0x8,
1581	DCP_OUT_ROUND_TRUNC_MODE_ROUND_11                = 0x9,
1582	DCP_OUT_ROUND_TRUNC_MODE_ROUND_10                = 0xa,
1583	DCP_OUT_ROUND_TRUNC_MODE_ROUND_9                 = 0xb,
1584	DCP_OUT_ROUND_TRUNC_MODE_ROUND_8                 = 0xc,
1585	DCP_OUT_ROUND_TRUNC_MODE_ROUND_RESERVED          = 0xd,
1586	DCP_OUT_ROUND_TRUNC_MODE_ROUND_14                = 0xe,
1587	DCP_OUT_ROUND_TRUNC_MODE_ROUND_13                = 0xf,
1588} DCP_OUT_ROUND_TRUNC_MODE;
1589typedef enum DCP_KEY_MODE {
1590	DCP_KEY_MODE_ALPHA0                              = 0x0,
1591	DCP_KEY_MODE_ALPHA1                              = 0x1,
1592	DCP_KEY_MODE_IN_RANGE_ALPHA1                     = 0x2,
1593	DCP_KEY_MODE_IN_RANGE_ALPHA0                     = 0x3,
1594} DCP_KEY_MODE;
1595typedef enum DCP_GRPH_DEGAMMA_MODE {
1596	DCP_GRPH_DEGAMMA_MODE_BYPASS                     = 0x0,
1597	DCP_GRPH_DEGAMMA_MODE_ROMA                       = 0x1,
1598	DCP_GRPH_DEGAMMA_MODE_ROMB                       = 0x2,
1599	DCP_GRPH_DEGAMMA_MODE_RESERVED                   = 0x3,
1600} DCP_GRPH_DEGAMMA_MODE;
1601typedef enum DCP_CURSOR2_DEGAMMA_MODE {
1602	DCP_CURSOR2_DEGAMMA_MODE_BYPASS                  = 0x0,
1603	DCP_CURSOR2_DEGAMMA_MODE_ROMA                    = 0x1,
1604	DCP_CURSOR2_DEGAMMA_MODE_ROMB                    = 0x2,
1605	DCP_CURSOR2_DEGAMMA_MODE_RESERVED                = 0x3,
1606} DCP_CURSOR2_DEGAMMA_MODE;
1607typedef enum DCP_CURSOR_DEGAMMA_MODE {
1608	DCP_CURSOR_DEGAMMA_MODE_BYPASS                   = 0x0,
1609	DCP_CURSOR_DEGAMMA_MODE_ROMA                     = 0x1,
1610	DCP_CURSOR_DEGAMMA_MODE_ROMB                     = 0x2,
1611	DCP_CURSOR_DEGAMMA_MODE_RESERVED                 = 0x3,
1612} DCP_CURSOR_DEGAMMA_MODE;
1613typedef enum DCP_GRPH_GAMUT_REMAP_MODE {
1614	DCP_GRPH_GAMUT_REMAP_MODE_BYPASS                 = 0x0,
1615	DCP_GRPH_GAMUT_REMAP_MODE_ROMA                   = 0x1,
1616	DCP_GRPH_GAMUT_REMAP_MODE_ROMB                   = 0x2,
1617	DCP_GRPH_GAMUT_REMAP_MODE_RESERVED               = 0x3,
1618} DCP_GRPH_GAMUT_REMAP_MODE;
1619typedef enum DCP_SPATIAL_DITHER_EN {
1620	DCP_SPATIAL_DITHER_EN_FALSE                      = 0x0,
1621	DCP_SPATIAL_DITHER_EN_TRUE                       = 0x1,
1622} DCP_SPATIAL_DITHER_EN;
1623typedef enum DCP_SPATIAL_DITHER_MODE {
1624	DCP_SPATIAL_DITHER_MODE_BYPASS                   = 0x0,
1625	DCP_SPATIAL_DITHER_MODE_ROMA                     = 0x1,
1626	DCP_SPATIAL_DITHER_MODE_ROMB                     = 0x2,
1627	DCP_SPATIAL_DITHER_MODE_RESERVED                 = 0x3,
1628} DCP_SPATIAL_DITHER_MODE;
1629typedef enum DCP_SPATIAL_DITHER_DEPTH {
1630	DCP_SPATIAL_DITHER_DEPTH_30BPP                   = 0x0,
1631	DCP_SPATIAL_DITHER_DEPTH_24BPP                   = 0x1,
1632	DCP_SPATIAL_DITHER_DEPTH_36BPP                   = 0x2,
1633	DCP_SPATIAL_DITHER_DEPTH_UNDEFINED               = 0x3,
1634} DCP_SPATIAL_DITHER_DEPTH;
1635typedef enum DCP_FRAME_RANDOM_ENABLE {
1636	DCP_FRAME_RANDOM_ENABLE_FALSE                    = 0x0,
1637	DCP_FRAME_RANDOM_ENABLE_TRUE                     = 0x1,
1638} DCP_FRAME_RANDOM_ENABLE;
1639typedef enum DCP_RGB_RANDOM_ENABLE {
1640	DCP_RGB_RANDOM_ENABLE_FALSE                      = 0x0,
1641	DCP_RGB_RANDOM_ENABLE_TRUE                       = 0x1,
1642} DCP_RGB_RANDOM_ENABLE;
1643typedef enum DCP_HIGHPASS_RANDOM_ENABLE {
1644	DCP_HIGHPASS_RANDOM_ENABLE_FALSE                 = 0x0,
1645	DCP_HIGHPASS_RANDOM_ENABLE_TRUE                  = 0x1,
1646} DCP_HIGHPASS_RANDOM_ENABLE;
1647typedef enum DCP_CURSOR_EN {
1648	DCP_CURSOR_EN_FALSE                              = 0x0,
1649	DCP_CURSOR_EN_TRUE                               = 0x1,
1650} DCP_CURSOR_EN;
1651typedef enum DCP_CUR_INV_TRANS_CLAMP {
1652	DCP_CUR_INV_TRANS_CLAMP_FALSE                    = 0x0,
1653	DCP_CUR_INV_TRANS_CLAMP_TRUE                     = 0x1,
1654} DCP_CUR_INV_TRANS_CLAMP;
1655typedef enum DCP_CURSOR_MODE {
1656	DCP_CURSOR_MODE_MONO_2BPP                        = 0x0,
1657	DCP_CURSOR_MODE_24BPP_1BIT                       = 0x1,
1658	DCP_CURSOR_MODE_24BPP_8BIT_PREMULTI              = 0x2,
1659	DCP_CURSOR_MODE_24BPP_8BIT_UNPREMULTI            = 0x3,
1660} DCP_CURSOR_MODE;
1661typedef enum DCP_CURSOR_2X_MAGNIFY {
1662	DCP_CURSOR_2X_MAGNIFY_FALSE                      = 0x0,
1663	DCP_CURSOR_2X_MAGNIFY_TRUE                       = 0x1,
1664} DCP_CURSOR_2X_MAGNIFY;
1665typedef enum DCP_CURSOR_FORCE_MC_ON {
1666	DCP_CURSOR_FORCE_MC_ON_FALSE                     = 0x0,
1667	DCP_CURSOR_FORCE_MC_ON_TRUE                      = 0x1,
1668} DCP_CURSOR_FORCE_MC_ON;
1669typedef enum DCP_CURSOR_URGENT_CONTROL {
1670	DCP_CURSOR_URGENT_CONTROL_MODE_0                 = 0x0,
1671	DCP_CURSOR_URGENT_CONTROL_MODE_1                 = 0x1,
1672	DCP_CURSOR_URGENT_CONTROL_MODE_2                 = 0x2,
1673	DCP_CURSOR_URGENT_CONTROL_MODE_3                 = 0x3,
1674	DCP_CURSOR_URGENT_CONTROL_MODE_4                 = 0x4,
1675} DCP_CURSOR_URGENT_CONTROL;
1676typedef enum DCP_CURSOR_UPDATE_PENDING {
1677	DCP_CURSOR_UPDATE_PENDING_FALSE                  = 0x0,
1678	DCP_CURSOR_UPDATE_PENDING_TRUE                   = 0x1,
1679} DCP_CURSOR_UPDATE_PENDING;
1680typedef enum DCP_CURSOR_UPDATE_TAKEN {
1681	DCP_CURSOR_UPDATE_TAKEN_FALSE                    = 0x0,
1682	DCP_CURSOR_UPDATE_TAKEN_TRUE                     = 0x1,
1683} DCP_CURSOR_UPDATE_TAKEN;
1684typedef enum DCP_CURSOR_UPDATE_LOCK {
1685	DCP_CURSOR_UPDATE_LOCK_FALSE                     = 0x0,
1686	DCP_CURSOR_UPDATE_LOCK_TRUE                      = 0x1,
1687} DCP_CURSOR_UPDATE_LOCK;
1688typedef enum DCP_CURSOR_DISABLE_MULTIPLE_UPDATE {
1689	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_FALSE         = 0x0,
1690	DCP_CURSOR_DISABLE_MULTIPLE_UPDATE_TRUE          = 0x1,
1691} DCP_CURSOR_DISABLE_MULTIPLE_UPDATE;
1692typedef enum DCP_CURSOR_UPDATE_STEREO_MODE {
1693	DCP_CURSOR_UPDATE_STEREO_MODE_BOTH               = 0x0,
1694	DCP_CURSOR_UPDATE_STEREO_MODE_SECONDARY_ONLY     = 0x1,
1695	DCP_CURSOR_UPDATE_STEREO_MODE_UNDEFINED          = 0x2,
1696	DCP_CURSOR_UPDATE_STEREO_MODE_PRIMARY_ONLY       = 0x3,
1697} DCP_CURSOR_UPDATE_STEREO_MODE;
1698typedef enum DCP_CURSOR2_EN {
1699	DCP_CURSOR2_EN_FALSE                             = 0x0,
1700	DCP_CURSOR2_EN_TRUE                              = 0x1,
1701} DCP_CURSOR2_EN;
1702typedef enum DCP_CUR2_INV_TRANS_CLAMP {
1703	DCP_CUR2_INV_TRANS_CLAMP_FALSE                   = 0x0,
1704	DCP_CUR2_INV_TRANS_CLAMP_TRUE                    = 0x1,
1705} DCP_CUR2_INV_TRANS_CLAMP;
1706typedef enum DCP_CURSOR2_MODE {
1707	DCP_CURSOR2_MODE_MONO_2BPP                       = 0x0,
1708	DCP_CURSOR2_MODE_24BPP_1BIT                      = 0x1,
1709	DCP_CURSOR2_MODE_24BPP_8BIT_PREMULTI             = 0x2,
1710	DCP_CURSOR2_MODE_24BPP_8BIT_UNPREMULTI           = 0x3,
1711} DCP_CURSOR2_MODE;
1712typedef enum DCP_CURSOR2_2X_MAGNIFY {
1713	DCP_CURSOR2_2X_MAGNIFY_FALSE                     = 0x0,
1714	DCP_CURSOR2_2X_MAGNIFY_TRUE                      = 0x1,
1715} DCP_CURSOR2_2X_MAGNIFY;
1716typedef enum DCP_CURSOR2_FORCE_MC_ON {
1717	DCP_CURSOR2_FORCE_MC_ON_FALSE                    = 0x0,
1718	DCP_CURSOR2_FORCE_MC_ON_TRUE                     = 0x1,
1719} DCP_CURSOR2_FORCE_MC_ON;
1720typedef enum DCP_CURSOR2_URGENT_CONTROL {
1721	DCP_CURSOR2_URGENT_CONTROL_MODE_0                = 0x0,
1722	DCP_CURSOR2_URGENT_CONTROL_MODE_1                = 0x1,
1723	DCP_CURSOR2_URGENT_CONTROL_MODE_2                = 0x2,
1724	DCP_CURSOR2_URGENT_CONTROL_MODE_3                = 0x3,
1725	DCP_CURSOR2_URGENT_CONTROL_MODE_4                = 0x4,
1726} DCP_CURSOR2_URGENT_CONTROL;
1727typedef enum DCP_CURSOR2_UPDATE_PENDING {
1728	DCP_CURSOR2_UPDATE_PENDING_FALSE                 = 0x0,
1729	DCP_CURSOR2_UPDATE_PENDING_TRUE                  = 0x1,
1730} DCP_CURSOR2_UPDATE_PENDING;
1731typedef enum DCP_CURSOR2_UPDATE_TAKEN {
1732	DCP_CURSOR2_UPDATE_TAKEN_FALSE                   = 0x0,
1733	DCP_CURSOR2_UPDATE_TAKEN_TRUE                    = 0x1,
1734} DCP_CURSOR2_UPDATE_TAKEN;
1735typedef enum DCP_CURSOR2_UPDATE_LOCK {
1736	DCP_CURSOR2_UPDATE_LOCK_FALSE                    = 0x0,
1737	DCP_CURSOR2_UPDATE_LOCK_TRUE                     = 0x1,
1738} DCP_CURSOR2_UPDATE_LOCK;
1739typedef enum DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE {
1740	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_FALSE        = 0x0,
1741	DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE_TRUE         = 0x1,
1742} DCP_CURSOR2_DISABLE_MULTIPLE_UPDATE;
1743typedef enum DCP_CURSOR2_UPDATE_STEREO_MODE {
1744	DCP_CURSOR2_UPDATE_STEREO_MODE_BOTH              = 0x0,
1745	DCP_CURSOR2_UPDATE_STEREO_MODE_SECONDARY_ONLY    = 0x1,
1746	DCP_CURSOR2_UPDATE_STEREO_MODE_UNDEFINED         = 0x2,
1747	DCP_CURSOR2_UPDATE_STEREO_MODE_PRIMARY_ONLY      = 0x3,
1748} DCP_CURSOR2_UPDATE_STEREO_MODE;
1749typedef enum DCP_CUR_REQUEST_FILTER_DIS {
1750	DCP_CUR_REQUEST_FILTER_DIS_FALSE                 = 0x0,
1751	DCP_CUR_REQUEST_FILTER_DIS_TRUE                  = 0x1,
1752} DCP_CUR_REQUEST_FILTER_DIS;
1753typedef enum DCP_CURSOR_STEREO_EN {
1754	DCP_CURSOR_STEREO_EN_FALSE                       = 0x0,
1755	DCP_CURSOR_STEREO_EN_TRUE                        = 0x1,
1756} DCP_CURSOR_STEREO_EN;
1757typedef enum DCP_CURSOR_STEREO_OFFSET_YNX {
1758	DCP_CURSOR_STEREO_OFFSET_YNX_X_POSITION          = 0x0,
1759	DCP_CURSOR_STEREO_OFFSET_YNX_Y_POSITION          = 0x1,
1760} DCP_CURSOR_STEREO_OFFSET_YNX;
1761typedef enum DCP_CURSOR2_STEREO_EN {
1762	DCP_CURSOR2_STEREO_EN_FALSE                      = 0x0,
1763	DCP_CURSOR2_STEREO_EN_TRUE                       = 0x1,
1764} DCP_CURSOR2_STEREO_EN;
1765typedef enum DCP_CURSOR2_STEREO_OFFSET_YNX {
1766	DCP_CURSOR2_STEREO_OFFSET_YNX_X_POSITION         = 0x0,
1767	DCP_CURSOR2_STEREO_OFFSET_YNX_Y_POSITION         = 0x1,
1768} DCP_CURSOR2_STEREO_OFFSET_YNX;
1769typedef enum DCP_DC_LUT_RW_MODE {
1770	DCP_DC_LUT_RW_MODE_256_ENTRY                     = 0x0,
1771	DCP_DC_LUT_RW_MODE_PWL                           = 0x1,
1772} DCP_DC_LUT_RW_MODE;
1773typedef enum DCP_DC_LUT_VGA_ACCESS_ENABLE {
1774	DCP_DC_LUT_VGA_ACCESS_ENABLE_FALSE               = 0x0,
1775	DCP_DC_LUT_VGA_ACCESS_ENABLE_TRUE                = 0x1,
1776} DCP_DC_LUT_VGA_ACCESS_ENABLE;
1777typedef enum DCP_DC_LUT_AUTOFILL {
1778	DCP_DC_LUT_AUTOFILL_FALSE                        = 0x0,
1779	DCP_DC_LUT_AUTOFILL_TRUE                         = 0x1,
1780} DCP_DC_LUT_AUTOFILL;
1781typedef enum DCP_DC_LUT_AUTOFILL_DONE {
1782	DCP_DC_LUT_AUTOFILL_DONE_FALSE                   = 0x0,
1783	DCP_DC_LUT_AUTOFILL_DONE_TRUE                    = 0x1,
1784} DCP_DC_LUT_AUTOFILL_DONE;
1785typedef enum DCP_DC_LUT_INC_B {
1786	DCP_DC_LUT_INC_B_NA                              = 0x0,
1787	DCP_DC_LUT_INC_B_2                               = 0x1,
1788	DCP_DC_LUT_INC_B_4                               = 0x2,
1789	DCP_DC_LUT_INC_B_8                               = 0x3,
1790	DCP_DC_LUT_INC_B_16                              = 0x4,
1791	DCP_DC_LUT_INC_B_32                              = 0x5,
1792	DCP_DC_LUT_INC_B_64                              = 0x6,
1793	DCP_DC_LUT_INC_B_128                             = 0x7,
1794	DCP_DC_LUT_INC_B_256                             = 0x8,
1795	DCP_DC_LUT_INC_B_512                             = 0x9,
1796} DCP_DC_LUT_INC_B;
1797typedef enum DCP_DC_LUT_DATA_B_SIGNED_EN {
1798	DCP_DC_LUT_DATA_B_SIGNED_EN_FALSE                = 0x0,
1799	DCP_DC_LUT_DATA_B_SIGNED_EN_TRUE                 = 0x1,
1800} DCP_DC_LUT_DATA_B_SIGNED_EN;
1801typedef enum DCP_DC_LUT_DATA_B_FLOAT_POINT_EN {
1802	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_FALSE           = 0x0,
1803	DCP_DC_LUT_DATA_B_FLOAT_POINT_EN_TRUE            = 0x1,
1804} DCP_DC_LUT_DATA_B_FLOAT_POINT_EN;
1805typedef enum DCP_DC_LUT_DATA_B_FORMAT {
1806	DCP_DC_LUT_DATA_B_FORMAT_U0P10                   = 0x0,
1807	DCP_DC_LUT_DATA_B_FORMAT_S1P10                   = 0x1,
1808	DCP_DC_LUT_DATA_B_FORMAT_U1P11                   = 0x2,
1809	DCP_DC_LUT_DATA_B_FORMAT_U0P12                   = 0x3,
1810} DCP_DC_LUT_DATA_B_FORMAT;
1811typedef enum DCP_DC_LUT_INC_G {
1812	DCP_DC_LUT_INC_G_NA                              = 0x0,
1813	DCP_DC_LUT_INC_G_2                               = 0x1,
1814	DCP_DC_LUT_INC_G_4                               = 0x2,
1815	DCP_DC_LUT_INC_G_8                               = 0x3,
1816	DCP_DC_LUT_INC_G_16                              = 0x4,
1817	DCP_DC_LUT_INC_G_32                              = 0x5,
1818	DCP_DC_LUT_INC_G_64                              = 0x6,
1819	DCP_DC_LUT_INC_G_128                             = 0x7,
1820	DCP_DC_LUT_INC_G_256                             = 0x8,
1821	DCP_DC_LUT_INC_G_512                             = 0x9,
1822} DCP_DC_LUT_INC_G;
1823typedef enum DCP_DC_LUT_DATA_G_SIGNED_EN {
1824	DCP_DC_LUT_DATA_G_SIGNED_EN_FALSE                = 0x0,
1825	DCP_DC_LUT_DATA_G_SIGNED_EN_TRUE                 = 0x1,
1826} DCP_DC_LUT_DATA_G_SIGNED_EN;
1827typedef enum DCP_DC_LUT_DATA_G_FLOAT_POINT_EN {
1828	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_FALSE           = 0x0,
1829	DCP_DC_LUT_DATA_G_FLOAT_POINT_EN_TRUE            = 0x1,
1830} DCP_DC_LUT_DATA_G_FLOAT_POINT_EN;
1831typedef enum DCP_DC_LUT_DATA_G_FORMAT {
1832	DCP_DC_LUT_DATA_G_FORMAT_U0P10                   = 0x0,
1833	DCP_DC_LUT_DATA_G_FORMAT_S1P10                   = 0x1,
1834	DCP_DC_LUT_DATA_G_FORMAT_U1P11                   = 0x2,
1835	DCP_DC_LUT_DATA_G_FORMAT_U0P12                   = 0x3,
1836} DCP_DC_LUT_DATA_G_FORMAT;
1837typedef enum DCP_DC_LUT_INC_R {
1838	DCP_DC_LUT_INC_R_NA                              = 0x0,
1839	DCP_DC_LUT_INC_R_2                               = 0x1,
1840	DCP_DC_LUT_INC_R_4                               = 0x2,
1841	DCP_DC_LUT_INC_R_8                               = 0x3,
1842	DCP_DC_LUT_INC_R_16                              = 0x4,
1843	DCP_DC_LUT_INC_R_32                              = 0x5,
1844	DCP_DC_LUT_INC_R_64                              = 0x6,
1845	DCP_DC_LUT_INC_R_128                             = 0x7,
1846	DCP_DC_LUT_INC_R_256                             = 0x8,
1847	DCP_DC_LUT_INC_R_512                             = 0x9,
1848} DCP_DC_LUT_INC_R;
1849typedef enum DCP_DC_LUT_DATA_R_SIGNED_EN {
1850	DCP_DC_LUT_DATA_R_SIGNED_EN_FALSE                = 0x0,
1851	DCP_DC_LUT_DATA_R_SIGNED_EN_TRUE                 = 0x1,
1852} DCP_DC_LUT_DATA_R_SIGNED_EN;
1853typedef enum DCP_DC_LUT_DATA_R_FLOAT_POINT_EN {
1854	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_FALSE           = 0x0,
1855	DCP_DC_LUT_DATA_R_FLOAT_POINT_EN_TRUE            = 0x1,
1856} DCP_DC_LUT_DATA_R_FLOAT_POINT_EN;
1857typedef enum DCP_DC_LUT_DATA_R_FORMAT {
1858	DCP_DC_LUT_DATA_R_FORMAT_U0P10                   = 0x0,
1859	DCP_DC_LUT_DATA_R_FORMAT_S1P10                   = 0x1,
1860	DCP_DC_LUT_DATA_R_FORMAT_U1P11                   = 0x2,
1861	DCP_DC_LUT_DATA_R_FORMAT_U0P12                   = 0x3,
1862} DCP_DC_LUT_DATA_R_FORMAT;
1863typedef enum DCP_CRC_ENABLE {
1864	DCP_CRC_ENABLE_FALSE                             = 0x0,
1865	DCP_CRC_ENABLE_TRUE                              = 0x1,
1866} DCP_CRC_ENABLE;
1867typedef enum DCP_CRC_SOURCE_SEL {
1868	DCP_CRC_SOURCE_SEL_OUTPUT_PIX                    = 0x0,
1869	DCP_CRC_SOURCE_SEL_INPUT_L32                     = 0x1,
1870	DCP_CRC_SOURCE_SEL_INPUT_H32                     = 0x2,
1871	DCP_CRC_SOURCE_SEL_OUTPUT_CNTL                   = 0x4,
1872} DCP_CRC_SOURCE_SEL;
1873typedef enum DCP_CRC_LINE_SEL {
1874	DCP_CRC_LINE_SEL_RESERVED                        = 0x0,
1875	DCP_CRC_LINE_SEL_EVEN                            = 0x1,
1876	DCP_CRC_LINE_SEL_ODD                             = 0x2,
1877	DCP_CRC_LINE_SEL_BOTH                            = 0x3,
1878} DCP_CRC_LINE_SEL;
1879typedef enum DCP_GRPH_FLIP_RATE {
1880	DCP_GRPH_FLIP_RATE_1FRAME                        = 0x0,
1881	DCP_GRPH_FLIP_RATE_2FRAME                        = 0x1,
1882	DCP_GRPH_FLIP_RATE_3FRAME                        = 0x2,
1883	DCP_GRPH_FLIP_RATE_4FRAME                        = 0x3,
1884	DCP_GRPH_FLIP_RATE_5FRAME                        = 0x4,
1885	DCP_GRPH_FLIP_RATE_6FRAME                        = 0x5,
1886	DCP_GRPH_FLIP_RATE_7FRAME                        = 0x6,
1887	DCP_GRPH_FLIP_RATE_8FRAME                        = 0x7,
1888} DCP_GRPH_FLIP_RATE;
1889typedef enum DCP_GRPH_FLIP_RATE_ENABLE {
1890	DCP_GRPH_FLIP_RATE_ENABLE_FALSE                  = 0x0,
1891	DCP_GRPH_FLIP_RATE_ENABLE_TRUE                   = 0x1,
1892} DCP_GRPH_FLIP_RATE_ENABLE;
1893typedef enum DCP_GSL0_EN {
1894	DCP_GSL0_EN_FALSE                                = 0x0,
1895	DCP_GSL0_EN_TRUE                                 = 0x1,
1896} DCP_GSL0_EN;
1897typedef enum DCP_GSL1_EN {
1898	DCP_GSL1_EN_FALSE                                = 0x0,
1899	DCP_GSL1_EN_TRUE                                 = 0x1,
1900} DCP_GSL1_EN;
1901typedef enum DCP_GSL2_EN {
1902	DCP_GSL2_EN_FALSE                                = 0x0,
1903	DCP_GSL2_EN_TRUE                                 = 0x1,
1904} DCP_GSL2_EN;
1905typedef enum DCP_GSL_MASTER_EN {
1906	DCP_GSL_MASTER_EN_FALSE                          = 0x0,
1907	DCP_GSL_MASTER_EN_TRUE                           = 0x1,
1908} DCP_GSL_MASTER_EN;
1909typedef enum DCP_GSL_XDMA_GROUP {
1910	DCP_GSL_XDMA_GROUP_VSYNC                         = 0x0,
1911	DCP_GSL_XDMA_GROUP_HSYNC0                        = 0x1,
1912	DCP_GSL_XDMA_GROUP_HSYNC1                        = 0x2,
1913	DCP_GSL_XDMA_GROUP_HSYNC2                        = 0x3,
1914} DCP_GSL_XDMA_GROUP;
1915typedef enum DCP_GSL_XDMA_GROUP_UNDERFLOW_EN {
1916	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_FALSE            = 0x0,
1917	DCP_GSL_XDMA_GROUP_UNDERFLOW_EN_TRUE             = 0x1,
1918} DCP_GSL_XDMA_GROUP_UNDERFLOW_EN;
1919typedef enum DCP_GSL_SYNC_SOURCE {
1920	DCP_GSL_SYNC_SOURCE_FLIP                         = 0x0,
1921	DCP_GSL_SYNC_SOURCE_PHASE0                       = 0x1,
1922	DCP_GSL_SYNC_SOURCE_RESET                        = 0x2,
1923	DCP_GSL_SYNC_SOURCE_PHASE1                       = 0x3,
1924} DCP_GSL_SYNC_SOURCE;
1925typedef enum DCP_GSL_DELAY_SURFACE_UPDATE_PENDING {
1926	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_FALSE       = 0x0,
1927	DCP_GSL_DELAY_SURFACE_UPDATE_PENDING_TRUE        = 0x1,
1928} DCP_GSL_DELAY_SURFACE_UPDATE_PENDING;
1929typedef enum DCP_TEST_DEBUG_WRITE_EN {
1930	DCP_TEST_DEBUG_WRITE_EN_FALSE                    = 0x0,
1931	DCP_TEST_DEBUG_WRITE_EN_TRUE                     = 0x1,
1932} DCP_TEST_DEBUG_WRITE_EN;
1933typedef enum DCP_GRPH_STEREOSYNC_FLIP_EN {
1934	DCP_GRPH_STEREOSYNC_FLIP_EN_FALSE                = 0x0,
1935	DCP_GRPH_STEREOSYNC_FLIP_EN_TRUE                 = 0x1,
1936} DCP_GRPH_STEREOSYNC_FLIP_EN;
1937typedef enum DCP_GRPH_STEREOSYNC_FLIP_MODE {
1938	DCP_GRPH_STEREOSYNC_FLIP_MODE_FLIP               = 0x0,
1939	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE0             = 0x1,
1940	DCP_GRPH_STEREOSYNC_FLIP_MODE_RESET              = 0x2,
1941	DCP_GRPH_STEREOSYNC_FLIP_MODE_PHASE1             = 0x3,
1942} DCP_GRPH_STEREOSYNC_FLIP_MODE;
1943typedef enum DCP_GRPH_STEREOSYNC_SELECT_DISABLE {
1944	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_FALSE         = 0x0,
1945	DCP_GRPH_STEREOSYNC_SELECT_DISABLE_TRUE          = 0x1,
1946} DCP_GRPH_STEREOSYNC_SELECT_DISABLE;
1947typedef enum DCP_GRPH_ROTATION_ANGLE {
1948	DCP_GRPH_ROTATION_ANGLE_0                        = 0x0,
1949	DCP_GRPH_ROTATION_ANGLE_90                       = 0x1,
1950	DCP_GRPH_ROTATION_ANGLE_180                      = 0x2,
1951	DCP_GRPH_ROTATION_ANGLE_270                      = 0x3,
1952} DCP_GRPH_ROTATION_ANGLE;
1953typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN {
1954	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_FALSE       = 0x0,
1955	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN_TRUE        = 0x1,
1956} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_EN;
1957typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE {
1958	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_NUM  = 0x0,
1959	DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE_RELY_ENABLE= 0x1,
1960} DCP_GRPH_XDMA_CACHE_UNDERFLOW_CNT_MODE;
1961typedef enum DCP_GRPH_REGAMMA_MODE {
1962	DCP_GRPH_REGAMMA_MODE_BYPASS                     = 0x0,
1963	DCP_GRPH_REGAMMA_MODE_SRGB                       = 0x1,
1964	DCP_GRPH_REGAMMA_MODE_XVYCC                      = 0x2,
1965	DCP_GRPH_REGAMMA_MODE_PROGA                      = 0x3,
1966	DCP_GRPH_REGAMMA_MODE_PROGB                      = 0x4,
1967} DCP_GRPH_REGAMMA_MODE;
1968typedef enum DCP_ALPHA_ROUND_TRUNC_MODE {
1969	DCP_ALPHA_ROUND_TRUNC_MODE_ROUND                 = 0x0,
1970	DCP_ALPHA_ROUND_TRUNC_MODE_TRUNC                 = 0x1,
1971} DCP_ALPHA_ROUND_TRUNC_MODE;
1972typedef enum DCP_CURSOR_ALPHA_BLND_ENA {
1973	DCP_CURSOR_ALPHA_BLND_ENA_FALSE                  = 0x0,
1974	DCP_CURSOR_ALPHA_BLND_ENA_TRUE                   = 0x1,
1975} DCP_CURSOR_ALPHA_BLND_ENA;
1976typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK {
1977	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_FALSE   = 0x0,
1978	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK_TRUE    = 0x1,
1979} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_MASK;
1980typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK {
1981	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_FALSE    = 0x0,
1982	DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK_TRUE     = 0x1,
1983} DCP_GRPH_XDMA_CACHE_UNDERFLOW_FRAME_ACK;
1984typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK {
1985	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_FALSE     = 0x0,
1986	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK_TRUE      = 0x1,
1987} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_MASK;
1988typedef enum DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK {
1989	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_FALSE      = 0x0,
1990	DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK_TRUE       = 0x1,
1991} DCP_GRPH_XDMA_CACHE_UNDERFLOW_INT_ACK;
1992typedef enum DCP_GRPH_SURFACE_COUNTER_EN {
1993	DCP_GRPH_SURFACE_COUNTER_EN_DISABLE              = 0x0,
1994	DCP_GRPH_SURFACE_COUNTER_EN_ENABLE               = 0x1,
1995} DCP_GRPH_SURFACE_COUNTER_EN;
1996typedef enum DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT {
1997	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_0          = 0x0,
1998	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_1          = 0x1,
1999	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_2          = 0x2,
2000	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_3          = 0x3,
2001	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_4          = 0x4,
2002	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_5          = 0x5,
2003	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_6          = 0x6,
2004	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_7          = 0x7,
2005	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_8          = 0x8,
2006	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_9          = 0x9,
2007	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_10         = 0xa,
2008	DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT_11         = 0xb,
2009} DCP_GRPH_SURFACE_COUNTER_EVENT_SELECT;
2010typedef enum DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED {
2011	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_NO     = 0x0,
2012	DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED_YES    = 0x1,
2013} DCP_GRPH_SURFACE_COUNTER_ERR_WRAP_OCCURED;
2014typedef enum HDMI_KEEPOUT_MODE {
2015	HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC                = 0x0,
2016	HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC              = 0x1,
2017} HDMI_KEEPOUT_MODE;
2018typedef enum HDMI_CLOCK_CHANNEL_RATE {
2019	HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE       = 0x0,
2020	HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE     = 0x1,
2021} HDMI_CLOCK_CHANNEL_RATE;
2022typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
2023	HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE             = 0x0,
2024	HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE            = 0x1,
2025} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
2026typedef enum HDMI_PACKET_GEN_VERSION {
2027	HDMI_PACKET_GEN_VERSION_OLD                      = 0x0,
2028	HDMI_PACKET_GEN_VERSION_NEW                      = 0x1,
2029} HDMI_PACKET_GEN_VERSION;
2030typedef enum HDMI_ERROR_ACK {
2031	HDMI_ERROR_ACK_INT                               = 0x0,
2032	HDMI_ERROR_NOT_ACK                               = 0x1,
2033} HDMI_ERROR_ACK;
2034typedef enum HDMI_ERROR_MASK {
2035	HDMI_ERROR_MASK_INT                              = 0x0,
2036	HDMI_ERROR_NOT_MASK                              = 0x1,
2037} HDMI_ERROR_MASK;
2038typedef enum HDMI_DEEP_COLOR_DEPTH {
2039	HDMI_DEEP_COLOR_DEPTH_24BPP                      = 0x0,
2040	HDMI_DEEP_COLOR_DEPTH_30BPP                      = 0x1,
2041	HDMI_DEEP_COLOR_DEPTH_36BPP                      = 0x2,
2042	HDMI_DEEP_COLOR_DEPTH_RESERVED                   = 0x3,
2043} HDMI_DEEP_COLOR_DEPTH;
2044typedef enum HDMI_AUDIO_DELAY_EN {
2045	HDMI_AUDIO_DELAY_DISABLE                         = 0x0,
2046	HDMI_AUDIO_DELAY_58CLK                           = 0x1,
2047	HDMI_AUDIO_DELAY_56CLK                           = 0x2,
2048	HDMI_AUDIO_DELAY_RESERVED                        = 0x3,
2049} HDMI_AUDIO_DELAY_EN;
2050typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
2051	HDMI_NOT_SEND_MAX_AUDIO_PACKETS                  = 0x0,
2052	HDMI_SEND_MAX_AUDIO_PACKETS                      = 0x1,
2053} HDMI_AUDIO_SEND_MAX_PACKETS;
2054typedef enum HDMI_ACR_SEND {
2055	HDMI_ACR_NOT_SEND                                = 0x0,
2056	HDMI_ACR_PKT_SEND                                = 0x1,
2057} HDMI_ACR_SEND;
2058typedef enum HDMI_ACR_CONT {
2059	HDMI_ACR_CONT_DISABLE                            = 0x0,
2060	HDMI_ACR_CONT_ENABLE                             = 0x1,
2061} HDMI_ACR_CONT;
2062typedef enum HDMI_ACR_SELECT {
2063	HDMI_ACR_SELECT_HW                               = 0x0,
2064	HDMI_ACR_SELECT_32K                              = 0x1,
2065	HDMI_ACR_SELECT_44K                              = 0x2,
2066	HDMI_ACR_SELECT_48K                              = 0x3,
2067} HDMI_ACR_SELECT;
2068typedef enum HDMI_ACR_SOURCE {
2069	HDMI_ACR_SOURCE_HW                               = 0x0,
2070	HDMI_ACR_SOURCE_SW                               = 0x1,
2071} HDMI_ACR_SOURCE;
2072typedef enum HDMI_ACR_N_MULTIPLE {
2073	HDMI_ACR_0_MULTIPLE_RESERVED                     = 0x0,
2074	HDMI_ACR_1_MULTIPLE                              = 0x1,
2075	HDMI_ACR_2_MULTIPLE                              = 0x2,
2076	HDMI_ACR_3_MULTIPLE_RESERVED                     = 0x3,
2077	HDMI_ACR_4_MULTIPLE                              = 0x4,
2078	HDMI_ACR_5_MULTIPLE_RESERVED                     = 0x5,
2079	HDMI_ACR_6_MULTIPLE_RESERVED                     = 0x6,
2080	HDMI_ACR_7_MULTIPLE_RESERVED                     = 0x7,
2081} HDMI_ACR_N_MULTIPLE;
2082typedef enum HDMI_ACR_AUDIO_PRIORITY {
2083	HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE     = 0x0,
2084	HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT     = 0x1,
2085} HDMI_ACR_AUDIO_PRIORITY;
2086typedef enum HDMI_NULL_SEND {
2087	HDMI_NULL_NOT_SEND                               = 0x0,
2088	HDMI_NULL_PKT_SEND                               = 0x1,
2089} HDMI_NULL_SEND;
2090typedef enum HDMI_GC_SEND {
2091	HDMI_GC_NOT_SEND                                 = 0x0,
2092	HDMI_GC_PKT_SEND                                 = 0x1,
2093} HDMI_GC_SEND;
2094typedef enum HDMI_GC_CONT {
2095	HDMI_GC_CONT_DISABLE                             = 0x0,
2096	HDMI_GC_CONT_ENABLE                              = 0x1,
2097} HDMI_GC_CONT;
2098typedef enum HDMI_ISRC_SEND {
2099	HDMI_ISRC_NOT_SEND                               = 0x0,
2100	HDMI_ISRC_PKT_SEND                               = 0x1,
2101} HDMI_ISRC_SEND;
2102typedef enum HDMI_ISRC_CONT {
2103	HDMI_ISRC_CONT_DISABLE                           = 0x0,
2104	HDMI_ISRC_CONT_ENABLE                            = 0x1,
2105} HDMI_ISRC_CONT;
2106typedef enum HDMI_AVI_INFO_SEND {
2107	HDMI_AVI_INFO_NOT_SEND                           = 0x0,
2108	HDMI_AVI_INFO_PKT_SEND                           = 0x1,
2109} HDMI_AVI_INFO_SEND;
2110typedef enum HDMI_AVI_INFO_CONT {
2111	HDMI_AVI_INFO_CONT_DISABLE                       = 0x0,
2112	HDMI_AVI_INFO_CONT_ENABLE                        = 0x1,
2113} HDMI_AVI_INFO_CONT;
2114typedef enum HDMI_AUDIO_INFO_SEND {
2115	HDMI_AUDIO_INFO_NOT_SEND                         = 0x0,
2116	HDMI_AUDIO_INFO_PKT_SEND                         = 0x1,
2117} HDMI_AUDIO_INFO_SEND;
2118typedef enum HDMI_AUDIO_INFO_CONT {
2119	HDMI_AUDIO_INFO_CONT_DISABLE                     = 0x0,
2120	HDMI_AUDIO_INFO_CONT_ENABLE                      = 0x1,
2121} HDMI_AUDIO_INFO_CONT;
2122typedef enum HDMI_MPEG_INFO_SEND {
2123	HDMI_MPEG_INFO_NOT_SEND                          = 0x0,
2124	HDMI_MPEG_INFO_PKT_SEND                          = 0x1,
2125} HDMI_MPEG_INFO_SEND;
2126typedef enum HDMI_MPEG_INFO_CONT {
2127	HDMI_MPEG_INFO_CONT_DISABLE                      = 0x0,
2128	HDMI_MPEG_INFO_CONT_ENABLE                       = 0x1,
2129} HDMI_MPEG_INFO_CONT;
2130typedef enum HDMI_GENERIC0_SEND {
2131	HDMI_GENERIC0_NOT_SEND                           = 0x0,
2132	HDMI_GENERIC0_PKT_SEND                           = 0x1,
2133} HDMI_GENERIC0_SEND;
2134typedef enum HDMI_GENERIC0_CONT {
2135	HDMI_GENERIC0_CONT_DISABLE                       = 0x0,
2136	HDMI_GENERIC0_CONT_ENABLE                        = 0x1,
2137} HDMI_GENERIC0_CONT;
2138typedef enum HDMI_GENERIC1_SEND {
2139	HDMI_GENERIC1_NOT_SEND                           = 0x0,
2140	HDMI_GENERIC1_PKT_SEND                           = 0x1,
2141} HDMI_GENERIC1_SEND;
2142typedef enum HDMI_GENERIC1_CONT {
2143	HDMI_GENERIC1_CONT_DISABLE                       = 0x0,
2144	HDMI_GENERIC1_CONT_ENABLE                        = 0x1,
2145} HDMI_GENERIC1_CONT;
2146typedef enum HDMI_GC_AVMUTE_CONT {
2147	HDMI_GC_AVMUTE_CONT_DISABLE                      = 0x0,
2148	HDMI_GC_AVMUTE_CONT_ENABLE                       = 0x1,
2149} HDMI_GC_AVMUTE_CONT;
2150typedef enum HDMI_PACKING_PHASE_OVERRIDE {
2151	HDMI_PACKING_PHASE_SET_BY_HW                     = 0x0,
2152	HDMI_PACKING_PHASE_SET_BY_SW                     = 0x1,
2153} HDMI_PACKING_PHASE_OVERRIDE;
2154typedef enum HDMI_GENERIC2_SEND {
2155	HDMI_GENERIC2_NOT_SEND                           = 0x0,
2156	HDMI_GENERIC2_PKT_SEND                           = 0x1,
2157} HDMI_GENERIC2_SEND;
2158typedef enum HDMI_GENERIC2_CONT {
2159	HDMI_GENERIC2_CONT_DISABLE                       = 0x0,
2160	HDMI_GENERIC2_CONT_ENABLE                        = 0x1,
2161} HDMI_GENERIC2_CONT;
2162typedef enum HDMI_GENERIC3_SEND {
2163	HDMI_GENERIC3_NOT_SEND                           = 0x0,
2164	HDMI_GENERIC3_PKT_SEND                           = 0x1,
2165} HDMI_GENERIC3_SEND;
2166typedef enum HDMI_GENERIC3_CONT {
2167	HDMI_GENERIC3_CONT_DISABLE                       = 0x0,
2168	HDMI_GENERIC3_CONT_ENABLE                        = 0x1,
2169} HDMI_GENERIC3_CONT;
2170typedef enum TMDS_PIXEL_ENCODING {
2171	TMDS_PIXEL_ENCODING_444                          = 0x0,
2172	TMDS_PIXEL_ENCODING_422                          = 0x1,
2173} TMDS_PIXEL_ENCODING;
2174typedef enum TMDS_COLOR_FORMAT {
2175	TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP= 0x0,
2176	TMDS_COLOR_FORMAT_TWIN30BPP_LSB                  = 0x1,
2177	TMDS_COLOR_FORMAT_DUAL30BPP                      = 0x2,
2178	TMDS_COLOR_FORMAT_RESERVED                       = 0x3,
2179} TMDS_COLOR_FORMAT;
2180typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
2181	TMDS_STEREOSYNC_CTL0                             = 0x0,
2182	TMDS_STEREOSYNC_CTL1                             = 0x1,
2183	TMDS_STEREOSYNC_CTL2                             = 0x2,
2184	TMDS_STEREOSYNC_CTL3                             = 0x3,
2185} TMDS_STEREOSYNC_CTL_SEL_REG;
2186typedef enum TMDS_CTL0_DATA_SEL {
2187	TMDS_CTL0_DATA_SEL0_RESERVED                     = 0x0,
2188	TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2189	TMDS_CTL0_DATA_SEL2_VSYNC                        = 0x2,
2190	TMDS_CTL0_DATA_SEL3_RESERVED                     = 0x3,
2191	TMDS_CTL0_DATA_SEL4_HSYNC                        = 0x4,
2192	TMDS_CTL0_DATA_SEL5_SEL7_RESERVED                = 0x5,
2193	TMDS_CTL0_DATA_SEL8_RANDOM_DATA                  = 0x6,
2194	TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA            = 0x7,
2195} TMDS_CTL0_DATA_SEL;
2196typedef enum TMDS_CTL0_DATA_DELAY {
2197	TMDS_CTL0_DATA_DELAY_0PIX                        = 0x0,
2198	TMDS_CTL0_DATA_DELAY_1PIX                        = 0x1,
2199	TMDS_CTL0_DATA_DELAY_2PIX                        = 0x2,
2200	TMDS_CTL0_DATA_DELAY_3PIX                        = 0x3,
2201	TMDS_CTL0_DATA_DELAY_4PIX                        = 0x4,
2202	TMDS_CTL0_DATA_DELAY_5PIX                        = 0x5,
2203	TMDS_CTL0_DATA_DELAY_6PIX                        = 0x6,
2204	TMDS_CTL0_DATA_DELAY_7PIX                        = 0x7,
2205} TMDS_CTL0_DATA_DELAY;
2206typedef enum TMDS_CTL0_DATA_INVERT {
2207	TMDS_CTL0_DATA_NORMAL                            = 0x0,
2208	TMDS_CTL0_DATA_INVERT_EN                         = 0x1,
2209} TMDS_CTL0_DATA_INVERT;
2210typedef enum TMDS_CTL0_DATA_MODULATION {
2211	TMDS_CTL0_DATA_MODULATION_DISABLE                = 0x0,
2212	TMDS_CTL0_DATA_MODULATION_BIT0                   = 0x1,
2213	TMDS_CTL0_DATA_MODULATION_BIT1                   = 0x2,
2214	TMDS_CTL0_DATA_MODULATION_BIT2                   = 0x3,
2215} TMDS_CTL0_DATA_MODULATION;
2216typedef enum TMDS_CTL0_PATTERN_OUT_EN {
2217	TMDS_CTL0_PATTERN_OUT_DISABLE                    = 0x0,
2218	TMDS_CTL0_PATTERN_OUT_ENABLE                     = 0x1,
2219} TMDS_CTL0_PATTERN_OUT_EN;
2220typedef enum TMDS_CTL1_DATA_SEL {
2221	TMDS_CTL1_DATA_SEL0_RESERVED                     = 0x0,
2222	TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2223	TMDS_CTL1_DATA_SEL2_VSYNC                        = 0x2,
2224	TMDS_CTL1_DATA_SEL3_RESERVED                     = 0x3,
2225	TMDS_CTL1_DATA_SEL4_HSYNC                        = 0x4,
2226	TMDS_CTL1_DATA_SEL5_SEL7_RESERVED                = 0x5,
2227	TMDS_CTL1_DATA_SEL8_BLANK_TIME                   = 0x6,
2228	TMDS_CTL1_DATA_SEL9_SEL15_RESERVED               = 0x7,
2229} TMDS_CTL1_DATA_SEL;
2230typedef enum TMDS_CTL1_DATA_DELAY {
2231	TMDS_CTL1_DATA_DELAY_0PIX                        = 0x0,
2232	TMDS_CTL1_DATA_DELAY_1PIX                        = 0x1,
2233	TMDS_CTL1_DATA_DELAY_2PIX                        = 0x2,
2234	TMDS_CTL1_DATA_DELAY_3PIX                        = 0x3,
2235	TMDS_CTL1_DATA_DELAY_4PIX                        = 0x4,
2236	TMDS_CTL1_DATA_DELAY_5PIX                        = 0x5,
2237	TMDS_CTL1_DATA_DELAY_6PIX                        = 0x6,
2238	TMDS_CTL1_DATA_DELAY_7PIX                        = 0x7,
2239} TMDS_CTL1_DATA_DELAY;
2240typedef enum TMDS_CTL1_DATA_INVERT {
2241	TMDS_CTL1_DATA_NORMAL                            = 0x0,
2242	TMDS_CTL1_DATA_INVERT_EN                         = 0x1,
2243} TMDS_CTL1_DATA_INVERT;
2244typedef enum TMDS_CTL1_DATA_MODULATION {
2245	TMDS_CTL1_DATA_MODULATION_DISABLE                = 0x0,
2246	TMDS_CTL1_DATA_MODULATION_BIT0                   = 0x1,
2247	TMDS_CTL1_DATA_MODULATION_BIT1                   = 0x2,
2248	TMDS_CTL1_DATA_MODULATION_BIT2                   = 0x3,
2249} TMDS_CTL1_DATA_MODULATION;
2250typedef enum TMDS_CTL1_PATTERN_OUT_EN {
2251	TMDS_CTL1_PATTERN_OUT_DISABLE                    = 0x0,
2252	TMDS_CTL1_PATTERN_OUT_ENABLE                     = 0x1,
2253} TMDS_CTL1_PATTERN_OUT_EN;
2254typedef enum TMDS_CTL2_DATA_SEL {
2255	TMDS_CTL2_DATA_SEL0_RESERVED                     = 0x0,
2256	TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2257	TMDS_CTL2_DATA_SEL2_VSYNC                        = 0x2,
2258	TMDS_CTL2_DATA_SEL3_RESERVED                     = 0x3,
2259	TMDS_CTL2_DATA_SEL4_HSYNC                        = 0x4,
2260	TMDS_CTL2_DATA_SEL5_SEL7_RESERVED                = 0x5,
2261	TMDS_CTL2_DATA_SEL8_BLANK_TIME                   = 0x6,
2262	TMDS_CTL2_DATA_SEL9_SEL15_RESERVED               = 0x7,
2263} TMDS_CTL2_DATA_SEL;
2264typedef enum TMDS_CTL2_DATA_DELAY {
2265	TMDS_CTL2_DATA_DELAY_0PIX                        = 0x0,
2266	TMDS_CTL2_DATA_DELAY_1PIX                        = 0x1,
2267	TMDS_CTL2_DATA_DELAY_2PIX                        = 0x2,
2268	TMDS_CTL2_DATA_DELAY_3PIX                        = 0x3,
2269	TMDS_CTL2_DATA_DELAY_4PIX                        = 0x4,
2270	TMDS_CTL2_DATA_DELAY_5PIX                        = 0x5,
2271	TMDS_CTL2_DATA_DELAY_6PIX                        = 0x6,
2272	TMDS_CTL2_DATA_DELAY_7PIX                        = 0x7,
2273} TMDS_CTL2_DATA_DELAY;
2274typedef enum TMDS_CTL2_DATA_INVERT {
2275	TMDS_CTL2_DATA_NORMAL                            = 0x0,
2276	TMDS_CTL2_DATA_INVERT_EN                         = 0x1,
2277} TMDS_CTL2_DATA_INVERT;
2278typedef enum TMDS_CTL2_DATA_MODULATION {
2279	TMDS_CTL2_DATA_MODULATION_DISABLE                = 0x0,
2280	TMDS_CTL2_DATA_MODULATION_BIT0                   = 0x1,
2281	TMDS_CTL2_DATA_MODULATION_BIT1                   = 0x2,
2282	TMDS_CTL2_DATA_MODULATION_BIT2                   = 0x3,
2283} TMDS_CTL2_DATA_MODULATION;
2284typedef enum TMDS_CTL2_PATTERN_OUT_EN {
2285	TMDS_CTL2_PATTERN_OUT_DISABLE                    = 0x0,
2286	TMDS_CTL2_PATTERN_OUT_ENABLE                     = 0x1,
2287} TMDS_CTL2_PATTERN_OUT_EN;
2288typedef enum TMDS_CTL3_DATA_DELAY {
2289	TMDS_CTL3_DATA_DELAY_0PIX                        = 0x0,
2290	TMDS_CTL3_DATA_DELAY_1PIX                        = 0x1,
2291	TMDS_CTL3_DATA_DELAY_2PIX                        = 0x2,
2292	TMDS_CTL3_DATA_DELAY_3PIX                        = 0x3,
2293	TMDS_CTL3_DATA_DELAY_4PIX                        = 0x4,
2294	TMDS_CTL3_DATA_DELAY_5PIX                        = 0x5,
2295	TMDS_CTL3_DATA_DELAY_6PIX                        = 0x6,
2296	TMDS_CTL3_DATA_DELAY_7PIX                        = 0x7,
2297} TMDS_CTL3_DATA_DELAY;
2298typedef enum TMDS_CTL3_DATA_INVERT {
2299	TMDS_CTL3_DATA_NORMAL                            = 0x0,
2300	TMDS_CTL3_DATA_INVERT_EN                         = 0x1,
2301} TMDS_CTL3_DATA_INVERT;
2302typedef enum TMDS_CTL3_DATA_MODULATION {
2303	TMDS_CTL3_DATA_MODULATION_DISABLE                = 0x0,
2304	TMDS_CTL3_DATA_MODULATION_BIT0                   = 0x1,
2305	TMDS_CTL3_DATA_MODULATION_BIT1                   = 0x2,
2306	TMDS_CTL3_DATA_MODULATION_BIT2                   = 0x3,
2307} TMDS_CTL3_DATA_MODULATION;
2308typedef enum TMDS_CTL3_PATTERN_OUT_EN {
2309	TMDS_CTL3_PATTERN_OUT_DISABLE                    = 0x0,
2310	TMDS_CTL3_PATTERN_OUT_ENABLE                     = 0x1,
2311} TMDS_CTL3_PATTERN_OUT_EN;
2312typedef enum TMDS_CTL3_DATA_SEL {
2313	TMDS_CTL3_DATA_SEL0_RESERVED                     = 0x0,
2314	TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE               = 0x1,
2315	TMDS_CTL3_DATA_SEL2_VSYNC                        = 0x2,
2316	TMDS_CTL3_DATA_SEL3_RESERVED                     = 0x3,
2317	TMDS_CTL3_DATA_SEL4_HSYNC                        = 0x4,
2318	TMDS_CTL3_DATA_SEL5_SEL7_RESERVED                = 0x5,
2319	TMDS_CTL3_DATA_SEL8_BLANK_TIME                   = 0x6,
2320	TMDS_CTL3_DATA_SEL9_SEL15_RESERVED               = 0x7,
2321} TMDS_CTL3_DATA_SEL;
2322typedef enum DIG_FE_CNTL_SOURCE_SELECT {
2323	DIG_FE_SOURCE_FROM_FMT0                          = 0x0,
2324	DIG_FE_SOURCE_FROM_FMT1                          = 0x1,
2325	DIG_FE_SOURCE_FROM_FMT2                          = 0x2,
2326	DIG_FE_SOURCE_FROM_FMT3                          = 0x3,
2327} DIG_FE_CNTL_SOURCE_SELECT;
2328typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
2329	DIG_FE_STEREOSYNC_FROM_FMT0                      = 0x0,
2330	DIG_FE_STEREOSYNC_FROM_FMT1                      = 0x1,
2331	DIG_FE_STEREOSYNC_FROM_FMT2                      = 0x2,
2332	DIG_FE_STEREOSYNC_FROM_FMT3                      = 0x3,
2333} DIG_FE_CNTL_STEREOSYNC_SELECT;
2334typedef enum DIG_FIFO_READ_CLOCK_SRC {
2335	DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG                = 0x0,
2336	DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE        = 0x1,
2337} DIG_FIFO_READ_CLOCK_SRC;
2338typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
2339	DIG_OUTPUT_CRC_ON_LINK0                          = 0x0,
2340	DIG_OUTPUT_CRC_ON_LINK1                          = 0x1,
2341} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
2342typedef enum DIG_OUTPUT_CRC_DATA_SEL {
2343	DIG_OUTPUT_CRC_FOR_FULLFRAME                     = 0x0,
2344	DIG_OUTPUT_CRC_FOR_ACTIVEONLY                    = 0x1,
2345	DIG_OUTPUT_CRC_FOR_VBI                           = 0x2,
2346	DIG_OUTPUT_CRC_FOR_AUDIO                         = 0x3,
2347} DIG_OUTPUT_CRC_DATA_SEL;
2348typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
2349	DIG_IN_NORMAL_OPERATION                          = 0x0,
2350	DIG_IN_DEBUG_MODE                                = 0x1,
2351} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
2352typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
2353	DIG_10BIT_TEST_PATTERN                           = 0x0,
2354	DIG_ALTERNATING_TEST_PATTERN                     = 0x1,
2355} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
2356typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
2357	DIG_TEST_PATTERN_NORMAL                          = 0x0,
2358	DIG_TEST_PATTERN_RANDOM                          = 0x1,
2359} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
2360typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
2361	DIG_RANDOM_PATTERN_ENABLED                       = 0x0,
2362	DIG_RANDOM_PATTERN_RESETED                       = 0x1,
2363} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
2364typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
2365	DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE           = 0x0,
2366	DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG       = 0x1,
2367} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
2368typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
2369	DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS       = 0x0,
2370	DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH          = 0x1,
2371} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
2372typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
2373	DIG_FIFO_USE_OVERWRITE_LEVEL                     = 0x0,
2374	DIG_FIFO_USE_CAL_AVERAGE_LEVEL                   = 0x1,
2375} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
2376typedef enum DIG_FIFO_ERROR_ACK {
2377	DIG_FIFO_ERROR_ACK_INT                           = 0x0,
2378	DIG_FIFO_ERROR_NOT_ACK                           = 0x1,
2379} DIG_FIFO_ERROR_ACK;
2380typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
2381	DIG_FIFO_NOT_FORCE_RECAL_AVERAGE                 = 0x0,
2382	DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL               = 0x1,
2383} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
2384typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
2385	DIG_FIFO_NOT_FORCE_RECOMP_MINMAX                 = 0x0,
2386	DIG_FIFO_FORCE_RECOMP_MINMAX                     = 0x1,
2387} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
2388typedef enum DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT {
2389	DIG_DISPCLK_SWITCH_AT_EARLY_VBLANK               = 0x0,
2390	DIG_DISPCLK_SWITCH_AT_FIRST_HSYNC                = 0x1,
2391} DIG_DISPCLK_SWITCH_CNTL_SWITCH_POINT;
2392typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK {
2393	DIG_DISPCLK_SWITCH_ALLOWED_ACK_INT               = 0x0,
2394	DIG_DISPCLK_SWITCH_ALLOWED_INT_NOT_ACK           = 0x1,
2395} DIG_DISPCLK_SWITCH_ALLOWED_INT_ACK;
2396typedef enum DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK {
2397	DIG_DISPCLK_SWITCH_ALLOWED_MASK_INT              = 0x0,
2398	DIG_DISPCLK_SWITCH_ALLOWED_INT_UNMASK            = 0x1,
2399} DIG_DISPCLK_SWITCH_ALLOWED_INT_MASK;
2400typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
2401	AFMT_INTERRUPT_DISABLE                           = 0x0,
2402	AFMT_INTERRUPT_ENABLE                            = 0x1,
2403} AFMT_INTERRUPT_STATUS_CHG_MASK;
2404typedef enum HDMI_GC_AVMUTE {
2405	HDMI_GC_AVMUTE_SET                               = 0x0,
2406	HDMI_GC_AVMUTE_UNSET                             = 0x1,
2407} HDMI_GC_AVMUTE;
2408typedef enum HDMI_DEFAULT_PAHSE {
2409	HDMI_DEFAULT_PHASE_IS_0                          = 0x0,
2410	HDMI_DEFAULT_PHASE_IS_1                          = 0x1,
2411} HDMI_DEFAULT_PAHSE;
2412typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
2413	AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS= 0x0,
2414	AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER               = 0x1,
2415} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
2416typedef enum AUDIO_LAYOUT_SELECT {
2417	AUDIO_LAYOUT_0                                   = 0x0,
2418	AUDIO_LAYOUT_1                                   = 0x1,
2419} AUDIO_LAYOUT_SELECT;
2420typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
2421	AFMT_AUDIO_CRC_ONESHOT                           = 0x0,
2422	AFMT_AUDIO_CRC_AUTO_RESTART                      = 0x1,
2423} AFMT_AUDIO_CRC_CONTROL_CONT;
2424typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
2425	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT            = 0x0,
2426	AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT           = 0x1,
2427} AFMT_AUDIO_CRC_CONTROL_SOURCE;
2428typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
2429	AFMT_AUDIO_CRC_CH0_SIG                           = 0x0,
2430	AFMT_AUDIO_CRC_CH1_SIG                           = 0x1,
2431	AFMT_AUDIO_CRC_CH2_SIG                           = 0x2,
2432	AFMT_AUDIO_CRC_CH3_SIG                           = 0x3,
2433	AFMT_AUDIO_CRC_CH4_SIG                           = 0x4,
2434	AFMT_AUDIO_CRC_CH5_SIG                           = 0x5,
2435	AFMT_AUDIO_CRC_CH6_SIG                           = 0x6,
2436	AFMT_AUDIO_CRC_CH7_SIG                           = 0x7,
2437	AFMT_AUDIO_CRC_RESERVED                          = 0x8,
2438	AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT                = 0x9,
2439} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
2440typedef enum AFMT_RAMP_CONTROL0_SIGN {
2441	AFMT_RAMP_SIGNED                                 = 0x0,
2442	AFMT_RAMP_UNSIGNED                               = 0x1,
2443} AFMT_RAMP_CONTROL0_SIGN;
2444typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
2445	AFMT_AUDIO_PACKET_SENT_DISABLED                  = 0x0,
2446	AFMT_AUDIO_PACKET_SENT_ENABLED                   = 0x1,
2447} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
2448typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
2449	AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED= 0x0,
2450	AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED        = 0x1,
2451} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
2452typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
2453	AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK          = 0x0,
2454	AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS        = 0x1,
2455} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
2456typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
2457	AFMT_AUDIO_SRC_FROM_AZ_STREAM0                   = 0x0,
2458	AFMT_AUDIO_SRC_FROM_AZ_STREAM1                   = 0x1,
2459	AFMT_AUDIO_SRC_FROM_AZ_STREAM2                   = 0x2,
2460	AFMT_AUDIO_SRC_FROM_AZ_STREAM3                   = 0x3,
2461	AFMT_AUDIO_SRC_FROM_AZ_STREAM4                   = 0x4,
2462	AFMT_AUDIO_SRC_FROM_AZ_STREAM5                   = 0x5,
2463	AFMT_AUDIO_SRC_RESERVED                          = 0x6,
2464} AFMT_AUDIO_SRC_CONTROL_SELECT;
2465typedef enum DIG_BE_CNTL_MODE {
2466	DIG_BE_DP_SST_MODE                               = 0x0,
2467	DIG_BE_RESERVED1                                 = 0x1,
2468	DIG_BE_TMDS_DVI_MODE                             = 0x2,
2469	DIG_BE_TMDS_HDMI_MODE                            = 0x3,
2470	DIG_BE_SDVO_RESERVED                             = 0x4,
2471	DIG_BE_DP_MST_MODE                               = 0x5,
2472	DIG_BE_RESERVED2                                 = 0x6,
2473	DIG_BE_RESERVED3                                 = 0x7,
2474} DIG_BE_CNTL_MODE;
2475typedef enum DIG_BE_CNTL_HPD_SELECT {
2476	DIG_BE_CNTL_HPD1                                 = 0x0,
2477	DIG_BE_CNTL_HPD2                                 = 0x1,
2478	DIG_BE_CNTL_HPD3                                 = 0x2,
2479	DIG_BE_CNTL_HPD4                                 = 0x3,
2480	DIG_BE_CNTL_HPD5                                 = 0x4,
2481	DIG_BE_CNTL_HPD6                                 = 0x5,
2482} DIG_BE_CNTL_HPD_SELECT;
2483typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
2484	LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS             = 0x0,
2485	LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH           = 0x1,
2486} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
2487typedef enum TMDS_SYNC_PHASE {
2488	TMDS_NOT_SYNC_PHASE_ON_FRAME_START               = 0x0,
2489	TMDS_SYNC_PHASE_ON_FRAME_START                   = 0x1,
2490} TMDS_SYNC_PHASE;
2491typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
2492	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS     = 0x0,
2493	TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL      = 0x1,
2494} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
2495typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
2496	TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE           = 0x0,
2497	TMDS_TRANSMITTER_HPD_MASK_OVERRIDE               = 0x1,
2498} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
2499typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
2500	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
2501	TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE        = 0x1,
2502} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
2503typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
2504	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE    = 0x0,
2505	TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE        = 0x1,
2506} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
2507typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
2508	TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE     = 0x0,
2509	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON= 0x1,
2510	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON  = 0x2,
2511	TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE         = 0x3,
2512} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
2513typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
2514	TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK           = 0x0,
2515	TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK             = 0x1,
2516} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
2517typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
2518	TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK           = 0x0,
2519	TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK             = 0x1,
2520} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
2521typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
2522	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE           = 0x0,
2523	TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE            = 0x1,
2524} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
2525typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
2526	TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD              = 0x0,
2527	TMDS_TRANSMITTER_PLL_RST_ON_HPD                  = 0x1,
2528} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
2529typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
2530	TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK           = 0x0,
2531	TMDS_TRANSMITTER_TMCLK_FROM_PADS                 = 0x1,
2532} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
2533typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
2534	TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK           = 0x0,
2535	TMDS_TRANSMITTER_TDCLK_FROM_PADS                 = 0x1,
2536} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
2537typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
2538	TMDS_TRANSMITTER_PLLSEL_BY_HW                    = 0x0,
2539	TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW          = 0x1,
2540} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
2541typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
2542	TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT            = 0x0,
2543	TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT          = 0x1,
2544} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
2545typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
2546	TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT            = 0x0,
2547	TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT          = 0x1,
2548} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
2549typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
2550	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0              = 0x0,
2551	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1              = 0x1,
2552	TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2              = 0x2,
2553	TMDS_REG_TEST_OUTPUTA_CNTLA_NA                   = 0x3,
2554} TMDS_REG_TEST_OUTPUTA_CNTLA;
2555typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
2556	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0              = 0x0,
2557	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1              = 0x1,
2558	TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2              = 0x2,
2559	TMDS_REG_TEST_OUTPUTB_CNTLB_NA                   = 0x3,
2560} TMDS_REG_TEST_OUTPUTB_CNTLB;
2561typedef enum DP_LINK_TRAINING_COMPLETE {
2562	DP_LINK_TRAINING_NOT_COMPLETE                    = 0x0,
2563	DP_LINK_TRAINING_ALREADY_COMPLETE                = 0x1,
2564} DP_LINK_TRAINING_COMPLETE;
2565typedef enum DP_EMBEDDED_PANEL_MODE {
2566	DP_EXTERNAL_PANEL                                = 0x0,
2567	DP_EMBEDDED_PANEL                                = 0x1,
2568} DP_EMBEDDED_PANEL_MODE;
2569typedef enum DP_PIXEL_ENCODING {
2570	DP_PIXEL_ENCODING_RGB444                         = 0x0,
2571	DP_PIXEL_ENCODING_YCBCR422                       = 0x1,
2572	DP_PIXEL_ENCODING_YCBCR444                       = 0x2,
2573	DP_PIXEL_ENCODING_RGB_WIDE_GAMUT                 = 0x3,
2574	DP_PIXEL_ENCODING_Y_ONLY                         = 0x4,
2575	DP_PIXEL_ENCODING_RESERVED                       = 0x5,
2576} DP_PIXEL_ENCODING;
2577typedef enum DP_DYN_RANGE {
2578	DP_DYN_VESA_RANGE                                = 0x0,
2579	DP_DYN_CEA_RANGE                                 = 0x1,
2580} DP_DYN_RANGE;
2581typedef enum DP_YCBCR_RANGE {
2582	DP_YCBCR_RANGE_BT601_5                           = 0x0,
2583	DP_YCBCR_RANGE_BT709_5                           = 0x1,
2584} DP_YCBCR_RANGE;
2585typedef enum DP_COMPONENT_DEPTH {
2586	DP_COMPONENT_DEPTH_6BPC                          = 0x0,
2587	DP_COMPONENT_DEPTH_8BPC                          = 0x1,
2588	DP_COMPONENT_DEPTH_10BPC                         = 0x2,
2589	DP_COMPONENT_DEPTH_12BPC                         = 0x3,
2590	DP_COMPONENT_DEPTH_16BPC                         = 0x4,
2591	DP_COMPONENT_DEPTH_RESERVED                      = 0x5,
2592} DP_COMPONENT_DEPTH;
2593typedef enum DP_MSA_MISC0_OVERRIDE_ENABLE {
2594	MSA_MISC0_OVERRIDE_DISABLE                       = 0x0,
2595	MSA_MISC0_OVERRIDE_ENABLE                        = 0x1,
2596} DP_MSA_MISC0_OVERRIDE_ENABLE;
2597typedef enum DP_UDI_LANES {
2598	DP_UDI_1_LANE                                    = 0x0,
2599	DP_UDI_2_LANES                                   = 0x1,
2600	DP_UDI_LANES_RESERVED                            = 0x2,
2601	DP_UDI_4_LANES                                   = 0x3,
2602} DP_UDI_LANES;
2603typedef enum DP_VID_STREAM_DIS_DEFER {
2604	DP_VID_STREAM_DIS_NO_DEFER                       = 0x0,
2605	DP_VID_STREAM_DIS_DEFER_TO_HBLANK                = 0x1,
2606	DP_VID_STREAM_DIS_DEFER_TO_VBLANK                = 0x2,
2607} DP_VID_STREAM_DIS_DEFER;
2608typedef enum DP_STEER_OVERFLOW_ACK {
2609	DP_STEER_OVERFLOW_ACK_NO_EFFECT                  = 0x0,
2610	DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT              = 0x1,
2611} DP_STEER_OVERFLOW_ACK;
2612typedef enum DP_STEER_OVERFLOW_MASK {
2613	DP_STEER_OVERFLOW_MASKED                         = 0x0,
2614	DP_STEER_OVERFLOW_UNMASK                         = 0x1,
2615} DP_STEER_OVERFLOW_MASK;
2616typedef enum DP_TU_OVERFLOW_ACK {
2617	DP_TU_OVERFLOW_ACK_NO_EFFECT                     = 0x0,
2618	DP_TU_OVERFLOW_ACK_CLR_INTERRUPT                 = 0x1,
2619} DP_TU_OVERFLOW_ACK;
2620typedef enum DP_VID_TIMING_MODE {
2621	DP_VID_TIMING_MODE_ASYNC                         = 0x0,
2622	DP_VID_TIMING_MODE_SYNC                          = 0x1,
2623} DP_VID_TIMING_MODE;
2624typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
2625	DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE      = 0x0,
2626	DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START          = 0x1,
2627} DP_VID_M_N_DOUBLE_BUFFER_MODE;
2628typedef enum DP_VID_M_N_GEN_EN {
2629	DP_VID_M_N_PROGRAMMED_VIA_REG                    = 0x0,
2630	DP_VID_M_N_CALC_AUTO                             = 0x1,
2631} DP_VID_M_N_GEN_EN;
2632typedef enum DP_VID_ENHANCED_FRAME_MODE {
2633	VID_NORMAL_FRAME_MODE                            = 0x0,
2634	VID_ENHANCED_MODE                                = 0x1,
2635} DP_VID_ENHANCED_FRAME_MODE;
2636typedef enum DP_VID_MSA_TOP_FIELD_MODE {
2637	DP_TOP_FIELD_ONLY                                = 0x0,
2638	DP_TOP_PLUS_BOTTOM_FIELD                         = 0x1,
2639} DP_VID_MSA_TOP_FIELD_MODE;
2640typedef enum DP_VID_VBID_FIELD_POL {
2641	DP_VID_VBID_FIELD_POL_NORMAL                     = 0x0,
2642	DP_VID_VBID_FIELD_POL_INV                        = 0x1,
2643} DP_VID_VBID_FIELD_POL;
2644typedef enum DP_VID_STREAM_DISABLE_ACK {
2645	ID_STREAM_DISABLE_NO_ACK                         = 0x0,
2646	ID_STREAM_DISABLE_ACKED                          = 0x1,
2647} DP_VID_STREAM_DISABLE_ACK;
2648typedef enum DP_VID_STREAM_DISABLE_MASK {
2649	VID_STREAM_DISABLE_MASKED                        = 0x0,
2650	VID_STREAM_DISABLE_UNMASK                        = 0x1,
2651} DP_VID_STREAM_DISABLE_MASK;
2652typedef enum DPHY_ATEST_SEL_LANE0 {
2653	DPHY_ATEST_LANE0_PRBS_PATTERN                    = 0x0,
2654	DPHY_ATEST_LANE0_REG_PATTERN                     = 0x1,
2655} DPHY_ATEST_SEL_LANE0;
2656typedef enum DPHY_ATEST_SEL_LANE1 {
2657	DPHY_ATEST_LANE1_PRBS_PATTERN                    = 0x0,
2658	DPHY_ATEST_LANE1_REG_PATTERN                     = 0x1,
2659} DPHY_ATEST_SEL_LANE1;
2660typedef enum DPHY_ATEST_SEL_LANE2 {
2661	DPHY_ATEST_LANE2_PRBS_PATTERN                    = 0x0,
2662	DPHY_ATEST_LANE2_REG_PATTERN                     = 0x1,
2663} DPHY_ATEST_SEL_LANE2;
2664typedef enum DPHY_ATEST_SEL_LANE3 {
2665	DPHY_ATEST_LANE3_PRBS_PATTERN                    = 0x0,
2666	DPHY_ATEST_LANE3_REG_PATTERN                     = 0x1,
2667} DPHY_ATEST_SEL_LANE3;
2668typedef enum DPHY_BYPASS {
2669	DPHY_8B10B_OUTPUT                                = 0x0,
2670	DPHY_DBG_OUTPUT                                  = 0x1,
2671} DPHY_BYPASS;
2672typedef enum DPHY_SKEW_BYPASS {
2673	DPHY_WITH_SKEW                                   = 0x0,
2674	DPHY_NO_SKEW                                     = 0x1,
2675} DPHY_SKEW_BYPASS;
2676typedef enum DPHY_TRAINING_PATTERN_SEL {
2677	DPHY_TRAINING_PATTERN_1                          = 0x0,
2678	DPHY_TRAINING_PATTERN_2                          = 0x1,
2679	DPHY_TRAINING_PATTERN_3                          = 0x2,
2680} DPHY_TRAINING_PATTERN_SEL;
2681typedef enum DPHY_8B10B_RESET {
2682	DPHY_8B10B_NOT_RESET                             = 0x0,
2683	DPHY_8B10B_RESETET                               = 0x1,
2684} DPHY_8B10B_RESET;
2685typedef enum DP_DPHY_8B10B_EXT_DISP {
2686	DP_DPHY_8B10B_EXT_DISP_ZERO                      = 0x0,
2687	DP_DPHY_8B10B_EXT_DISP_ONE                       = 0x1,
2688} DP_DPHY_8B10B_EXT_DISP;
2689typedef enum DPHY_8B10B_CUR_DISP {
2690	DPHY_8B10B_CUR_DISP_ZERO                         = 0x0,
2691	DPHY_8B10B_CUR_DISP_ONE                          = 0x1,
2692} DPHY_8B10B_CUR_DISP;
2693typedef enum DPHY_PRBS_EN {
2694	DPHY_PRBS_DISABLE                                = 0x0,
2695	DPHY_PRBS_ENABLE                                 = 0x1,
2696} DPHY_PRBS_EN;
2697typedef enum DPHY_PRBS_SEL {
2698	DPHY_PRBS7_SELECTED                              = 0x0,
2699	DPHY_PRBS23_SELECTED                             = 0x1,
2700	DPHY_PRBS11_SELECTED                             = 0x2,
2701} DPHY_PRBS_SEL;
2702typedef enum DPHY_LOAD_BS_COUNT_START {
2703	DPHY_LOAD_BS_COUNT_STARTED                       = 0x0,
2704	DPHY_LOAD_BS_COUNT_NOT_STARTED                   = 0x1,
2705} DPHY_LOAD_BS_COUNT_START;
2706typedef enum DPHY_CRC_EN {
2707	DPHY_CRC_DISABLED                                = 0x0,
2708	DPHY_CRC_ENABLED                                 = 0x1,
2709} DPHY_CRC_EN;
2710typedef enum DPHY_CRC_CONT_EN {
2711	DPHY_CRC_ONE_SHOT                                = 0x0,
2712	DPHY_CRC_CONTINUOUS                              = 0x1,
2713} DPHY_CRC_CONT_EN;
2714typedef enum DPHY_CRC_FIELD {
2715	DPHY_CRC_START_FROM_TOP_FIELD                    = 0x0,
2716	DPHY_CRC_START_FROM_BOTTOM_FIELD                 = 0x1,
2717} DPHY_CRC_FIELD;
2718typedef enum DPHY_CRC_SEL {
2719	DPHY_CRC_LANE0_SELECTED                          = 0x0,
2720	DPHY_CRC_LANE1_SELECTED                          = 0x1,
2721	DPHY_CRC_LANE2_SELECTED                          = 0x2,
2722	DPHY_CRC_LANE3_SELECTED                          = 0x3,
2723} DPHY_CRC_SEL;
2724typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
2725	DPHY_FAST_TRAINING_NOT_CAPABLE_0                 = 0x0,
2726	DPHY_FAST_TRAINING_CAPABLE                       = 0x1,
2727} DPHY_RX_FAST_TRAINING_CAPABLE;
2728typedef enum DP_SEC_COLLISION_ACK {
2729	DP_SEC_COLLISION_ACK_NO_EFFECT                   = 0x0,
2730	DP_SEC_COLLISION_ACK_CLR_FLAG                    = 0x1,
2731} DP_SEC_COLLISION_ACK;
2732typedef enum DP_SEC_AUDIO_MUTE {
2733	DP_SEC_AUDIO_MUTE_HW_CTRL                        = 0x0,
2734	DP_SEC_AUDIO_MUTE_SW_CTRL                        = 0x1,
2735} DP_SEC_AUDIO_MUTE;
2736typedef enum DP_SEC_TIMESTAMP_MODE {
2737	DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE               = 0x0,
2738	DP_SEC_TIMESTAMP_AUTO_CALC_MODE                  = 0x1,
2739} DP_SEC_TIMESTAMP_MODE;
2740typedef enum DP_SEC_ASP_PRIORITY {
2741	DP_SEC_ASP_LOW_PRIORITY                          = 0x0,
2742	DP_SEC_ASP_HIGH_PRIORITY                         = 0x1,
2743} DP_SEC_ASP_PRIORITY;
2744typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
2745	DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ                 = 0x0,
2746	DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED        = 0x1,
2747} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
2748typedef enum DP_MSE_SAT_UPDATE_ACT {
2749	DP_MSE_SAT_UPDATE_NO_ACTION                      = 0x0,
2750	DP_MSE_SAT_UPDATE_WITH_TRIGGER                   = 0x1,
2751	DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER                = 0x2,
2752} DP_MSE_SAT_UPDATE_ACT;
2753typedef enum DP_MSE_LINK_LINE {
2754	DP_MSE_LINK_LINE_32_MTP_LONG                     = 0x0,
2755	DP_MSE_LINK_LINE_64_MTP_LONG                     = 0x1,
2756	DP_MSE_LINK_LINE_128_MTP_LONG                    = 0x2,
2757	DP_MSE_LINK_LINE_256_MTP_LONG                    = 0x3,
2758} DP_MSE_LINK_LINE;
2759typedef enum DP_MSE_BLANK_CODE {
2760	DP_MSE_BLANK_CODE_SF_FILLED                      = 0x0,
2761	DP_MSE_BLANK_CODE_ZERO_FILLED                    = 0x1,
2762} DP_MSE_BLANK_CODE;
2763typedef enum DP_MSE_TIMESTAMP_MODE {
2764	DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE         = 0x0,
2765	DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE           = 0x1,
2766} DP_MSE_TIMESTAMP_MODE;
2767typedef enum DP_MSE_ZERO_ENCODER {
2768	DP_MSE_NOT_ZERO_FE_ENCODER                       = 0x0,
2769	DP_MSE_ZERO_FE_ENCODER                           = 0x1,
2770} DP_MSE_ZERO_ENCODER;
2771typedef enum DP_MSE_OUTPUT_DPDBG_DATA {
2772	DP_MSE_OUTPUT_DPDBG_DATA_DIS                     = 0x0,
2773	DP_MSE_OUTPUT_DPDBG_DATA_EN                      = 0x1,
2774} DP_MSE_OUTPUT_DPDBG_DATA;
2775typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
2776	DP_DPHY_HBR2_PASS_THROUGH                        = 0x0,
2777	DP_DPHY_HBR2_PATTERN_1                           = 0x1,
2778	DP_DPHY_HBR2_PATTERN_2_NEG                       = 0x2,
2779	DP_DPHY_HBR2_PATTERN_3                           = 0x3,
2780	DP_DPHY_HBR2_PATTERN_2_POS                       = 0x6,
2781} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
2782typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
2783	DPHY_CRC_MST_PHASE_ERROR_NO_ACK                  = 0x0,
2784	DPHY_CRC_MST_PHASE_ERROR_ACKED                   = 0x1,
2785} DPHY_CRC_MST_PHASE_ERROR_ACK;
2786typedef enum DPHY_SW_FAST_TRAINING_START {
2787	DPHY_SW_FAST_TRAINING_NOT_STARTED                = 0x0,
2788	DPHY_SW_FAST_TRAINING_STARTED                    = 0x1,
2789} DPHY_SW_FAST_TRAINING_START;
2790typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
2791	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED= 0x0,
2792	DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x1,
2793} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
2794typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
2795	DP_DPHY_FAST_TRAINING_COMPLETE_MASKED            = 0x0,
2796	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED        = 0x1,
2797} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
2798typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
2799	DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED         = 0x0,
2800	DP_DPHY_FAST_TRAINING_COMPLETE_ACKED             = 0x1,
2801} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
2802typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
2803	MSA_V_TIMING_OVERRIDE_DISABLED                   = 0x0,
2804	MSA_V_TIMING_OVERRIDE_ENABLED                    = 0x1,
2805} DP_MSA_V_TIMING_OVERRIDE_EN;
2806typedef enum DP_SEC_GSP0_PRIORITY {
2807	SEC_GSP0_PRIORITY_LOW                            = 0x0,
2808	SEC_GSP0_PRIORITY_HIGH                           = 0x1,
2809} DP_SEC_GSP0_PRIORITY;
2810typedef enum DP_SEC_GSP0_SEND {
2811	NOT_SENT                                         = 0x0,
2812	FORCE_SENT                                       = 0x1,
2813} DP_SEC_GSP0_SEND;
2814typedef enum DP_AUX_CONTROL_HPD_SEL {
2815	DP_AUX_CONTROL_HPD1_SELECTED                     = 0x0,
2816	DP_AUX_CONTROL_HPD2_SELECTED                     = 0x1,
2817	DP_AUX_CONTROL_HPD3_SELECTED                     = 0x2,
2818	DP_AUX_CONTROL_HPD4_SELECTED                     = 0x3,
2819	DP_AUX_CONTROL_HPD5_SELECTED                     = 0x4,
2820	DP_AUX_CONTROL_HPD6_SELECTED                     = 0x5,
2821} DP_AUX_CONTROL_HPD_SEL;
2822typedef enum DP_AUX_CONTROL_TEST_MODE {
2823	DP_AUX_CONTROL_TEST_MODE_DISABLE                 = 0x0,
2824	DP_AUX_CONTROL_TEST_MODE_ENABLE                  = 0x1,
2825} DP_AUX_CONTROL_TEST_MODE;
2826typedef enum DP_AUX_SW_CONTROL_SW_GO {
2827	DP_AUX_SW_CONTROL_SW__NOT_GO                     = 0x0,
2828	DP_AUX_SW_CONTROL_SW__GO                         = 0x1,
2829} DP_AUX_SW_CONTROL_SW_GO;
2830typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
2831	DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG              = 0x0,
2832	DP_AUX_SW_CONTROL_LS_READ__TRIG                  = 0x1,
2833} DP_AUX_SW_CONTROL_LS_READ_TRIG;
2834typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
2835	DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW       = 0x0,
2836	DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW       = 0x1,
2837	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC       = 0x2,
2838	DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS       = 0x3,
2839} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
2840typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
2841	DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ          = 0x0,
2842	DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ              = 0x1,
2843} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
2844typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
2845	DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG       = 0x0,
2846	DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG           = 0x1,
2847} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
2848typedef enum DP_AUX_INT_ACK {
2849	DP_AUX_INT__NOT_ACK                              = 0x0,
2850	DP_AUX_INT__ACK                                  = 0x1,
2851} DP_AUX_INT_ACK;
2852typedef enum DP_AUX_LS_UPDATE_ACK {
2853	DP_AUX_INT_LS_UPDATE_NOT_ACK                     = 0x0,
2854	DP_AUX_INT_LS_UPDATE_ACK                         = 0x1,
2855} DP_AUX_LS_UPDATE_ACK;
2856typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
2857	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK= 0x0,
2858	DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF= 0x1,
2859} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
2860typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
2861	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ         = 0x0,
2862	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ         = 0x1,
2863	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ         = 0x2,
2864	DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ         = 0x3,
2865} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
2866typedef enum DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN {
2867	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__0US        = 0x0,
2868	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__8US        = 0x1,
2869	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__16US       = 0x2,
2870	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__24US       = 0x3,
2871	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__32US       = 0x4,
2872	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__40US       = 0x5,
2873	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__48US       = 0x6,
2874	DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN__56US       = 0x7,
2875} DP_AUX_DPHY_TX_CONTROL_PRECHARGE_LEN;
2876typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
2877	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0   = 0x0,
2878	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US= 0x1,
2879	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US= 0x2,
2880	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US= 0x3,
2881	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US= 0x4,
2882	DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US= 0x5,
2883} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
2884typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
2885	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x0,
2886	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x1,
2887	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x2,
2888	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD= 0x3,
2889	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD= 0x4,
2890	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD= 0x5,
2891	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD= 0x6,
2892	DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD= 0x7,
2893} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
2894typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
2895	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD= 0x0,
2896	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD= 0x1,
2897	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD= 0x2,
2898	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD= 0x3,
2899	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD= 0x4,
2900	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD= 0x5,
2901	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD= 0x6,
2902	DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD= 0x7,
2903} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
2904typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
2905	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES= 0x0,
2906	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES= 0x1,
2907	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES= 0x2,
2908	DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED= 0x3,
2909} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
2910typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
2911	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x0,
2912	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT= 0x1,
2913} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
2914typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
2915	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START= 0x0,
2916	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START= 0x1,
2917} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
2918typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
2919	DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP= 0x0,
2920	DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP= 0x1,
2921} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
2922typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
2923	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS= 0x0,
2924	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS= 0x1,
2925	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS= 0x2,
2926	DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS= 0x3,
2927} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
2928typedef enum DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN {
2929	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_450US         = 0x0,
2930	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_500US         = 0x1,
2931	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_550US         = 0x2,
2932	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_600US         = 0x3,
2933	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_650US         = 0x4,
2934	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_700US         = 0x5,
2935	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_750US         = 0x6,
2936	DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN_800US         = 0x7,
2937} DP_AUX_DPHY_RX_CONTROL_TIMEOUT_LEN;
2938typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
2939	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2         = 0x0,
2940	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4         = 0x1,
2941	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8         = 0x2,
2942	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16       = 0x3,
2943	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32       = 0x4,
2944	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64       = 0x5,
2945	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128     = 0x6,
2946	DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256     = 0x7,
2947} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
2948typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
2949	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX= 0x0,
2950	DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX= 0x1,
2951} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
2952typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
2953	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US= 0x0,
2954	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US= 0x1,
2955	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US= 0x2,
2956	DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US= 0x3,
2957} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
2958typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
2959	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS= 0x0,
2960	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS= 0x1,
2961	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS= 0x2,
2962	DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED= 0x3,
2963} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
2964typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
2965	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0= 0x0,
2966	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64= 0x1,
2967	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128= 0x2,
2968	DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256= 0x3,
2969} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
2970typedef enum DP_AUX_ERR_OCCURRED_ACK {
2971	DP_AUX_ERR_OCCURRED__NOT_ACK                     = 0x0,
2972	DP_AUX_ERR_OCCURRED__ACK                         = 0x1,
2973} DP_AUX_ERR_OCCURRED_ACK;
2974typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
2975	DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK            = 0x0,
2976	DP_AUX_POTENTIAL_ERR_REACHED__ACK                = 0x1,
2977} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
2978typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
2979	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK        = 0x0,
2980	ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK            = 0x1,
2981} DP_AUX_DEFINITE_ERR_REACHED_ACK;
2982typedef enum DP_AUX_RESET {
2983	DP_AUX_RESET_DEASSERTED                          = 0x0,
2984	DP_AUX_RESET_ASSERTED                            = 0x1,
2985} DP_AUX_RESET;
2986typedef enum DP_AUX_RESET_DONE {
2987	DP_AUX_RESET_SEQUENCE_NOT_DONE                   = 0x0,
2988	DP_AUX_RESET_SEQUENCE_DONE                       = 0x1,
2989} DP_AUX_RESET_DONE;
2990typedef enum FMT_CONTROL_PIXEL_ENCODING {
2991	FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444    = 0x0,
2992	FMT_CONTROL_PIXEL_ENCODING_YCBCR422              = 0x1,
2993} FMT_CONTROL_PIXEL_ENCODING;
2994typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
2995	FMT_CONTROL_SUBSAMPLING_MODE_DROP                = 0x0,
2996	FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE             = 0x1,
2997} FMT_CONTROL_SUBSAMPLING_MODE;
2998typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
2999	FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR       = 0x0,
3000	FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB       = 0x1,
3001} FMT_CONTROL_SUBSAMPLING_ORDER;
3002typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3003	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION   = 0x0,
3004	FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING     = 0x1,
3005} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3006typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3007	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP       = 0x0,
3008	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP       = 0x1,
3009	FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP       = 0x2,
3010} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3011typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3012	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x0,
3013	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x1,
3014	FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x2,
3015} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3016typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3017	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP= 0x0,
3018	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP= 0x1,
3019	FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP= 0x2,
3020} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3021typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3022	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x0,
3023	FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x1,
3024} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3025typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3026	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei               = 0x0,
3027	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi               = 0x1,
3028	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi               = 0x2,
3029	FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED         = 0x3,
3030} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3031typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3032	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A                = 0x0,
3033	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B                = 0x1,
3034	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C                = 0x2,
3035	FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D                = 0x3,
3036} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3037typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3038	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E                = 0x0,
3039	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F                = 0x1,
3040	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G                = 0x2,
3041	FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED         = 0x3,
3042} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3043typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT {
3044	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_LEGACY_HARDCODED_PATTERN= 0x0,
3045	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT_PROGRAMMABLE_PATTERN= 0x1,
3046} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_SELECT;
3047typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3048	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR= 0x0,
3049	FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB= 0x1,
3050} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3051typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3052	FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC                 = 0x0,
3053	FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC                 = 0x1,
3054	FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC                = 0x2,
3055	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED0            = 0x3,
3056	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1            = 0x4,
3057	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2            = 0x5,
3058	FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3            = 0x6,
3059	FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE         = 0x7,
3060} FMT_CLAMP_CNTL_COLOR_FORMAT;
3061typedef enum FMT_CRC_CNTL_CONT_EN {
3062	FMT_CRC_CNTL_CONT_EN_ONE_SHOT                    = 0x0,
3063	FMT_CRC_CNTL_CONT_EN_CONT                        = 0x1,
3064} FMT_CRC_CNTL_CONT_EN;
3065typedef enum FMT_CRC_CNTL_INCLUDE_OVERSCAN {
3066	FMT_CRC_CNTL_INCLUDE_OVERSCAN_NOT_INCLUDE        = 0x0,
3067	FMT_CRC_CNTL_INCLUDE_OVERSCAN_INCLUDE            = 0x1,
3068} FMT_CRC_CNTL_INCLUDE_OVERSCAN;
3069typedef enum FMT_CRC_CNTL_ONLY_BLANKB {
3070	FMT_CRC_CNTL_ONLY_BLANKB_ENTIRE_FIELD            = 0x0,
3071	FMT_CRC_CNTL_ONLY_BLANKB_NON_BLANK               = 0x1,
3072} FMT_CRC_CNTL_ONLY_BLANKB;
3073typedef enum FMT_CRC_CNTL_PSR_MODE_ENABLE {
3074	FMT_CRC_CNTL_PSR_MODE_ENABLE_NORMAL              = 0x0,
3075	FMT_CRC_CNTL_PSR_MODE_ENABLE_EDP_PSR_CRC         = 0x1,
3076} FMT_CRC_CNTL_PSR_MODE_ENABLE;
3077typedef enum FMT_CRC_CNTL_INTERLACE_MODE {
3078	FMT_CRC_CNTL_INTERLACE_MODE_TOP                  = 0x0,
3079	FMT_CRC_CNTL_INTERLACE_MODE_BOTTOM               = 0x1,
3080	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_BOTTOM          = 0x2,
3081	FMT_CRC_CNTL_INTERLACE_MODE_BOTH_EACH            = 0x3,
3082} FMT_CRC_CNTL_INTERLACE_MODE;
3083typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE {
3084	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ALL             = 0x0,
3085	FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE_ODD_EVEN        = 0x1,
3086} FMT_CRC_CNTL_EVEN_ODD_PIX_ENABLE;
3087typedef enum FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT {
3088	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_EVEN            = 0x0,
3089	FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT_ODD             = 0x1,
3090} FMT_CRC_CNTL_EVEN_ODD_PIX_SELECT;
3091typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3092	FMT_DEBUG_CNTL_COLOR_SELECT_BLUE                 = 0x0,
3093	FMT_DEBUG_CNTL_COLOR_SELECT_GREEN                = 0x1,
3094	FMT_DEBUG_CNTL_COLOR_SELECT_RED1                 = 0x2,
3095	FMT_DEBUG_CNTL_COLOR_SELECT_RED2                 = 0x3,
3096} FMT_DEBUG_CNTL_COLOR_SELECT;
3097typedef enum FMT_SPATIAL_DITHER_MODE {
3098	FMT_SPATIAL_DITHER_MODE_0                        = 0x0,
3099	FMT_SPATIAL_DITHER_MODE_1                        = 0x1,
3100	FMT_SPATIAL_DITHER_MODE_2                        = 0x2,
3101	FMT_SPATIAL_DITHER_MODE_3                        = 0x3,
3102} FMT_SPATIAL_DITHER_MODE;
3103typedef enum FMT_STEREOSYNC_OVR_POL {
3104	FMT_STEREOSYNC_OVR_POL_INVERTED                  = 0x0,
3105	FMT_STEREOSYNC_OVR_POL_NOT_INVERTED              = 0x1,
3106} FMT_STEREOSYNC_OVR_POL;
3107typedef enum FMT_DYNAMIC_EXP_MODE {
3108	FMT_DYNAMIC_EXP_MODE_10to12                      = 0x0,
3109	FMT_DYNAMIC_EXP_MODE_8to12                       = 0x1,
3110} FMT_DYNAMIC_EXP_MODE;
3111typedef enum LB_DATA_FORMAT_PIXEL_DEPTH {
3112	LB_DATA_FORMAT_PIXEL_DEPTH_30BPP                 = 0x0,
3113	LB_DATA_FORMAT_PIXEL_DEPTH_24BPP                 = 0x1,
3114	LB_DATA_FORMAT_PIXEL_DEPTH_18BPP                 = 0x2,
3115	LB_DATA_FORMAT_PIXEL_DEPTH_36BPP                 = 0x3,
3116} LB_DATA_FORMAT_PIXEL_DEPTH;
3117typedef enum LB_DATA_FORMAT_PIXEL_EXPAN_MODE {
3118	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_ZERO_PIXEL_EXPANSION= 0x0,
3119	LB_DATA_FORMAT_PIXEL_EXPAN_MODE_DYNAMIC_PIXEL_EXPANSION= 0x1,
3120} LB_DATA_FORMAT_PIXEL_EXPAN_MODE;
3121typedef enum LB_DATA_FORMAT_PIXEL_REDUCE_MODE {
3122	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_TRUNCATION      = 0x0,
3123	LB_DATA_FORMAT_PIXEL_REDUCE_MODE_ROUNDING        = 0x1,
3124} LB_DATA_FORMAT_PIXEL_REDUCE_MODE;
3125typedef enum LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH {
3126	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_36BPP         = 0x0,
3127	LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH_30BPP         = 0x1,
3128} LB_DATA_FORMAT_DYNAMIC_PIXEL_DEPTH;
3129typedef enum LB_DATA_FORMAT_INTERLEAVE_EN {
3130	LB_DATA_FORMAT_INTERLEAVE_DISABLE                = 0x0,
3131	LB_DATA_FORMAT_INTERLEAVE_ENABLE                 = 0x1,
3132} LB_DATA_FORMAT_INTERLEAVE_EN;
3133typedef enum LB_DATA_FORMAT_REQUEST_MODE {
3134	LB_DATA_FORMAT_REQUEST_MODE_NORMAL               = 0x0,
3135	LB_DATA_FORMAT_REQUEST_MODE_START_OF_LINE        = 0x1,
3136} LB_DATA_FORMAT_REQUEST_MODE;
3137typedef enum LB_DATA_FORMAT_ALPHA_EN {
3138	LB_DATA_FORMAT_ALPHA_DISABLE                     = 0x0,
3139	LB_DATA_FORMAT_ALPHA_ENABLE                      = 0x1,
3140} LB_DATA_FORMAT_ALPHA_EN;
3141typedef enum LB_VLINE_START_END_VLINE_INV {
3142	LB_VLINE_START_END_VLINE_NORMAL                  = 0x0,
3143	LB_VLINE_START_END_VLINE_INVERSE                 = 0x1,
3144} LB_VLINE_START_END_VLINE_INV;
3145typedef enum LB_VLINE2_START_END_VLINE2_INV {
3146	LB_VLINE2_START_END_VLINE2_NORMAL                = 0x0,
3147	LB_VLINE2_START_END_VLINE2_INVERSE               = 0x1,
3148} LB_VLINE2_START_END_VLINE2_INV;
3149typedef enum LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK {
3150	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_DISABLE       = 0x0,
3151	LB_INTERRUPT_MASK_VBLANK_INTERRUPT_ENABLE        = 0x1,
3152} LB_INTERRUPT_MASK_VBLANK_INTERRUPT_MASK;
3153typedef enum LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK {
3154	LB_INTERRUPT_MASK_VLINE_INTERRUPT_DISABLE        = 0x0,
3155	LB_INTERRUPT_MASK_VLINE_INTERRUPT_ENABLE         = 0x1,
3156} LB_INTERRUPT_MASK_VLINE_INTERRUPT_MASK;
3157typedef enum LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK {
3158	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_DISABLE       = 0x0,
3159	LB_INTERRUPT_MASK_VLINE2_INTERRUPT_ENABLE        = 0x1,
3160} LB_INTERRUPT_MASK_VLINE2_INTERRUPT_MASK;
3161typedef enum LB_VLINE_STATUS_VLINE_ACK {
3162	LB_VLINE_STATUS_VLINE_NORMAL                     = 0x0,
3163	LB_VLINE_STATUS_VLINE_CLEAR                      = 0x1,
3164} LB_VLINE_STATUS_VLINE_ACK;
3165typedef enum LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE {
3166	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_LEVEL_BASED = 0x0,
3167	LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE_PULSE_BASED = 0x1,
3168} LB_VLINE_STATUS_VLINE_INTERRUPT_TYPE;
3169typedef enum LB_VLINE2_STATUS_VLINE2_ACK {
3170	LB_VLINE2_STATUS_VLINE2_NORMAL                   = 0x0,
3171	LB_VLINE2_STATUS_VLINE2_CLEAR                    = 0x1,
3172} LB_VLINE2_STATUS_VLINE2_ACK;
3173typedef enum LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE {
3174	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3175	LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3176} LB_VLINE2_STATUS_VLINE2_INTERRUPT_TYPE;
3177typedef enum LB_VBLANK_STATUS_VBLANK_ACK {
3178	LB_VBLANK_STATUS_VBLANK_NORMAL                   = 0x0,
3179	LB_VBLANK_STATUS_VBLANK_CLEAR                    = 0x1,
3180} LB_VBLANK_STATUS_VBLANK_ACK;
3181typedef enum LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE {
3182	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_LEVEL_BASED= 0x0,
3183	LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE_PULSE_BASED= 0x1,
3184} LB_VBLANK_STATUS_VBLANK_INTERRUPT_TYPE;
3185typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL {
3186	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_DISABLE      = 0x0,
3187	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK= 0x1,
3188	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_POWERDOWN_RESET= 0x2,
3189	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL_FROM_VSYNC_VBLANK_POWERDOWN_RESET= 0x3,
3190} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL;
3191typedef enum LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2 {
3192	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VBLANK  = 0x0,
3193	LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2_USE_VSYNC   = 0x1,
3194} LB_SYNC_RESET_SEL_LB_SYNC_RESET_SEL2;
3195typedef enum LB_SYNC_RESET_SEL_LB_SYNC_DURATION {
3196	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_16_CLOCKS     = 0x0,
3197	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_32_CLOCKS     = 0x1,
3198	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_64_CLOCKS     = 0x2,
3199	LB_SYNC_RESET_SEL_LB_SYNC_DURATION_128_CLOCKS    = 0x3,
3200} LB_SYNC_RESET_SEL_LB_SYNC_DURATION;
3201typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN {
3202	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_DISABLE       = 0x0,
3203	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_ENABLE        = 0x1,
3204} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_EN;
3205typedef enum LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN {
3206	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_DISABLE= 0x0,
3207	LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REPLACEMENT_ENABLE= 0x1,
3208} LB_KEYER_COLOR_CTRL_LB_KEYER_COLOR_REP_EN;
3209typedef enum LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK {
3210	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_NORMAL          = 0x0,
3211	LB_BUFFER_STATUS_LB_BUFFER_EMPTY_RESET           = 0x1,
3212} LB_BUFFER_STATUS_LB_BUFFER_EMPTY_ACK;
3213typedef enum LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK {
3214	LB_BUFFER_STATUS_LB_BUFFER_FULL_NORMAL           = 0x0,
3215	LB_BUFFER_STATUS_LB_BUFFER_FULL_RESET            = 0x1,
3216} LB_BUFFER_STATUS_LB_BUFFER_FULL_ACK;
3217typedef enum LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE {
3218	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_REAL_FLIP = 0x2,
3219	LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE_DUMMY_FLIP= 0x3,
3220} LB_MVP_AFR_FLIP_MODE_MVP_AFR_FLIP_MODE;
3221typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET {
3222	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_NORMAL= 0x0,
3223	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACTIVE= 0x1,
3224} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET;
3225typedef enum LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK {
3226	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED0= 0x0,
3227	LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK_NOT_USED1= 0x1,
3228} LB_MVP_AFR_FLIP_FIFO_CNTL_MVP_AFR_FLIP_FIFO_RESET_ACK;
3229typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE {
3230	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_NO_INSERT= 0x0,
3231	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_DEBUG= 0x1,
3232	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE_HSYNC_MODE= 0x2,
3233} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_LINE_NUM_INSERT_MODE;
3234typedef enum LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE {
3235	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_DISABLE= 0x0,
3236	LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_EN     = 0x1,
3237} LB_MVP_FLIP_LINE_NUM_INSERT_MVP_FLIP_AUTO_ENABLE;
3238typedef enum LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE {
3239	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_MASTER= 0x1,
3240	ALPHA_LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE_SLAVE= 0x2,
3241} LB_DC_MVP_LB_CONTROL_MVP_SWAP_LOCK_IN_MODE;
3242typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL {
3243	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED0= 0x0,
3244	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL_NOT_USED1= 0x1,
3245} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_SEL;
3246typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE {
3247	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ONE= 0x0,
3248	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ONE= 0x1,
3249} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ONE;
3250typedef enum LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO {
3251	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_NO_FORCE_ZERO= 0x0,
3252	LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_TO_ZERO= 0x1,
3253} LB_DC_MVP_LB_CONTROL_DC_MVP_SWAP_LOCK_OUT_FORCE_ZERO;
3254typedef enum LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN {
3255	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED0= 0x0,
3256	LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN_NOT_USED1= 0x1,
3257} LB_TEST_DEBUG_INDEX_LB_TEST_DEBUG_WRITE_EN;
3258typedef enum LBV_PIXEL_DEPTH {
3259	PIXEL_DEPTH_30BPP                                = 0x0,
3260	PIXEL_DEPTH_24BPP                                = 0x1,
3261	PIXEL_DEPTH_18BPP                                = 0x2,
3262	PIXEL_DEPTH_38BPP                                = 0x3,
3263} LBV_PIXEL_DEPTH;
3264typedef enum LBV_PIXEL_EXPAN_MODE {
3265	PIXEL_EXPAN_MODE_ZERO_EXP                        = 0x0,
3266	PIXEL_EXPAN_MODE_DYN_EXP                         = 0x1,
3267} LBV_PIXEL_EXPAN_MODE;
3268typedef enum LBV_INTERLEAVE_EN {
3269	INTERLEAVE_DIS                                   = 0x0,
3270	INTERLEAVE_EN                                    = 0x1,
3271} LBV_INTERLEAVE_EN;
3272typedef enum LBV_PIXEL_REDUCE_MODE {
3273	PIXEL_REDUCE_MODE_TRUNCATION                     = 0x0,
3274	PIXEL_REDUCE_MODE_ROUNDING                       = 0x1,
3275} LBV_PIXEL_REDUCE_MODE;
3276typedef enum LBV_DYNAMIC_PIXEL_DEPTH {
3277	DYNAMIC_PIXEL_DEPTH_36BPP                        = 0x0,
3278	DYNAMIC_PIXEL_DEPTH_30BPP                        = 0x1,
3279} LBV_DYNAMIC_PIXEL_DEPTH;
3280typedef enum LBV_DITHER_EN {
3281	DITHER_DIS                                       = 0x0,
3282	DITHER_EN                                        = 0x1,
3283} LBV_DITHER_EN;
3284typedef enum LBV_DOWNSCALE_PREFETCH_EN {
3285	DOWNSCALE_PREFETCH_DIS                           = 0x0,
3286	DOWNSCALE_PREFETCH_EN                            = 0x1,
3287} LBV_DOWNSCALE_PREFETCH_EN;
3288typedef enum LBV_MEMORY_CONFIG {
3289	MEMORY_CONFIG_0                                  = 0x0,
3290	MEMORY_CONFIG_1                                  = 0x1,
3291	MEMORY_CONFIG_2                                  = 0x2,
3292	MEMORY_CONFIG_3                                  = 0x3,
3293} LBV_MEMORY_CONFIG;
3294typedef enum LBV_SYNC_RESET_SEL2 {
3295	SYNC_RESET_SEL2_VBLANK                           = 0x0,
3296	SYNC_RESET_SEL2_VSYNC                            = 0x1,
3297} LBV_SYNC_RESET_SEL2;
3298typedef enum LBV_SYNC_DURATION {
3299	SYNC_DURATION_16                                 = 0x0,
3300	SYNC_DURATION_32                                 = 0x1,
3301	SYNC_DURATION_64                                 = 0x2,
3302	SYNC_DURATION_128                                = 0x3,
3303} LBV_SYNC_DURATION;
3304typedef enum SCL_C_RAM_TAP_PAIR_IDX {
3305	SCL_C_RAM_TAP_PAIR_ID0                           = 0x0,
3306	SCL_C_RAM_TAP_PAIR_ID1                           = 0x1,
3307	SCL_C_RAM_TAP_PAIR_ID2                           = 0x2,
3308	SCL_C_RAM_TAP_PAIR_ID3                           = 0x3,
3309	SCL_C_RAM_TAP_PAIR_ID4                           = 0x4,
3310} SCL_C_RAM_TAP_PAIR_IDX;
3311typedef enum SCL_C_RAM_PHASE {
3312	SCL_C_RAM_PHASE_0                                = 0x0,
3313	SCL_C_RAM_PHASE_1                                = 0x1,
3314	SCL_C_RAM_PHASE_2                                = 0x2,
3315	SCL_C_RAM_PHASE_3                                = 0x3,
3316	SCL_C_RAM_PHASE_4                                = 0x4,
3317	SCL_C_RAM_PHASE_5                                = 0x5,
3318	SCL_C_RAM_PHASE_6                                = 0x6,
3319	SCL_C_RAM_PHASE_7                                = 0x7,
3320	SCL_C_RAM_PHASE_8                                = 0x8,
3321} SCL_C_RAM_PHASE;
3322typedef enum SCL_C_RAM_FILTER_TYPE {
3323	SCL_C_RAM_FILTER_TYPE_VERT_LUMA_RGB_LUT          = 0x0,
3324	SCL_C_RAM_FILTER_TYPE_VERT_CHROMA_LUT            = 0x1,
3325	SCL_C_RAM_FILTER_TYPE_HORI_LUMA_RGB_LUT          = 0x2,
3326	SCL_C_RAM_FILTER_TYPE_HORI_CHROMA_LUT            = 0x3,
3327	SCL_C_RAM_FILTER_TYPE_VERT_ALPHA_LUT             = 0x4,
3328	SCL_C_RAM_FILTER_TYPE_HORI_ALPHA_LUT             = 0x5,
3329} SCL_C_RAM_FILTER_TYPE;
3330typedef enum SCL_MODE_SEL {
3331	SCL_MODE_SCL_BYPASS                              = 0x0,
3332	SCL_MODE_RGB_SCALING                             = 0x1,
3333	SCL_MODE_YCBCR_SCALING                           = 0x2,
3334} SCL_MODE_SEL;
3335typedef enum SCL_PSCL_EN {
3336	SCL_PSCL_DISABLE                                 = 0x0,
3337	SCL_PSCL_ENANBLE                                 = 0x1,
3338} SCL_PSCL_EN;
3339typedef enum SCL_V_NUM_OF_TAPS {
3340	SCL_V_NUM_OF_TAPS_1                              = 0x0,
3341	SCL_V_NUM_OF_TAPS_2                              = 0x1,
3342	SCL_V_NUM_OF_TAPS_3                              = 0x2,
3343	SCL_V_NUM_OF_TAPS_4                              = 0x3,
3344	SCL_V_NUM_OF_TAPS_5                              = 0x4,
3345	SCL_V_NUM_OF_TAPS_6                              = 0x5,
3346} SCL_V_NUM_OF_TAPS;
3347typedef enum SCL_H_NUM_OF_TAPS {
3348	SCL_H_NUM_OF_TAPS_1                              = 0x0,
3349	SCL_H_NUM_OF_TAPS_2                              = 0x1,
3350	SCL_H_NUM_OF_TAPS_4                              = 0x3,
3351	SCL_H_NUM_OF_TAPS_6                              = 0x5,
3352	SCL_H_NUM_OF_TAPS_8                              = 0x7,
3353	SCL_H_NUM_OF_TAPS_10                             = 0x9,
3354} SCL_H_NUM_OF_TAPS;
3355typedef enum SCL_BOUNDARY_MODE {
3356	SCL_BOUNDARY_MODE_BLACK                          = 0x0,
3357	SCL_BOUNDARY_MODE_EDGE                           = 0x1,
3358} SCL_BOUNDARY_MODE;
3359typedef enum SCL_EARLY_EOL_MOD {
3360	SCL_EARLY_EOL_MODE_CRTC                          = 0x0,
3361	SCL_EARLY_EOL_MODE_INTERNAL                      = 0x1,
3362} SCL_EARLY_EOL_MOD;
3363typedef enum SCL_BYPASS_MODE {
3364	SCL_BYPASS_MODE_MC_MR                            = 0x0,
3365	SCL_BYPASS_MODE_AC_NR                            = 0x1,
3366	SCL_BYPASS_MODE_AC_AR                            = 0x2,
3367	SCL_BYPASS_MODE_RESERVED                         = 0x3,
3368} SCL_BYPASS_MODE;
3369typedef enum SCL_V_MANUAL_REPLICATE_FACTOR {
3370	SCL_V_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
3371	SCL_V_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
3372	SCL_V_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
3373	SCL_V_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
3374	SCL_V_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
3375	SCL_V_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
3376	SCL_V_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
3377	SCL_V_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
3378	SCL_V_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
3379	SCL_V_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
3380	SCL_V_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
3381	SCL_V_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
3382	SCL_V_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
3383	SCL_V_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
3384	SCL_V_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
3385	SCL_V_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
3386} SCL_V_MANUAL_REPLICATE_FACTOR;
3387typedef enum SCL_H_MANUAL_REPLICATE_FACTOR {
3388	SCL_H_MANUAL_REPLICATE_FACTOR_1                  = 0x0,
3389	SCL_H_MANUAL_REPLICATE_FACTOR_2                  = 0x1,
3390	SCL_H_MANUAL_REPLICATE_FACTOR_3                  = 0x2,
3391	SCL_H_MANUAL_REPLICATE_FACTOR_4                  = 0x3,
3392	SCL_H_MANUAL_REPLICATE_FACTOR_5                  = 0x4,
3393	SCL_H_MANUAL_REPLICATE_FACTOR_6                  = 0x5,
3394	SCL_H_MANUAL_REPLICATE_FACTOR_7                  = 0x6,
3395	SCL_H_MANUAL_REPLICATE_FACTOR_8                  = 0x7,
3396	SCL_H_MANUAL_REPLICATE_FACTOR_9                  = 0x8,
3397	SCL_H_MANUAL_REPLICATE_FACTOR_10                 = 0x9,
3398	SCL_H_MANUAL_REPLICATE_FACTOR_11                 = 0xa,
3399	SCL_H_MANUAL_REPLICATE_FACTOR_12                 = 0xb,
3400	SCL_H_MANUAL_REPLICATE_FACTOR_13                 = 0xc,
3401	SCL_H_MANUAL_REPLICATE_FACTOR_14                 = 0xd,
3402	SCL_H_MANUAL_REPLICATE_FACTOR_15                 = 0xe,
3403	SCL_H_MANUAL_REPLICATE_FACTOR_16                 = 0xf,
3404} SCL_H_MANUAL_REPLICATE_FACTOR;
3405typedef enum SCL_V_CALC_AUTO_RATIO_EN {
3406	SCL_V_CALC_AUTO_RATIO_DISABLE                    = 0x0,
3407	SCL_V_CALC_AUTO_RATIO_ENABLE                     = 0x1,
3408} SCL_V_CALC_AUTO_RATIO_EN;
3409typedef enum SCL_H_CALC_AUTO_RATIO_EN {
3410	SCL_H_CALC_AUTO_RATIO_DISABLE                    = 0x0,
3411	SCL_H_CALC_AUTO_RATIO_ENABLE                     = 0x1,
3412} SCL_H_CALC_AUTO_RATIO_EN;
3413typedef enum SCL_H_FILTER_PICK_NEAREST {
3414	SCL_H_FILTER_PICK_NEAREST_DISABLE                = 0x0,
3415	SCL_H_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
3416} SCL_H_FILTER_PICK_NEAREST;
3417typedef enum SCL_H_2TAP_HARDCODE_COEF_EN {
3418	SCL_H_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
3419	SCL_H_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
3420} SCL_H_2TAP_HARDCODE_COEF_EN;
3421typedef enum SCL_V_FILTER_PICK_NEAREST {
3422	SCL_V_FILTER_PICK_NEAREST_DISABLE                = 0x0,
3423	SCL_V_FILTER_PICK_NEAREST_ENABLE                 = 0x1,
3424} SCL_V_FILTER_PICK_NEAREST;
3425typedef enum SCL_V_2TAP_HARDCODE_COEF_EN {
3426	SCL_V_2TAP_HARDCODE_COEF_DISABLE                 = 0x0,
3427	SCL_V_2TAP_HARDCODE_COEF_ENABLE                  = 0x1,
3428} SCL_V_2TAP_HARDCODE_COEF_EN;
3429typedef enum SCL_UPDATE_TAKEN {
3430	SCL_UPDATE_TAKEN_NO                              = 0x0,
3431	SCL_UPDATE_TAKEN_YES                             = 0x1,
3432} SCL_UPDATE_TAKEN;
3433typedef enum SCL_UPDATE_LOCK {
3434	SCL_UPDATE_UNLOCKED                              = 0x0,
3435	SCL_UPDATE_LOCKED                                = 0x1,
3436} SCL_UPDATE_LOCK;
3437typedef enum SCL_COEF_UPDATE_COMPLETE {
3438	SCL_COEF_UPDATE_NOT_COMPLETED                    = 0x0,
3439	SCL_COEF_UPDATE_COMPLETED                        = 0x1,
3440} SCL_COEF_UPDATE_COMPLETE;
3441typedef enum SCL_HF_SHARP_SCALE_FACTOR {
3442	SCL_HF_SHARP_SCALE_FACTOR_0                      = 0x0,
3443	SCL_HF_SHARP_SCALE_FACTOR_1                      = 0x1,
3444	SCL_HF_SHARP_SCALE_FACTOR_2                      = 0x2,
3445	SCL_HF_SHARP_SCALE_FACTOR_3                      = 0x3,
3446	SCL_HF_SHARP_SCALE_FACTOR_4                      = 0x4,
3447	SCL_HF_SHARP_SCALE_FACTOR_5                      = 0x5,
3448	SCL_HF_SHARP_SCALE_FACTOR_6                      = 0x6,
3449	SCL_HF_SHARP_SCALE_FACTOR_7                      = 0x7,
3450} SCL_HF_SHARP_SCALE_FACTOR;
3451typedef enum SCL_HF_SHARP_EN {
3452	SCL_HF_SHARP_DISABLE                             = 0x0,
3453	SCL_HF_SHARP_ENABLE                              = 0x1,
3454} SCL_HF_SHARP_EN;
3455typedef enum SCL_VF_SHARP_SCALE_FACTOR {
3456	SCL_VF_SHARP_SCALE_FACTOR_0                      = 0x0,
3457	SCL_VF_SHARP_SCALE_FACTOR_1                      = 0x1,
3458	SCL_VF_SHARP_SCALE_FACTOR_2                      = 0x2,
3459	SCL_VF_SHARP_SCALE_FACTOR_3                      = 0x3,
3460	SCL_VF_SHARP_SCALE_FACTOR_4                      = 0x4,
3461	SCL_VF_SHARP_SCALE_FACTOR_5                      = 0x5,
3462	SCL_VF_SHARP_SCALE_FACTOR_6                      = 0x6,
3463	SCL_VF_SHARP_SCALE_FACTOR_7                      = 0x7,
3464} SCL_VF_SHARP_SCALE_FACTOR;
3465typedef enum SCL_VF_SHARP_EN {
3466	SCL_VF_SHARP_DISABLE                             = 0x0,
3467	SCL_VF_SHARP_ENABLE                              = 0x1,
3468} SCL_VF_SHARP_EN;
3469typedef enum SCL_ALU_DISABLE {
3470	SCL_ALU_ENABLED                                  = 0x0,
3471	SCL_ALU_DISABLED                                 = 0x1,
3472} SCL_ALU_DISABLE;
3473typedef enum SCL_HOST_CONFLICT_MASK {
3474	SCL_HOST_CONFLICT_DISABLE_INTERRUPT              = 0x0,
3475	SCL_HOST_CONFLICT_ENABLE_INTERRUPT               = 0x1,
3476} SCL_HOST_CONFLICT_MASK;
3477typedef enum SCL_SCL_MODE_CHANGE_MASK {
3478	SCL_MODE_CHANGE_DISABLE_INTERRUPT                = 0x0,
3479	SCL_MODE_CHANGE_ENABLE_INTERRUPT                 = 0x1,
3480} SCL_SCL_MODE_CHANGE_MASK;
3481typedef enum SCLV_INTERLACE_SOURCE {
3482	INTERLACE_SOURCE_PROGRESSIVE                     = 0x0,
3483	INTERLACE_SOURCE_INTERLEAVE                      = 0x1,
3484	INTERLACE_SOURCE_STACK                           = 0x2,
3485} SCLV_INTERLACE_SOURCE;
3486typedef enum SCLV_UPDATE_LOCK {
3487	UPDATE_UNLOCKED                                  = 0x0,
3488	UPDATE_LOCKED                                    = 0x1,
3489} SCLV_UPDATE_LOCK;
3490typedef enum SCLV_COEF_UPDATE_COMPLETE {
3491	COEF_UPDATE_NOT_COMPLETE                         = 0x0,
3492	COEF_UPDATE_COMPLETE                             = 0x1,
3493} SCLV_COEF_UPDATE_COMPLETE;
3494typedef enum COL_MAN_UPDATE_LOCK {
3495	COL_MAN_UPDATE_UNLOCKED                          = 0x0,
3496	COL_MAN_UPDATE_LOCKED                            = 0x1,
3497} COL_MAN_UPDATE_LOCK;
3498typedef enum COL_MAN_DISABLE_MULTIPLE_UPDATE {
3499	COL_MAN_MULTIPLE_UPDATE                          = 0x0,
3500	COL_MAN_MULTIPLE_UPDAT_EDISABLE                  = 0x1,
3501} COL_MAN_DISABLE_MULTIPLE_UPDATE;
3502typedef enum COL_MAN_INPUTCSC_MODE {
3503	INPUTCSC_MODE_BYPASS                             = 0x0,
3504	INPUTCSC_MODE_A                                  = 0x1,
3505	INPUTCSC_MODE_B                                  = 0x2,
3506	INPUTCSC_MODE_UNITY                              = 0x3,
3507} COL_MAN_INPUTCSC_MODE;
3508typedef enum COL_MAN_INPUTCSC_TYPE {
3509	INPUTCSC_TYPE_12_0                               = 0x0,
3510	INPUTCSC_TYPE_10_2                               = 0x1,
3511	INPUTCSC_TYPE_8_4                                = 0x2,
3512} COL_MAN_INPUTCSC_TYPE;
3513typedef enum COL_MAN_INPUTCSC_CONVERT {
3514	INPUTCSC_ROUND                                   = 0x0,
3515	INPUTCSC_TRUNCATE                                = 0x1,
3516} COL_MAN_INPUTCSC_CONVERT;
3517typedef enum COL_MAN_PRESCALE_MODE {
3518	PRESCALE_MODE_BYPASS                             = 0x0,
3519	PRESCALE_MODE_PROGRAM                            = 0x1,
3520	PRESCALE_MODE_UNITY                              = 0x2,
3521} COL_MAN_PRESCALE_MODE;
3522typedef enum COL_MAN_INPUT_GAMMA_MODE {
3523	INGAMMA_MODE_BYPASS                              = 0x0,
3524	INGAMMA_MODE_FIX                                 = 0x1,
3525	INGAMMA_MODE_FLOAT                               = 0x2,
3526} COL_MAN_INPUT_GAMMA_MODE;
3527typedef enum COL_MAN_OUTPUT_CSC_MODE {
3528	COL_MAN_OUTPUT_CSC_BYPASS                        = 0x0,
3529	COL_MAN_OUTPUT_CSC_RGB                           = 0x1,
3530	COL_MAN_OUTPUT_CSC_YCrCb601                      = 0x2,
3531	COL_MAN_OUTPUT_CSC_YCrCb709                      = 0x3,
3532	COL_MAN_OUTPUT_CSC_A                             = 0x4,
3533	COL_MAN_OUTPUT_CSC_B                             = 0x5,
3534	COL_MAN_OUTPUT_CSC_UNITY                         = 0x6,
3535} COL_MAN_OUTPUT_CSC_MODE;
3536typedef enum COL_MAN_DENORM_CLAMP_CONTROL {
3537	DENORM_CLAMP_MODE_UNITY                          = 0x0,
3538	DENORM_CLAMP_MODE_8                              = 0x1,
3539	DENORM_CLAMP_MODE_10                             = 0x2,
3540	DENORM_CLAMP_MODE_12                             = 0x3,
3541} COL_MAN_DENORM_CLAMP_CONTROL;
3542typedef enum COL_MAN_GAMMA_CORR_CONTROL {
3543	GAMMA_CORR_MODE_BYPASS                           = 0x0,
3544	GAMMA_CORR_MODE_A                                = 0x1,
3545	GAMMA_CORR_MODE_B                                = 0x2,
3546} COL_MAN_GAMMA_CORR_CONTROL;
3547typedef enum COL_MAN_GLOBAL_PASSTHROUGH_ENABLE {
3548	CM_GLOBAL_PASSTHROUGH_DISBALE                    = 0x0,
3549	CM_GLOBAL_PASSTHROUGH_ENABLE                     = 0x1,
3550} COL_MAN_GLOBAL_PASSTHROUGH_ENABLE;
3551typedef enum UNP_GRPH_EN {
3552	UNP_GRPH_DISABLED                                = 0x0,
3553	UNP_GRPH_ENABLED                                 = 0x1,
3554} UNP_GRPH_EN;
3555typedef enum UNP_GRPH_DEPTH {
3556	UNP_GRPH_8BPP                                    = 0x0,
3557	UNP_GRPH_16BPP                                   = 0x1,
3558	UNP_GRPH_32BPP                                   = 0x2,
3559} UNP_GRPH_DEPTH;
3560typedef enum UNP_GRPH_NUM_BANKS {
3561	UNP_GRPH_ADDR_SURF_2_BANK                        = 0x0,
3562	UNP_GRPH_ADDR_SURF_4_BANK                        = 0x1,
3563	UNP_GRPH_ADDR_SURF_8_BANK                        = 0x2,
3564	UNP_GRPH_ADDR_SURF_16_BANK                       = 0x3,
3565} UNP_GRPH_NUM_BANKS;
3566typedef enum UNP_GRPH_BANK_WIDTH {
3567	UNP_GRPH_ADDR_SURF_BANK_WIDTH_1                  = 0x0,
3568	UNP_GRPH_ADDR_SURF_BANK_WIDTH_2                  = 0x1,
3569	UNP_GRPH_ADDR_SURF_BANK_WIDTH_4                  = 0x2,
3570	UNP_GRPH_ADDR_SURF_BANK_WIDTH_8                  = 0x3,
3571} UNP_GRPH_BANK_WIDTH;
3572typedef enum UNP_GRPH_BANK_HEIGHT {
3573	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_1                 = 0x0,
3574	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_2                 = 0x1,
3575	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_4                 = 0x2,
3576	UNP_GRPH_ADDR_SURF_BANK_HEIGHT_8                 = 0x3,
3577} UNP_GRPH_BANK_HEIGHT;
3578typedef enum UNP_GRPH_TILE_SPLIT {
3579	UNP_ADDR_SURF_TILE_SPLIT_64B                     = 0x0,
3580	UNP_ADDR_SURF_TILE_SPLIT_128B                    = 0x1,
3581	UNP_ADDR_SURF_TILE_SPLIT_256B                    = 0x2,
3582	UNP_ADDR_SURF_TILE_SPLIT_512B                    = 0x3,
3583	UNP_ADDR_SURF_TILE_SPLIT_1KB                     = 0x4,
3584	UNP_ADDR_SURF_TILE_SPLIT_2KB                     = 0x5,
3585	UNP_ADDR_SURF_TILE_SPLIT_4KB                     = 0x6,
3586} UNP_GRPH_TILE_SPLIT;
3587typedef enum UNP_GRPH_ADDRESS_TRANSLATION_ENABLE {
3588	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE0             = 0x0,
3589	UNP_GRPH_ADDRESS_TRANSLATION_ENABLE1             = 0x1,
3590} UNP_GRPH_ADDRESS_TRANSLATION_ENABLE;
3591typedef enum UNP_GRPH_PRIVILEGED_ACCESS_ENABLE {
3592	UNP_GRPH_PRIVILEGED_ACCESS_DIS                   = 0x0,
3593	UNP_GRPH_PRIVILEGED_ACCESS_EN                    = 0x1,
3594} UNP_GRPH_PRIVILEGED_ACCESS_ENABLE;
3595typedef enum UNP_GRPH_MACRO_TILE_ASPECT {
3596	UNP_ADDR_SURF_MACRO_ASPECT_1                     = 0x0,
3597	UNP_ADDR_SURF_MACRO_ASPECT_2                     = 0x1,
3598	UNP_ADDR_SURF_MACRO_ASPECT_4                     = 0x2,
3599	UNP_ADDR_SURF_MACRO_ASPECT_8                     = 0x3,
3600} UNP_GRPH_MACRO_TILE_ASPECT;
3601typedef enum UNP_GRPH_COLOR_EXPANSION_MODE {
3602	UNP_GRPH_DYNAMIC_EXPANSION                       = 0x0,
3603	UNP_GRPH_ZERO_EXPANSION                          = 0x1,
3604} UNP_GRPH_COLOR_EXPANSION_MODE;
3605typedef enum UNP_VIDEO_FORMAT {
3606	UNP_VIDEO_FORMAT0                                = 0x0,
3607	UNP_VIDEO_FORMAT1                                = 0x1,
3608	UNP_VIDEO_FORMAT_YUV420_YCbCr                    = 0x2,
3609	UNP_VIDEO_FORMAT_YUV420_YCrCb                    = 0x3,
3610	UNP_VIDEO_FORMAT_YUV422_YCb                      = 0x4,
3611	UNP_VIDEO_FORMAT_YUV422_YCr                      = 0x5,
3612	UNP_VIDEO_FORMAT_YUV422_CbY                      = 0x6,
3613	UNP_VIDEO_FORMAT_YUV422_CrY                      = 0x7,
3614} UNP_VIDEO_FORMAT;
3615typedef enum UNP_GRPH_ENDIAN_SWAP {
3616	UNP_GRPH_ENDIAN_SWAP_NONE                        = 0x0,
3617	UNP_GRPH_ENDIAN_SWAP_8IN16                       = 0x1,
3618	UNP_GRPH_ENDIAN_SWAP_8IN32                       = 0x2,
3619	UNP_GRPH_ENDIAN_SWAP_8IN43                       = 0x3,
3620} UNP_GRPH_ENDIAN_SWAP;
3621typedef enum UNP_GRPH_RED_CROSSBAR {
3622	UNP_GRPH_RED_CROSSBAR_R_Cr                       = 0x0,
3623	UNP_GRPH_RED_CROSSBAR_G_Y                        = 0x1,
3624	UNP_GRPH_RED_CROSSBAR_B_Cb                       = 0x2,
3625	UNP_GRPH_RED_CROSSBAR_A                          = 0x3,
3626} UNP_GRPH_RED_CROSSBAR;
3627typedef enum UNP_GRPH_GREEN_CROSSBAR {
3628	UNP_UNP_GRPH_GREEN_CROSSBAR_GY_AND_Y             = 0x0,
3629	UNP_UNP_GRPH_GREEN_CROSSBAR_B_Cb_AND_C           = 0x1,
3630	UNP_UNP_GRPH_GREEN_CROSSBAR_A                    = 0x2,
3631	UNP_UNP_GRPH_GREEN_CROSSBAR_R_Cr                 = 0x3,
3632} UNP_GRPH_GREEN_CROSSBAR;
3633typedef enum UNP_GRPH_BLUE_CROSSBAR {
3634	UNP_GRPH_BLUE_CROSSBAR_B_Cb_AND_C                = 0x0,
3635	UNP_GRPH_BLUE_CROSSBAR_A                         = 0x1,
3636	UNP_GRPH_BLUE_CROSSBAR_R_Cr                      = 0x2,
3637	UNP_GRPH_BLUE_CROSSBAR_GY_AND_Y                  = 0x3,
3638} UNP_GRPH_BLUE_CROSSBAR;
3639typedef enum UNP_GRPH_MODE_UPDATE_LOCKG {
3640	UNP_GRPH_UPDATE_LOCK_0                           = 0x0,
3641	UNP_GRPH_UPDATE_LOCK_1                           = 0x1,
3642} UNP_GRPH_MODE_UPDATE_LOCKG;
3643typedef enum UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK {
3644	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_0            = 0x0,
3645	UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK_1            = 0x1,
3646} UNP_GRPH_SURFACE_IGNORE_UPDATE_LOCK;
3647typedef enum UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE {
3648	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_0          = 0x0,
3649	UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE_1          = 0x1,
3650} UNP_GRPH_MODE_DISABLE_MULTIPLE_UPDATE;
3651typedef enum UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE {
3652	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_0       = 0x0,
3653	UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE_1       = 0x1,
3654} UNP_GRPH_SURFACE_DISABLE_MULTIPLE_UPDATE;
3655typedef enum UNP_GRPH_STEREOSYNC_FLIP_EN {
3656	UNP_GRPH_STEREOSYNC_FLIP_DISABLE                 = 0x0,
3657	UNP_GRPH_STEREOSYNC_FLIP_ENABLE                  = 0x1,
3658} UNP_GRPH_STEREOSYNC_FLIP_EN;
3659typedef enum UNP_GRPH_STEREOSYNC_FLIP_MODE {
3660	UNP_GRPH_STEREOSYNC_FLIP_MODE_0                  = 0x0,
3661	UNP_GRPH_STEREOSYNC_FLIP_MODE_1                  = 0x1,
3662	UNP_GRPH_STEREOSYNC_FLIP_MODE_2                  = 0x2,
3663	UNP_GRPH_STEREOSYNC_FLIP_MODE_3                  = 0x3,
3664} UNP_GRPH_STEREOSYNC_FLIP_MODE;
3665typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_EN {
3666	UNP_GRPH_STACK_INTERLACE_FLIP_DISABLE            = 0x0,
3667	UNP_GRPH_STACK_INTERLACE_FLIP_ENABLE             = 0x1,
3668} UNP_GRPH_STACK_INTERLACE_FLIP_EN;
3669typedef enum UNP_GRPH_STACK_INTERLACE_FLIP_MODE {
3670	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_0             = 0x0,
3671	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_1             = 0x1,
3672	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_2             = 0x2,
3673	UNP_GRPH_STACK_INTERLACE_FLIP_MODE_3             = 0x3,
3674} UNP_GRPH_STACK_INTERLACE_FLIP_MODE;
3675typedef enum UNP_GRPH_STEREOSYNC_SELECT_DISABLE {
3676	UNP_GRPH_STEREOSYNC_SELECT_EN                    = 0x0,
3677	UNP_GRPH_STEREOSYNC_SELECT_DIS                   = 0x1,
3678} UNP_GRPH_STEREOSYNC_SELECT_DISABLE;
3679typedef enum UNP_CRC_SOURCE_SEL {
3680	UNP_CRC_SOURCE_SEL_NP_TO_LBV                     = 0x0,
3681	UNP_CRC_SOURCE_SEL_LOWER32                       = 0x1,
3682	UNP_CRC_SOURCE_SEL_RESERVED                      = 0x2,
3683	UNP_CRC_SOURCE_SEL_LOWER16                       = 0x3,
3684	UNP_CRC_SOURCE_SEL_UNP_TO_LBV                    = 0x4,
3685} UNP_CRC_SOURCE_SEL;
3686typedef enum UNP_CRC_LINE_SEL {
3687	UNP_CRC_LINE_SEL_RESERVED                        = 0x0,
3688	UNP_CRC_LINE_SEL_EVEN_ONLY                       = 0x1,
3689	UNP_CRC_LINE_SEL_ODD_ONLY                        = 0x2,
3690	UNP_CRC_LINE_SEL_ODD_EVEN                        = 0x3,
3691} UNP_CRC_LINE_SEL;
3692typedef enum UNP_ROTATION_ANGLE {
3693	UNP_ROTATION_ANGLE_0                             = 0x0,
3694	UNP_ROTATION_ANGLE_90                            = 0x1,
3695	UNP_ROTATION_ANGLE_180                           = 0x2,
3696	UNP_ROTATION_ANGLE_270                           = 0x3,
3697	UNP_ROTATION_ANGLE_0m                            = 0x4,
3698	UNP_ROTATION_ANGLE_90m                           = 0x5,
3699	UNP_ROTATION_ANGLE_180m                          = 0x6,
3700	UNP_ROTATION_ANGLE_270m                          = 0x7,
3701} UNP_ROTATION_ANGLE;
3702typedef enum UNP_PIXEL_DROP {
3703	UNP_PIXEL_NO_DROP                                = 0x0,
3704	UNP_PIXEL_DROPPING                               = 0x1,
3705} UNP_PIXEL_DROP;
3706typedef enum UNP_BUFFER_MODE {
3707	UNP_BUFFER_MODE_LUMA                             = 0x0,
3708	UNP_BUFFER_MODE_LUMA_CHROMA                      = 0x1,
3709} UNP_BUFFER_MODE;
3710typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
3711	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET= 0x0,
3712	AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET= 0x1,
3713} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
3714typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
3715	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL= 0x0,
3716	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6= 0x1,
3717	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5= 0x2,
3718	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4= 0x3,
3719	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3= 0x4,
3720	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2= 0x5,
3721	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1= 0x6,
3722	CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0= 0x7,
3723} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
3724typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
3725	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL= 0x0,
3726	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6= 0x1,
3727	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5= 0x2,
3728	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4= 0x3,
3729	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3= 0x4,
3730	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2= 0x5,
3731	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1= 0x6,
3732	CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0= 0x7,
3733} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
3734typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
3735	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE           = 0x0,
3736	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE            = 0x1,
3737} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
3738typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
3739	GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED  = 0x0,
3740	GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED   = 0x1,
3741} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
3742typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
3743	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET    = 0x0,
3744	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET        = 0x1,
3745} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
3746typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
3747	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED= 0x0,
3748	GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED= 0x1,
3749} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
3750typedef enum AZ_GLOBAL_CAPABILITIES {
3751	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED= 0x0,
3752	AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED= 0x1,
3753} AZ_GLOBAL_CAPABILITIES;
3754typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
3755	ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE           = 0x0,
3756	ACCEPT_UNSOLICITED_RESPONSE_ENABLE               = 0x1,
3757} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
3758typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
3759	FLUSH_CONTROL_FLUSH_NOT_STARTED                  = 0x0,
3760	FLUSH_CONTROL_FLUSH_STARTED                      = 0x1,
3761} GLOBAL_CONTROL_FLUSH_CONTROL;
3762typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
3763	CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET          = 0x0,
3764	CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET      = 0x1,
3765} GLOBAL_CONTROL_CONTROLLER_RESET;
3766typedef enum AZ_STATE_CHANGE_STATUS {
3767	AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT         = 0x0,
3768	AZ_STATE_CHANGE_STATUS_CODEC_PRESENT             = 0x1,
3769} AZ_STATE_CHANGE_STATUS;
3770typedef enum GLOBAL_STATUS_FLUSH_STATUS {
3771	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED       = 0x0,
3772	GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED           = 0x1,
3773} GLOBAL_STATUS_FLUSH_STATUS;
3774typedef enum STREAM_0_SYNCHRONIZATION {
3775	STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
3776	STREAM_0_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
3777} STREAM_0_SYNCHRONIZATION;
3778typedef enum STREAM_1_SYNCHRONIZATION {
3779	STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
3780	STREAM_1_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
3781} STREAM_1_SYNCHRONIZATION;
3782typedef enum STREAM_2_SYNCHRONIZATION {
3783	STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED       = 0x0,
3784	STREAM_2_SYNCHRONIZATION_STEAM_STOPPED           = 0x1,
3785} STREAM_2_SYNCHRONIZATION;
3786typedef enum STREAM_3_SYNCHRONIZATION {
3787	STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3788	STREAM_3_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3789} STREAM_3_SYNCHRONIZATION;
3790typedef enum STREAM_4_SYNCHRONIZATION {
3791	STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3792	STREAM_4_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3793} STREAM_4_SYNCHRONIZATION;
3794typedef enum STREAM_5_SYNCHRONIZATION {
3795	STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3796	STREAM_5_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3797} STREAM_5_SYNCHRONIZATION;
3798typedef enum STREAM_6_SYNCHRONIZATION {
3799	STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3800	STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3801} STREAM_6_SYNCHRONIZATION;
3802typedef enum STREAM_7_SYNCHRONIZATION {
3803	STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3804	STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3805} STREAM_7_SYNCHRONIZATION;
3806typedef enum STREAM_8_SYNCHRONIZATION {
3807	STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3808	STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3809} STREAM_8_SYNCHRONIZATION;
3810typedef enum STREAM_9_SYNCHRONIZATION {
3811	STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3812	STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED  = 0x1,
3813} STREAM_9_SYNCHRONIZATION;
3814typedef enum STREAM_10_SYNCHRONIZATION {
3815	STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3816	STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3817} STREAM_10_SYNCHRONIZATION;
3818typedef enum STREAM_11_SYNCHRONIZATION {
3819	STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3820	STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3821} STREAM_11_SYNCHRONIZATION;
3822typedef enum STREAM_12_SYNCHRONIZATION {
3823	STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3824	STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3825} STREAM_12_SYNCHRONIZATION;
3826typedef enum STREAM_13_SYNCHRONIZATION {
3827	STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3828	STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3829} STREAM_13_SYNCHRONIZATION;
3830typedef enum STREAM_14_SYNCHRONIZATION {
3831	STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3832	STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3833} STREAM_14_SYNCHRONIZATION;
3834typedef enum STREAM_15_SYNCHRONIZATION {
3835	STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED= 0x0,
3836	STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x1,
3837} STREAM_15_SYNCHRONIZATION;
3838typedef enum CORB_READ_POINTER_RESET {
3839	CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET    = 0x0,
3840	CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET        = 0x1,
3841} CORB_READ_POINTER_RESET;
3842typedef enum AZ_CORB_SIZE {
3843	AZ_CORB_SIZE_2ENTRIES_RESERVED                   = 0x0,
3844	AZ_CORB_SIZE_16ENTRIES_RESERVED                  = 0x1,
3845	AZ_CORB_SIZE_256ENTRIES                          = 0x2,
3846	AZ_CORB_SIZE_RESERVED                            = 0x3,
3847} AZ_CORB_SIZE;
3848typedef enum AZ_RIRB_WRITE_POINTER_RESET {
3849	AZ_RIRB_WRITE_POINTER_NOT_RESET                  = 0x0,
3850	AZ_RIRB_WRITE_POINTER_DO_RESET                   = 0x1,
3851} AZ_RIRB_WRITE_POINTER_RESET;
3852typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
3853	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
3854	RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
3855} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
3856typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
3857	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED= 0x0,
3858	RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED= 0x1,
3859} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
3860typedef enum AZ_RIRB_SIZE {
3861	AZ_RIRB_SIZE_2ENTRIES_RESERVED                   = 0x0,
3862	AZ_RIRB_SIZE_16ENTRIES_RESERVED                  = 0x1,
3863	AZ_RIRB_SIZE_256ENTRIES                          = 0x2,
3864	AZ_RIRB_SIZE_UNDEFINED                           = 0x3,
3865} AZ_RIRB_SIZE;
3866typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
3867	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID= 0x0,
3868	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID= 0x1,
3869} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
3870typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
3871	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY= 0x0,
3872	IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY= 0x1,
3873} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
3874typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
3875	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE= 0x0,
3876	DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE= 0x1,
3877} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
3878typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
3879	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET= 0x0,
3880	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET= 0x1,
3881} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
3882typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
3883	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET= 0x0,
3884	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET= 0x1,
3885} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
3886typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
3887	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET= 0x0,
3888	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET= 0x1,
3889} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
3890typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
3891	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY= 0x0,
3892	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY= 0x1,
3893} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
3894typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
3895	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED= 0x0,
3896	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED= 0x1,
3897} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
3898typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
3899	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED= 0x0,
3900	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED= 0x1,
3901} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
3902typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
3903	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED= 0x0,
3904	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED= 0x1,
3905} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
3906typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
3907	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN= 0x0,
3908	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN= 0x1,
3909} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
3910typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
3911	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET= 0x0,
3912	OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET= 0x1,
3913} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
3914typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
3915	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
3916	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
3917} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
3918typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
3919	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
3920	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
3921	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3922	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
3923	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
3924} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
3925typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
3926	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
3927	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
3928	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3929	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
3930	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
3931	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
3932	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
3933	OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
3934} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
3935typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
3936	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
3937	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16= 0x1,
3938	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3939	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24= 0x3,
3940	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
3941	OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
3942} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
3943typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
3944	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
3945	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
3946	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
3947	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
3948	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
3949	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
3950	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
3951	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
3952	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED= 0x8,
3953	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED= 0x9,
3954	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED= 0xa,
3955	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED= 0xb,
3956	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED= 0xc,
3957	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED= 0xd,
3958	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED= 0xe,
3959	OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED= 0xf,
3960} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
3961typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
3962	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
3963	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
3964} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
3965typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
3966	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
3967	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
3968} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
3969typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
3970	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
3971	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
3972	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
3973	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
3974	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
3975} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
3976typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
3977	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
3978	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
3979	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
3980	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
3981	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
3982	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
3983	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
3984	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
3985} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
3986typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
3987	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
3988	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
3989	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
3990	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
3991	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
3992	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
3993} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
3994typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
3995	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
3996	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
3997	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
3998	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
3999	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4000	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4001	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4002	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4003	AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4004} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4005typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
4006	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET= 0x0,
4007	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET= 0x1,
4008} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
4009typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
4010	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET= 0x0,
4011	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET= 0x1,
4012} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
4013typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
4014	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET= 0x0,
4015	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET= 0x1,
4016} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
4017typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
4018	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET= 0x0,
4019	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET= 0x1,
4020} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
4021typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
4022	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET= 0x0,
4023	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET= 0x1,
4024} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
4025typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
4026	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON= 0x0,
4027	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON= 0x1,
4028} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
4029typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
4030	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO= 0x0,
4031	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE= 0x1,
4032} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
4033typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4034	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4035	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4036} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4037typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
4038	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE= 0x0,
4039	AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE= 0x1,
4040} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
4041typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
4042	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF= 0x0,
4043	AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN= 0x1,
4044} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
4045typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4046	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4047	AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4048} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4049typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
4050	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED= 0x0,
4051	AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN   = 0x1,
4052} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
4053typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
4054	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED= 0x0,
4055	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED= 0x1,
4056} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
4057typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
4058	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED= 0x0,
4059	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED= 0x1,
4060} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
4061typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
4062	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED= 0x0,
4063	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED= 0x1,
4064} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
4065typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
4066	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED= 0x0,
4067	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED= 0x1,
4068} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
4069typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4070	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4071	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4072} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4073typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4074	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4075	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4076} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4077typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4078	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4079	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4080} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4081typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4082	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4083	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4084} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4085typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4086	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4087	AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4088} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4089typedef enum AZ_LATENCY_COUNTER_CONTROL {
4090	AZ_LATENCY_COUNTER_NO_RESET                      = 0x0,
4091	AZ_LATENCY_COUNTER_RESET_DONE                    = 0x1,
4092} AZ_LATENCY_COUNTER_CONTROL;
4093typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4094	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4095	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4096	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4097	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4098	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4099	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4100	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4101	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4102	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4103	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4104} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4105typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4106	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4107	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4108} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4109typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4110	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4111	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4112} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4113typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4114	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4115	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4116} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4117typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4118	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4119	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4120} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4121typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4122	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4123	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4124} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4125typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4126	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4127	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4128} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4129typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4130	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4131	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4132} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4133typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4134	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4135	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE= 0x1,
4136} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4137typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4138	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4139	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4140} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4141typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4142	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4143	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4144} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4145typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4146	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4147	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4148} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4149typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4150	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4151	AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4152} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4153typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4154	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4155	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4156	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4157	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4158	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4159	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4160	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4161	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4162	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED= 0x8,
4163	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4164} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4165typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4166	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4167	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4168} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4169typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4170	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4171	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4172} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4173typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4174	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4175	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4176} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4177typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4178	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4179	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4180} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4181typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4182	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4183	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4184} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4185typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4186	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES= 0x0,
4187	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES= 0x1,
4188} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4189typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4190	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4191	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4192} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4193typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4194	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4195	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4196} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4197typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4198	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4199	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4200} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4201typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4202	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT= 0x0,
4203	AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4204} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4205typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4206	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN= 0x0,
4207	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN= 0x1,
4208} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4209typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4210	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED= 0x0,
4211	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4212} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4213typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4214	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4215	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4216} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4217typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4218	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4219	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4220} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4221typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4222	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4223	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4224} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4225typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4226	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY= 0x0,
4227	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY= 0x1,
4228} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4229typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4230	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4231	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4232} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4233typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4234	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4235	AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4236} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4237typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
4238	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE= 0x0,
4239	AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE= 0x1,
4240} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
4241typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4242	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY= 0x0,
4243	AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY= 0x1,
4244} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4245typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4246	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4247	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4248	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4249	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4250	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4251	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4252	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4253	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4254	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4255	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4256} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4257typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4258	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY= 0x0,
4259	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY= 0x1,
4260} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4261typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4262	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4263	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4264} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4265typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4266	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG= 0x0,
4267	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL= 0x1,
4268} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4269typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4270	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4271	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4272} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4273typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4274	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4275	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4276} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4277typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4278	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES= 0x0,
4279	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES= 0x1,
4280} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4281typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4282	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING= 0x0,
4283	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4284} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4285typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
4286	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE= 0x0,
4287	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE= 0x1,
4288} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
4289typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4290	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4291	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER= 0x1,
4292} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4293typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4294	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4295	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4296} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4297typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4298	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4299	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4300} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4301typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
4302	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC= 0x0,
4303	AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO= 0x1,
4304} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
4305typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
4306	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED= 0x0,
4307	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED= 0x1,
4308	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED= 0x2,
4309	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED= 0x3,
4310	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED= 0x4,
4311	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED= 0x5,
4312	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED= 0x6,
4313	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED= 0x7,
4314	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED= 0x8,
4315	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED= 0x9,
4316} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
4317typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
4318	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP= 0x0,
4319	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP= 0x1,
4320} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
4321typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
4322	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY= 0x0,
4323	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY= 0x1,
4324} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
4325typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
4326	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG= 0x0,
4327	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL= 0x1,
4328} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
4329typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
4330	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST= 0x0,
4331	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST= 0x1,
4332} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
4333typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
4334	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY= 0x0,
4335	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY= 0x1,
4336} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
4337typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
4338	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES= 0x0,
4339	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES= 0x1,
4340} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
4341typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
4342	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING= 0x0,
4343	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING= 0x1,
4344} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
4345typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
4346	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER= 0x0,
4347	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE= 0x1,
4348} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
4349typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
4350	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER= 0x0,
4351	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER= 0x1,
4352} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
4353typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
4354	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER= 0x0,
4355	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER= 0x1,
4356} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
4357typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
4358	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED= 0x0,
4359	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED= 0x1,
4360} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
4361typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
4362	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN= 0x0,
4363	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN= 0x1,
4364} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
4365typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
4366	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED= 0x0,
4367	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED= 0x1,
4368} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
4369typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
4370	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED= 0x0,
4371	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED= 0x1,
4372} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
4373typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
4374	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN= 0x0,
4375	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN= 0x1,
4376} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
4377typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
4378	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN= 0x0,
4379	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN= 0x1,
4380} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
4381typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
4382	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY= 0x0,
4383	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY= 0x1,
4384} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
4385typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
4386	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY= 0x0,
4387	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY= 0x1,
4388} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
4389typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
4390	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x0,
4391	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT= 0x1,
4392} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
4393typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
4394	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY= 0x0,
4395	AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY= 0x1,
4396} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
4397typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
4398	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY= 0x0,
4399	AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY= 0x1,
4400} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
4401typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
4402	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM= 0x0,
4403	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM= 0x1,
4404} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
4405typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
4406	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ= 0x0,
4407	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ= 0x1,
4408} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
4409typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
4410	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1= 0x0,
4411	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2= 0x1,
4412	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED= 0x2,
4413	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4= 0x3,
4414	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED= 0x4,
4415} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
4416typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
4417	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1= 0x0,
4418	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED= 0x1,
4419	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3= 0x2,
4420	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED= 0x3,
4421	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED= 0x4,
4422	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED= 0x5,
4423	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED= 0x6,
4424	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED= 0x7,
4425} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
4426typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
4427	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED= 0x0,
4428	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16= 0x1,
4429	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20= 0x2,
4430	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24= 0x3,
4431	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED= 0x4,
4432	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED= 0x5,
4433} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
4434typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
4435	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1= 0x0,
4436	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2= 0x1,
4437	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3= 0x2,
4438	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4= 0x3,
4439	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5= 0x4,
4440	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6= 0x5,
4441	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7= 0x6,
4442	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8= 0x7,
4443	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED= 0x8,
4444} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
4445typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
4446	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED= 0x0,
4447	AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED= 0x1,
4448} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
4449typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
4450	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF= 0x0,
4451	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN= 0x1,
4452} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
4453typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
4454	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED= 0x0,
4455	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED= 0x1,
4456} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
4457typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
4458	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED= 0x0,
4459	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED= 0x1,
4460} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
4461typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
4462	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED= 0x0,
4463	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED= 0x1,
4464} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
4465typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
4466	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED= 0x0,
4467	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED= 0x1,
4468} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
4469typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
4470	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED= 0x0,
4471	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED= 0x1,
4472} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
4473typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
4474	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED= 0x0,
4475	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED= 0x1,
4476} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
4477typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
4478	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED= 0x0,
4479	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED= 0x1,
4480} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
4481typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
4482	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED= 0x0,
4483	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED= 0x1,
4484} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
4485typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
4486	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED= 0x0,
4487	AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED= 0x1,
4488} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
4489typedef enum BLND_CONTROL_BLND_MODE {
4490	BLND_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY         = 0x0,
4491	BLND_CONTROL_BLND_MODE_OTHER_PIPE_ONLY           = 0x1,
4492	BLND_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE       = 0x2,
4493	BLND_CONTROL_BLND_MODE_OTHER_STEREO_TYPE         = 0x3,
4494} BLND_CONTROL_BLND_MODE;
4495typedef enum BLND_CONTROL_BLND_STEREO_TYPE {
4496	BLND_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
4497	BLND_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
4498	BLND_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
4499	BLND_CONTROL_BLND_STEREO_TYPE_UNUSED             = 0x3,
4500} BLND_CONTROL_BLND_STEREO_TYPE;
4501typedef enum BLND_CONTROL_BLND_STEREO_POLARITY {
4502	BLND_CONTROL_BLND_STEREO_POLARITY_LOW            = 0x0,
4503	BLND_CONTROL_BLND_STEREO_POLARITY_HIGH           = 0x1,
4504} BLND_CONTROL_BLND_STEREO_POLARITY;
4505typedef enum BLND_CONTROL_BLND_FEEDTHROUGH_EN {
4506	BLND_CONTROL_BLND_FEEDTHROUGH_EN_FALSE           = 0x0,
4507	BLND_CONTROL_BLND_FEEDTHROUGH_EN_TRUE            = 0x1,
4508} BLND_CONTROL_BLND_FEEDTHROUGH_EN;
4509typedef enum BLND_CONTROL_BLND_ALPHA_MODE {
4510	BLND_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA = 0x0,
4511	BLND_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
4512	BLND_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY   = 0x2,
4513	BLND_CONTROL_BLND_ALPHA_MODE_UNUSED              = 0x3,
4514} BLND_CONTROL_BLND_ALPHA_MODE;
4515typedef enum BLND_CONTROL_BLND_MULTIPLIED_MODE {
4516	BLND_CONTROL_BLND_MULTIPLIED_MODE_FALSE          = 0x0,
4517	BLND_CONTROL_BLND_MULTIPLIED_MODE_TRUE           = 0x1,
4518} BLND_CONTROL_BLND_MULTIPLIED_MODE;
4519typedef enum BLND_SM_CONTROL2_SM_MODE {
4520	BLND_SM_CONTROL2_SM_MODE_SINGLE_PLANE            = 0x0,
4521	BLND_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING         = 0x2,
4522	BLND_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING      = 0x4,
4523	BLND_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
4524} BLND_SM_CONTROL2_SM_MODE;
4525typedef enum BLND_SM_CONTROL2_SM_FRAME_ALTERNATE {
4526	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE        = 0x0,
4527	BLND_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE         = 0x1,
4528} BLND_SM_CONTROL2_SM_FRAME_ALTERNATE;
4529typedef enum BLND_SM_CONTROL2_SM_FIELD_ALTERNATE {
4530	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE        = 0x0,
4531	BLND_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE         = 0x1,
4532} BLND_SM_CONTROL2_SM_FIELD_ALTERNATE;
4533typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
4534	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
4535	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
4536	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
4537	BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
4538} BLND_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
4539typedef enum BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
4540	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE  = 0x0,
4541	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED  = 0x1,
4542	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x2,
4543	BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
4544} BLND_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
4545typedef enum BLND_CONTROL2_PTI_ENABLE {
4546	BLND_CONTROL2_PTI_ENABLE_FALSE                   = 0x0,
4547	BLND_CONTROL2_PTI_ENABLE_TRUE                    = 0x1,
4548} BLND_CONTROL2_PTI_ENABLE;
4549typedef enum BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
4550	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE      = 0x0,
4551	BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE       = 0x1,
4552} BLND_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
4553typedef enum BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
4554	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE      = 0x0,
4555	BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE       = 0x1,
4556} BLND_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
4557typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
4558	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
4559	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
4560} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
4561typedef enum BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
4562	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
4563	BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
4564} BLND_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
4565typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
4566	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
4567	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
4568} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
4569typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
4570	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
4571	BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
4572} BLND_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
4573typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
4574	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
4575	BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
4576} BLND_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
4577typedef enum BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
4578	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
4579	BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
4580} BLND_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
4581typedef enum BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
4582	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE  = 0x0,
4583	BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE   = 0x1,
4584} BLND_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
4585typedef enum BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
4586	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE = 0x0,
4587	BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE  = 0x1,
4588} BLND_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
4589typedef enum BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
4590	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE = 0x0,
4591	BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE  = 0x1,
4592} BLND_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
4593typedef enum BLND_DEBUG_BLND_CNV_MUX_SELECT {
4594	BLND_DEBUG_BLND_CNV_MUX_SELECT_LOW               = 0x0,
4595	BLND_DEBUG_BLND_CNV_MUX_SELECT_HIGH              = 0x1,
4596} BLND_DEBUG_BLND_CNV_MUX_SELECT;
4597typedef enum BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
4598	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
4599	BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
4600} BLND_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
4601typedef enum DebugBlockId {
4602	DBG_BLOCK_ID_RESERVED                            = 0x0,
4603	DBG_BLOCK_ID_DBG                                 = 0x1,
4604	DBG_BLOCK_ID_VMC                                 = 0x2,
4605	DBG_BLOCK_ID_PDMA                                = 0x3,
4606	DBG_BLOCK_ID_CG                                  = 0x4,
4607	DBG_BLOCK_ID_SRBM                                = 0x5,
4608	DBG_BLOCK_ID_GRBM                                = 0x6,
4609	DBG_BLOCK_ID_RLC                                 = 0x7,
4610	DBG_BLOCK_ID_CSC                                 = 0x8,
4611	DBG_BLOCK_ID_SEM                                 = 0x9,
4612	DBG_BLOCK_ID_IH                                  = 0xa,
4613	DBG_BLOCK_ID_SC                                  = 0xb,
4614	DBG_BLOCK_ID_SQ                                  = 0xc,
4615	DBG_BLOCK_ID_UVDU                                = 0xd,
4616	DBG_BLOCK_ID_SQA                                 = 0xe,
4617	DBG_BLOCK_ID_SDMA0                               = 0xf,
4618	DBG_BLOCK_ID_SDMA1                               = 0x10,
4619	DBG_BLOCK_ID_SPIM                                = 0x11,
4620	DBG_BLOCK_ID_GDS                                 = 0x12,
4621	DBG_BLOCK_ID_VC0                                 = 0x13,
4622	DBG_BLOCK_ID_VC1                                 = 0x14,
4623	DBG_BLOCK_ID_PA0                                 = 0x15,
4624	DBG_BLOCK_ID_PA1                                 = 0x16,
4625	DBG_BLOCK_ID_CP0                                 = 0x17,
4626	DBG_BLOCK_ID_CP1                                 = 0x18,
4627	DBG_BLOCK_ID_CP2                                 = 0x19,
4628	DBG_BLOCK_ID_XBR                                 = 0x1a,
4629	DBG_BLOCK_ID_UVDM                                = 0x1b,
4630	DBG_BLOCK_ID_VGT0                                = 0x1c,
4631	DBG_BLOCK_ID_VGT1                                = 0x1d,
4632	DBG_BLOCK_ID_IA                                  = 0x1e,
4633	DBG_BLOCK_ID_SXM0                                = 0x1f,
4634	DBG_BLOCK_ID_SXM1                                = 0x20,
4635	DBG_BLOCK_ID_SCT0                                = 0x21,
4636	DBG_BLOCK_ID_SCT1                                = 0x22,
4637	DBG_BLOCK_ID_SPM0                                = 0x23,
4638	DBG_BLOCK_ID_SPM1                                = 0x24,
4639	DBG_BLOCK_ID_UNUSED0                             = 0x25,
4640	DBG_BLOCK_ID_UNUSED1                             = 0x26,
4641	DBG_BLOCK_ID_TCAA                                = 0x27,
4642	DBG_BLOCK_ID_TCAB                                = 0x28,
4643	DBG_BLOCK_ID_TCCA                                = 0x29,
4644	DBG_BLOCK_ID_TCCB                                = 0x2a,
4645	DBG_BLOCK_ID_MCC0                                = 0x2b,
4646	DBG_BLOCK_ID_MCC1                                = 0x2c,
4647	DBG_BLOCK_ID_MCC2                                = 0x2d,
4648	DBG_BLOCK_ID_MCC3                                = 0x2e,
4649	DBG_BLOCK_ID_SXS0                                = 0x2f,
4650	DBG_BLOCK_ID_SXS1                                = 0x30,
4651	DBG_BLOCK_ID_SXS2                                = 0x31,
4652	DBG_BLOCK_ID_SXS3                                = 0x32,
4653	DBG_BLOCK_ID_SXS4                                = 0x33,
4654	DBG_BLOCK_ID_SXS5                                = 0x34,
4655	DBG_BLOCK_ID_SXS6                                = 0x35,
4656	DBG_BLOCK_ID_SXS7                                = 0x36,
4657	DBG_BLOCK_ID_SXS8                                = 0x37,
4658	DBG_BLOCK_ID_SXS9                                = 0x38,
4659	DBG_BLOCK_ID_BCI0                                = 0x39,
4660	DBG_BLOCK_ID_BCI1                                = 0x3a,
4661	DBG_BLOCK_ID_BCI2                                = 0x3b,
4662	DBG_BLOCK_ID_BCI3                                = 0x3c,
4663	DBG_BLOCK_ID_MCB                                 = 0x3d,
4664	DBG_BLOCK_ID_UNUSED6                             = 0x3e,
4665	DBG_BLOCK_ID_SQA00                               = 0x3f,
4666	DBG_BLOCK_ID_SQA01                               = 0x40,
4667	DBG_BLOCK_ID_SQA02                               = 0x41,
4668	DBG_BLOCK_ID_SQA10                               = 0x42,
4669	DBG_BLOCK_ID_SQA11                               = 0x43,
4670	DBG_BLOCK_ID_SQA12                               = 0x44,
4671	DBG_BLOCK_ID_UNUSED7                             = 0x45,
4672	DBG_BLOCK_ID_UNUSED8                             = 0x46,
4673	DBG_BLOCK_ID_SQB00                               = 0x47,
4674	DBG_BLOCK_ID_SQB01                               = 0x48,
4675	DBG_BLOCK_ID_SQB10                               = 0x49,
4676	DBG_BLOCK_ID_SQB11                               = 0x4a,
4677	DBG_BLOCK_ID_SQ00                                = 0x4b,
4678	DBG_BLOCK_ID_SQ01                                = 0x4c,
4679	DBG_BLOCK_ID_SQ10                                = 0x4d,
4680	DBG_BLOCK_ID_SQ11                                = 0x4e,
4681	DBG_BLOCK_ID_CB00                                = 0x4f,
4682	DBG_BLOCK_ID_CB01                                = 0x50,
4683	DBG_BLOCK_ID_CB02                                = 0x51,
4684	DBG_BLOCK_ID_CB03                                = 0x52,
4685	DBG_BLOCK_ID_CB04                                = 0x53,
4686	DBG_BLOCK_ID_UNUSED9                             = 0x54,
4687	DBG_BLOCK_ID_UNUSED10                            = 0x55,
4688	DBG_BLOCK_ID_UNUSED11                            = 0x56,
4689	DBG_BLOCK_ID_CB10                                = 0x57,
4690	DBG_BLOCK_ID_CB11                                = 0x58,
4691	DBG_BLOCK_ID_CB12                                = 0x59,
4692	DBG_BLOCK_ID_CB13                                = 0x5a,
4693	DBG_BLOCK_ID_CB14                                = 0x5b,
4694	DBG_BLOCK_ID_UNUSED12                            = 0x5c,
4695	DBG_BLOCK_ID_UNUSED13                            = 0x5d,
4696	DBG_BLOCK_ID_UNUSED14                            = 0x5e,
4697	DBG_BLOCK_ID_TCP0                                = 0x5f,
4698	DBG_BLOCK_ID_TCP1                                = 0x60,
4699	DBG_BLOCK_ID_TCP2                                = 0x61,
4700	DBG_BLOCK_ID_TCP3                                = 0x62,
4701	DBG_BLOCK_ID_TCP4                                = 0x63,
4702	DBG_BLOCK_ID_TCP5                                = 0x64,
4703	DBG_BLOCK_ID_TCP6                                = 0x65,
4704	DBG_BLOCK_ID_TCP7                                = 0x66,
4705	DBG_BLOCK_ID_TCP8                                = 0x67,
4706	DBG_BLOCK_ID_TCP9                                = 0x68,
4707	DBG_BLOCK_ID_TCP10                               = 0x69,
4708	DBG_BLOCK_ID_TCP11                               = 0x6a,
4709	DBG_BLOCK_ID_TCP12                               = 0x6b,
4710	DBG_BLOCK_ID_TCP13                               = 0x6c,
4711	DBG_BLOCK_ID_TCP14                               = 0x6d,
4712	DBG_BLOCK_ID_TCP15                               = 0x6e,
4713	DBG_BLOCK_ID_TCP16                               = 0x6f,
4714	DBG_BLOCK_ID_TCP17                               = 0x70,
4715	DBG_BLOCK_ID_TCP18                               = 0x71,
4716	DBG_BLOCK_ID_TCP19                               = 0x72,
4717	DBG_BLOCK_ID_TCP20                               = 0x73,
4718	DBG_BLOCK_ID_TCP21                               = 0x74,
4719	DBG_BLOCK_ID_TCP22                               = 0x75,
4720	DBG_BLOCK_ID_TCP23                               = 0x76,
4721	DBG_BLOCK_ID_TCP_RESERVED0                       = 0x77,
4722	DBG_BLOCK_ID_TCP_RESERVED1                       = 0x78,
4723	DBG_BLOCK_ID_TCP_RESERVED2                       = 0x79,
4724	DBG_BLOCK_ID_TCP_RESERVED3                       = 0x7a,
4725	DBG_BLOCK_ID_TCP_RESERVED4                       = 0x7b,
4726	DBG_BLOCK_ID_TCP_RESERVED5                       = 0x7c,
4727	DBG_BLOCK_ID_TCP_RESERVED6                       = 0x7d,
4728	DBG_BLOCK_ID_TCP_RESERVED7                       = 0x7e,
4729	DBG_BLOCK_ID_DB00                                = 0x7f,
4730	DBG_BLOCK_ID_DB01                                = 0x80,
4731	DBG_BLOCK_ID_DB02                                = 0x81,
4732	DBG_BLOCK_ID_DB03                                = 0x82,
4733	DBG_BLOCK_ID_DB04                                = 0x83,
4734	DBG_BLOCK_ID_UNUSED15                            = 0x84,
4735	DBG_BLOCK_ID_UNUSED16                            = 0x85,
4736	DBG_BLOCK_ID_UNUSED17                            = 0x86,
4737	DBG_BLOCK_ID_DB10                                = 0x87,
4738	DBG_BLOCK_ID_DB11                                = 0x88,
4739	DBG_BLOCK_ID_DB12                                = 0x89,
4740	DBG_BLOCK_ID_DB13                                = 0x8a,
4741	DBG_BLOCK_ID_DB14                                = 0x8b,
4742	DBG_BLOCK_ID_UNUSED18                            = 0x8c,
4743	DBG_BLOCK_ID_UNUSED19                            = 0x8d,
4744	DBG_BLOCK_ID_UNUSED20                            = 0x8e,
4745	DBG_BLOCK_ID_TCC0                                = 0x8f,
4746	DBG_BLOCK_ID_TCC1                                = 0x90,
4747	DBG_BLOCK_ID_TCC2                                = 0x91,
4748	DBG_BLOCK_ID_TCC3                                = 0x92,
4749	DBG_BLOCK_ID_TCC4                                = 0x93,
4750	DBG_BLOCK_ID_TCC5                                = 0x94,
4751	DBG_BLOCK_ID_TCC6                                = 0x95,
4752	DBG_BLOCK_ID_TCC7                                = 0x96,
4753	DBG_BLOCK_ID_SPS00                               = 0x97,
4754	DBG_BLOCK_ID_SPS01                               = 0x98,
4755	DBG_BLOCK_ID_SPS02                               = 0x99,
4756	DBG_BLOCK_ID_SPS10                               = 0x9a,
4757	DBG_BLOCK_ID_SPS11                               = 0x9b,
4758	DBG_BLOCK_ID_SPS12                               = 0x9c,
4759	DBG_BLOCK_ID_UNUSED21                            = 0x9d,
4760	DBG_BLOCK_ID_UNUSED22                            = 0x9e,
4761	DBG_BLOCK_ID_TA00                                = 0x9f,
4762	DBG_BLOCK_ID_TA01                                = 0xa0,
4763	DBG_BLOCK_ID_TA02                                = 0xa1,
4764	DBG_BLOCK_ID_TA03                                = 0xa2,
4765	DBG_BLOCK_ID_TA04                                = 0xa3,
4766	DBG_BLOCK_ID_TA05                                = 0xa4,
4767	DBG_BLOCK_ID_TA06                                = 0xa5,
4768	DBG_BLOCK_ID_TA07                                = 0xa6,
4769	DBG_BLOCK_ID_TA08                                = 0xa7,
4770	DBG_BLOCK_ID_TA09                                = 0xa8,
4771	DBG_BLOCK_ID_TA0A                                = 0xa9,
4772	DBG_BLOCK_ID_TA0B                                = 0xaa,
4773	DBG_BLOCK_ID_UNUSED23                            = 0xab,
4774	DBG_BLOCK_ID_UNUSED24                            = 0xac,
4775	DBG_BLOCK_ID_UNUSED25                            = 0xad,
4776	DBG_BLOCK_ID_UNUSED26                            = 0xae,
4777	DBG_BLOCK_ID_TA10                                = 0xaf,
4778	DBG_BLOCK_ID_TA11                                = 0xb0,
4779	DBG_BLOCK_ID_TA12                                = 0xb1,
4780	DBG_BLOCK_ID_TA13                                = 0xb2,
4781	DBG_BLOCK_ID_TA14                                = 0xb3,
4782	DBG_BLOCK_ID_TA15                                = 0xb4,
4783	DBG_BLOCK_ID_TA16                                = 0xb5,
4784	DBG_BLOCK_ID_TA17                                = 0xb6,
4785	DBG_BLOCK_ID_TA18                                = 0xb7,
4786	DBG_BLOCK_ID_TA19                                = 0xb8,
4787	DBG_BLOCK_ID_TA1A                                = 0xb9,
4788	DBG_BLOCK_ID_TA1B                                = 0xba,
4789	DBG_BLOCK_ID_UNUSED27                            = 0xbb,
4790	DBG_BLOCK_ID_UNUSED28                            = 0xbc,
4791	DBG_BLOCK_ID_UNUSED29                            = 0xbd,
4792	DBG_BLOCK_ID_UNUSED30                            = 0xbe,
4793	DBG_BLOCK_ID_TD00                                = 0xbf,
4794	DBG_BLOCK_ID_TD01                                = 0xc0,
4795	DBG_BLOCK_ID_TD02                                = 0xc1,
4796	DBG_BLOCK_ID_TD03                                = 0xc2,
4797	DBG_BLOCK_ID_TD04                                = 0xc3,
4798	DBG_BLOCK_ID_TD05                                = 0xc4,
4799	DBG_BLOCK_ID_TD06                                = 0xc5,
4800	DBG_BLOCK_ID_TD07                                = 0xc6,
4801	DBG_BLOCK_ID_TD08                                = 0xc7,
4802	DBG_BLOCK_ID_TD09                                = 0xc8,
4803	DBG_BLOCK_ID_TD0A                                = 0xc9,
4804	DBG_BLOCK_ID_TD0B                                = 0xca,
4805	DBG_BLOCK_ID_UNUSED31                            = 0xcb,
4806	DBG_BLOCK_ID_UNUSED32                            = 0xcc,
4807	DBG_BLOCK_ID_UNUSED33                            = 0xcd,
4808	DBG_BLOCK_ID_UNUSED34                            = 0xce,
4809	DBG_BLOCK_ID_TD10                                = 0xcf,
4810	DBG_BLOCK_ID_TD11                                = 0xd0,
4811	DBG_BLOCK_ID_TD12                                = 0xd1,
4812	DBG_BLOCK_ID_TD13                                = 0xd2,
4813	DBG_BLOCK_ID_TD14                                = 0xd3,
4814	DBG_BLOCK_ID_TD15                                = 0xd4,
4815	DBG_BLOCK_ID_TD16                                = 0xd5,
4816	DBG_BLOCK_ID_TD17                                = 0xd6,
4817	DBG_BLOCK_ID_TD18                                = 0xd7,
4818	DBG_BLOCK_ID_TD19                                = 0xd8,
4819	DBG_BLOCK_ID_TD1A                                = 0xd9,
4820	DBG_BLOCK_ID_TD1B                                = 0xda,
4821	DBG_BLOCK_ID_UNUSED35                            = 0xdb,
4822	DBG_BLOCK_ID_UNUSED36                            = 0xdc,
4823	DBG_BLOCK_ID_UNUSED37                            = 0xdd,
4824	DBG_BLOCK_ID_UNUSED38                            = 0xde,
4825	DBG_BLOCK_ID_LDS00                               = 0xdf,
4826	DBG_BLOCK_ID_LDS01                               = 0xe0,
4827	DBG_BLOCK_ID_LDS02                               = 0xe1,
4828	DBG_BLOCK_ID_LDS03                               = 0xe2,
4829	DBG_BLOCK_ID_LDS04                               = 0xe3,
4830	DBG_BLOCK_ID_LDS05                               = 0xe4,
4831	DBG_BLOCK_ID_LDS06                               = 0xe5,
4832	DBG_BLOCK_ID_LDS07                               = 0xe6,
4833	DBG_BLOCK_ID_LDS08                               = 0xe7,
4834	DBG_BLOCK_ID_LDS09                               = 0xe8,
4835	DBG_BLOCK_ID_LDS0A                               = 0xe9,
4836	DBG_BLOCK_ID_LDS0B                               = 0xea,
4837	DBG_BLOCK_ID_UNUSED39                            = 0xeb,
4838	DBG_BLOCK_ID_UNUSED40                            = 0xec,
4839	DBG_BLOCK_ID_UNUSED41                            = 0xed,
4840	DBG_BLOCK_ID_UNUSED42                            = 0xee,
4841	DBG_BLOCK_ID_LDS10                               = 0xef,
4842	DBG_BLOCK_ID_LDS11                               = 0xf0,
4843	DBG_BLOCK_ID_LDS12                               = 0xf1,
4844	DBG_BLOCK_ID_LDS13                               = 0xf2,
4845	DBG_BLOCK_ID_LDS14                               = 0xf3,
4846	DBG_BLOCK_ID_LDS15                               = 0xf4,
4847	DBG_BLOCK_ID_LDS16                               = 0xf5,
4848	DBG_BLOCK_ID_LDS17                               = 0xf6,
4849	DBG_BLOCK_ID_LDS18                               = 0xf7,
4850	DBG_BLOCK_ID_LDS19                               = 0xf8,
4851	DBG_BLOCK_ID_LDS1A                               = 0xf9,
4852	DBG_BLOCK_ID_LDS1B                               = 0xfa,
4853	DBG_BLOCK_ID_UNUSED43                            = 0xfb,
4854	DBG_BLOCK_ID_UNUSED44                            = 0xfc,
4855	DBG_BLOCK_ID_UNUSED45                            = 0xfd,
4856	DBG_BLOCK_ID_UNUSED46                            = 0xfe,
4857} DebugBlockId;
4858typedef enum DebugBlockId_BY2 {
4859	DBG_BLOCK_ID_RESERVED_BY2                        = 0x0,
4860	DBG_BLOCK_ID_VMC_BY2                             = 0x1,
4861	DBG_BLOCK_ID_UNUSED0_BY2                         = 0x2,
4862	DBG_BLOCK_ID_GRBM_BY2                            = 0x3,
4863	DBG_BLOCK_ID_CSC_BY2                             = 0x4,
4864	DBG_BLOCK_ID_IH_BY2                              = 0x5,
4865	DBG_BLOCK_ID_SQ_BY2                              = 0x6,
4866	DBG_BLOCK_ID_UVD_BY2                             = 0x7,
4867	DBG_BLOCK_ID_SDMA0_BY2                           = 0x8,
4868	DBG_BLOCK_ID_SPIM_BY2                            = 0x9,
4869	DBG_BLOCK_ID_VC0_BY2                             = 0xa,
4870	DBG_BLOCK_ID_PA_BY2                              = 0xb,
4871	DBG_BLOCK_ID_CP0_BY2                             = 0xc,
4872	DBG_BLOCK_ID_CP2_BY2                             = 0xd,
4873	DBG_BLOCK_ID_PC0_BY2                             = 0xe,
4874	DBG_BLOCK_ID_BCI0_BY2                            = 0xf,
4875	DBG_BLOCK_ID_SXM0_BY2                            = 0x10,
4876	DBG_BLOCK_ID_SCT0_BY2                            = 0x11,
4877	DBG_BLOCK_ID_SPM0_BY2                            = 0x12,
4878	DBG_BLOCK_ID_BCI2_BY2                            = 0x13,
4879	DBG_BLOCK_ID_TCA_BY2                             = 0x14,
4880	DBG_BLOCK_ID_TCCA_BY2                            = 0x15,
4881	DBG_BLOCK_ID_MCC_BY2                             = 0x16,
4882	DBG_BLOCK_ID_MCC2_BY2                            = 0x17,
4883	DBG_BLOCK_ID_MCD_BY2                             = 0x18,
4884	DBG_BLOCK_ID_MCD2_BY2                            = 0x19,
4885	DBG_BLOCK_ID_MCD4_BY2                            = 0x1a,
4886	DBG_BLOCK_ID_MCB_BY2                             = 0x1b,
4887	DBG_BLOCK_ID_SQA_BY2                             = 0x1c,
4888	DBG_BLOCK_ID_SQA02_BY2                           = 0x1d,
4889	DBG_BLOCK_ID_SQA11_BY2                           = 0x1e,
4890	DBG_BLOCK_ID_UNUSED8_BY2                         = 0x1f,
4891	DBG_BLOCK_ID_SQB_BY2                             = 0x20,
4892	DBG_BLOCK_ID_SQB10_BY2                           = 0x21,
4893	DBG_BLOCK_ID_UNUSED10_BY2                        = 0x22,
4894	DBG_BLOCK_ID_UNUSED12_BY2                        = 0x23,
4895	DBG_BLOCK_ID_CB_BY2                              = 0x24,
4896	DBG_BLOCK_ID_CB02_BY2                            = 0x25,
4897	DBG_BLOCK_ID_CB10_BY2                            = 0x26,
4898	DBG_BLOCK_ID_CB12_BY2                            = 0x27,
4899	DBG_BLOCK_ID_SXS_BY2                             = 0x28,
4900	DBG_BLOCK_ID_SXS2_BY2                            = 0x29,
4901	DBG_BLOCK_ID_SXS4_BY2                            = 0x2a,
4902	DBG_BLOCK_ID_SXS6_BY2                            = 0x2b,
4903	DBG_BLOCK_ID_DB_BY2                              = 0x2c,
4904	DBG_BLOCK_ID_DB02_BY2                            = 0x2d,
4905	DBG_BLOCK_ID_DB10_BY2                            = 0x2e,
4906	DBG_BLOCK_ID_DB12_BY2                            = 0x2f,
4907	DBG_BLOCK_ID_TCP_BY2                             = 0x30,
4908	DBG_BLOCK_ID_TCP2_BY2                            = 0x31,
4909	DBG_BLOCK_ID_TCP4_BY2                            = 0x32,
4910	DBG_BLOCK_ID_TCP6_BY2                            = 0x33,
4911	DBG_BLOCK_ID_TCP8_BY2                            = 0x34,
4912	DBG_BLOCK_ID_TCP10_BY2                           = 0x35,
4913	DBG_BLOCK_ID_TCP12_BY2                           = 0x36,
4914	DBG_BLOCK_ID_TCP14_BY2                           = 0x37,
4915	DBG_BLOCK_ID_TCP16_BY2                           = 0x38,
4916	DBG_BLOCK_ID_TCP18_BY2                           = 0x39,
4917	DBG_BLOCK_ID_TCP20_BY2                           = 0x3a,
4918	DBG_BLOCK_ID_TCP22_BY2                           = 0x3b,
4919	DBG_BLOCK_ID_TCP_RESERVED0_BY2                   = 0x3c,
4920	DBG_BLOCK_ID_TCP_RESERVED2_BY2                   = 0x3d,
4921	DBG_BLOCK_ID_TCP_RESERVED4_BY2                   = 0x3e,
4922	DBG_BLOCK_ID_TCP_RESERVED6_BY2                   = 0x3f,
4923	DBG_BLOCK_ID_TCC_BY2                             = 0x40,
4924	DBG_BLOCK_ID_TCC2_BY2                            = 0x41,
4925	DBG_BLOCK_ID_TCC4_BY2                            = 0x42,
4926	DBG_BLOCK_ID_TCC6_BY2                            = 0x43,
4927	DBG_BLOCK_ID_SPS_BY2                             = 0x44,
4928	DBG_BLOCK_ID_SPS02_BY2                           = 0x45,
4929	DBG_BLOCK_ID_SPS11_BY2                           = 0x46,
4930	DBG_BLOCK_ID_UNUSED14_BY2                        = 0x47,
4931	DBG_BLOCK_ID_TA_BY2                              = 0x48,
4932	DBG_BLOCK_ID_TA02_BY2                            = 0x49,
4933	DBG_BLOCK_ID_TA04_BY2                            = 0x4a,
4934	DBG_BLOCK_ID_TA06_BY2                            = 0x4b,
4935	DBG_BLOCK_ID_TA08_BY2                            = 0x4c,
4936	DBG_BLOCK_ID_TA0A_BY2                            = 0x4d,
4937	DBG_BLOCK_ID_UNUSED20_BY2                        = 0x4e,
4938	DBG_BLOCK_ID_UNUSED22_BY2                        = 0x4f,
4939	DBG_BLOCK_ID_TA10_BY2                            = 0x50,
4940	DBG_BLOCK_ID_TA12_BY2                            = 0x51,
4941	DBG_BLOCK_ID_TA14_BY2                            = 0x52,
4942	DBG_BLOCK_ID_TA16_BY2                            = 0x53,
4943	DBG_BLOCK_ID_TA18_BY2                            = 0x54,
4944	DBG_BLOCK_ID_TA1A_BY2                            = 0x55,
4945	DBG_BLOCK_ID_UNUSED24_BY2                        = 0x56,
4946	DBG_BLOCK_ID_UNUSED26_BY2                        = 0x57,
4947	DBG_BLOCK_ID_TD_BY2                              = 0x58,
4948	DBG_BLOCK_ID_TD02_BY2                            = 0x59,
4949	DBG_BLOCK_ID_TD04_BY2                            = 0x5a,
4950	DBG_BLOCK_ID_TD06_BY2                            = 0x5b,
4951	DBG_BLOCK_ID_TD08_BY2                            = 0x5c,
4952	DBG_BLOCK_ID_TD0A_BY2                            = 0x5d,
4953	DBG_BLOCK_ID_UNUSED28_BY2                        = 0x5e,
4954	DBG_BLOCK_ID_UNUSED30_BY2                        = 0x5f,
4955	DBG_BLOCK_ID_TD10_BY2                            = 0x60,
4956	DBG_BLOCK_ID_TD12_BY2                            = 0x61,
4957	DBG_BLOCK_ID_TD14_BY2                            = 0x62,
4958	DBG_BLOCK_ID_TD16_BY2                            = 0x63,
4959	DBG_BLOCK_ID_TD18_BY2                            = 0x64,
4960	DBG_BLOCK_ID_TD1A_BY2                            = 0x65,
4961	DBG_BLOCK_ID_UNUSED32_BY2                        = 0x66,
4962	DBG_BLOCK_ID_UNUSED34_BY2                        = 0x67,
4963	DBG_BLOCK_ID_LDS_BY2                             = 0x68,
4964	DBG_BLOCK_ID_LDS02_BY2                           = 0x69,
4965	DBG_BLOCK_ID_LDS04_BY2                           = 0x6a,
4966	DBG_BLOCK_ID_LDS06_BY2                           = 0x6b,
4967	DBG_BLOCK_ID_LDS08_BY2                           = 0x6c,
4968	DBG_BLOCK_ID_LDS0A_BY2                           = 0x6d,
4969	DBG_BLOCK_ID_UNUSED36_BY2                        = 0x6e,
4970	DBG_BLOCK_ID_UNUSED38_BY2                        = 0x6f,
4971	DBG_BLOCK_ID_LDS10_BY2                           = 0x70,
4972	DBG_BLOCK_ID_LDS12_BY2                           = 0x71,
4973	DBG_BLOCK_ID_LDS14_BY2                           = 0x72,
4974	DBG_BLOCK_ID_LDS16_BY2                           = 0x73,
4975	DBG_BLOCK_ID_LDS18_BY2                           = 0x74,
4976	DBG_BLOCK_ID_LDS1A_BY2                           = 0x75,
4977	DBG_BLOCK_ID_UNUSED40_BY2                        = 0x76,
4978	DBG_BLOCK_ID_UNUSED42_BY2                        = 0x77,
4979} DebugBlockId_BY2;
4980typedef enum DebugBlockId_BY4 {
4981	DBG_BLOCK_ID_RESERVED_BY4                        = 0x0,
4982	DBG_BLOCK_ID_UNUSED0_BY4                         = 0x1,
4983	DBG_BLOCK_ID_CSC_BY4                             = 0x2,
4984	DBG_BLOCK_ID_SQ_BY4                              = 0x3,
4985	DBG_BLOCK_ID_SDMA0_BY4                           = 0x4,
4986	DBG_BLOCK_ID_VC0_BY4                             = 0x5,
4987	DBG_BLOCK_ID_CP0_BY4                             = 0x6,
4988	DBG_BLOCK_ID_UNUSED1_BY4                         = 0x7,
4989	DBG_BLOCK_ID_SXM0_BY4                            = 0x8,
4990	DBG_BLOCK_ID_SPM0_BY4                            = 0x9,
4991	DBG_BLOCK_ID_TCAA_BY4                            = 0xa,
4992	DBG_BLOCK_ID_MCC_BY4                             = 0xb,
4993	DBG_BLOCK_ID_MCD_BY4                             = 0xc,
4994	DBG_BLOCK_ID_MCD4_BY4                            = 0xd,
4995	DBG_BLOCK_ID_SQA_BY4                             = 0xe,
4996	DBG_BLOCK_ID_SQA11_BY4                           = 0xf,
4997	DBG_BLOCK_ID_SQB_BY4                             = 0x10,
4998	DBG_BLOCK_ID_UNUSED10_BY4                        = 0x11,
4999	DBG_BLOCK_ID_CB_BY4                              = 0x12,
5000	DBG_BLOCK_ID_CB10_BY4                            = 0x13,
5001	DBG_BLOCK_ID_SXS_BY4                             = 0x14,
5002	DBG_BLOCK_ID_SXS4_BY4                            = 0x15,
5003	DBG_BLOCK_ID_DB_BY4                              = 0x16,
5004	DBG_BLOCK_ID_DB10_BY4                            = 0x17,
5005	DBG_BLOCK_ID_TCP_BY4                             = 0x18,
5006	DBG_BLOCK_ID_TCP4_BY4                            = 0x19,
5007	DBG_BLOCK_ID_TCP8_BY4                            = 0x1a,
5008	DBG_BLOCK_ID_TCP12_BY4                           = 0x1b,
5009	DBG_BLOCK_ID_TCP16_BY4                           = 0x1c,
5010	DBG_BLOCK_ID_TCP20_BY4                           = 0x1d,
5011	DBG_BLOCK_ID_TCP_RESERVED0_BY4                   = 0x1e,
5012	DBG_BLOCK_ID_TCP_RESERVED4_BY4                   = 0x1f,
5013	DBG_BLOCK_ID_TCC_BY4                             = 0x20,
5014	DBG_BLOCK_ID_TCC4_BY4                            = 0x21,
5015	DBG_BLOCK_ID_SPS_BY4                             = 0x22,
5016	DBG_BLOCK_ID_SPS11_BY4                           = 0x23,
5017	DBG_BLOCK_ID_TA_BY4                              = 0x24,
5018	DBG_BLOCK_ID_TA04_BY4                            = 0x25,
5019	DBG_BLOCK_ID_TA08_BY4                            = 0x26,
5020	DBG_BLOCK_ID_UNUSED20_BY4                        = 0x27,
5021	DBG_BLOCK_ID_TA10_BY4                            = 0x28,
5022	DBG_BLOCK_ID_TA14_BY4                            = 0x29,
5023	DBG_BLOCK_ID_TA18_BY4                            = 0x2a,
5024	DBG_BLOCK_ID_UNUSED24_BY4                        = 0x2b,
5025	DBG_BLOCK_ID_TD_BY4                              = 0x2c,
5026	DBG_BLOCK_ID_TD04_BY4                            = 0x2d,
5027	DBG_BLOCK_ID_TD08_BY4                            = 0x2e,
5028	DBG_BLOCK_ID_UNUSED28_BY4                        = 0x2f,
5029	DBG_BLOCK_ID_TD10_BY4                            = 0x30,
5030	DBG_BLOCK_ID_TD14_BY4                            = 0x31,
5031	DBG_BLOCK_ID_TD18_BY4                            = 0x32,
5032	DBG_BLOCK_ID_UNUSED32_BY4                        = 0x33,
5033	DBG_BLOCK_ID_LDS_BY4                             = 0x34,
5034	DBG_BLOCK_ID_LDS04_BY4                           = 0x35,
5035	DBG_BLOCK_ID_LDS08_BY4                           = 0x36,
5036	DBG_BLOCK_ID_UNUSED36_BY4                        = 0x37,
5037	DBG_BLOCK_ID_LDS10_BY4                           = 0x38,
5038	DBG_BLOCK_ID_LDS14_BY4                           = 0x39,
5039	DBG_BLOCK_ID_LDS18_BY4                           = 0x3a,
5040	DBG_BLOCK_ID_UNUSED40_BY4                        = 0x3b,
5041} DebugBlockId_BY4;
5042typedef enum DebugBlockId_BY8 {
5043	DBG_BLOCK_ID_RESERVED_BY8                        = 0x0,
5044	DBG_BLOCK_ID_CSC_BY8                             = 0x1,
5045	DBG_BLOCK_ID_SDMA0_BY8                           = 0x2,
5046	DBG_BLOCK_ID_CP0_BY8                             = 0x3,
5047	DBG_BLOCK_ID_SXM0_BY8                            = 0x4,
5048	DBG_BLOCK_ID_TCA_BY8                             = 0x5,
5049	DBG_BLOCK_ID_MCD_BY8                             = 0x6,
5050	DBG_BLOCK_ID_SQA_BY8                             = 0x7,
5051	DBG_BLOCK_ID_SQB_BY8                             = 0x8,
5052	DBG_BLOCK_ID_CB_BY8                              = 0x9,
5053	DBG_BLOCK_ID_SXS_BY8                             = 0xa,
5054	DBG_BLOCK_ID_DB_BY8                              = 0xb,
5055	DBG_BLOCK_ID_TCP_BY8                             = 0xc,
5056	DBG_BLOCK_ID_TCP8_BY8                            = 0xd,
5057	DBG_BLOCK_ID_TCP16_BY8                           = 0xe,
5058	DBG_BLOCK_ID_TCP_RESERVED0_BY8                   = 0xf,
5059	DBG_BLOCK_ID_TCC_BY8                             = 0x10,
5060	DBG_BLOCK_ID_SPS_BY8                             = 0x11,
5061	DBG_BLOCK_ID_TA_BY8                              = 0x12,
5062	DBG_BLOCK_ID_TA08_BY8                            = 0x13,
5063	DBG_BLOCK_ID_TA10_BY8                            = 0x14,
5064	DBG_BLOCK_ID_TA18_BY8                            = 0x15,
5065	DBG_BLOCK_ID_TD_BY8                              = 0x16,
5066	DBG_BLOCK_ID_TD08_BY8                            = 0x17,
5067	DBG_BLOCK_ID_TD10_BY8                            = 0x18,
5068	DBG_BLOCK_ID_TD18_BY8                            = 0x19,
5069	DBG_BLOCK_ID_LDS_BY8                             = 0x1a,
5070	DBG_BLOCK_ID_LDS08_BY8                           = 0x1b,
5071	DBG_BLOCK_ID_LDS10_BY8                           = 0x1c,
5072	DBG_BLOCK_ID_LDS18_BY8                           = 0x1d,
5073} DebugBlockId_BY8;
5074typedef enum DebugBlockId_BY16 {
5075	DBG_BLOCK_ID_RESERVED_BY16                       = 0x0,
5076	DBG_BLOCK_ID_SDMA0_BY16                          = 0x1,
5077	DBG_BLOCK_ID_SXM_BY16                            = 0x2,
5078	DBG_BLOCK_ID_MCD_BY16                            = 0x3,
5079	DBG_BLOCK_ID_SQB_BY16                            = 0x4,
5080	DBG_BLOCK_ID_SXS_BY16                            = 0x5,
5081	DBG_BLOCK_ID_TCP_BY16                            = 0x6,
5082	DBG_BLOCK_ID_TCP16_BY16                          = 0x7,
5083	DBG_BLOCK_ID_TCC_BY16                            = 0x8,
5084	DBG_BLOCK_ID_TA_BY16                             = 0x9,
5085	DBG_BLOCK_ID_TA10_BY16                           = 0xa,
5086	DBG_BLOCK_ID_TD_BY16                             = 0xb,
5087	DBG_BLOCK_ID_TD10_BY16                           = 0xc,
5088	DBG_BLOCK_ID_LDS_BY16                            = 0xd,
5089	DBG_BLOCK_ID_LDS10_BY16                          = 0xe,
5090} DebugBlockId_BY16;
5091typedef enum SurfaceEndian {
5092	ENDIAN_NONE                                      = 0x0,
5093	ENDIAN_8IN16                                     = 0x1,
5094	ENDIAN_8IN32                                     = 0x2,
5095	ENDIAN_8IN64                                     = 0x3,
5096} SurfaceEndian;
5097typedef enum ArrayMode {
5098	ARRAY_LINEAR_GENERAL                             = 0x0,
5099	ARRAY_LINEAR_ALIGNED                             = 0x1,
5100	ARRAY_1D_TILED_THIN1                             = 0x2,
5101	ARRAY_1D_TILED_THICK                             = 0x3,
5102	ARRAY_2D_TILED_THIN1                             = 0x4,
5103	ARRAY_PRT_TILED_THIN1                            = 0x5,
5104	ARRAY_PRT_2D_TILED_THIN1                         = 0x6,
5105	ARRAY_2D_TILED_THICK                             = 0x7,
5106	ARRAY_2D_TILED_XTHICK                            = 0x8,
5107	ARRAY_PRT_TILED_THICK                            = 0x9,
5108	ARRAY_PRT_2D_TILED_THICK                         = 0xa,
5109	ARRAY_PRT_3D_TILED_THIN1                         = 0xb,
5110	ARRAY_3D_TILED_THIN1                             = 0xc,
5111	ARRAY_3D_TILED_THICK                             = 0xd,
5112	ARRAY_3D_TILED_XTHICK                            = 0xe,
5113	ARRAY_PRT_3D_TILED_THICK                         = 0xf,
5114} ArrayMode;
5115typedef enum PipeTiling {
5116	CONFIG_1_PIPE                                    = 0x0,
5117	CONFIG_2_PIPE                                    = 0x1,
5118	CONFIG_4_PIPE                                    = 0x2,
5119	CONFIG_8_PIPE                                    = 0x3,
5120} PipeTiling;
5121typedef enum BankTiling {
5122	CONFIG_4_BANK                                    = 0x0,
5123	CONFIG_8_BANK                                    = 0x1,
5124} BankTiling;
5125typedef enum GroupInterleave {
5126	CONFIG_256B_GROUP                                = 0x0,
5127	CONFIG_512B_GROUP                                = 0x1,
5128} GroupInterleave;
5129typedef enum RowTiling {
5130	CONFIG_1KB_ROW                                   = 0x0,
5131	CONFIG_2KB_ROW                                   = 0x1,
5132	CONFIG_4KB_ROW                                   = 0x2,
5133	CONFIG_8KB_ROW                                   = 0x3,
5134	CONFIG_1KB_ROW_OPT                               = 0x4,
5135	CONFIG_2KB_ROW_OPT                               = 0x5,
5136	CONFIG_4KB_ROW_OPT                               = 0x6,
5137	CONFIG_8KB_ROW_OPT                               = 0x7,
5138} RowTiling;
5139typedef enum BankSwapBytes {
5140	CONFIG_128B_SWAPS                                = 0x0,
5141	CONFIG_256B_SWAPS                                = 0x1,
5142	CONFIG_512B_SWAPS                                = 0x2,
5143	CONFIG_1KB_SWAPS                                 = 0x3,
5144} BankSwapBytes;
5145typedef enum SampleSplitBytes {
5146	CONFIG_1KB_SPLIT                                 = 0x0,
5147	CONFIG_2KB_SPLIT                                 = 0x1,
5148	CONFIG_4KB_SPLIT                                 = 0x2,
5149	CONFIG_8KB_SPLIT                                 = 0x3,
5150} SampleSplitBytes;
5151typedef enum NumPipes {
5152	ADDR_CONFIG_1_PIPE                               = 0x0,
5153	ADDR_CONFIG_2_PIPE                               = 0x1,
5154	ADDR_CONFIG_4_PIPE                               = 0x2,
5155	ADDR_CONFIG_8_PIPE                               = 0x3,
5156} NumPipes;
5157typedef enum PipeInterleaveSize {
5158	ADDR_CONFIG_PIPE_INTERLEAVE_256B                 = 0x0,
5159	ADDR_CONFIG_PIPE_INTERLEAVE_512B                 = 0x1,
5160} PipeInterleaveSize;
5161typedef enum BankInterleaveSize {
5162	ADDR_CONFIG_BANK_INTERLEAVE_1                    = 0x0,
5163	ADDR_CONFIG_BANK_INTERLEAVE_2                    = 0x1,
5164	ADDR_CONFIG_BANK_INTERLEAVE_4                    = 0x2,
5165	ADDR_CONFIG_BANK_INTERLEAVE_8                    = 0x3,
5166} BankInterleaveSize;
5167typedef enum NumShaderEngines {
5168	ADDR_CONFIG_1_SHADER_ENGINE                      = 0x0,
5169	ADDR_CONFIG_2_SHADER_ENGINE                      = 0x1,
5170} NumShaderEngines;
5171typedef enum ShaderEngineTileSize {
5172	ADDR_CONFIG_SE_TILE_16                           = 0x0,
5173	ADDR_CONFIG_SE_TILE_32                           = 0x1,
5174} ShaderEngineTileSize;
5175typedef enum NumGPUs {
5176	ADDR_CONFIG_1_GPU                                = 0x0,
5177	ADDR_CONFIG_2_GPU                                = 0x1,
5178	ADDR_CONFIG_4_GPU                                = 0x2,
5179} NumGPUs;
5180typedef enum MultiGPUTileSize {
5181	ADDR_CONFIG_GPU_TILE_16                          = 0x0,
5182	ADDR_CONFIG_GPU_TILE_32                          = 0x1,
5183	ADDR_CONFIG_GPU_TILE_64                          = 0x2,
5184	ADDR_CONFIG_GPU_TILE_128                         = 0x3,
5185} MultiGPUTileSize;
5186typedef enum RowSize {
5187	ADDR_CONFIG_1KB_ROW                              = 0x0,
5188	ADDR_CONFIG_2KB_ROW                              = 0x1,
5189	ADDR_CONFIG_4KB_ROW                              = 0x2,
5190} RowSize;
5191typedef enum NumLowerPipes {
5192	ADDR_CONFIG_1_LOWER_PIPES                        = 0x0,
5193	ADDR_CONFIG_2_LOWER_PIPES                        = 0x1,
5194} NumLowerPipes;
5195typedef enum ColorTransform {
5196	DCC_CT_AUTO                                      = 0x0,
5197	DCC_CT_NONE                                      = 0x1,
5198	ABGR_TO_A_BG_G_RB                                = 0x2,
5199	BGRA_TO_BG_G_RB_A                                = 0x3,
5200} ColorTransform;
5201typedef enum CompareRef {
5202	REF_NEVER                                        = 0x0,
5203	REF_LESS                                         = 0x1,
5204	REF_EQUAL                                        = 0x2,
5205	REF_LEQUAL                                       = 0x3,
5206	REF_GREATER                                      = 0x4,
5207	REF_NOTEQUAL                                     = 0x5,
5208	REF_GEQUAL                                       = 0x6,
5209	REF_ALWAYS                                       = 0x7,
5210} CompareRef;
5211typedef enum ReadSize {
5212	READ_256_BITS                                    = 0x0,
5213	READ_512_BITS                                    = 0x1,
5214} ReadSize;
5215typedef enum DepthFormat {
5216	DEPTH_INVALID                                    = 0x0,
5217	DEPTH_16                                         = 0x1,
5218	DEPTH_X8_24                                      = 0x2,
5219	DEPTH_8_24                                       = 0x3,
5220	DEPTH_X8_24_FLOAT                                = 0x4,
5221	DEPTH_8_24_FLOAT                                 = 0x5,
5222	DEPTH_32_FLOAT                                   = 0x6,
5223	DEPTH_X24_8_32_FLOAT                             = 0x7,
5224} DepthFormat;
5225typedef enum ZFormat {
5226	Z_INVALID                                        = 0x0,
5227	Z_16                                             = 0x1,
5228	Z_24                                             = 0x2,
5229	Z_32_FLOAT                                       = 0x3,
5230} ZFormat;
5231typedef enum StencilFormat {
5232	STENCIL_INVALID                                  = 0x0,
5233	STENCIL_8                                        = 0x1,
5234} StencilFormat;
5235typedef enum CmaskMode {
5236	CMASK_CLEAR_NONE                                 = 0x0,
5237	CMASK_CLEAR_ONE                                  = 0x1,
5238	CMASK_CLEAR_ALL                                  = 0x2,
5239	CMASK_ANY_EXPANDED                               = 0x3,
5240	CMASK_ALPHA0_FRAG1                               = 0x4,
5241	CMASK_ALPHA0_FRAG2                               = 0x5,
5242	CMASK_ALPHA0_FRAG4                               = 0x6,
5243	CMASK_ALPHA0_FRAGS                               = 0x7,
5244	CMASK_ALPHA1_FRAG1                               = 0x8,
5245	CMASK_ALPHA1_FRAG2                               = 0x9,
5246	CMASK_ALPHA1_FRAG4                               = 0xa,
5247	CMASK_ALPHA1_FRAGS                               = 0xb,
5248	CMASK_ALPHAX_FRAG1                               = 0xc,
5249	CMASK_ALPHAX_FRAG2                               = 0xd,
5250	CMASK_ALPHAX_FRAG4                               = 0xe,
5251	CMASK_ALPHAX_FRAGS                               = 0xf,
5252} CmaskMode;
5253typedef enum QuadExportFormat {
5254	EXPORT_UNUSED                                    = 0x0,
5255	EXPORT_32_R                                      = 0x1,
5256	EXPORT_32_GR                                     = 0x2,
5257	EXPORT_32_AR                                     = 0x3,
5258	EXPORT_FP16_ABGR                                 = 0x4,
5259	EXPORT_UNSIGNED16_ABGR                           = 0x5,
5260	EXPORT_SIGNED16_ABGR                             = 0x6,
5261	EXPORT_32_ABGR                                   = 0x7,
5262} QuadExportFormat;
5263typedef enum QuadExportFormatOld {
5264	EXPORT_4P_32BPC_ABGR                             = 0x0,
5265	EXPORT_4P_16BPC_ABGR                             = 0x1,
5266	EXPORT_4P_32BPC_GR                               = 0x2,
5267	EXPORT_4P_32BPC_AR                               = 0x3,
5268	EXPORT_2P_32BPC_ABGR                             = 0x4,
5269	EXPORT_8P_32BPC_R                                = 0x5,
5270} QuadExportFormatOld;
5271typedef enum ColorFormat {
5272	COLOR_INVALID                                    = 0x0,
5273	COLOR_8                                          = 0x1,
5274	COLOR_16                                         = 0x2,
5275	COLOR_8_8                                        = 0x3,
5276	COLOR_32                                         = 0x4,
5277	COLOR_16_16                                      = 0x5,
5278	COLOR_10_11_11                                   = 0x6,
5279	COLOR_11_11_10                                   = 0x7,
5280	COLOR_10_10_10_2                                 = 0x8,
5281	COLOR_2_10_10_10                                 = 0x9,
5282	COLOR_8_8_8_8                                    = 0xa,
5283	COLOR_32_32                                      = 0xb,
5284	COLOR_16_16_16_16                                = 0xc,
5285	COLOR_RESERVED_13                                = 0xd,
5286	COLOR_32_32_32_32                                = 0xe,
5287	COLOR_RESERVED_15                                = 0xf,
5288	COLOR_5_6_5                                      = 0x10,
5289	COLOR_1_5_5_5                                    = 0x11,
5290	COLOR_5_5_5_1                                    = 0x12,
5291	COLOR_4_4_4_4                                    = 0x13,
5292	COLOR_8_24                                       = 0x14,
5293	COLOR_24_8                                       = 0x15,
5294	COLOR_X24_8_32_FLOAT                             = 0x16,
5295	COLOR_RESERVED_23                                = 0x17,
5296} ColorFormat;
5297typedef enum SurfaceFormat {
5298	FMT_INVALID                                      = 0x0,
5299	FMT_8                                            = 0x1,
5300	FMT_16                                           = 0x2,
5301	FMT_8_8                                          = 0x3,
5302	FMT_32                                           = 0x4,
5303	FMT_16_16                                        = 0x5,
5304	FMT_10_11_11                                     = 0x6,
5305	FMT_11_11_10                                     = 0x7,
5306	FMT_10_10_10_2                                   = 0x8,
5307	FMT_2_10_10_10                                   = 0x9,
5308	FMT_8_8_8_8                                      = 0xa,
5309	FMT_32_32                                        = 0xb,
5310	FMT_16_16_16_16                                  = 0xc,
5311	FMT_32_32_32                                     = 0xd,
5312	FMT_32_32_32_32                                  = 0xe,
5313	FMT_RESERVED_4                                   = 0xf,
5314	FMT_5_6_5                                        = 0x10,
5315	FMT_1_5_5_5                                      = 0x11,
5316	FMT_5_5_5_1                                      = 0x12,
5317	FMT_4_4_4_4                                      = 0x13,
5318	FMT_8_24                                         = 0x14,
5319	FMT_24_8                                         = 0x15,
5320	FMT_X24_8_32_FLOAT                               = 0x16,
5321	FMT_RESERVED_33                                  = 0x17,
5322	FMT_11_11_10_FLOAT                               = 0x18,
5323	FMT_16_FLOAT                                     = 0x19,
5324	FMT_32_FLOAT                                     = 0x1a,
5325	FMT_16_16_FLOAT                                  = 0x1b,
5326	FMT_8_24_FLOAT                                   = 0x1c,
5327	FMT_24_8_FLOAT                                   = 0x1d,
5328	FMT_32_32_FLOAT                                  = 0x1e,
5329	FMT_10_11_11_FLOAT                               = 0x1f,
5330	FMT_16_16_16_16_FLOAT                            = 0x20,
5331	FMT_3_3_2                                        = 0x21,
5332	FMT_6_5_5                                        = 0x22,
5333	FMT_32_32_32_32_FLOAT                            = 0x23,
5334	FMT_RESERVED_36                                  = 0x24,
5335	FMT_1                                            = 0x25,
5336	FMT_1_REVERSED                                   = 0x26,
5337	FMT_GB_GR                                        = 0x27,
5338	FMT_BG_RG                                        = 0x28,
5339	FMT_32_AS_8                                      = 0x29,
5340	FMT_32_AS_8_8                                    = 0x2a,
5341	FMT_5_9_9_9_SHAREDEXP                            = 0x2b,
5342	FMT_8_8_8                                        = 0x2c,
5343	FMT_16_16_16                                     = 0x2d,
5344	FMT_16_16_16_FLOAT                               = 0x2e,
5345	FMT_4_4                                          = 0x2f,
5346	FMT_32_32_32_FLOAT                               = 0x30,
5347	FMT_BC1                                          = 0x31,
5348	FMT_BC2                                          = 0x32,
5349	FMT_BC3                                          = 0x33,
5350	FMT_BC4                                          = 0x34,
5351	FMT_BC5                                          = 0x35,
5352	FMT_BC6                                          = 0x36,
5353	FMT_BC7                                          = 0x37,
5354	FMT_32_AS_32_32_32_32                            = 0x38,
5355	FMT_APC3                                         = 0x39,
5356	FMT_APC4                                         = 0x3a,
5357	FMT_APC5                                         = 0x3b,
5358	FMT_APC6                                         = 0x3c,
5359	FMT_APC7                                         = 0x3d,
5360	FMT_CTX1                                         = 0x3e,
5361	FMT_RESERVED_63                                  = 0x3f,
5362} SurfaceFormat;
5363typedef enum BUF_DATA_FORMAT {
5364	BUF_DATA_FORMAT_INVALID                          = 0x0,
5365	BUF_DATA_FORMAT_8                                = 0x1,
5366	BUF_DATA_FORMAT_16                               = 0x2,
5367	BUF_DATA_FORMAT_8_8                              = 0x3,
5368	BUF_DATA_FORMAT_32                               = 0x4,
5369	BUF_DATA_FORMAT_16_16                            = 0x5,
5370	BUF_DATA_FORMAT_10_11_11                         = 0x6,
5371	BUF_DATA_FORMAT_11_11_10                         = 0x7,
5372	BUF_DATA_FORMAT_10_10_10_2                       = 0x8,
5373	BUF_DATA_FORMAT_2_10_10_10                       = 0x9,
5374	BUF_DATA_FORMAT_8_8_8_8                          = 0xa,
5375	BUF_DATA_FORMAT_32_32                            = 0xb,
5376	BUF_DATA_FORMAT_16_16_16_16                      = 0xc,
5377	BUF_DATA_FORMAT_32_32_32                         = 0xd,
5378	BUF_DATA_FORMAT_32_32_32_32                      = 0xe,
5379	BUF_DATA_FORMAT_RESERVED_15                      = 0xf,
5380} BUF_DATA_FORMAT;
5381typedef enum IMG_DATA_FORMAT {
5382	IMG_DATA_FORMAT_INVALID                          = 0x0,
5383	IMG_DATA_FORMAT_8                                = 0x1,
5384	IMG_DATA_FORMAT_16                               = 0x2,
5385	IMG_DATA_FORMAT_8_8                              = 0x3,
5386	IMG_DATA_FORMAT_32                               = 0x4,
5387	IMG_DATA_FORMAT_16_16                            = 0x5,
5388	IMG_DATA_FORMAT_10_11_11                         = 0x6,
5389	IMG_DATA_FORMAT_11_11_10                         = 0x7,
5390	IMG_DATA_FORMAT_10_10_10_2                       = 0x8,
5391	IMG_DATA_FORMAT_2_10_10_10                       = 0x9,
5392	IMG_DATA_FORMAT_8_8_8_8                          = 0xa,
5393	IMG_DATA_FORMAT_32_32                            = 0xb,
5394	IMG_DATA_FORMAT_16_16_16_16                      = 0xc,
5395	IMG_DATA_FORMAT_32_32_32                         = 0xd,
5396	IMG_DATA_FORMAT_32_32_32_32                      = 0xe,
5397	IMG_DATA_FORMAT_RESERVED_15                      = 0xf,
5398	IMG_DATA_FORMAT_5_6_5                            = 0x10,
5399	IMG_DATA_FORMAT_1_5_5_5                          = 0x11,
5400	IMG_DATA_FORMAT_5_5_5_1                          = 0x12,
5401	IMG_DATA_FORMAT_4_4_4_4                          = 0x13,
5402	IMG_DATA_FORMAT_8_24                             = 0x14,
5403	IMG_DATA_FORMAT_24_8                             = 0x15,
5404	IMG_DATA_FORMAT_X24_8_32                         = 0x16,
5405	IMG_DATA_FORMAT_RESERVED_23                      = 0x17,
5406	IMG_DATA_FORMAT_RESERVED_24                      = 0x18,
5407	IMG_DATA_FORMAT_RESERVED_25                      = 0x19,
5408	IMG_DATA_FORMAT_RESERVED_26                      = 0x1a,
5409	IMG_DATA_FORMAT_RESERVED_27                      = 0x1b,
5410	IMG_DATA_FORMAT_RESERVED_28                      = 0x1c,
5411	IMG_DATA_FORMAT_RESERVED_29                      = 0x1d,
5412	IMG_DATA_FORMAT_RESERVED_30                      = 0x1e,
5413	IMG_DATA_FORMAT_RESERVED_31                      = 0x1f,
5414	IMG_DATA_FORMAT_GB_GR                            = 0x20,
5415	IMG_DATA_FORMAT_BG_RG                            = 0x21,
5416	IMG_DATA_FORMAT_5_9_9_9                          = 0x22,
5417	IMG_DATA_FORMAT_BC1                              = 0x23,
5418	IMG_DATA_FORMAT_BC2                              = 0x24,
5419	IMG_DATA_FORMAT_BC3                              = 0x25,
5420	IMG_DATA_FORMAT_BC4                              = 0x26,
5421	IMG_DATA_FORMAT_BC5                              = 0x27,
5422	IMG_DATA_FORMAT_BC6                              = 0x28,
5423	IMG_DATA_FORMAT_BC7                              = 0x29,
5424	IMG_DATA_FORMAT_RESERVED_42                      = 0x2a,
5425	IMG_DATA_FORMAT_RESERVED_43                      = 0x2b,
5426	IMG_DATA_FORMAT_FMASK8_S2_F1                     = 0x2c,
5427	IMG_DATA_FORMAT_FMASK8_S4_F1                     = 0x2d,
5428	IMG_DATA_FORMAT_FMASK8_S8_F1                     = 0x2e,
5429	IMG_DATA_FORMAT_FMASK8_S2_F2                     = 0x2f,
5430	IMG_DATA_FORMAT_FMASK8_S4_F2                     = 0x30,
5431	IMG_DATA_FORMAT_FMASK8_S4_F4                     = 0x31,
5432	IMG_DATA_FORMAT_FMASK16_S16_F1                   = 0x32,
5433	IMG_DATA_FORMAT_FMASK16_S8_F2                    = 0x33,
5434	IMG_DATA_FORMAT_FMASK32_S16_F2                   = 0x34,
5435	IMG_DATA_FORMAT_FMASK32_S8_F4                    = 0x35,
5436	IMG_DATA_FORMAT_FMASK32_S8_F8                    = 0x36,
5437	IMG_DATA_FORMAT_FMASK64_S16_F4                   = 0x37,
5438	IMG_DATA_FORMAT_FMASK64_S16_F8                   = 0x38,
5439	IMG_DATA_FORMAT_4_4                              = 0x39,
5440	IMG_DATA_FORMAT_6_5_5                            = 0x3a,
5441	IMG_DATA_FORMAT_1                                = 0x3b,
5442	IMG_DATA_FORMAT_1_REVERSED                       = 0x3c,
5443	IMG_DATA_FORMAT_32_AS_8                          = 0x3d,
5444	IMG_DATA_FORMAT_32_AS_8_8                        = 0x3e,
5445	IMG_DATA_FORMAT_32_AS_32_32_32_32                = 0x3f,
5446} IMG_DATA_FORMAT;
5447typedef enum BUF_NUM_FORMAT {
5448	BUF_NUM_FORMAT_UNORM                             = 0x0,
5449	BUF_NUM_FORMAT_SNORM                             = 0x1,
5450	BUF_NUM_FORMAT_USCALED                           = 0x2,
5451	BUF_NUM_FORMAT_SSCALED                           = 0x3,
5452	BUF_NUM_FORMAT_UINT                              = 0x4,
5453	BUF_NUM_FORMAT_SINT                              = 0x5,
5454	BUF_NUM_FORMAT_RESERVED_6                        = 0x6,
5455	BUF_NUM_FORMAT_FLOAT                             = 0x7,
5456} BUF_NUM_FORMAT;
5457typedef enum IMG_NUM_FORMAT {
5458	IMG_NUM_FORMAT_UNORM                             = 0x0,
5459	IMG_NUM_FORMAT_SNORM                             = 0x1,
5460	IMG_NUM_FORMAT_USCALED                           = 0x2,
5461	IMG_NUM_FORMAT_SSCALED                           = 0x3,
5462	IMG_NUM_FORMAT_UINT                              = 0x4,
5463	IMG_NUM_FORMAT_SINT                              = 0x5,
5464	IMG_NUM_FORMAT_RESERVED_6                        = 0x6,
5465	IMG_NUM_FORMAT_FLOAT                             = 0x7,
5466	IMG_NUM_FORMAT_RESERVED_8                        = 0x8,
5467	IMG_NUM_FORMAT_SRGB                              = 0x9,
5468	IMG_NUM_FORMAT_RESERVED_10                       = 0xa,
5469	IMG_NUM_FORMAT_RESERVED_11                       = 0xb,
5470	IMG_NUM_FORMAT_RESERVED_12                       = 0xc,
5471	IMG_NUM_FORMAT_RESERVED_13                       = 0xd,
5472	IMG_NUM_FORMAT_RESERVED_14                       = 0xe,
5473	IMG_NUM_FORMAT_RESERVED_15                       = 0xf,
5474} IMG_NUM_FORMAT;
5475typedef enum TileType {
5476	ARRAY_COLOR_TILE                                 = 0x0,
5477	ARRAY_DEPTH_TILE                                 = 0x1,
5478} TileType;
5479typedef enum NonDispTilingOrder {
5480	ADDR_SURF_MICRO_TILING_DISPLAY                   = 0x0,
5481	ADDR_SURF_MICRO_TILING_NON_DISPLAY               = 0x1,
5482} NonDispTilingOrder;
5483typedef enum MicroTileMode {
5484	ADDR_SURF_DISPLAY_MICRO_TILING                   = 0x0,
5485	ADDR_SURF_THIN_MICRO_TILING                      = 0x1,
5486	ADDR_SURF_DEPTH_MICRO_TILING                     = 0x2,
5487	ADDR_SURF_ROTATED_MICRO_TILING                   = 0x3,
5488	ADDR_SURF_THICK_MICRO_TILING                     = 0x4,
5489} MicroTileMode;
5490typedef enum TileSplit {
5491	ADDR_SURF_TILE_SPLIT_64B                         = 0x0,
5492	ADDR_SURF_TILE_SPLIT_128B                        = 0x1,
5493	ADDR_SURF_TILE_SPLIT_256B                        = 0x2,
5494	ADDR_SURF_TILE_SPLIT_512B                        = 0x3,
5495	ADDR_SURF_TILE_SPLIT_1KB                         = 0x4,
5496	ADDR_SURF_TILE_SPLIT_2KB                         = 0x5,
5497	ADDR_SURF_TILE_SPLIT_4KB                         = 0x6,
5498} TileSplit;
5499typedef enum SampleSplit {
5500	ADDR_SURF_SAMPLE_SPLIT_1                         = 0x0,
5501	ADDR_SURF_SAMPLE_SPLIT_2                         = 0x1,
5502	ADDR_SURF_SAMPLE_SPLIT_4                         = 0x2,
5503	ADDR_SURF_SAMPLE_SPLIT_8                         = 0x3,
5504} SampleSplit;
5505typedef enum PipeConfig {
5506	ADDR_SURF_P2                                     = 0x0,
5507	ADDR_SURF_P2_RESERVED0                           = 0x1,
5508	ADDR_SURF_P2_RESERVED1                           = 0x2,
5509	ADDR_SURF_P2_RESERVED2                           = 0x3,
5510	ADDR_SURF_P4_8x16                                = 0x4,
5511	ADDR_SURF_P4_16x16                               = 0x5,
5512	ADDR_SURF_P4_16x32                               = 0x6,
5513	ADDR_SURF_P4_32x32                               = 0x7,
5514	ADDR_SURF_P8_16x16_8x16                          = 0x8,
5515	ADDR_SURF_P8_16x32_8x16                          = 0x9,
5516	ADDR_SURF_P8_32x32_8x16                          = 0xa,
5517	ADDR_SURF_P8_16x32_16x16                         = 0xb,
5518	ADDR_SURF_P8_32x32_16x16                         = 0xc,
5519	ADDR_SURF_P8_32x32_16x32                         = 0xd,
5520	ADDR_SURF_P8_32x64_32x32                         = 0xe,
5521	ADDR_SURF_P8_RESERVED0                           = 0xf,
5522	ADDR_SURF_P16_32x32_8x16                         = 0x10,
5523	ADDR_SURF_P16_32x32_16x16                        = 0x11,
5524} PipeConfig;
5525typedef enum NumBanks {
5526	ADDR_SURF_2_BANK                                 = 0x0,
5527	ADDR_SURF_4_BANK                                 = 0x1,
5528	ADDR_SURF_8_BANK                                 = 0x2,
5529	ADDR_SURF_16_BANK                                = 0x3,
5530} NumBanks;
5531typedef enum BankWidth {
5532	ADDR_SURF_BANK_WIDTH_1                           = 0x0,
5533	ADDR_SURF_BANK_WIDTH_2                           = 0x1,
5534	ADDR_SURF_BANK_WIDTH_4                           = 0x2,
5535	ADDR_SURF_BANK_WIDTH_8                           = 0x3,
5536} BankWidth;
5537typedef enum BankHeight {
5538	ADDR_SURF_BANK_HEIGHT_1                          = 0x0,
5539	ADDR_SURF_BANK_HEIGHT_2                          = 0x1,
5540	ADDR_SURF_BANK_HEIGHT_4                          = 0x2,
5541	ADDR_SURF_BANK_HEIGHT_8                          = 0x3,
5542} BankHeight;
5543typedef enum BankWidthHeight {
5544	ADDR_SURF_BANK_WH_1                              = 0x0,
5545	ADDR_SURF_BANK_WH_2                              = 0x1,
5546	ADDR_SURF_BANK_WH_4                              = 0x2,
5547	ADDR_SURF_BANK_WH_8                              = 0x3,
5548} BankWidthHeight;
5549typedef enum MacroTileAspect {
5550	ADDR_SURF_MACRO_ASPECT_1                         = 0x0,
5551	ADDR_SURF_MACRO_ASPECT_2                         = 0x1,
5552	ADDR_SURF_MACRO_ASPECT_4                         = 0x2,
5553	ADDR_SURF_MACRO_ASPECT_8                         = 0x3,
5554} MacroTileAspect;
5555typedef enum GATCL1RequestType {
5556	GATCL1_TYPE_NORMAL                               = 0x0,
5557	GATCL1_TYPE_SHOOTDOWN                            = 0x1,
5558	GATCL1_TYPE_BYPASS                               = 0x2,
5559} GATCL1RequestType;
5560typedef enum TCC_CACHE_POLICIES {
5561	TCC_CACHE_POLICY_LRU                             = 0x0,
5562	TCC_CACHE_POLICY_STREAM                          = 0x1,
5563} TCC_CACHE_POLICIES;
5564typedef enum MTYPE {
5565	MTYPE_NC_NV                                      = 0x0,
5566	MTYPE_NC                                         = 0x1,
5567	MTYPE_CC                                         = 0x2,
5568	MTYPE_UC                                         = 0x3,
5569} MTYPE;
5570typedef enum PERFMON_COUNTER_MODE {
5571	PERFMON_COUNTER_MODE_ACCUM                       = 0x0,
5572	PERFMON_COUNTER_MODE_ACTIVE_CYCLES               = 0x1,
5573	PERFMON_COUNTER_MODE_MAX                         = 0x2,
5574	PERFMON_COUNTER_MODE_DIRTY                       = 0x3,
5575	PERFMON_COUNTER_MODE_SAMPLE                      = 0x4,
5576	PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT    = 0x5,
5577	PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT     = 0x6,
5578	PERFMON_COUNTER_MODE_CYCLES_GE_HI                = 0x7,
5579	PERFMON_COUNTER_MODE_CYCLES_EQ_HI                = 0x8,
5580	PERFMON_COUNTER_MODE_INACTIVE_CYCLES             = 0x9,
5581	PERFMON_COUNTER_MODE_RESERVED                    = 0xf,
5582} PERFMON_COUNTER_MODE;
5583typedef enum PERFMON_SPM_MODE {
5584	PERFMON_SPM_MODE_OFF                             = 0x0,
5585	PERFMON_SPM_MODE_16BIT_CLAMP                     = 0x1,
5586	PERFMON_SPM_MODE_16BIT_NO_CLAMP                  = 0x2,
5587	PERFMON_SPM_MODE_32BIT_CLAMP                     = 0x3,
5588	PERFMON_SPM_MODE_32BIT_NO_CLAMP                  = 0x4,
5589	PERFMON_SPM_MODE_RESERVED_5                      = 0x5,
5590	PERFMON_SPM_MODE_RESERVED_6                      = 0x6,
5591	PERFMON_SPM_MODE_RESERVED_7                      = 0x7,
5592	PERFMON_SPM_MODE_TEST_MODE_0                     = 0x8,
5593	PERFMON_SPM_MODE_TEST_MODE_1                     = 0x9,
5594	PERFMON_SPM_MODE_TEST_MODE_2                     = 0xa,
5595} PERFMON_SPM_MODE;
5596typedef enum SurfaceTiling {
5597	ARRAY_LINEAR                                     = 0x0,
5598	ARRAY_TILED                                      = 0x1,
5599} SurfaceTiling;
5600typedef enum SurfaceArray {
5601	ARRAY_1D                                         = 0x0,
5602	ARRAY_2D                                         = 0x1,
5603	ARRAY_3D                                         = 0x2,
5604	ARRAY_3D_SLICE                                   = 0x3,
5605} SurfaceArray;
5606typedef enum ColorArray {
5607	ARRAY_2D_ALT_COLOR                               = 0x0,
5608	ARRAY_2D_COLOR                                   = 0x1,
5609	ARRAY_3D_SLICE_COLOR                             = 0x3,
5610} ColorArray;
5611typedef enum DepthArray {
5612	ARRAY_2D_ALT_DEPTH                               = 0x0,
5613	ARRAY_2D_DEPTH                                   = 0x1,
5614} DepthArray;
5615typedef enum ENUM_NUM_SIMD_PER_CU {
5616	NUM_SIMD_PER_CU                                  = 0x4,
5617} ENUM_NUM_SIMD_PER_CU;
5618typedef enum MEM_PWR_FORCE_CTRL {
5619	NO_FORCE_REQUEST                                 = 0x0,
5620	FORCE_LIGHT_SLEEP_REQUEST                        = 0x1,
5621	FORCE_DEEP_SLEEP_REQUEST                         = 0x2,
5622	FORCE_SHUT_DOWN_REQUEST                          = 0x3,
5623} MEM_PWR_FORCE_CTRL;
5624typedef enum MEM_PWR_FORCE_CTRL2 {
5625	NO_FORCE_REQ                                     = 0x0,
5626	FORCE_LIGHT_SLEEP_REQ                            = 0x1,
5627} MEM_PWR_FORCE_CTRL2;
5628typedef enum MEM_PWR_DIS_CTRL {
5629	ENABLE_MEM_PWR_CTRL                              = 0x0,
5630	DISABLE_MEM_PWR_CTRL                             = 0x1,
5631} MEM_PWR_DIS_CTRL;
5632typedef enum MEM_PWR_SEL_CTRL {
5633	DYNAMIC_SHUT_DOWN_ENABLE                         = 0x0,
5634	DYNAMIC_DEEP_SLEEP_ENABLE                        = 0x1,
5635	DYNAMIC_LIGHT_SLEEP_ENABLE                       = 0x2,
5636} MEM_PWR_SEL_CTRL;
5637typedef enum MEM_PWR_SEL_CTRL2 {
5638	DYNAMIC_DEEP_SLEEP_EN                            = 0x0,
5639	DYNAMIC_LIGHT_SLEEP_EN                           = 0x1,
5640} MEM_PWR_SEL_CTRL2;
5641typedef enum HPD_INT_CONTROL_ACK {
5642	HPD_INT_CONTROL_ACK_0                            = 0x0,
5643	HPD_INT_CONTROL_ACK_1                            = 0x1,
5644} HPD_INT_CONTROL_ACK;
5645typedef enum HPD_INT_CONTROL_POLARITY {
5646	HPD_INT_CONTROL_GEN_INT_ON_DISCON                = 0x0,
5647	HPD_INT_CONTROL_GEN_INT_ON_CON                   = 0x1,
5648} HPD_INT_CONTROL_POLARITY;
5649typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5650	HPD_INT_CONTROL_RX_INT_ACK_0                     = 0x0,
5651	HPD_INT_CONTROL_RX_INT_ACK_1                     = 0x1,
5652} HPD_INT_CONTROL_RX_INT_ACK;
5653typedef enum DPDBG_EN {
5654	DPDBG_DISABLE                                    = 0x0,
5655	DPDBG_ENABLE                                     = 0x1,
5656} DPDBG_EN;
5657typedef enum DPDBG_INPUT_EN {
5658	DPDBG_INPUT_DISABLE                              = 0x0,
5659	DPDBG_INPUT_ENABLE                               = 0x1,
5660} DPDBG_INPUT_EN;
5661typedef enum DPDBG_ERROR_DETECTION_MODE {
5662	DPDBG_ERROR_DETECTION_MODE_CSC                   = 0x0,
5663	DPDBG_ERROR_DETECTION_MODE_RS_ENCODING           = 0x1,
5664} DPDBG_ERROR_DETECTION_MODE;
5665typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK {
5666	DPDBG_FIFO_OVERFLOW_INT_DISABLE                  = 0x0,
5667	DPDBG_FIFO_OVERFLOW_INT_ENABLE                   = 0x1,
5668} DPDBG_FIFO_OVERFLOW_INTERRUPT_MASK;
5669typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE {
5670	DPDBG_FIFO_OVERFLOW_INT_LEVEL_BASED              = 0x0,
5671	DPDBG_FIFO_OVERFLOW_INT_PULSE_BASED              = 0x1,
5672} DPDBG_FIFO_OVERFLOW_INTERRUPT_TYPE;
5673typedef enum DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK {
5674	DPDBG_FIFO_OVERFLOW_INT_NO_ACK                   = 0x0,
5675	DPDBG_FIFO_OVERFLOW_INT_CLEAR                    = 0x1,
5676} DPDBG_FIFO_OVERFLOW_INTERRUPT_ACK;
5677typedef enum PM_ASSERT_RESET {
5678	PM_ASSERT_RESET_0                                = 0x0,
5679	PM_ASSERT_RESET_1                                = 0x1,
5680} PM_ASSERT_RESET;
5681typedef enum DAC_MUX_SELECT {
5682	DAC_MUX_SELECT_DACA                              = 0x0,
5683	DAC_MUX_SELECT_DACB                              = 0x1,
5684} DAC_MUX_SELECT;
5685typedef enum TMDS_DVO_MUX_SELECT {
5686	TMDS_DVO_MUX_SELECT_B                            = 0x0,
5687	TMDS_DVO_MUX_SELECT_G                            = 0x1,
5688	TMDS_DVO_MUX_SELECT_R                            = 0x2,
5689	TMDS_DVO_MUX_SELECT_RESERVED                     = 0x3,
5690} TMDS_DVO_MUX_SELECT;
5691typedef enum DACA_SOFT_RESET {
5692	DACA_SOFT_RESET_0                                = 0x0,
5693	DACA_SOFT_RESET_1                                = 0x1,
5694} DACA_SOFT_RESET;
5695typedef enum I2S0_SPDIF0_SOFT_RESET {
5696	I2S0_SPDIF0_SOFT_RESET_0                         = 0x0,
5697	I2S0_SPDIF0_SOFT_RESET_1                         = 0x1,
5698} I2S0_SPDIF0_SOFT_RESET;
5699typedef enum I2S1_SOFT_RESET {
5700	I2S1_SOFT_RESET_0                                = 0x0,
5701	I2S1_SOFT_RESET_1                                = 0x1,
5702} I2S1_SOFT_RESET;
5703typedef enum SPDIF1_SOFT_RESET {
5704	SPDIF1_SOFT_RESET_0                              = 0x0,
5705	SPDIF1_SOFT_RESET_1                              = 0x1,
5706} SPDIF1_SOFT_RESET;
5707typedef enum DB_CLK_SOFT_RESET {
5708	DB_CLK_SOFT_RESET_0                              = 0x0,
5709	DB_CLK_SOFT_RESET_1                              = 0x1,
5710} DB_CLK_SOFT_RESET;
5711typedef enum FMT0_SOFT_RESET {
5712	FMT0_SOFT_RESET_0                                = 0x0,
5713	FMT0_SOFT_RESET_1                                = 0x1,
5714} FMT0_SOFT_RESET;
5715typedef enum FMT1_SOFT_RESET {
5716	FMT1_SOFT_RESET_0                                = 0x0,
5717	FMT1_SOFT_RESET_1                                = 0x1,
5718} FMT1_SOFT_RESET;
5719typedef enum FMT2_SOFT_RESET {
5720	FMT2_SOFT_RESET_0                                = 0x0,
5721	FMT2_SOFT_RESET_1                                = 0x1,
5722} FMT2_SOFT_RESET;
5723typedef enum FMT3_SOFT_RESET {
5724	FMT3_SOFT_RESET_0                                = 0x0,
5725	FMT3_SOFT_RESET_1                                = 0x1,
5726} FMT3_SOFT_RESET;
5727typedef enum FMT4_SOFT_RESET {
5728	FMT4_SOFT_RESET_0                                = 0x0,
5729	FMT4_SOFT_RESET_1                                = 0x1,
5730} FMT4_SOFT_RESET;
5731typedef enum FMT5_SOFT_RESET {
5732	FMT5_SOFT_RESET_0                                = 0x0,
5733	FMT5_SOFT_RESET_1                                = 0x1,
5734} FMT5_SOFT_RESET;
5735typedef enum MVP_SOFT_RESET {
5736	MVP_SOFT_RESET_0                                 = 0x0,
5737	MVP_SOFT_RESET_1                                 = 0x1,
5738} MVP_SOFT_RESET;
5739typedef enum ABM_SOFT_RESET {
5740	ABM_SOFT_RESET_0                                 = 0x0,
5741	ABM_SOFT_RESET_1                                 = 0x1,
5742} ABM_SOFT_RESET;
5743typedef enum DVO_SOFT_RESET {
5744	DVO_SOFT_RESET_0                                 = 0x0,
5745	DVO_SOFT_RESET_1                                 = 0x1,
5746} DVO_SOFT_RESET;
5747typedef enum DIGA_FE_SOFT_RESET {
5748	DIGA_FE_SOFT_RESET_0                             = 0x0,
5749	DIGA_FE_SOFT_RESET_1                             = 0x1,
5750} DIGA_FE_SOFT_RESET;
5751typedef enum DIGA_BE_SOFT_RESET {
5752	DIGA_BE_SOFT_RESET_0                             = 0x0,
5753	DIGA_BE_SOFT_RESET_1                             = 0x1,
5754} DIGA_BE_SOFT_RESET;
5755typedef enum DIGB_FE_SOFT_RESET {
5756	DIGB_FE_SOFT_RESET_0                             = 0x0,
5757	DIGB_FE_SOFT_RESET_1                             = 0x1,
5758} DIGB_FE_SOFT_RESET;
5759typedef enum DIGB_BE_SOFT_RESET {
5760	DIGB_BE_SOFT_RESET_0                             = 0x0,
5761	DIGB_BE_SOFT_RESET_1                             = 0x1,
5762} DIGB_BE_SOFT_RESET;
5763typedef enum DIGC_FE_SOFT_RESET {
5764	DIGC_FE_SOFT_RESET_0                             = 0x0,
5765	DIGC_FE_SOFT_RESET_1                             = 0x1,
5766} DIGC_FE_SOFT_RESET;
5767typedef enum DIGC_BE_SOFT_RESET {
5768	DIGC_BE_SOFT_RESET_0                             = 0x0,
5769	DIGC_BE_SOFT_RESET_1                             = 0x1,
5770} DIGC_BE_SOFT_RESET;
5771typedef enum DIGD_FE_SOFT_RESET {
5772	DIGD_FE_SOFT_RESET_0                             = 0x0,
5773	DIGD_FE_SOFT_RESET_1                             = 0x1,
5774} DIGD_FE_SOFT_RESET;
5775typedef enum DIGD_BE_SOFT_RESET {
5776	DIGD_BE_SOFT_RESET_0                             = 0x0,
5777	DIGD_BE_SOFT_RESET_1                             = 0x1,
5778} DIGD_BE_SOFT_RESET;
5779typedef enum DIGE_FE_SOFT_RESET {
5780	DIGE_FE_SOFT_RESET_0                             = 0x0,
5781	DIGE_FE_SOFT_RESET_1                             = 0x1,
5782} DIGE_FE_SOFT_RESET;
5783typedef enum DIGE_BE_SOFT_RESET {
5784	DIGE_BE_SOFT_RESET_0                             = 0x0,
5785	DIGE_BE_SOFT_RESET_1                             = 0x1,
5786} DIGE_BE_SOFT_RESET;
5787typedef enum DIGF_FE_SOFT_RESET {
5788	DIGF_FE_SOFT_RESET_0                             = 0x0,
5789	DIGF_FE_SOFT_RESET_1                             = 0x1,
5790} DIGF_FE_SOFT_RESET;
5791typedef enum DIGF_BE_SOFT_RESET {
5792	DIGF_BE_SOFT_RESET_0                             = 0x0,
5793	DIGF_BE_SOFT_RESET_1                             = 0x1,
5794} DIGF_BE_SOFT_RESET;
5795typedef enum DIGG_FE_SOFT_RESET {
5796	DIGG_FE_SOFT_RESET_0                             = 0x0,
5797	DIGG_FE_SOFT_RESET_1                             = 0x1,
5798} DIGG_FE_SOFT_RESET;
5799typedef enum DIGG_BE_SOFT_RESET {
5800	DIGG_BE_SOFT_RESET_0                             = 0x0,
5801	DIGG_BE_SOFT_RESET_1                             = 0x1,
5802} DIGG_BE_SOFT_RESET;
5803typedef enum DPDBG_SOFT_RESET {
5804	DPDBG_SOFT_RESET_0                               = 0x0,
5805	DPDBG_SOFT_RESET_1                               = 0x1,
5806} DPDBG_SOFT_RESET;
5807typedef enum DIGLPA_FE_SOFT_RESET {
5808	DIGLPA_FE_SOFT_RESET_0                           = 0x0,
5809	DIGLPA_FE_SOFT_RESET_1                           = 0x1,
5810} DIGLPA_FE_SOFT_RESET;
5811typedef enum DIGLPA_BE_SOFT_RESET {
5812	DIGLPA_BE_SOFT_RESET_0                           = 0x0,
5813	DIGLPA_BE_SOFT_RESET_1                           = 0x1,
5814} DIGLPA_BE_SOFT_RESET;
5815typedef enum DIGLPB_FE_SOFT_RESET {
5816	DIGLPB_FE_SOFT_RESET_0                           = 0x0,
5817	DIGLPB_FE_SOFT_RESET_1                           = 0x1,
5818} DIGLPB_FE_SOFT_RESET;
5819typedef enum DIGLPB_BE_SOFT_RESET {
5820	DIGLPB_BE_SOFT_RESET_0                           = 0x0,
5821	DIGLPB_BE_SOFT_RESET_1                           = 0x1,
5822} DIGLPB_BE_SOFT_RESET;
5823typedef enum GENERICA_STEREOSYNC_SEL {
5824	GENERICA_STEREOSYNC_SEL_D1                       = 0x0,
5825	GENERICA_STEREOSYNC_SEL_D2                       = 0x1,
5826	GENERICA_STEREOSYNC_SEL_D3                       = 0x2,
5827	GENERICA_STEREOSYNC_SEL_D4                       = 0x3,
5828	GENERICA_STEREOSYNC_SEL_D5                       = 0x4,
5829	GENERICA_STEREOSYNC_SEL_D6                       = 0x5,
5830	GENERICA_STEREOSYNC_SEL_RESERVED                 = 0x6,
5831} GENERICA_STEREOSYNC_SEL;
5832typedef enum GENERICB_STEREOSYNC_SEL {
5833	GENERICB_STEREOSYNC_SEL_D1                       = 0x0,
5834	GENERICB_STEREOSYNC_SEL_D2                       = 0x1,
5835	GENERICB_STEREOSYNC_SEL_D3                       = 0x2,
5836	GENERICB_STEREOSYNC_SEL_D4                       = 0x3,
5837	GENERICB_STEREOSYNC_SEL_D5                       = 0x4,
5838	GENERICB_STEREOSYNC_SEL_D6                       = 0x5,
5839	GENERICB_STEREOSYNC_SEL_RESERVED                 = 0x6,
5840} GENERICB_STEREOSYNC_SEL;
5841typedef enum DCO_DBG_BLOCK_SEL {
5842	DCO_DBG_BLOCK_SEL_DCO                            = 0x0,
5843	DCO_DBG_BLOCK_SEL_ABM                            = 0x1,
5844	DCO_DBG_BLOCK_SEL_DVO                            = 0x2,
5845	DCO_DBG_BLOCK_SEL_DAC                            = 0x3,
5846	DCO_DBG_BLOCK_SEL_MVP                            = 0x4,
5847	DCO_DBG_BLOCK_SEL_FMT0                           = 0x5,
5848	DCO_DBG_BLOCK_SEL_FMT1                           = 0x6,
5849	DCO_DBG_BLOCK_SEL_FMT2                           = 0x7,
5850	DCO_DBG_BLOCK_SEL_FMT3                           = 0x8,
5851	DCO_DBG_BLOCK_SEL_FMT4                           = 0x9,
5852	DCO_DBG_BLOCK_SEL_FMT5                           = 0xa,
5853	DCO_DBG_BLOCK_SEL_DIGFE_A                        = 0xb,
5854	DCO_DBG_BLOCK_SEL_DIGFE_B                        = 0xc,
5855	DCO_DBG_BLOCK_SEL_DIGFE_C                        = 0xd,
5856	DCO_DBG_BLOCK_SEL_DIGFE_D                        = 0xe,
5857	DCO_DBG_BLOCK_SEL_DIGFE_E                        = 0xf,
5858	DCO_DBG_BLOCK_SEL_DIGFE_F                        = 0x10,
5859	DCO_DBG_BLOCK_SEL_DIGFE_G                        = 0x11,
5860	DCO_DBG_BLOCK_SEL_DIGA                           = 0x12,
5861	DCO_DBG_BLOCK_SEL_DIGB                           = 0x13,
5862	DCO_DBG_BLOCK_SEL_DIGC                           = 0x14,
5863	DCO_DBG_BLOCK_SEL_DIGD                           = 0x15,
5864	DCO_DBG_BLOCK_SEL_DIGE                           = 0x16,
5865	DCO_DBG_BLOCK_SEL_DIGF                           = 0x17,
5866	DCO_DBG_BLOCK_SEL_DIGG                           = 0x18,
5867	DCO_DBG_BLOCK_SEL_DPFE_A                         = 0x19,
5868	DCO_DBG_BLOCK_SEL_DPFE_B                         = 0x1a,
5869	DCO_DBG_BLOCK_SEL_DPFE_C                         = 0x1b,
5870	DCO_DBG_BLOCK_SEL_DPFE_D                         = 0x1c,
5871	DCO_DBG_BLOCK_SEL_DPFE_E                         = 0x1d,
5872	DCO_DBG_BLOCK_SEL_DPFE_F                         = 0x1e,
5873	DCO_DBG_BLOCK_SEL_DPFE_G                         = 0x1f,
5874	DCO_DBG_BLOCK_SEL_DPA                            = 0x20,
5875	DCO_DBG_BLOCK_SEL_DPB                            = 0x21,
5876	DCO_DBG_BLOCK_SEL_DPC                            = 0x22,
5877	DCO_DBG_BLOCK_SEL_DPD                            = 0x23,
5878	DCO_DBG_BLOCK_SEL_DPE                            = 0x24,
5879	DCO_DBG_BLOCK_SEL_DPF                            = 0x25,
5880	DCO_DBG_BLOCK_SEL_DPG                            = 0x26,
5881	DCO_DBG_BLOCK_SEL_AUX0                           = 0x27,
5882	DCO_DBG_BLOCK_SEL_AUX1                           = 0x28,
5883	DCO_DBG_BLOCK_SEL_AUX2                           = 0x29,
5884	DCO_DBG_BLOCK_SEL_AUX3                           = 0x2a,
5885	DCO_DBG_BLOCK_SEL_AUX4                           = 0x2b,
5886	DCO_DBG_BLOCK_SEL_AUX5                           = 0x2c,
5887	DCO_DBG_BLOCK_SEL_PERFMON_DCO                    = 0x2d,
5888	DCO_DBG_BLOCK_SEL_AUDIO_OUT                      = 0x2e,
5889	DCO_DBG_BLOCK_SEL_DIGLPFEA                       = 0x2f,
5890	DCO_DBG_BLOCK_SEL_DIGLPFEB                       = 0x30,
5891	DCO_DBG_BLOCK_SEL_DIGLPA                         = 0x31,
5892	DCO_DBG_BLOCK_SEL_DIGLPB                         = 0x32,
5893	DCO_DBG_BLOCK_SEL_DPLPFEA                        = 0x33,
5894	DCO_DBG_BLOCK_SEL_DPLPFEB                        = 0x34,
5895	DCO_DBG_BLOCK_SEL_DPLPA                          = 0x35,
5896	DCO_DBG_BLOCK_SEL_DPLPB                          = 0x36,
5897} DCO_DBG_BLOCK_SEL;
5898typedef enum DCO_DBG_CLOCK_SEL {
5899	DCO_DBG_CLOCK_SEL_DISPCLK                        = 0x0,
5900	DCO_DBG_CLOCK_SEL_SCLK                           = 0x1,
5901	DCO_DBG_CLOCK_SEL_MVPCLK                         = 0x2,
5902	DCO_DBG_CLOCK_SEL_DVOCLK                         = 0x3,
5903	DCO_DBG_CLOCK_SEL_DACCLK                         = 0x4,
5904	DCO_DBG_CLOCK_SEL_REFCLK                         = 0x5,
5905	DCO_DBG_CLOCK_SEL_SYMCLKA                        = 0x6,
5906	DCO_DBG_CLOCK_SEL_SYMCLKB                        = 0x7,
5907	DCO_DBG_CLOCK_SEL_SYMCLKC                        = 0x8,
5908	DCO_DBG_CLOCK_SEL_SYMCLKD                        = 0x9,
5909	DCO_DBG_CLOCK_SEL_SYMCLKE                        = 0xa,
5910	DCO_DBG_CLOCK_SEL_SYMCLKF                        = 0xb,
5911	DCO_DBG_CLOCK_SEL_SYMCLKG                        = 0xc,
5912	DCO_DBG_CLOCK_SEL_RESERVED                       = 0xd,
5913	DCO_DBG_CLOCK_SEL_AM0CLK                         = 0xe,
5914	DCO_DBG_CLOCK_SEL_AM1CLK                         = 0xf,
5915	DCO_DBG_CLOCK_SEL_AM2CLK                         = 0x10,
5916	DCO_DBG_CLOCK_SEL_SYMCLKLPA                      = 0x11,
5917	DCO_DBG_CLOCK_SEL_SYMCLKLPB                      = 0x12,
5918} DCO_DBG_CLOCK_SEL;
5919typedef enum DOUT_I2C_CONTROL_GO {
5920	DOUT_I2C_CONTROL_STOP_TRANSFER                   = 0x0,
5921	DOUT_I2C_CONTROL_START_TRANSFER                  = 0x1,
5922} DOUT_I2C_CONTROL_GO;
5923typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
5924	DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER        = 0x0,
5925	DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER            = 0x1,
5926} DOUT_I2C_CONTROL_SOFT_RESET;
5927typedef enum DOUT_I2C_CONTROL_SEND_RESET {
5928	DOUT_I2C_CONTROL__NOT_SEND_RESET                 = 0x0,
5929	DOUT_I2C_CONTROL__SEND_RESET                     = 0x1,
5930} DOUT_I2C_CONTROL_SEND_RESET;
5931typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
5932	DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS             = 0x0,
5933	DOUT_I2C_CONTROL_RESET_SW_STATUS                 = 0x1,
5934} DOUT_I2C_CONTROL_SW_STATUS_RESET;
5935typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
5936	DOUT_I2C_CONTROL_SELECT_DDC1                     = 0x0,
5937	DOUT_I2C_CONTROL_SELECT_DDC2                     = 0x1,
5938	DOUT_I2C_CONTROL_SELECT_DDC3                     = 0x2,
5939	DOUT_I2C_CONTROL_SELECT_DDC4                     = 0x3,
5940	DOUT_I2C_CONTROL_SELECT_DDC5                     = 0x4,
5941	DOUT_I2C_CONTROL_SELECT_DDC6                     = 0x5,
5942	DOUT_I2C_CONTROL_SELECT_DDCVGA                   = 0x6,
5943} DOUT_I2C_CONTROL_DDC_SELECT;
5944typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
5945	DOUT_I2C_CONTROL_TRANS0                          = 0x0,
5946	DOUT_I2C_CONTROL_TRANS0_TRANS1                   = 0x1,
5947	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2            = 0x2,
5948	DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3     = 0x3,
5949} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
5950typedef enum DOUT_I2C_CONTROL_DBG_REF_SEL {
5951	DOUT_I2C_CONTROL_NORMAL_DEBUG                    = 0x0,
5952	DOUT_I2C_CONTROL_FAST_REFERENCE_DEBUG            = 0x1,
5953} DOUT_I2C_CONTROL_DBG_REF_SEL;
5954typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
5955	DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL          = 0x0,
5956	DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH            = 0x1,
5957	DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED      = 0x2,
5958	DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED      = 0x3,
5959} DOUT_I2C_ARBITRATION_SW_PRIORITY;
5960typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
5961	DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED            = 0x0,
5962	DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED           = 0x1,
5963} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
5964typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
5965	DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER  = 0x0,
5966	DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER      = 0x1,
5967} DOUT_I2C_ARBITRATION_ABORT_XFER;
5968typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
5969	DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ        = 0x0,
5970	DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ            = 0x1,
5971} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
5972typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
5973	DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG     = 0x0,
5974	DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG         = 0x1,
5975} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
5976typedef enum DOUT_I2C_ACK {
5977	DOUT_I2C_NO_ACK                                  = 0x0,
5978	DOUT_I2C_ACK_TO_CLEAN                            = 0x1,
5979} DOUT_I2C_ACK;
5980typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
5981	DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO       = 0x0,
5982	DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE= 0x1,
5983	DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE= 0x2,
5984	DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE= 0x3,
5985} DOUT_I2C_DDC_SPEED_THRESHOLD;
5986typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
5987	DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
5988	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA             = 0x1,
5989} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
5990typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
5991	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS        = 0x0,
5992	DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS        = 0x1,
5993} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
5994typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
5995	DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT           = 0x0,
5996	DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT        = 0x1,
5997} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
5998typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
5999	DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR= 0x0,
6000	DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL             = 0x1,
6001} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
6002typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
6003	DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS          = 0x0,
6004	DOUT_I2C_TRANSACTION_STOP_ALL_TRANS              = 0x1,
6005} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
6006typedef enum DOUT_I2C_DATA_INDEX_WRITE {
6007	DOUT_I2C_DATA__NOT_INDEX_WRITE                   = 0x0,
6008	DOUT_I2C_DATA__INDEX_WRITE                       = 0x1,
6009} DOUT_I2C_DATA_INDEX_WRITE;
6010typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
6011	DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x0,
6012	DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION= 0x1,
6013} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
6014typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
6015	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL      = 0x0,
6016	DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE      = 0x1,
6017} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
6018typedef enum BLNDV_CONTROL_BLND_MODE {
6019	BLNDV_CONTROL_BLND_MODE_CURRENT_PIPE_ONLY        = 0x0,
6020	BLNDV_CONTROL_BLND_MODE_OTHER_PIPE_ONLY          = 0x1,
6021	BLNDV_CONTROL_BLND_MODE_ALPHA_BLENDING_MODE      = 0x2,
6022	BLNDV_CONTROL_BLND_MODE_OTHER_STEREO_TYPE        = 0x3,
6023} BLNDV_CONTROL_BLND_MODE;
6024typedef enum BLNDV_CONTROL_BLND_STEREO_TYPE {
6025	BLNDV_CONTROL_BLND_STEREO_TYPE_NON_SINGLE_PIPE_STEREO= 0x0,
6026	BLNDV_CONTROL_BLND_STEREO_TYPE_SIDE_BY_SIDE_SINGLE_PIPE_STEREO= 0x1,
6027	BLNDV_CONTROL_BLND_STEREO_TYPE_TOP_BOTTOM_SINGLE_PIPE_STEREO= 0x2,
6028	BLNDV_CONTROL_BLND_STEREO_TYPE_UNUSED            = 0x3,
6029} BLNDV_CONTROL_BLND_STEREO_TYPE;
6030typedef enum BLNDV_CONTROL_BLND_STEREO_POLARITY {
6031	BLNDV_CONTROL_BLND_STEREO_POLARITY_LOW           = 0x0,
6032	BLNDV_CONTROL_BLND_STEREO_POLARITY_HIGH          = 0x1,
6033} BLNDV_CONTROL_BLND_STEREO_POLARITY;
6034typedef enum BLNDV_CONTROL_BLND_FEEDTHROUGH_EN {
6035	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_FALSE          = 0x0,
6036	BLNDV_CONTROL_BLND_FEEDTHROUGH_EN_TRUE           = 0x1,
6037} BLNDV_CONTROL_BLND_FEEDTHROUGH_EN;
6038typedef enum BLNDV_CONTROL_BLND_ALPHA_MODE {
6039	BLNDV_CONTROL_BLND_ALPHA_MODE_CURRENT_PIXEL_ALPHA= 0x0,
6040	BLNDV_CONTROL_BLND_ALPHA_MODE_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN= 0x1,
6041	BLNDV_CONTROL_BLND_ALPHA_MODE_GLOBAL_ALPHA_ONLY  = 0x2,
6042	BLNDV_CONTROL_BLND_ALPHA_MODE_UNUSED             = 0x3,
6043} BLNDV_CONTROL_BLND_ALPHA_MODE;
6044typedef enum BLNDV_CONTROL_BLND_MULTIPLIED_MODE {
6045	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_FALSE         = 0x0,
6046	BLNDV_CONTROL_BLND_MULTIPLIED_MODE_TRUE          = 0x1,
6047} BLNDV_CONTROL_BLND_MULTIPLIED_MODE;
6048typedef enum BLNDV_SM_CONTROL2_SM_MODE {
6049	BLNDV_SM_CONTROL2_SM_MODE_SINGLE_PLANE           = 0x0,
6050	BLNDV_SM_CONTROL2_SM_MODE_ROW_SUBSAMPLING        = 0x2,
6051	BLNDV_SM_CONTROL2_SM_MODE_COLUMN_SUBSAMPLING     = 0x4,
6052	BLNDV_SM_CONTROL2_SM_MODE_CHECKERBOARD_SUBSAMPLING= 0x6,
6053} BLNDV_SM_CONTROL2_SM_MODE;
6054typedef enum BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE {
6055	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_FALSE       = 0x0,
6056	BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE_TRUE        = 0x1,
6057} BLNDV_SM_CONTROL2_SM_FRAME_ALTERNATE;
6058typedef enum BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE {
6059	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_FALSE       = 0x0,
6060	BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE_TRUE        = 0x1,
6061} BLNDV_SM_CONTROL2_SM_FIELD_ALTERNATE;
6062typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL {
6063	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_NO_FORCE= 0x0,
6064	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_RESERVED= 0x1,
6065	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW= 0x2,
6066	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH= 0x3,
6067} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_FRAME_POL;
6068typedef enum BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL {
6069	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x0,
6070	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x1,
6071	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_LOW= 0x2,
6072	BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH= 0x3,
6073} BLNDV_SM_CONTROL2_SM_FORCE_NEXT_TOP_POL;
6074typedef enum BLNDV_CONTROL2_PTI_ENABLE {
6075	BLNDV_CONTROL2_PTI_ENABLE_FALSE                  = 0x0,
6076	BLNDV_CONTROL2_PTI_ENABLE_TRUE                   = 0x1,
6077} BLNDV_CONTROL2_PTI_ENABLE;
6078typedef enum BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN {
6079	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_FALSE     = 0x0,
6080	BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN_TRUE      = 0x1,
6081} BLNDV_CONTROL2_BLND_SUPERAA_DEGAMMA_EN;
6082typedef enum BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN {
6083	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_FALSE     = 0x0,
6084	BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN_TRUE      = 0x1,
6085} BLNDV_CONTROL2_BLND_SUPERAA_REGAMMA_EN;
6086typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK {
6087	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_FALSE= 0x0,
6088	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK_TRUE= 0x1,
6089} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_ACK;
6090typedef enum BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK {
6091	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_FALSE= 0x0,
6092	BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK_TRUE= 0x1,
6093} BLNDV_UNDERFLOW_INTERRUPT_BLND_UNDERFLOW_INT_MASK;
6094typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK {
6095	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_FALSE= 0x0,
6096	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK_TRUE= 0x1,
6097} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_V_UPDATE_LOCK;
6098typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK {
6099	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_FALSE= 0x0,
6100	BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK_TRUE= 0x1,
6101} BLNDV_V_UPDATE_LOCK_BLND_DCP_GRPH_SURF_V_UPDATE_LOCK;
6102typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK {
6103	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_FALSE= 0x0,
6104	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK_TRUE= 0x1,
6105} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR_V_UPDATE_LOCK;
6106typedef enum BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK {
6107	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_FALSE= 0x0,
6108	BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK_TRUE= 0x1,
6109} BLNDV_V_UPDATE_LOCK_BLND_DCP_CUR2_V_UPDATE_LOCK;
6110typedef enum BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK {
6111	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_FALSE = 0x0,
6112	BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK_TRUE  = 0x1,
6113} BLNDV_V_UPDATE_LOCK_BLND_SCL_V_UPDATE_LOCK;
6114typedef enum BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK {
6115	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_FALSE= 0x0,
6116	BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK_TRUE = 0x1,
6117} BLNDV_V_UPDATE_LOCK_BLND_BLND_V_UPDATE_LOCK;
6118typedef enum BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE {
6119	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_FALSE= 0x0,
6120	BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE_TRUE = 0x1,
6121} BLNDV_V_UPDATE_LOCK_BLND_V_UPDATE_LOCK_MODE;
6122typedef enum BLNDV_DEBUG_BLND_CNV_MUX_SELECT {
6123	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_LOW              = 0x0,
6124	BLNDV_DEBUG_BLND_CNV_MUX_SELECT_HIGH             = 0x1,
6125} BLNDV_DEBUG_BLND_CNV_MUX_SELECT;
6126typedef enum BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN {
6127	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_FALSE= 0x0,
6128	BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN_TRUE= 0x1,
6129} BLNDV_TEST_DEBUG_INDEX_BLND_TEST_DEBUG_WRITE_EN;
6130
6131#endif /* DCE_11_0_ENUM_H */
6132