1/*	$NetBSD: link_service_types.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $	*/
2
3/*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#ifndef __DAL_LINK_SERVICE_TYPES_H__
29#define __DAL_LINK_SERVICE_TYPES_H__
30
31#include "grph_object_id.h"
32#include "dal_types.h"
33#include "irq_types.h"
34
35/*struct mst_mgr_callback_object;*/
36struct ddc;
37struct irq_manager;
38
39enum {
40	MAX_CONTROLLER_NUM = 6
41};
42
43enum dp_power_state {
44	DP_POWER_STATE_D0 = 1,
45	DP_POWER_STATE_D3
46};
47
48enum edp_revision {
49	/* eDP version 1.1 or lower */
50	EDP_REVISION_11 = 0x00,
51	/* eDP version 1.2 */
52	EDP_REVISION_12 = 0x01,
53	/* eDP version 1.3 */
54	EDP_REVISION_13 = 0x02
55};
56
57enum {
58	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
59};
60
61enum link_training_result {
62	LINK_TRAINING_SUCCESS,
63	LINK_TRAINING_CR_FAIL_LANE0,
64	LINK_TRAINING_CR_FAIL_LANE1,
65	LINK_TRAINING_CR_FAIL_LANE23,
66	/* CR DONE bit is cleared during EQ step */
67	LINK_TRAINING_EQ_FAIL_CR,
68	/* other failure during EQ step */
69	LINK_TRAINING_EQ_FAIL_EQ,
70	LINK_TRAINING_LQA_FAIL,
71};
72
73struct link_training_settings {
74	struct dc_link_settings link_settings;
75	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];
76
77	enum dc_voltage_swing *voltage_swing;
78	enum dc_pre_emphasis *pre_emphasis;
79	enum dc_post_cursor2 *post_cursor2;
80
81	uint16_t cr_pattern_time;
82	uint16_t eq_pattern_time;
83	enum dc_dp_training_pattern pattern_for_eq;
84
85	bool enhanced_framing;
86	bool allow_invalid_msa_timing_param;
87};
88
89/*TODO: Move this enum test harness*/
90/* Test patterns*/
91enum dp_test_pattern {
92	/* Input data is pass through Scrambler
93	 * and 8b10b Encoder straight to output*/
94	DP_TEST_PATTERN_VIDEO_MODE = 0,
95
96	/* phy test patterns*/
97	DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
98	DP_TEST_PATTERN_D102 = DP_TEST_PATTERN_PHY_PATTERN_BEGIN,
99	DP_TEST_PATTERN_SYMBOL_ERROR,
100	DP_TEST_PATTERN_PRBS7,
101	DP_TEST_PATTERN_80BIT_CUSTOM,
102	DP_TEST_PATTERN_CP2520_1,
103	DP_TEST_PATTERN_CP2520_2,
104	DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE = DP_TEST_PATTERN_CP2520_2,
105	DP_TEST_PATTERN_CP2520_3,
106
107	/* Link Training Patterns */
108	DP_TEST_PATTERN_TRAINING_PATTERN1,
109	DP_TEST_PATTERN_TRAINING_PATTERN2,
110	DP_TEST_PATTERN_TRAINING_PATTERN3,
111	DP_TEST_PATTERN_TRAINING_PATTERN4,
112	DP_TEST_PATTERN_PHY_PATTERN_END = DP_TEST_PATTERN_TRAINING_PATTERN4,
113
114	/* link test patterns*/
115	DP_TEST_PATTERN_COLOR_SQUARES,
116	DP_TEST_PATTERN_COLOR_SQUARES_CEA,
117	DP_TEST_PATTERN_VERTICAL_BARS,
118	DP_TEST_PATTERN_HORIZONTAL_BARS,
119	DP_TEST_PATTERN_COLOR_RAMP,
120
121	/* audio test patterns*/
122	DP_TEST_PATTERN_AUDIO_OPERATOR_DEFINED,
123	DP_TEST_PATTERN_AUDIO_SAWTOOTH,
124
125	DP_TEST_PATTERN_UNSUPPORTED
126};
127
128enum dp_test_pattern_color_space {
129	DP_TEST_PATTERN_COLOR_SPACE_RGB,
130	DP_TEST_PATTERN_COLOR_SPACE_YCBCR601,
131	DP_TEST_PATTERN_COLOR_SPACE_YCBCR709,
132	DP_TEST_PATTERN_COLOR_SPACE_UNDEFINED
133};
134
135enum dp_panel_mode {
136	/* not required */
137	DP_PANEL_MODE_DEFAULT,
138	/* standard mode for eDP */
139	DP_PANEL_MODE_EDP,
140	/* external chips specific settings */
141	DP_PANEL_MODE_SPECIAL
142};
143
144/* DPCD_ADDR_TRAINING_LANEx_SET registers value */
145union dpcd_training_lane_set {
146	struct {
147#if defined(LITTLEENDIAN_CPU)
148		uint8_t VOLTAGE_SWING_SET:2;
149		uint8_t MAX_SWING_REACHED:1;
150		uint8_t PRE_EMPHASIS_SET:2;
151		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
152		/* following is reserved in DP 1.1 */
153		uint8_t POST_CURSOR2_SET:2;
154#elif defined(BIGENDIAN_CPU)
155		uint8_t POST_CURSOR2_SET:2;
156		uint8_t MAX_PRE_EMPHASIS_REACHED:1;
157		uint8_t PRE_EMPHASIS_SET:2;
158		uint8_t MAX_SWING_REACHED:1;
159		uint8_t VOLTAGE_SWING_SET:2;
160#else
161	#error ARCH not defined!
162#endif
163	} bits;
164
165	uint8_t raw;
166};
167
168
169/* DP MST stream allocation (payload bandwidth number) */
170struct dp_mst_stream_allocation {
171	uint8_t vcp_id;
172	/* number of slots required for the DP stream in
173	 * transport packet */
174	uint8_t slot_count;
175};
176
177/* DP MST stream allocation table */
178struct dp_mst_stream_allocation_table {
179	/* number of DP video streams */
180	int stream_count;
181	/* array of stream allocations */
182	struct dp_mst_stream_allocation stream_allocations[MAX_CONTROLLER_NUM];
183};
184
185#endif /*__DAL_LINK_SERVICE_TYPES_H__*/
186