1/*	$NetBSD: grph_object_defs.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $	*/
2
3/*
4 * Copyright 2012-15 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#ifndef __DAL_GRPH_OBJECT_DEFS_H__
29#define __DAL_GRPH_OBJECT_DEFS_H__
30
31#include "grph_object_id.h"
32
33/* ********************************************************************
34 * ********************************************************************
35 *
36 *  These defines shared between All Graphics Objects
37 *
38 * ********************************************************************
39 * ********************************************************************
40 */
41
42#define MAX_CONNECTOR_NUMBER_PER_SLOT	(16)
43#define MAX_BOARD_SLOTS					(4)
44#define INVALID_CONNECTOR_INDEX			((unsigned int)(-1))
45
46/* HPD unit id - HW direct translation */
47enum hpd_source_id {
48	HPD_SOURCEID1 = 0,
49	HPD_SOURCEID2,
50	HPD_SOURCEID3,
51	HPD_SOURCEID4,
52	HPD_SOURCEID5,
53	HPD_SOURCEID6,
54
55	HPD_SOURCEID_COUNT,
56	HPD_SOURCEID_UNKNOWN
57};
58
59/* DDC unit id - HW direct translation */
60enum channel_id {
61	CHANNEL_ID_UNKNOWN = 0,
62	CHANNEL_ID_DDC1,
63	CHANNEL_ID_DDC2,
64	CHANNEL_ID_DDC3,
65	CHANNEL_ID_DDC4,
66	CHANNEL_ID_DDC5,
67	CHANNEL_ID_DDC6,
68	CHANNEL_ID_DDC_VGA,
69	CHANNEL_ID_I2C_PAD,
70	CHANNEL_ID_COUNT
71};
72
73#define DECODE_CHANNEL_ID(ch_id) \
74	(ch_id) == CHANNEL_ID_DDC1 ? "CHANNEL_ID_DDC1" : \
75	(ch_id) == CHANNEL_ID_DDC2 ? "CHANNEL_ID_DDC2" : \
76	(ch_id) == CHANNEL_ID_DDC3 ? "CHANNEL_ID_DDC3" : \
77	(ch_id) == CHANNEL_ID_DDC4 ? "CHANNEL_ID_DDC4" : \
78	(ch_id) == CHANNEL_ID_DDC5 ? "CHANNEL_ID_DDC5" : \
79	(ch_id) == CHANNEL_ID_DDC6 ? "CHANNEL_ID_DDC6" : \
80	(ch_id) == CHANNEL_ID_DDC_VGA ? "CHANNEL_ID_DDC_VGA" : \
81	(ch_id) == CHANNEL_ID_I2C_PAD ? "CHANNEL_ID_I2C_PAD" : "Invalid"
82
83enum transmitter {
84	TRANSMITTER_UNKNOWN = (-1L),
85	TRANSMITTER_UNIPHY_A,
86	TRANSMITTER_UNIPHY_B,
87	TRANSMITTER_UNIPHY_C,
88	TRANSMITTER_UNIPHY_D,
89	TRANSMITTER_UNIPHY_E,
90	TRANSMITTER_UNIPHY_F,
91	TRANSMITTER_NUTMEG_CRT,
92	TRANSMITTER_TRAVIS_CRT,
93	TRANSMITTER_TRAVIS_LCD,
94	TRANSMITTER_UNIPHY_G,
95	TRANSMITTER_COUNT
96};
97
98/* Generic source of the synchronisation input/output signal */
99/* Can be used for flow control, stereo sync, timing sync, frame sync, etc */
100enum sync_source {
101	SYNC_SOURCE_NONE = 0,
102
103	/* Source based on controllers */
104	SYNC_SOURCE_CONTROLLER0,
105	SYNC_SOURCE_CONTROLLER1,
106	SYNC_SOURCE_CONTROLLER2,
107	SYNC_SOURCE_CONTROLLER3,
108	SYNC_SOURCE_CONTROLLER4,
109	SYNC_SOURCE_CONTROLLER5,
110
111	/* Source based on GSL group */
112	SYNC_SOURCE_GSL_GROUP0,
113	SYNC_SOURCE_GSL_GROUP1,
114	SYNC_SOURCE_GSL_GROUP2,
115
116	/* Source based on GSL IOs */
117	/* These IOs normally used as GSL input/output */
118	SYNC_SOURCE_GSL_IO_FIRST,
119	SYNC_SOURCE_GSL_IO_GENLOCK_CLOCK = SYNC_SOURCE_GSL_IO_FIRST,
120	SYNC_SOURCE_GSL_IO_GENLOCK_VSYNC,
121	SYNC_SOURCE_GSL_IO_SWAPLOCK_A,
122	SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
123	SYNC_SOURCE_GSL_IO_LAST = SYNC_SOURCE_GSL_IO_SWAPLOCK_B,
124
125	/* Source based on regular IOs */
126	SYNC_SOURCE_IO_FIRST,
127	SYNC_SOURCE_IO_GENERIC_A = SYNC_SOURCE_IO_FIRST,
128	SYNC_SOURCE_IO_GENERIC_B,
129	SYNC_SOURCE_IO_GENERIC_C,
130	SYNC_SOURCE_IO_GENERIC_D,
131	SYNC_SOURCE_IO_GENERIC_E,
132	SYNC_SOURCE_IO_GENERIC_F,
133	SYNC_SOURCE_IO_HPD1,
134	SYNC_SOURCE_IO_HPD2,
135	SYNC_SOURCE_IO_HSYNC_A,
136	SYNC_SOURCE_IO_VSYNC_A,
137	SYNC_SOURCE_IO_HSYNC_B,
138	SYNC_SOURCE_IO_VSYNC_B,
139	SYNC_SOURCE_IO_LAST = SYNC_SOURCE_IO_VSYNC_B,
140
141	/* Misc. flow control sources */
142	SYNC_SOURCE_DUAL_GPU_PIN
143};
144
145/* connector sizes in millimeters - from BiosParserTypes.hpp */
146#define CONNECTOR_SIZE_DVI			40
147#define CONNECTOR_SIZE_VGA			32
148#define CONNECTOR_SIZE_HDMI			16
149#define CONNECTOR_SIZE_DP			16
150#define CONNECTOR_SIZE_MINI_DP			9
151#define CONNECTOR_SIZE_UNKNOWN			30
152
153enum connector_layout_type {
154	CONNECTOR_LAYOUT_TYPE_UNKNOWN,
155	CONNECTOR_LAYOUT_TYPE_DVI_D,
156	CONNECTOR_LAYOUT_TYPE_DVI_I,
157	CONNECTOR_LAYOUT_TYPE_VGA,
158	CONNECTOR_LAYOUT_TYPE_HDMI,
159	CONNECTOR_LAYOUT_TYPE_DP,
160	CONNECTOR_LAYOUT_TYPE_MINI_DP,
161};
162struct connector_layout_info {
163	struct graphics_object_id connector_id;
164	enum connector_layout_type connector_type;
165	unsigned int length;
166	unsigned int position;  /* offset in mm from right side of the board */
167};
168
169/* length and width in mm */
170struct slot_layout_info {
171	unsigned int length;
172	unsigned int width;
173	unsigned int num_of_connectors;
174	struct connector_layout_info connectors[MAX_CONNECTOR_NUMBER_PER_SLOT];
175};
176
177struct board_layout_info {
178	unsigned int num_of_slots;
179
180	/* indicates valid information in bracket layout structure. */
181	unsigned int is_number_of_slots_valid : 1;
182	unsigned int is_slots_size_valid : 1;
183	unsigned int is_connector_offsets_valid : 1;
184	unsigned int is_connector_lengths_valid : 1;
185
186	struct slot_layout_info slots[MAX_BOARD_SLOTS];
187};
188#endif
189