amdgpu_irq_service_dce80.c revision 1.2
1/* $NetBSD: amdgpu_irq_service_dce80.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $ */ 2 3/* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: amdgpu_irq_service_dce80.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $"); 30 31#include <linux/slab.h> 32 33#include "dm_services.h" 34 35#include "include/logger_interface.h" 36 37#include "irq_service_dce80.h" 38#include "../dce110/irq_service_dce110.h" 39 40#include "dce/dce_8_0_d.h" 41#include "dce/dce_8_0_sh_mask.h" 42 43#include "ivsrcid/ivsrcid_vislands30.h" 44 45#include "dc_types.h" 46 47static bool hpd_ack( 48 struct irq_service *irq_service, 49 const struct irq_source_info *info) 50{ 51 uint32_t addr = info->status_reg; 52 uint32_t value = dm_read_reg(irq_service->ctx, addr); 53 uint32_t current_status = 54 get_reg_field_value( 55 value, 56 DC_HPD1_INT_STATUS, 57 DC_HPD1_SENSE_DELAYED); 58 59 dal_irq_service_ack_generic(irq_service, info); 60 61 value = dm_read_reg(irq_service->ctx, info->enable_reg); 62 63 set_reg_field_value( 64 value, 65 current_status ? 0 : 1, 66 DC_HPD1_INT_CONTROL, 67 DC_HPD1_INT_POLARITY); 68 69 dm_write_reg(irq_service->ctx, info->enable_reg, value); 70 71 return true; 72} 73 74static const struct irq_source_info_funcs hpd_irq_info_funcs = { 75 .set = NULL, 76 .ack = hpd_ack 77}; 78 79static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 80 .set = NULL, 81 .ack = NULL 82}; 83 84static const struct irq_source_info_funcs pflip_irq_info_funcs = { 85 .set = NULL, 86 .ack = NULL 87}; 88 89static const struct irq_source_info_funcs vblank_irq_info_funcs = { 90 .set = dce110_vblank_set, 91 .ack = NULL 92}; 93 94static const struct irq_source_info_funcs vupdate_irq_info_funcs = { 95 .set = NULL, 96 .ack = NULL 97}; 98 99#define hpd_int_entry(reg_num)\ 100 [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 101 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 102 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\ 103 .enable_value = {\ 104 DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK,\ 105 ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK\ 106 },\ 107 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 108 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\ 109 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK,\ 110 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 111 .funcs = &hpd_irq_info_funcs\ 112 } 113 114#define hpd_rx_int_entry(reg_num)\ 115 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 116 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 117 .enable_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\ 118 .enable_value = {\ 119 DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK,\ 120 ~DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_EN_MASK },\ 121 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\ 122 .ack_mask = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\ 123 .ack_value = DC_HPD1_INT_CONTROL__DC_HPD1_RX_INT_ACK_MASK,\ 124 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\ 125 .funcs = &hpd_rx_irq_info_funcs\ 126 } 127 128#define pflip_int_entry(reg_num)\ 129 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 130 .enable_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_CONTROL,\ 131 .enable_mask =\ 132 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 133 .enable_value = {\ 134 GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK,\ 135 ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK},\ 136 .ack_reg = mmDCP ## reg_num ## _GRPH_INTERRUPT_STATUS,\ 137 .ack_mask = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 138 .ack_value = GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK,\ 139 .status_reg = mmDCP ## reg_num ##_GRPH_INTERRUPT_STATUS,\ 140 .funcs = &pflip_irq_info_funcs\ 141 } 142 143#define vupdate_int_entry(reg_num)\ 144 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 145 .enable_reg = mmCRTC ## reg_num ## _CRTC_INTERRUPT_CONTROL,\ 146 .enable_mask =\ 147 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 148 .enable_value = {\ 149 CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK,\ 150 ~CRTC_INTERRUPT_CONTROL__CRTC_V_UPDATE_INT_MSK_MASK},\ 151 .ack_reg = mmCRTC ## reg_num ## _CRTC_V_UPDATE_INT_STATUS,\ 152 .ack_mask =\ 153 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 154 .ack_value =\ 155 CRTC_V_UPDATE_INT_STATUS__CRTC_V_UPDATE_INT_CLEAR_MASK,\ 156 .funcs = &vupdate_irq_info_funcs\ 157 } 158 159#define vblank_int_entry(reg_num)\ 160 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 161 .enable_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ 162 .enable_mask =\ 163 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ 164 .enable_value = {\ 165 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK,\ 166 ~CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_INT_ENABLE_MASK},\ 167 .ack_reg = mmCRTC ## reg_num ## _CRTC_VERTICAL_INTERRUPT0_CONTROL,\ 168 .ack_mask =\ 169 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ 170 .ack_value =\ 171 CRTC_VERTICAL_INTERRUPT0_CONTROL__CRTC_VERTICAL_INTERRUPT0_CLEAR_MASK,\ 172 .funcs = &vblank_irq_info_funcs,\ 173 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\ 174 } 175 176#define dummy_irq_entry() \ 177 {\ 178 .funcs = &dummy_irq_info_funcs\ 179 } 180 181#define i2c_int_entry(reg_num) \ 182 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 183 184#define dp_sink_int_entry(reg_num) \ 185 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 186 187#define gpio_pad_int_entry(reg_num) \ 188 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 189 190#define dc_underflow_int_entry(reg_num) \ 191 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 192 193 194static const struct irq_source_info_funcs dummy_irq_info_funcs = { 195 .set = dal_irq_service_dummy_set, 196 .ack = dal_irq_service_dummy_ack 197}; 198 199static const struct irq_source_info 200irq_source_info_dce80[DAL_IRQ_SOURCES_NUMBER] = { 201 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 202 hpd_int_entry(1), 203 hpd_int_entry(2), 204 hpd_int_entry(3), 205 hpd_int_entry(4), 206 hpd_int_entry(5), 207 hpd_int_entry(6), 208 hpd_rx_int_entry(1), 209 hpd_rx_int_entry(2), 210 hpd_rx_int_entry(3), 211 hpd_rx_int_entry(4), 212 hpd_rx_int_entry(5), 213 hpd_rx_int_entry(6), 214 i2c_int_entry(1), 215 i2c_int_entry(2), 216 i2c_int_entry(3), 217 i2c_int_entry(4), 218 i2c_int_entry(5), 219 i2c_int_entry(6), 220 dp_sink_int_entry(1), 221 dp_sink_int_entry(2), 222 dp_sink_int_entry(3), 223 dp_sink_int_entry(4), 224 dp_sink_int_entry(5), 225 dp_sink_int_entry(6), 226 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 227 pflip_int_entry(0), 228 pflip_int_entry(1), 229 pflip_int_entry(2), 230 pflip_int_entry(3), 231 pflip_int_entry(4), 232 pflip_int_entry(5), 233 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 234 gpio_pad_int_entry(0), 235 gpio_pad_int_entry(1), 236 gpio_pad_int_entry(2), 237 gpio_pad_int_entry(3), 238 gpio_pad_int_entry(4), 239 gpio_pad_int_entry(5), 240 gpio_pad_int_entry(6), 241 gpio_pad_int_entry(7), 242 gpio_pad_int_entry(8), 243 gpio_pad_int_entry(9), 244 gpio_pad_int_entry(10), 245 gpio_pad_int_entry(11), 246 gpio_pad_int_entry(12), 247 gpio_pad_int_entry(13), 248 gpio_pad_int_entry(14), 249 gpio_pad_int_entry(15), 250 gpio_pad_int_entry(16), 251 gpio_pad_int_entry(17), 252 gpio_pad_int_entry(18), 253 gpio_pad_int_entry(19), 254 gpio_pad_int_entry(20), 255 gpio_pad_int_entry(21), 256 gpio_pad_int_entry(22), 257 gpio_pad_int_entry(23), 258 gpio_pad_int_entry(24), 259 gpio_pad_int_entry(25), 260 gpio_pad_int_entry(26), 261 gpio_pad_int_entry(27), 262 gpio_pad_int_entry(28), 263 gpio_pad_int_entry(29), 264 gpio_pad_int_entry(30), 265 dc_underflow_int_entry(1), 266 dc_underflow_int_entry(2), 267 dc_underflow_int_entry(3), 268 dc_underflow_int_entry(4), 269 dc_underflow_int_entry(5), 270 dc_underflow_int_entry(6), 271 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 272 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 273 vupdate_int_entry(0), 274 vupdate_int_entry(1), 275 vupdate_int_entry(2), 276 vupdate_int_entry(3), 277 vupdate_int_entry(4), 278 vupdate_int_entry(5), 279 vblank_int_entry(0), 280 vblank_int_entry(1), 281 vblank_int_entry(2), 282 vblank_int_entry(3), 283 vblank_int_entry(4), 284 vblank_int_entry(5), 285}; 286 287static const struct irq_service_funcs irq_service_funcs_dce80 = { 288 .to_dal_irq_source = to_dal_irq_source_dce110 289}; 290 291static void dce80_irq_construct( 292 struct irq_service *irq_service, 293 struct irq_service_init_data *init_data) 294{ 295 dal_irq_service_construct(irq_service, init_data); 296 297 irq_service->info = irq_source_info_dce80; 298 irq_service->funcs = &irq_service_funcs_dce80; 299} 300 301struct irq_service *dal_irq_service_dce80_create( 302 struct irq_service_init_data *init_data) 303{ 304 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 305 GFP_KERNEL); 306 307 if (!irq_service) 308 return NULL; 309 310 dce80_irq_construct(irq_service, init_data); 311 return irq_service; 312} 313 314 315