1/*	$NetBSD: core_types.h,v 1.3 2021/12/19 11:59:19 riastradh Exp $	*/
2
3/*
4 * Copyright 2015 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: AMD
25 *
26 */
27
28#ifndef _CORE_TYPES_H_
29#define _CORE_TYPES_H_
30
31#include "dc.h"
32#include "dce_calcs.h"
33#include "dcn_calcs.h"
34#include "ddc_service_types.h"
35#include "dc_bios_types.h"
36#include "mem_input.h"
37#include "hubp.h"
38#if defined(CONFIG_DRM_AMD_DC_DCN)
39#include "mpc.h"
40#endif
41#include "dwb.h"
42#include "mcif_wb.h"
43
44#define MAX_CLOCK_SOURCES 7
45
46void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
47		uint32_t controller_id);
48
49#include "grph_object_id.h"
50#include "link_encoder.h"
51#include "stream_encoder.h"
52#include "clock_source.h"
53#include "hw/audio.h"
54#include "dm_pp_smu.h"
55#ifdef CONFIG_DRM_AMD_DC_HDCP
56#include "dm_cp_psp.h"
57#endif
58
59/************ link *****************/
60struct link_init_data {
61	const struct dc *dc;
62	struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */
63	uint32_t connector_index; /* this will be mapped to the HPD pins */
64	uint32_t link_index; /* this is mapped to DAL display_index
65				TODO: remove it when DC is complete. */
66};
67
68struct dc_link *link_create(const struct link_init_data *init_params);
69void link_destroy(struct dc_link **link);
70
71enum dc_status dc_link_validate_mode_timing(
72		const struct dc_stream_state *stream,
73		struct dc_link *link,
74		const struct dc_crtc_timing *timing);
75
76void core_link_resume(struct dc_link *link);
77
78void core_link_enable_stream(
79		struct dc_state *state,
80		struct pipe_ctx *pipe_ctx);
81
82void core_link_disable_stream(struct pipe_ctx *pipe_ctx);
83
84void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
85/********** DAL Core*********************/
86#include "transform.h"
87#include "dpp.h"
88
89struct resource_pool;
90struct dc_state;
91struct resource_context;
92struct clk_bw_params;
93
94struct resource_funcs {
95	void (*destroy)(struct resource_pool **pool);
96	void (*link_init)(struct dc_link *link);
97	struct link_encoder *(*link_enc_create)(
98			const struct encoder_init_data *init);
99	bool (*validate_bandwidth)(
100					struct dc *dc,
101					struct dc_state *context,
102					bool fast_validate);
103
104	int (*populate_dml_pipes)(
105		struct dc *dc,
106		struct dc_state *context,
107		display_e2e_pipe_params_st *pipes);
108
109	enum dc_status (*validate_global)(
110		struct dc *dc,
111		struct dc_state *context);
112
113	struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
114			struct dc_state *context,
115			const struct resource_pool *pool,
116			struct dc_stream_state *stream);
117
118	enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps);
119
120	enum dc_status (*add_stream_to_ctx)(
121			struct dc *dc,
122			struct dc_state *new_ctx,
123			struct dc_stream_state *dc_stream);
124
125	enum dc_status (*remove_stream_from_ctx)(
126				struct dc *dc,
127				struct dc_state *new_ctx,
128				struct dc_stream_state *stream);
129	enum dc_status (*get_default_swizzle_mode)(
130			struct dc_plane_state *plane_state);
131
132	struct stream_encoder *(*find_first_free_match_stream_enc_for_link)(
133			struct resource_context *res_ctx,
134			const struct resource_pool *pool,
135			struct dc_stream_state *stream);
136	void (*populate_dml_writeback_from_context)(
137			struct dc *dc,
138			struct resource_context *res_ctx,
139			display_e2e_pipe_params_st *pipes);
140
141	void (*set_mcif_arb_params)(
142			struct dc *dc,
143			struct dc_state *context,
144			display_e2e_pipe_params_st *pipes,
145			int pipe_cnt);
146	void (*update_bw_bounding_box)(
147			struct dc *dc,
148			struct clk_bw_params *bw_params);
149
150};
151
152struct audio_support{
153	bool dp_audio;
154	bool hdmi_audio_on_dongle;
155	bool hdmi_audio_native;
156};
157
158#define NO_UNDERLAY_PIPE -1
159
160struct resource_pool {
161	struct mem_input *mis[MAX_PIPES];
162	struct hubp *hubps[MAX_PIPES];
163	struct input_pixel_processor *ipps[MAX_PIPES];
164	struct transform *transforms[MAX_PIPES];
165	struct dpp *dpps[MAX_PIPES];
166	struct output_pixel_processor *opps[MAX_PIPES];
167	struct timing_generator *timing_generators[MAX_PIPES];
168	struct stream_encoder *stream_enc[MAX_PIPES * 2];
169	struct hubbub *hubbub;
170	struct mpc *mpc;
171	struct pp_smu_funcs *pp_smu;
172	struct dce_aux *engines[MAX_PIPES];
173	struct dce_i2c_hw *hw_i2cs[MAX_PIPES];
174	struct dce_i2c_sw *sw_i2cs[MAX_PIPES];
175	bool i2c_hw_buffer_in_use;
176
177	struct dwbc *dwbc[MAX_DWB_PIPES];
178	struct mcif_wb *mcif_wb[MAX_DWB_PIPES];
179	struct {
180		unsigned int gsl_0:1;
181		unsigned int gsl_1:1;
182		unsigned int gsl_2:1;
183	} gsl_groups;
184
185	struct display_stream_compressor *dscs[MAX_PIPES];
186
187	unsigned int pipe_count;
188	unsigned int underlay_pipe_index;
189	unsigned int stream_enc_count;
190
191	struct {
192		unsigned int xtalin_clock_inKhz;
193		unsigned int dccg_ref_clock_inKhz;
194		unsigned int dchub_ref_clock_inKhz;
195	} ref_clocks;
196	unsigned int timing_generator_count;
197	unsigned int mpcc_count;
198
199	unsigned int writeback_pipe_count;
200	/*
201	 * reserved clock source for DP
202	 */
203	struct clock_source *dp_clock_source;
204
205	struct clock_source *clock_sources[MAX_CLOCK_SOURCES];
206	unsigned int clk_src_count;
207
208	struct audio *audios[MAX_AUDIOS];
209	unsigned int audio_count;
210	struct audio_support audio_support;
211
212	struct dccg *dccg;
213	struct irq_service *irqs;
214
215	struct abm *abm;
216	struct dmcu *dmcu;
217	struct dmub_psr *psr;
218
219	const struct resource_funcs *funcs;
220	const struct resource_caps *res_cap;
221
222	struct ddc_service *oem_device;
223};
224
225struct dcn_fe_bandwidth {
226	int dppclk_khz;
227
228};
229
230struct stream_resource {
231	struct output_pixel_processor *opp;
232	struct display_stream_compressor *dsc;
233	struct timing_generator *tg;
234	struct stream_encoder *stream_enc;
235	struct audio *audio;
236
237	struct pixel_clk_params pix_clk_params;
238	struct encoder_info_frame encoder_info_frame;
239
240	struct abm *abm;
241	/* There are only (num_pipes+1)/2 groups. 0 means unassigned,
242	 * otherwise it's using group number 'gsl_group-1'
243	 */
244	uint8_t gsl_group;
245};
246
247struct plane_resource {
248	struct scaler_data scl_data;
249	struct hubp *hubp;
250	struct mem_input *mi;
251	struct input_pixel_processor *ipp;
252	struct transform *xfm;
253	struct dpp *dpp;
254	uint8_t mpcc_inst;
255
256	struct dcn_fe_bandwidth bw;
257};
258
259union pipe_update_flags {
260	struct {
261		uint32_t enable : 1;
262		uint32_t disable : 1;
263		uint32_t odm : 1;
264		uint32_t global_sync : 1;
265		uint32_t opp_changed : 1;
266		uint32_t tg_changed : 1;
267		uint32_t mpcc : 1;
268		uint32_t dppclk : 1;
269		uint32_t hubp_interdependent : 1;
270		uint32_t hubp_rq_dlg_ttu : 1;
271		uint32_t gamut_remap : 1;
272		uint32_t scaler : 1;
273		uint32_t viewport : 1;
274	} bits;
275	uint32_t raw;
276};
277
278struct pipe_ctx {
279	struct dc_plane_state *plane_state;
280	struct dc_stream_state *stream;
281
282	struct plane_resource plane_res;
283	struct stream_resource stream_res;
284
285	struct clock_source *clock_source;
286
287	struct pll_settings pll_settings;
288
289	uint8_t pipe_idx;
290
291	struct pipe_ctx *top_pipe;
292	struct pipe_ctx *bottom_pipe;
293	struct pipe_ctx *next_odm_pipe;
294	struct pipe_ctx *prev_odm_pipe;
295
296#ifdef CONFIG_DRM_AMD_DC_DCN
297	struct _vcs_dpi_display_dlg_regs_st dlg_regs;
298	struct _vcs_dpi_display_ttu_regs_st ttu_regs;
299	struct _vcs_dpi_display_rq_regs_st rq_regs;
300	struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param;
301#endif
302	union pipe_update_flags update_flags;
303	struct dwbc *dwbc;
304	struct mcif_wb *mcif_wb;
305};
306
307struct resource_context {
308	struct pipe_ctx pipe_ctx[MAX_PIPES];
309	bool is_stream_enc_acquired[MAX_PIPES * 2];
310	bool is_audio_acquired[MAX_PIPES];
311	uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES];
312	uint8_t dp_clock_source_ref_count;
313	bool is_dsc_acquired[MAX_PIPES];
314};
315
316struct dce_bw_output {
317	bool cpuc_state_change_enable;
318	bool cpup_state_change_enable;
319	bool stutter_mode_enable;
320	bool nbp_state_change_enable;
321	bool all_displays_in_sync;
322	struct dce_watermarks urgent_wm_ns[MAX_PIPES];
323	struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES];
324	struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES];
325	struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES];
326	int sclk_khz;
327	int sclk_deep_sleep_khz;
328	int yclk_khz;
329	int dispclk_khz;
330	int blackout_recovery_time_us;
331};
332
333struct dcn_bw_writeback {
334	struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES];
335};
336
337struct dcn_bw_output {
338	struct dc_clocks clk;
339	struct dcn_watermark_set watermarks;
340	struct dcn_bw_writeback bw_writeback;
341};
342
343union bw_output {
344	struct dcn_bw_output dcn;
345	struct dce_bw_output dce;
346};
347
348struct bw_context {
349	union bw_output bw;
350	struct display_mode_lib dml;
351};
352/**
353 * struct dc_state - The full description of a state requested by a user
354 *
355 * @streams: Stream properties
356 * @stream_status: The planes on a given stream
357 * @res_ctx: Persistent state of resources
358 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
359 * @pp_display_cfg: PowerPlay clocks and settings
360 * @dcn_bw_vars: non-stack memory to support bandwidth calculations
361 *
362 */
363struct dc_state {
364	struct dc_stream_state *streams[MAX_PIPES];
365	struct dc_stream_status stream_status[MAX_PIPES];
366	uint8_t stream_count;
367
368	struct resource_context res_ctx;
369
370	struct bw_context bw_ctx;
371
372	/* Note: these are big structures, do *not* put on stack! */
373	struct dm_pp_display_configuration pp_display_cfg;
374#ifdef CONFIG_DRM_AMD_DC_DCN
375	struct dcn_bw_internal_vars dcn_bw_vars;
376#endif
377
378	struct clk_mgr *clk_mgr;
379
380	struct kref refcount;
381};
382
383#endif /* _CORE_TYPES_H_ */
384