1/* $NetBSD: dc.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3/* 4 * Copyright 2012-14 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#ifndef DC_INTERFACE_H_ 29#define DC_INTERFACE_H_ 30 31#include "dc_types.h" 32#include "grph_object_defs.h" 33#include "logger_types.h" 34#include "gpio_types.h" 35#include "link_service_types.h" 36#include "grph_object_ctrl_defs.h" 37#include <inc/hw/opp.h> 38 39#include "inc/hw_sequencer.h" 40#include "inc/compressor.h" 41#include "inc/hw/dmcu.h" 42#include "dml/display_mode_lib.h" 43 44#define DC_VER "3.2.69" 45 46#define MAX_SURFACES 3 47#define MAX_PLANES 6 48#define MAX_STREAMS 6 49#define MAX_SINKS_PER_LINK 4 50 51/******************************************************************************* 52 * Display Core Interfaces 53 ******************************************************************************/ 54struct dc_versions { 55 const char *dc_ver; 56 struct dmcu_version dmcu_version; 57}; 58 59enum dp_protocol_version { 60 DP_VERSION_1_4, 61}; 62 63enum dc_plane_type { 64 DC_PLANE_TYPE_INVALID, 65 DC_PLANE_TYPE_DCE_RGB, 66 DC_PLANE_TYPE_DCE_UNDERLAY, 67 DC_PLANE_TYPE_DCN_UNIVERSAL, 68}; 69 70struct dc_plane_cap { 71 enum dc_plane_type type; 72 uint32_t blends_with_above : 1; 73 uint32_t blends_with_below : 1; 74 uint32_t per_pixel_alpha : 1; 75 struct { 76 uint32_t argb8888 : 1; 77 uint32_t nv12 : 1; 78 uint32_t fp16 : 1; 79 uint32_t p010 : 1; 80 uint32_t ayuv : 1; 81 } pixel_format_support; 82 // max upscaling factor x1000 83 // upscaling factors are always >= 1 84 // for example, 1080p -> 8K is 4.0, or 4000 raw value 85 struct { 86 uint32_t argb8888; 87 uint32_t nv12; 88 uint32_t fp16; 89 } max_upscale_factor; 90 // max downscale factor x1000 91 // downscale factors are always <= 1 92 // for example, 8K -> 1080p is 0.25, or 250 raw value 93 struct { 94 uint32_t argb8888; 95 uint32_t nv12; 96 uint32_t fp16; 97 } max_downscale_factor; 98}; 99 100struct dc_caps { 101 uint32_t max_streams; 102 uint32_t max_links; 103 uint32_t max_audios; 104 uint32_t max_slave_planes; 105 uint32_t max_planes; 106 uint32_t max_downscale_ratio; 107 uint32_t i2c_speed_in_khz; 108 uint32_t dmdata_alloc_size; 109 unsigned int max_cursor_size; 110 unsigned int max_video_width; 111 int linear_pitch_alignment; 112 bool dcc_const_color; 113 bool dynamic_audio; 114 bool is_apu; 115 bool dual_link_dvi; 116 bool post_blend_color_processing; 117 bool force_dp_tps4_for_cp2520; 118 bool disable_dp_clk_share; 119 bool psp_setup_panel_mode; 120 bool extended_aux_timeout_support; 121 bool dmcub_support; 122 bool hw_3d_lut; 123 enum dp_protocol_version max_dp_protocol_version; 124 struct dc_plane_cap planes[MAX_PLANES]; 125}; 126 127struct dc_bug_wa { 128 bool no_connect_phy_config; 129 bool dedcn20_305_wa; 130 bool skip_clock_update; 131}; 132 133struct dc_dcc_surface_param { 134 struct dc_size surface_size; 135 enum surface_pixel_format format; 136 enum swizzle_mode_values swizzle_mode; 137 enum dc_scan_direction scan; 138}; 139 140struct dc_dcc_setting { 141 unsigned int max_compressed_blk_size; 142 unsigned int max_uncompressed_blk_size; 143 bool independent_64b_blks; 144}; 145 146struct dc_surface_dcc_cap { 147 union { 148 struct { 149 struct dc_dcc_setting rgb; 150 } grph; 151 152 struct { 153 struct dc_dcc_setting luma; 154 struct dc_dcc_setting chroma; 155 } video; 156 }; 157 158 bool capable; 159 bool const_color_support; 160}; 161 162struct dc_static_screen_params { 163 struct { 164 bool force_trigger; 165 bool cursor_update; 166 bool surface_update; 167 bool overlay_update; 168 } triggers; 169 unsigned int num_frames; 170}; 171 172 173/* Surface update type is used by dc_update_surfaces_and_stream 174 * The update type is determined at the very beginning of the function based 175 * on parameters passed in and decides how much programming (or updating) is 176 * going to be done during the call. 177 * 178 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 179 * logical calculations or hardware register programming. This update MUST be 180 * ISR safe on windows. Currently fast update will only be used to flip surface 181 * address. 182 * 183 * UPDATE_TYPE_MED is used for slower updates which require significant hw 184 * re-programming however do not affect bandwidth consumption or clock 185 * requirements. At present, this is the level at which front end updates 186 * that do not require us to run bw_calcs happen. These are in/out transfer func 187 * updates, viewport offset changes, recout size changes and pixel depth changes. 188 * This update can be done at ISR, but we want to minimize how often this happens. 189 * 190 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 191 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 192 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 193 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 194 * a full update. This cannot be done at ISR level and should be a rare event. 195 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 196 * underscan we don't expect to see this call at all. 197 */ 198 199enum surface_update_type { 200 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 201 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 202 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 203}; 204 205/* Forward declaration*/ 206struct dc; 207struct dc_plane_state; 208struct dc_state; 209 210 211struct dc_cap_funcs { 212 bool (*get_dcc_compression_cap)(const struct dc *dc, 213 const struct dc_dcc_surface_param *input, 214 struct dc_surface_dcc_cap *output); 215}; 216 217struct link_training_settings; 218 219 220/* Structure to hold configuration flags set by dm at dc creation. */ 221struct dc_config { 222 bool gpu_vm_support; 223 bool disable_disp_pll_sharing; 224 bool fbc_support; 225 bool optimize_edp_link_rate; 226 bool disable_fractional_pwm; 227 bool allow_seamless_boot_optimization; 228 bool power_down_display_on_boot; 229 bool edp_not_connected; 230 bool force_enum_edp; 231 bool forced_clocks; 232 bool disable_extended_timeout_support; // Used to disable extended timeout and lttpr feature as well 233 bool multi_mon_pp_mclk_switch; 234}; 235 236enum visual_confirm { 237 VISUAL_CONFIRM_DISABLE = 0, 238 VISUAL_CONFIRM_SURFACE = 1, 239 VISUAL_CONFIRM_HDR = 2, 240 VISUAL_CONFIRM_MPCTREE = 4, 241}; 242 243enum dcc_option { 244 DCC_ENABLE = 0, 245 DCC_DISABLE = 1, 246 DCC_HALF_REQ_DISALBE = 2, 247}; 248 249enum pipe_split_policy { 250 MPC_SPLIT_DYNAMIC = 0, 251 MPC_SPLIT_AVOID = 1, 252 MPC_SPLIT_AVOID_MULT_DISP = 2, 253}; 254 255enum wm_report_mode { 256 WM_REPORT_DEFAULT = 0, 257 WM_REPORT_OVERRIDE = 1, 258}; 259enum dtm_pstate{ 260 dtm_level_p0 = 0,/*highest voltage*/ 261 dtm_level_p1, 262 dtm_level_p2, 263 dtm_level_p3, 264 dtm_level_p4,/*when active_display_count = 0*/ 265}; 266 267enum dcn_pwr_state { 268 DCN_PWR_STATE_UNKNOWN = -1, 269 DCN_PWR_STATE_MISSION_MODE = 0, 270 DCN_PWR_STATE_LOW_POWER = 3, 271}; 272 273/* 274 * For any clocks that may differ per pipe 275 * only the max is stored in this structure 276 */ 277struct dc_clocks { 278 int dispclk_khz; 279 int dppclk_khz; 280 int dcfclk_khz; 281 int socclk_khz; 282 int dcfclk_deep_sleep_khz; 283 int fclk_khz; 284 int phyclk_khz; 285 int dramclk_khz; 286 bool p_state_change_support; 287 enum dcn_pwr_state pwr_state; 288 /* 289 * Elements below are not compared for the purposes of 290 * optimization required 291 */ 292 bool prev_p_state_change_support; 293 enum dtm_pstate dtm_level; 294 int max_supported_dppclk_khz; 295 int max_supported_dispclk_khz; 296 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 297 int bw_dispclk_khz; 298}; 299 300struct dc_bw_validation_profile { 301 bool enable; 302 303 unsigned long long total_ticks; 304 unsigned long long voltage_level_ticks; 305 unsigned long long watermark_ticks; 306 unsigned long long rq_dlg_ticks; 307 308 unsigned long long total_count; 309 unsigned long long skip_fast_count; 310 unsigned long long skip_pass_count; 311 unsigned long long skip_fail_count; 312}; 313 314#define BW_VAL_TRACE_SETUP() \ 315 unsigned long long end_tick = 0; \ 316 unsigned long long voltage_level_tick = 0; \ 317 unsigned long long watermark_tick = 0; \ 318 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 319 dm_get_timestamp(dc->ctx) : 0 320 321#define BW_VAL_TRACE_COUNT() \ 322 if (dc->debug.bw_val_profile.enable) \ 323 dc->debug.bw_val_profile.total_count++ 324 325#define BW_VAL_TRACE_SKIP(status) \ 326 if (dc->debug.bw_val_profile.enable) { \ 327 if (!voltage_level_tick) \ 328 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 329 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 330 } 331 332#define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 333 if (dc->debug.bw_val_profile.enable) \ 334 voltage_level_tick = dm_get_timestamp(dc->ctx) 335 336#define BW_VAL_TRACE_END_WATERMARKS() \ 337 if (dc->debug.bw_val_profile.enable) \ 338 watermark_tick = dm_get_timestamp(dc->ctx) 339 340#define BW_VAL_TRACE_FINISH() \ 341 if (dc->debug.bw_val_profile.enable) { \ 342 end_tick = dm_get_timestamp(dc->ctx); \ 343 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 344 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 345 if (watermark_tick) { \ 346 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 347 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 348 } \ 349 } 350 351struct dc_debug_options { 352 enum visual_confirm visual_confirm; 353 bool sanity_checks; 354 bool max_disp_clk; 355 bool surface_trace; 356 bool timing_trace; 357 bool clock_trace; 358 bool validation_trace; 359 bool bandwidth_calcs_trace; 360 int max_downscale_src_width; 361 362 /* stutter efficiency related */ 363 bool disable_stutter; 364 bool use_max_lb; 365 enum dcc_option disable_dcc; 366 enum pipe_split_policy pipe_split_policy; 367 bool force_single_disp_pipe_split; 368 bool voltage_align_fclk; 369 370 bool disable_dfs_bypass; 371 bool disable_dpp_power_gate; 372 bool disable_hubp_power_gate; 373 bool disable_dsc_power_gate; 374 int dsc_min_slice_height_override; 375 int dsc_bpp_increment_div; 376 bool native422_support; 377 bool disable_pplib_wm_range; 378 enum wm_report_mode pplib_wm_report_mode; 379 unsigned int min_disp_clk_khz; 380 unsigned int min_dpp_clk_khz; 381 int sr_exit_time_dpm0_ns; 382 int sr_enter_plus_exit_time_dpm0_ns; 383 int sr_exit_time_ns; 384 int sr_enter_plus_exit_time_ns; 385 int urgent_latency_ns; 386 uint32_t underflow_assert_delay_us; 387 int percent_of_ideal_drambw; 388 int dram_clock_change_latency_ns; 389 bool optimized_watermark; 390 int always_scale; 391 bool disable_pplib_clock_request; 392 bool disable_clock_gate; 393 bool disable_dmcu; 394 bool disable_psr; 395 bool force_abm_enable; 396 bool disable_stereo_support; 397 bool vsr_support; 398 bool performance_trace; 399 bool az_endpoint_mute_only; 400 bool always_use_regamma; 401 bool p010_mpo_support; 402 bool recovery_enabled; 403 bool avoid_vbios_exec_table; 404 bool scl_reset_length10; 405 bool hdmi20_disable; 406 bool skip_detection_link_training; 407 bool remove_disconnect_edp; 408 unsigned int force_odm_combine; //bit vector based on otg inst 409 unsigned int force_fclk_khz; 410 bool disable_tri_buf; 411 bool dmub_offload_enabled; 412 bool dmcub_emulation; 413 bool dmub_command_table; /* for testing only */ 414 struct dc_bw_validation_profile bw_val_profile; 415 bool disable_fec; 416 bool disable_48mhz_pwrdwn; 417 /* This forces a hard min on the DCFCLK requested to SMU/PP 418 * watermarks are not affected. 419 */ 420 unsigned int force_min_dcfclk_mhz; 421 bool disable_timing_sync; 422 bool cm_in_bypass; 423 int force_clock_mode;/*every mode change.*/ 424 425 bool nv12_iflip_vm_wa; 426 bool disable_dram_clock_change_vactive_support; 427 bool validate_dml_output; 428 bool enable_dmcub_surface_flip; 429 bool usbc_combo_phy_reset_wa; 430 bool disable_dsc; 431}; 432 433struct dc_debug_data { 434 uint32_t ltFailCount; 435 uint32_t i2cErrorCount; 436 uint32_t auxErrorCount; 437}; 438 439struct dc_phy_addr_space_config { 440 struct { 441 uint64_t start_addr; 442 uint64_t end_addr; 443 uint64_t fb_top; 444 uint64_t fb_offset; 445 uint64_t fb_base; 446 uint64_t agp_top; 447 uint64_t agp_bot; 448 uint64_t agp_base; 449 } system_aperture; 450 451 struct { 452 uint64_t page_table_start_addr; 453 uint64_t page_table_end_addr; 454 uint64_t page_table_base_addr; 455 } gart_config; 456 457 bool valid; 458 uint64_t page_table_default_page_addr; 459}; 460 461struct dc_virtual_addr_space_config { 462 uint64_t page_table_base_addr; 463 uint64_t page_table_start_addr; 464 uint64_t page_table_end_addr; 465 uint32_t page_table_block_size_in_bytes; 466 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 467}; 468 469struct dc_bounding_box_overrides { 470 int sr_exit_time_ns; 471 int sr_enter_plus_exit_time_ns; 472 int urgent_latency_ns; 473 int percent_of_ideal_drambw; 474 int dram_clock_change_latency_ns; 475 /* This forces a hard min on the DCFCLK we use 476 * for DML. Unlike the debug option for forcing 477 * DCFCLK, this override affects watermark calculations 478 */ 479 int min_dcfclk_mhz; 480}; 481 482struct dc_state; 483struct resource_pool; 484struct dce_hwseq; 485struct gpu_info_soc_bounding_box_v1_0; 486struct dc { 487 struct dc_versions versions; 488 struct dc_caps caps; 489 struct dc_cap_funcs cap_funcs; 490 struct dc_config config; 491 struct dc_debug_options debug; 492 struct dc_bounding_box_overrides bb_overrides; 493 struct dc_bug_wa work_arounds; 494 struct dc_context *ctx; 495 struct dc_phy_addr_space_config vm_pa_config; 496 497 uint8_t link_count; 498 struct dc_link *links[MAX_PIPES * 2]; 499 500 struct dc_state *current_state; 501 struct resource_pool *res_pool; 502 503 struct clk_mgr *clk_mgr; 504 505 /* Display Engine Clock levels */ 506 struct dm_pp_clock_levels sclk_lvls; 507 508 /* Inputs into BW and WM calculations. */ 509 struct bw_calcs_dceip *bw_dceip; 510 struct bw_calcs_vbios *bw_vbios; 511#ifdef CONFIG_DRM_AMD_DC_DCN 512 struct dcn_soc_bounding_box *dcn_soc; 513 struct dcn_ip_params *dcn_ip; 514 struct display_mode_lib dml; 515#endif 516 517 /* HW functions */ 518 struct hw_sequencer_funcs hwss; 519 struct dce_hwseq *hwseq; 520 521 /* Require to optimize clocks and bandwidth for added/removed planes */ 522 bool optimized_required; 523 524 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 525 int optimize_seamless_boot_streams; 526 527 /* FBC compressor */ 528 struct compressor *fbc_compressor; 529 530 struct dc_debug_data debug_data; 531 532 const char *build_id; 533 struct vm_helper *vm_helper; 534 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 535}; 536 537enum frame_buffer_mode { 538 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 539 FRAME_BUFFER_MODE_ZFB_ONLY, 540 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 541} ; 542 543struct dchub_init_data { 544 int64_t zfb_phys_addr_base; 545 int64_t zfb_mc_base_addr; 546 uint64_t zfb_size_in_byte; 547 enum frame_buffer_mode fb_mode; 548 bool dchub_initialzied; 549 bool dchub_info_valid; 550}; 551 552struct dc_init_data { 553 struct hw_asic_id asic_id; 554 void *driver; /* ctx */ 555 struct cgs_device *cgs_device; 556 struct dc_bounding_box_overrides bb_overrides; 557 558 int num_virtual_links; 559 /* 560 * If 'vbios_override' not NULL, it will be called instead 561 * of the real VBIOS. Intended use is Diagnostics on FPGA. 562 */ 563 struct dc_bios *vbios_override; 564 enum dce_environment dce_environment; 565 566 struct dmub_offload_funcs *dmub_if; 567 struct dc_reg_helper_state *dmub_offload; 568 569 struct dc_config flags; 570 uint32_t log_mask; 571 /** 572 * gpu_info FW provided soc bounding box struct or 0 if not 573 * available in FW 574 */ 575 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 576}; 577 578struct dc_callback_init { 579#ifdef CONFIG_DRM_AMD_DC_HDCP 580 struct cp_psp cp_psp; 581#else 582 uint8_t reserved; 583#endif 584}; 585 586struct dc *dc_create(const struct dc_init_data *init_params); 587void dc_hardware_init(struct dc *dc); 588 589int dc_get_vmid_use_vector(struct dc *dc); 590void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 591/* Returns the number of vmids supported */ 592int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 593void dc_init_callbacks(struct dc *dc, 594 const struct dc_callback_init *init_params); 595void dc_deinit_callbacks(struct dc *dc); 596void dc_destroy(struct dc **dc); 597 598/******************************************************************************* 599 * Surface Interfaces 600 ******************************************************************************/ 601 602enum { 603 TRANSFER_FUNC_POINTS = 1025 604}; 605 606struct dc_hdr_static_metadata { 607 /* display chromaticities and white point in units of 0.00001 */ 608 unsigned int chromaticity_green_x; 609 unsigned int chromaticity_green_y; 610 unsigned int chromaticity_blue_x; 611 unsigned int chromaticity_blue_y; 612 unsigned int chromaticity_red_x; 613 unsigned int chromaticity_red_y; 614 unsigned int chromaticity_white_point_x; 615 unsigned int chromaticity_white_point_y; 616 617 uint32_t min_luminance; 618 uint32_t max_luminance; 619 uint32_t maximum_content_light_level; 620 uint32_t maximum_frame_average_light_level; 621}; 622 623enum dc_transfer_func_type { 624 TF_TYPE_PREDEFINED, 625 TF_TYPE_DISTRIBUTED_POINTS, 626 TF_TYPE_BYPASS, 627 TF_TYPE_HWPWL 628}; 629 630struct dc_transfer_func_distributed_points { 631 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 632 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 633 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 634 635 uint16_t end_exponent; 636 uint16_t x_point_at_y1_red; 637 uint16_t x_point_at_y1_green; 638 uint16_t x_point_at_y1_blue; 639}; 640 641enum dc_transfer_func_predefined { 642 TRANSFER_FUNCTION_SRGB, 643 TRANSFER_FUNCTION_BT709, 644 TRANSFER_FUNCTION_PQ, 645 TRANSFER_FUNCTION_LINEAR, 646 TRANSFER_FUNCTION_UNITY, 647 TRANSFER_FUNCTION_HLG, 648 TRANSFER_FUNCTION_HLG12, 649 TRANSFER_FUNCTION_GAMMA22, 650 TRANSFER_FUNCTION_GAMMA24, 651 TRANSFER_FUNCTION_GAMMA26 652}; 653 654 655struct dc_transfer_func { 656 struct kref refcount; 657 enum dc_transfer_func_type type; 658 enum dc_transfer_func_predefined tf; 659 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 660 uint32_t sdr_ref_white_level; 661 struct dc_context *ctx; 662 union { 663 struct pwl_params pwl; 664 struct dc_transfer_func_distributed_points tf_pts; 665 }; 666}; 667 668 669union dc_3dlut_state { 670 struct { 671 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 672 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 673 uint32_t rmu_mux_num:3; /*index of mux to use*/ 674 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 675 uint32_t mpc_rmu1_mux:4; 676 uint32_t mpc_rmu2_mux:4; 677 uint32_t reserved:15; 678 } bits; 679 uint32_t raw; 680}; 681 682 683struct dc_3dlut { 684 struct kref refcount; 685 struct tetrahedral_params lut_3d; 686 struct fixed31_32 hdr_multiplier; 687 bool initialized; /*remove after diag fix*/ 688 union dc_3dlut_state state; 689 struct dc_context *ctx; 690}; 691/* 692 * This structure is filled in by dc_surface_get_status and contains 693 * the last requested address and the currently active address so the called 694 * can determine if there are any outstanding flips 695 */ 696struct dc_plane_status { 697 struct dc_plane_address requested_address; 698 struct dc_plane_address current_address; 699 bool is_flip_pending; 700 bool is_right_eye; 701}; 702 703union surface_update_flags { 704 705 struct { 706 uint32_t addr_update:1; 707 /* Medium updates */ 708 uint32_t dcc_change:1; 709 uint32_t color_space_change:1; 710 uint32_t horizontal_mirror_change:1; 711 uint32_t per_pixel_alpha_change:1; 712 uint32_t global_alpha_change:1; 713 uint32_t hdr_mult:1; 714 uint32_t rotation_change:1; 715 uint32_t swizzle_change:1; 716 uint32_t scaling_change:1; 717 uint32_t position_change:1; 718 uint32_t in_transfer_func_change:1; 719 uint32_t input_csc_change:1; 720 uint32_t coeff_reduction_change:1; 721 uint32_t output_tf_change:1; 722 uint32_t pixel_format_change:1; 723 uint32_t plane_size_change:1; 724 725 /* Full updates */ 726 uint32_t new_plane:1; 727 uint32_t bpp_change:1; 728 uint32_t gamma_change:1; 729 uint32_t bandwidth_change:1; 730 uint32_t clock_change:1; 731 uint32_t stereo_format_change:1; 732 uint32_t full_update:1; 733 } bits; 734 735 uint32_t raw; 736}; 737 738struct dc_plane_state { 739 struct dc_plane_address address; 740 struct dc_plane_flip_time time; 741 bool triplebuffer_flips; 742 struct scaling_taps scaling_quality; 743 struct rect src_rect; 744 struct rect dst_rect; 745 struct rect clip_rect; 746 747 struct plane_size plane_size; 748 union dc_tiling_info tiling_info; 749 750 struct dc_plane_dcc_param dcc; 751 752 struct dc_gamma *gamma_correction; 753 struct dc_transfer_func *in_transfer_func; 754 struct dc_bias_and_scale *bias_and_scale; 755 struct dc_csc_transform input_csc_color_matrix; 756 struct fixed31_32 coeff_reduction_factor; 757 struct fixed31_32 hdr_mult; 758 759 // TODO: No longer used, remove 760 struct dc_hdr_static_metadata hdr_static_ctx; 761 762 enum dc_color_space color_space; 763 764 struct dc_3dlut *lut3d_func; 765 struct dc_transfer_func *in_shaper_func; 766 struct dc_transfer_func *blend_tf; 767 768 enum surface_pixel_format format; 769 enum dc_rotation_angle rotation; 770 enum plane_stereo_format stereo_format; 771 772 bool is_tiling_rotated; 773 bool per_pixel_alpha; 774 bool global_alpha; 775 int global_alpha_value; 776 bool visible; 777 bool flip_immediate; 778 bool horizontal_mirror; 779 int layer_index; 780 781 union surface_update_flags update_flags; 782 /* private to DC core */ 783 struct dc_plane_status status; 784 struct dc_context *ctx; 785 786 /* HACK: Workaround for forcing full reprogramming under some conditions */ 787 bool force_full_update; 788 789 /* private to dc_surface.c */ 790 enum dc_irq_source irq_source; 791 struct kref refcount; 792}; 793 794struct dc_plane_info { 795 struct plane_size plane_size; 796 union dc_tiling_info tiling_info; 797 struct dc_plane_dcc_param dcc; 798 enum surface_pixel_format format; 799 enum dc_rotation_angle rotation; 800 enum plane_stereo_format stereo_format; 801 enum dc_color_space color_space; 802 bool horizontal_mirror; 803 bool visible; 804 bool per_pixel_alpha; 805 bool global_alpha; 806 int global_alpha_value; 807 bool input_csc_enabled; 808 int layer_index; 809}; 810 811struct dc_scaling_info { 812 struct rect src_rect; 813 struct rect dst_rect; 814 struct rect clip_rect; 815 struct scaling_taps scaling_quality; 816}; 817 818struct dc_surface_update { 819 struct dc_plane_state *surface; 820 821 /* isr safe update parameters. null means no updates */ 822 const struct dc_flip_addrs *flip_addr; 823 const struct dc_plane_info *plane_info; 824 const struct dc_scaling_info *scaling_info; 825 struct fixed31_32 hdr_mult; 826 /* following updates require alloc/sleep/spin that is not isr safe, 827 * null means no updates 828 */ 829 const struct dc_gamma *gamma; 830 const struct dc_transfer_func *in_transfer_func; 831 832 const struct dc_csc_transform *input_csc_color_matrix; 833 const struct fixed31_32 *coeff_reduction_factor; 834 const struct dc_transfer_func *func_shaper; 835 const struct dc_3dlut *lut3d_func; 836 const struct dc_transfer_func *blend_tf; 837}; 838 839/* 840 * Create a new surface with default parameters; 841 */ 842struct dc_plane_state *dc_create_plane_state(struct dc *dc); 843const struct dc_plane_status *dc_plane_get_status( 844 const struct dc_plane_state *plane_state); 845 846void dc_plane_state_retain(struct dc_plane_state *plane_state); 847void dc_plane_state_release(struct dc_plane_state *plane_state); 848 849void dc_gamma_retain(struct dc_gamma *dc_gamma); 850void dc_gamma_release(struct dc_gamma **dc_gamma); 851struct dc_gamma *dc_create_gamma(void); 852 853void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 854void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 855struct dc_transfer_func *dc_create_transfer_func(void); 856 857struct dc_3dlut *dc_create_3dlut_func(void); 858void dc_3dlut_func_release(struct dc_3dlut *lut); 859void dc_3dlut_func_retain(struct dc_3dlut *lut); 860/* 861 * This structure holds a surface address. There could be multiple addresses 862 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such 863 * as frame durations and DCC format can also be set. 864 */ 865struct dc_flip_addrs { 866 struct dc_plane_address address; 867 unsigned int flip_timestamp_in_us; 868 bool flip_immediate; 869 /* TODO: add flip duration for FreeSync */ 870}; 871 872bool dc_post_update_surfaces_to_stream( 873 struct dc *dc); 874 875#include "dc_stream.h" 876 877/* 878 * Structure to store surface/stream associations for validation 879 */ 880struct dc_validation_set { 881 struct dc_stream_state *stream; 882 struct dc_plane_state *plane_states[MAX_SURFACES]; 883 uint8_t plane_count; 884}; 885 886bool dc_validate_seamless_boot_timing(const struct dc *dc, 887 const struct dc_sink *sink, 888 struct dc_crtc_timing *crtc_timing); 889 890enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 891 892void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info); 893 894bool dc_set_generic_gpio_for_stereo(bool enable, 895 struct gpio_service *gpio_service); 896 897/* 898 * fast_validate: we return after determining if we can support the new state, 899 * but before we populate the programming info 900 */ 901enum dc_status dc_validate_global_state( 902 struct dc *dc, 903 struct dc_state *new_ctx, 904 bool fast_validate); 905 906 907void dc_resource_state_construct( 908 const struct dc *dc, 909 struct dc_state *dst_ctx); 910 911void dc_resource_state_copy_construct( 912 const struct dc_state *src_ctx, 913 struct dc_state *dst_ctx); 914 915void dc_resource_state_copy_construct_current( 916 const struct dc *dc, 917 struct dc_state *dst_ctx); 918 919void dc_resource_state_destruct(struct dc_state *context); 920 921bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 922 923/* 924 * TODO update to make it about validation sets 925 * Set up streams and links associated to drive sinks 926 * The streams parameter is an absolute set of all active streams. 927 * 928 * After this call: 929 * Phy, Encoder, Timing Generator are programmed and enabled. 930 * New streams are enabled with blank stream; no memory read. 931 */ 932bool dc_commit_state(struct dc *dc, struct dc_state *context); 933 934 935struct dc_state *dc_create_state(struct dc *dc); 936struct dc_state *dc_copy_state(struct dc_state *src_ctx); 937void dc_retain_state(struct dc_state *context); 938void dc_release_state(struct dc_state *context); 939 940/******************************************************************************* 941 * Link Interfaces 942 ******************************************************************************/ 943 944struct dpcd_caps { 945 union dpcd_rev dpcd_rev; 946 union max_lane_count max_ln_count; 947 union max_down_spread max_down_spread; 948 union dprx_feature dprx_feature; 949 950 /* valid only for eDP v1.4 or higher*/ 951 uint8_t edp_supported_link_rates_count; 952 enum dc_link_rate edp_supported_link_rates[8]; 953 954 /* dongle type (DP converter, CV smart dongle) */ 955 enum display_dongle_type dongle_type; 956 /* branch device or sink device */ 957 bool is_branch_dev; 958 /* Dongle's downstream count. */ 959 union sink_count sink_count; 960 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 961 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 962 struct dc_dongle_caps dongle_caps; 963 964 uint32_t sink_dev_id; 965 int8_t sink_dev_id_str[6]; 966 int8_t sink_hw_revision; 967 int8_t sink_fw_revision[2]; 968 969 uint32_t branch_dev_id; 970 int8_t branch_dev_name[6]; 971 int8_t branch_hw_revision; 972 int8_t branch_fw_revision[2]; 973 974 bool allow_invalid_MSA_timing_param; 975 bool panel_mode_edp; 976 bool dpcd_display_control_capable; 977 bool ext_receiver_cap_field_present; 978 union dpcd_fec_capability fec_cap; 979 struct dpcd_dsc_capabilities dsc_caps; 980 struct dc_lttpr_caps lttpr_caps; 981 982}; 983 984#include "dc_link.h" 985 986/******************************************************************************* 987 * Sink Interfaces - A sink corresponds to a display output device 988 ******************************************************************************/ 989 990struct dc_container_id { 991 // 128bit GUID in binary form 992 unsigned char guid[16]; 993 // 8 byte port ID -> ELD.PortID 994 unsigned int portId[2]; 995 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 996 unsigned short manufacturerName; 997 // 2 byte product code -> ELD.ProductCode 998 unsigned short productCode; 999}; 1000 1001 1002struct dc_sink_dsc_caps { 1003 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 1004 // 'false' if they are sink's DSC caps 1005 bool is_virtual_dpcd_dsc; 1006 struct dsc_dec_dpcd_caps dsc_dec_caps; 1007}; 1008 1009/* 1010 * The sink structure contains EDID and other display device properties 1011 */ 1012struct dc_sink { 1013 enum signal_type sink_signal; 1014 struct dc_edid dc_edid; /* raw edid */ 1015 struct dc_edid_caps edid_caps; /* parse display caps */ 1016 struct dc_container_id *dc_container_id; 1017 uint32_t dongle_max_pix_clk; 1018 void *priv; 1019 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 1020 bool converter_disable_audio; 1021 1022 struct dc_sink_dsc_caps sink_dsc_caps; 1023 1024 /* private to DC core */ 1025 struct dc_link *link; 1026 struct dc_context *ctx; 1027 1028 uint32_t sink_id; 1029 1030 /* private to dc_sink.c */ 1031 // refcount must be the last member in dc_sink, since we want the 1032 // sink structure to be logically cloneable up to (but not including) 1033 // refcount 1034 struct kref refcount; 1035}; 1036 1037void dc_sink_retain(struct dc_sink *sink); 1038void dc_sink_release(struct dc_sink *sink); 1039 1040struct dc_sink_init_data { 1041 enum signal_type sink_signal; 1042 struct dc_link *link; 1043 uint32_t dongle_max_pix_clk; 1044 bool converter_disable_audio; 1045}; 1046 1047struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 1048 1049/* Newer interfaces */ 1050struct dc_cursor { 1051 struct dc_plane_address address; 1052 struct dc_cursor_attributes attributes; 1053}; 1054 1055 1056/******************************************************************************* 1057 * Interrupt interfaces 1058 ******************************************************************************/ 1059enum dc_irq_source dc_interrupt_to_irq_source( 1060 struct dc *dc, 1061 uint32_t src_id, 1062 uint32_t ext_id); 1063bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 1064void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 1065enum dc_irq_source dc_get_hpd_irq_source_at_index( 1066 struct dc *dc, uint32_t link_index); 1067 1068/******************************************************************************* 1069 * Power Interfaces 1070 ******************************************************************************/ 1071 1072void dc_set_power_state( 1073 struct dc *dc, 1074 enum dc_acpi_cm_power_state power_state); 1075void dc_resume(struct dc *dc); 1076unsigned int dc_get_current_backlight_pwm(struct dc *dc); 1077unsigned int dc_get_target_backlight_pwm(struct dc *dc); 1078 1079bool dc_is_dmcu_initialized(struct dc *dc); 1080bool dc_is_hw_initialized(struct dc *dc); 1081 1082enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 1083void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 1084/******************************************************************************* 1085 * DSC Interfaces 1086 ******************************************************************************/ 1087#include "dc_dsc.h" 1088#endif /* DC_INTERFACE_H_ */ 1089