1/* $NetBSD: amdgpu_dc_link.c,v 1.3 2021/12/19 10:59:01 riastradh Exp $ */ 2 3/* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28#include <sys/cdefs.h> 29__KERNEL_RCSID(0, "$NetBSD: amdgpu_dc_link.c,v 1.3 2021/12/19 10:59:01 riastradh Exp $"); 30 31#include <linux/slab.h> 32 33#include "dm_services.h" 34#include "atom.h" 35#include "dm_helpers.h" 36#include "dc.h" 37#include "grph_object_id.h" 38#include "gpio_service_interface.h" 39#include "core_status.h" 40#include "dc_link_dp.h" 41#include "dc_link_ddc.h" 42#include "link_hwss.h" 43#include "opp.h" 44 45#include "link_encoder.h" 46#include "hw_sequencer.h" 47#include "resource.h" 48#include "abm.h" 49#include "fixed31_32.h" 50#include "dpcd_defs.h" 51#include "dmcu.h" 52#include "hw/clk_mgr.h" 53#include "../dce/dmub_psr.h" 54 55#define DC_LOGGER_INIT(logger) 56 57 58#define LINK_INFO(...) \ 59 DC_LOG_HW_HOTPLUG( \ 60 __VA_ARGS__) 61 62#define RETIMER_REDRIVER_INFO(...) \ 63 DC_LOG_RETIMER_REDRIVER( \ 64 __VA_ARGS__) 65/******************************************************************************* 66 * Private structures 67 ******************************************************************************/ 68 69enum { 70 PEAK_FACTOR_X1000 = 1006, 71 /* 72 * Some receivers fail to train on first try and are good 73 * on subsequent tries. 2 retries should be plenty. If we 74 * don't have a successful training then we don't expect to 75 * ever get one. 76 */ 77 LINK_TRAINING_MAX_VERIFY_RETRY = 2 78}; 79 80/******************************************************************************* 81 * Private functions 82 ******************************************************************************/ 83static void dc_link_destruct(struct dc_link *link) 84{ 85 int i; 86 87 if (link->hpd_gpio != NULL) { 88 dal_gpio_destroy_irq(&link->hpd_gpio); 89 link->hpd_gpio = NULL; 90 } 91 92 if (link->ddc) 93 dal_ddc_service_destroy(&link->ddc); 94 95 if(link->link_enc) 96 link->link_enc->funcs->destroy(&link->link_enc); 97 98 if (link->local_sink) 99 dc_sink_release(link->local_sink); 100 101 for (i = 0; i < link->sink_count; ++i) 102 dc_sink_release(link->remote_sinks[i]); 103} 104 105struct gpio *get_hpd_gpio(struct dc_bios *dcb, 106 struct graphics_object_id link_id, 107 struct gpio_service *gpio_service) 108{ 109 enum bp_result bp_result; 110 struct graphics_object_hpd_info hpd_info; 111 struct gpio_pin_info pin_info; 112 113 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK) 114 return NULL; 115 116 bp_result = dcb->funcs->get_gpio_pin_info(dcb, 117 hpd_info.hpd_int_gpio_uid, &pin_info); 118 119 if (bp_result != BP_RESULT_OK) { 120 ASSERT(bp_result == BP_RESULT_NORECORD); 121 return NULL; 122 } 123 124 return dal_gpio_service_create_irq( 125 gpio_service, 126 pin_info.offset, 127 pin_info.mask); 128} 129 130/* 131 * Function: program_hpd_filter 132 * 133 * @brief 134 * Programs HPD filter on associated HPD line 135 * 136 * @param [in] delay_on_connect_in_ms: Connect filter timeout 137 * @param [in] delay_on_disconnect_in_ms: Disconnect filter timeout 138 * 139 * @return 140 * true on success, false otherwise 141 */ 142static bool program_hpd_filter( 143 const struct dc_link *link) 144{ 145 bool result = false; 146 147 struct gpio *hpd; 148 149 int delay_on_connect_in_ms = 0; 150 int delay_on_disconnect_in_ms = 0; 151 152 if (link->is_hpd_filter_disabled) 153 return false; 154 /* Verify feature is supported */ 155 switch (link->connector_signal) { 156 case SIGNAL_TYPE_DVI_SINGLE_LINK: 157 case SIGNAL_TYPE_DVI_DUAL_LINK: 158 case SIGNAL_TYPE_HDMI_TYPE_A: 159 /* Program hpd filter */ 160 delay_on_connect_in_ms = 500; 161 delay_on_disconnect_in_ms = 100; 162 break; 163 case SIGNAL_TYPE_DISPLAY_PORT: 164 case SIGNAL_TYPE_DISPLAY_PORT_MST: 165 /* Program hpd filter to allow DP signal to settle */ 166 /* 500: not able to detect MST <-> SST switch as HPD is low for 167 * only 100ms on DELL U2413 168 * 0: some passive dongle still show aux mode instead of i2c 169 * 20-50:not enough to hide bouncing HPD with passive dongle. 170 * also see intermittent i2c read issues. 171 */ 172 delay_on_connect_in_ms = 80; 173 delay_on_disconnect_in_ms = 0; 174 break; 175 case SIGNAL_TYPE_LVDS: 176 case SIGNAL_TYPE_EDP: 177 default: 178 /* Don't program hpd filter */ 179 return false; 180 } 181 182 /* Obtain HPD handle */ 183 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); 184 185 if (!hpd) 186 return result; 187 188 /* Setup HPD filtering */ 189 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) { 190 struct gpio_hpd_config config; 191 192 config.delay_on_connect = delay_on_connect_in_ms; 193 config.delay_on_disconnect = delay_on_disconnect_in_ms; 194 195 dal_irq_setup_hpd_filter(hpd, &config); 196 197 dal_gpio_close(hpd); 198 199 result = true; 200 } else { 201 ASSERT_CRITICAL(false); 202 } 203 204 /* Release HPD handle */ 205 dal_gpio_destroy_irq(&hpd); 206 207 return result; 208} 209 210/** 211 * dc_link_detect_sink() - Determine if there is a sink connected 212 * 213 * @type: Returned connection type 214 * Does not detect downstream devices, such as MST sinks 215 * or display connected through active dongles 216 */ 217bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type) 218{ 219 uint32_t is_hpd_high = 0; 220 struct gpio *hpd_pin; 221 222 if (link->connector_signal == SIGNAL_TYPE_LVDS) { 223 *type = dc_connection_single; 224 return true; 225 } 226 227 if (link->connector_signal == SIGNAL_TYPE_EDP) { 228 /*in case it is not on*/ 229 link->dc->hwss.edp_power_control(link, true); 230 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 231 } 232 233 /* todo: may need to lock gpio access */ 234 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); 235 if (hpd_pin == NULL) 236 goto hpd_gpio_failure; 237 238 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT); 239 dal_gpio_get_value(hpd_pin, &is_hpd_high); 240 dal_gpio_close(hpd_pin); 241 dal_gpio_destroy_irq(&hpd_pin); 242 243 if (is_hpd_high) { 244 *type = dc_connection_single; 245 /* TODO: need to do the actual detection */ 246 } else { 247 *type = dc_connection_none; 248 } 249 250 return true; 251 252hpd_gpio_failure: 253 return false; 254} 255 256static enum ddc_transaction_type get_ddc_transaction_type( 257 enum signal_type sink_signal) 258{ 259 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE; 260 261 switch (sink_signal) { 262 case SIGNAL_TYPE_DVI_SINGLE_LINK: 263 case SIGNAL_TYPE_DVI_DUAL_LINK: 264 case SIGNAL_TYPE_HDMI_TYPE_A: 265 case SIGNAL_TYPE_LVDS: 266 case SIGNAL_TYPE_RGB: 267 transaction_type = DDC_TRANSACTION_TYPE_I2C; 268 break; 269 270 case SIGNAL_TYPE_DISPLAY_PORT: 271 case SIGNAL_TYPE_EDP: 272 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 273 break; 274 275 case SIGNAL_TYPE_DISPLAY_PORT_MST: 276 /* MST does not use I2COverAux, but there is the 277 * SPECIAL use case for "immediate dwnstrm device 278 * access" (EPR#370830). */ 279 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 280 break; 281 282 default: 283 break; 284 } 285 286 return transaction_type; 287} 288 289static enum signal_type get_basic_signal_type( 290 struct graphics_object_id encoder, 291 struct graphics_object_id downstream) 292{ 293 if (downstream.type == OBJECT_TYPE_CONNECTOR) { 294 switch (downstream.id) { 295 case CONNECTOR_ID_SINGLE_LINK_DVII: 296 switch (encoder.id) { 297 case ENCODER_ID_INTERNAL_DAC1: 298 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 299 case ENCODER_ID_INTERNAL_DAC2: 300 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 301 return SIGNAL_TYPE_RGB; 302 default: 303 return SIGNAL_TYPE_DVI_SINGLE_LINK; 304 } 305 break; 306 case CONNECTOR_ID_DUAL_LINK_DVII: 307 { 308 switch (encoder.id) { 309 case ENCODER_ID_INTERNAL_DAC1: 310 case ENCODER_ID_INTERNAL_KLDSCP_DAC1: 311 case ENCODER_ID_INTERNAL_DAC2: 312 case ENCODER_ID_INTERNAL_KLDSCP_DAC2: 313 return SIGNAL_TYPE_RGB; 314 default: 315 return SIGNAL_TYPE_DVI_DUAL_LINK; 316 } 317 } 318 break; 319 case CONNECTOR_ID_SINGLE_LINK_DVID: 320 return SIGNAL_TYPE_DVI_SINGLE_LINK; 321 case CONNECTOR_ID_DUAL_LINK_DVID: 322 return SIGNAL_TYPE_DVI_DUAL_LINK; 323 case CONNECTOR_ID_VGA: 324 return SIGNAL_TYPE_RGB; 325 case CONNECTOR_ID_HDMI_TYPE_A: 326 return SIGNAL_TYPE_HDMI_TYPE_A; 327 case CONNECTOR_ID_LVDS: 328 return SIGNAL_TYPE_LVDS; 329 case CONNECTOR_ID_DISPLAY_PORT: 330 return SIGNAL_TYPE_DISPLAY_PORT; 331 case CONNECTOR_ID_EDP: 332 return SIGNAL_TYPE_EDP; 333 default: 334 return SIGNAL_TYPE_NONE; 335 } 336 } else if (downstream.type == OBJECT_TYPE_ENCODER) { 337 switch (downstream.id) { 338 case ENCODER_ID_EXTERNAL_NUTMEG: 339 case ENCODER_ID_EXTERNAL_TRAVIS: 340 return SIGNAL_TYPE_DISPLAY_PORT; 341 default: 342 return SIGNAL_TYPE_NONE; 343 } 344 } 345 346 return SIGNAL_TYPE_NONE; 347} 348 349/** 350 * dc_link_is_dp_sink_present() - Check if there is a native DP 351 * or passive DP-HDMI dongle connected 352 */ 353bool dc_link_is_dp_sink_present(struct dc_link *link) 354{ 355 enum gpio_result gpio_result; 356 uint32_t clock_pin = 0; 357 uint8_t retry = 0; 358 struct ddc *ddc; 359 360 enum connector_id connector_id = 361 dal_graphics_object_id_get_connector_id(link->link_id); 362 363 bool present = 364 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) || 365 (connector_id == CONNECTOR_ID_EDP)); 366 367 ddc = dal_ddc_service_get_ddc_pin(link->ddc); 368 369 if (!ddc) { 370 BREAK_TO_DEBUGGER(); 371 return present; 372 } 373 374 /* Open GPIO and set it to I2C mode */ 375 /* Note: this GpioMode_Input will be converted 376 * to GpioConfigType_I2cAuxDualMode in GPIO component, 377 * which indicates we need additional delay */ 378 379 if (GPIO_RESULT_OK != dal_ddc_open( 380 ddc, GPIO_MODE_INPUT, GPIO_DDC_CONFIG_TYPE_MODE_I2C)) { 381 dal_ddc_close(ddc); 382 383 return present; 384 } 385 386 /* 387 * Read GPIO: DP sink is present if both clock and data pins are zero 388 * 389 * [W/A] plug-unplug DP cable, sometimes customer board has 390 * one short pulse on clk_pin(1V, < 1ms). DP will be config to HDMI/DVI 391 * then monitor can't br light up. Add retry 3 times 392 * But in real passive dongle, it need additional 3ms to detect 393 */ 394 do { 395 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin); 396 ASSERT(gpio_result == GPIO_RESULT_OK); 397 if (clock_pin) 398 udelay(1000); 399 else 400 break; 401 } while (retry++ < 3); 402 403 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin; 404 405 dal_ddc_close(ddc); 406 407 return present; 408} 409 410/* 411 * @brief 412 * Detect output sink type 413 */ 414static enum signal_type link_detect_sink( 415 struct dc_link *link, 416 enum dc_detect_reason reason) 417{ 418 enum signal_type result = get_basic_signal_type( 419 link->link_enc->id, link->link_id); 420 421 /* Internal digital encoder will detect only dongles 422 * that require digital signal */ 423 424 /* Detection mechanism is different 425 * for different native connectors. 426 * LVDS connector supports only LVDS signal; 427 * PCIE is a bus slot, the actual connector needs to be detected first; 428 * eDP connector supports only eDP signal; 429 * HDMI should check straps for audio */ 430 431 /* PCIE detects the actual connector on add-on board */ 432 433 if (link->link_id.id == CONNECTOR_ID_PCIE) { 434 /* ZAZTODO implement PCIE add-on card detection */ 435 } 436 437 switch (link->link_id.id) { 438 case CONNECTOR_ID_HDMI_TYPE_A: { 439 /* check audio support: 440 * if native HDMI is not supported, switch to DVI */ 441 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 442 443 if (!aud_support->hdmi_audio_native) 444 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A) 445 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 446 } 447 break; 448 case CONNECTOR_ID_DISPLAY_PORT: { 449 /* DP HPD short pulse. Passive DP dongle will not 450 * have short pulse 451 */ 452 if (reason != DETECT_REASON_HPDRX) { 453 /* Check whether DP signal detected: if not - 454 * we assume signal is DVI; it could be corrected 455 * to HDMI after dongle detection 456 */ 457 if (!dm_helpers_is_dp_sink_present(link)) 458 result = SIGNAL_TYPE_DVI_SINGLE_LINK; 459 } 460 } 461 break; 462 default: 463 break; 464 } 465 466 return result; 467} 468 469static enum signal_type decide_signal_from_strap_and_dongle_type( 470 enum display_dongle_type dongle_type, 471 struct audio_support *audio_support) 472{ 473 enum signal_type signal = SIGNAL_TYPE_NONE; 474 475 switch (dongle_type) { 476 case DISPLAY_DONGLE_DP_HDMI_DONGLE: 477 if (audio_support->hdmi_audio_on_dongle) 478 signal = SIGNAL_TYPE_HDMI_TYPE_A; 479 else 480 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 481 break; 482 case DISPLAY_DONGLE_DP_DVI_DONGLE: 483 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 484 break; 485 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE: 486 if (audio_support->hdmi_audio_native) 487 signal = SIGNAL_TYPE_HDMI_TYPE_A; 488 else 489 signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 490 break; 491 default: 492 signal = SIGNAL_TYPE_NONE; 493 break; 494 } 495 496 return signal; 497} 498 499static enum signal_type dp_passive_dongle_detection( 500 struct ddc_service *ddc, 501 struct display_sink_capability *sink_cap, 502 struct audio_support *audio_support) 503{ 504 dal_ddc_service_i2c_query_dp_dual_mode_adaptor( 505 ddc, sink_cap); 506 return decide_signal_from_strap_and_dongle_type( 507 sink_cap->dongle_type, 508 audio_support); 509} 510 511static void link_disconnect_sink(struct dc_link *link) 512{ 513 if (link->local_sink) { 514 dc_sink_release(link->local_sink); 515 link->local_sink = NULL; 516 } 517 518 link->dpcd_sink_count = 0; 519} 520 521static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link) 522{ 523 dc_sink_release(link->local_sink); 524 link->local_sink = prev_sink; 525} 526 527 528static void read_current_link_settings_on_detect(struct dc_link *link) 529{ 530 union lane_count_set lane_count_set = { {0} }; 531 uint8_t link_bw_set; 532 uint8_t link_rate_set; 533 uint32_t read_dpcd_retry_cnt = 10; 534 enum dc_status status = DC_ERROR_UNEXPECTED; 535 int i; 536 union max_down_spread max_down_spread = { {0} }; 537 538 // Read DPCD 00101h to find out the number of lanes currently set 539 for (i = 0; i < read_dpcd_retry_cnt; i++) { 540 status = core_link_read_dpcd( 541 link, 542 DP_LANE_COUNT_SET, 543 &lane_count_set.raw, 544 sizeof(lane_count_set)); 545 /* First DPCD read after VDD ON can fail if the particular board 546 * does not have HPD pin wired correctly. So if DPCD read fails, 547 * which it should never happen, retry a few times. Target worst 548 * case scenario of 80 ms. 549 */ 550 if (status == DC_OK) { 551 link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET; 552 break; 553 } 554 555 msleep(8); 556 } 557 558 // Read DPCD 00100h to find if standard link rates are set 559 core_link_read_dpcd(link, DP_LINK_BW_SET, 560 &link_bw_set, sizeof(link_bw_set)); 561 562 if (link_bw_set == 0) { 563 if (link->connector_signal == SIGNAL_TYPE_EDP) { 564 /* If standard link rates are not being used, 565 * Read DPCD 00115h to find the edp link rate set used 566 */ 567 core_link_read_dpcd(link, DP_LINK_RATE_SET, 568 &link_rate_set, sizeof(link_rate_set)); 569 570 // edp_supported_link_rates_count = 0 for DP 571 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { 572 link->cur_link_settings.link_rate = 573 link->dpcd_caps.edp_supported_link_rates[link_rate_set]; 574 link->cur_link_settings.link_rate_set = link_rate_set; 575 link->cur_link_settings.use_link_rate_set = true; 576 } 577 } else { 578 // Link Rate not found. Seamless boot may not work. 579 ASSERT(false); 580 } 581 } else { 582 link->cur_link_settings.link_rate = link_bw_set; 583 link->cur_link_settings.use_link_rate_set = false; 584 } 585 // Read DPCD 00003h to find the max down spread. 586 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD, 587 &max_down_spread.raw, sizeof(max_down_spread)); 588 link->cur_link_settings.link_spread = 589 max_down_spread.bits.MAX_DOWN_SPREAD ? 590 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED; 591} 592 593static bool detect_dp( 594 struct dc_link *link, 595 struct display_sink_capability *sink_caps, 596 bool *converter_disable_audio, 597 struct audio_support *audio_support, 598 enum dc_detect_reason reason) 599{ 600 bool boot = false; 601 sink_caps->signal = link_detect_sink(link, reason); 602 sink_caps->transaction_type = 603 get_ddc_transaction_type(sink_caps->signal); 604 605 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 606 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 607 if (!detect_dp_sink_caps(link)) 608 return false; 609 610 if (is_mst_supported(link)) { 611 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 612 link->type = dc_connection_mst_branch; 613 614 dal_ddc_service_set_transaction_type( 615 link->ddc, 616 sink_caps->transaction_type); 617 618 /* 619 * This call will initiate MST topology discovery. Which 620 * will detect MST ports and add new DRM connector DRM 621 * framework. Then read EDID via remote i2c over aux. In 622 * the end, will notify DRM detect result and save EDID 623 * into DRM framework. 624 * 625 * .detect is called by .fill_modes. 626 * .fill_modes is called by user mode ioctl 627 * DRM_IOCTL_MODE_GETCONNECTOR. 628 * 629 * .get_modes is called by .fill_modes. 630 * 631 * call .get_modes, AMDGPU DM implementation will create 632 * new dc_sink and add to dc_link. For long HPD plug 633 * in/out, MST has its own handle. 634 * 635 * Therefore, just after dc_create, link->sink is not 636 * created for MST until user mode app calls 637 * DRM_IOCTL_MODE_GETCONNECTOR. 638 * 639 * Need check ->sink usages in case ->sink = NULL 640 * TODO: s3 resume check 641 */ 642 if (reason == DETECT_REASON_BOOT) 643 boot = true; 644 645 dm_helpers_dp_update_branch_info( 646 link->ctx, 647 link); 648 649 if (!dm_helpers_dp_mst_start_top_mgr( 650 link->ctx, 651 link, boot)) { 652 /* MST not supported */ 653 link->type = dc_connection_single; 654 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT; 655 } 656 } 657 658 if (link->type != dc_connection_mst_branch && 659 is_dp_active_dongle(link)) { 660 /* DP active dongles */ 661 link->type = dc_connection_active_dongle; 662 if (!link->dpcd_caps.sink_count.bits.SINK_COUNT) { 663 /* 664 * active dongle unplug processing for short irq 665 */ 666 link_disconnect_sink(link); 667 return true; 668 } 669 670 if (link->dpcd_caps.dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER) 671 *converter_disable_audio = true; 672 } 673 } else { 674 /* DP passive dongles */ 675 sink_caps->signal = dp_passive_dongle_detection(link->ddc, 676 sink_caps, 677 audio_support); 678 } 679 680 return true; 681} 682 683static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid) 684{ 685 if (old_edid->length != new_edid->length) 686 return false; 687 688 if (new_edid->length == 0) 689 return false; 690 691 return (memcmp(old_edid->raw_edid, new_edid->raw_edid, new_edid->length) == 0); 692} 693 694static bool wait_for_alt_mode(struct dc_link *link) 695{ 696 697 /** 698 * something is terribly wrong if time out is > 200ms. (5Hz) 699 * 500 microseconds * 400 tries us 200 ms 700 **/ 701 unsigned int sleep_time_in_microseconds = 500; 702 unsigned int tries_allowed = 400; 703 bool is_in_alt_mode; 704 unsigned long long enter_timestamp; 705 unsigned long long finish_timestamp; 706 unsigned long long time_taken_in_ns; 707 int tries_taken; 708 709 DC_LOGGER_INIT(link->ctx->logger); 710 711 if (link->link_enc->funcs->is_in_alt_mode == NULL) 712 return true; 713 714 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc); 715 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode); 716 717 if (is_in_alt_mode) 718 return true; 719 720 enter_timestamp = dm_get_timestamp(link->ctx); 721 722 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) { 723 udelay(sleep_time_in_microseconds); 724 /* ask the link if alt mode is enabled, if so return ok */ 725 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) { 726 727 finish_timestamp = dm_get_timestamp(link->ctx); 728 time_taken_in_ns = dm_get_elapse_time_in_ns( 729 link->ctx, finish_timestamp, enter_timestamp); 730 DC_LOG_WARNING("Alt mode entered finished after %"PRIu64" ms\n", 731 div_u64(time_taken_in_ns, 1000000)); 732 return true; 733 } 734 735 } 736 finish_timestamp = dm_get_timestamp(link->ctx); 737 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp, 738 enter_timestamp); 739 DC_LOG_WARNING("Alt mode has timed out after %"PRIu64" ms\n", 740 div_u64(time_taken_in_ns, 1000000)); 741 return false; 742} 743 744/** 745 * dc_link_detect() - Detect if a sink is attached to a given link 746 * 747 * link->local_sink is created or destroyed as needed. 748 * 749 * This does not create remote sinks but will trigger DM 750 * to start MST detection if a branch is detected. 751 */ 752static bool dc_link_detect_helper(struct dc_link *link, 753 enum dc_detect_reason reason) 754{ 755 struct dc_sink_init_data sink_init_data = { 0 }; 756 struct display_sink_capability sink_caps = { 0 }; 757 uint8_t i; 758 bool converter_disable_audio = false; 759 struct audio_support *aud_support = &link->dc->res_pool->audio_support; 760 bool same_edid = false; 761 enum dc_edid_status edid_status; 762 struct dc_context *dc_ctx = link->ctx; 763 struct dc_sink *sink = NULL; 764 struct dc_sink *prev_sink = NULL; 765 struct dpcd_caps prev_dpcd_caps; 766 bool same_dpcd = true; 767 enum dc_connection_type new_connection_type = dc_connection_none; 768 bool perform_dp_seamless_boot = false; 769 770 DC_LOGGER_INIT(link->ctx->logger); 771 772 if (dc_is_virtual_signal(link->connector_signal)) 773 return false; 774 775 if ((link->connector_signal == SIGNAL_TYPE_LVDS || 776 link->connector_signal == SIGNAL_TYPE_EDP) && 777 link->local_sink) 778 return true; 779 780 if (false == dc_link_detect_sink(link, &new_connection_type)) { 781 BREAK_TO_DEBUGGER(); 782 return false; 783 } 784 785 prev_sink = link->local_sink; 786 if (prev_sink != NULL) { 787 dc_sink_retain(prev_sink); 788 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps)); 789 } 790 link_disconnect_sink(link); 791 792 if (new_connection_type != dc_connection_none) { 793 link->type = new_connection_type; 794 link->link_state_valid = false; 795 796 /* From Disconnected-to-Connected. */ 797 switch (link->connector_signal) { 798 case SIGNAL_TYPE_HDMI_TYPE_A: { 799 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 800 if (aud_support->hdmi_audio_native) 801 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A; 802 else 803 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 804 break; 805 } 806 807 case SIGNAL_TYPE_DVI_SINGLE_LINK: { 808 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 809 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 810 break; 811 } 812 813 case SIGNAL_TYPE_DVI_DUAL_LINK: { 814 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 815 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK; 816 break; 817 } 818 819 case SIGNAL_TYPE_LVDS: { 820 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C; 821 sink_caps.signal = SIGNAL_TYPE_LVDS; 822 break; 823 } 824 825 case SIGNAL_TYPE_EDP: { 826 detect_edp_sink_caps(link); 827 read_current_link_settings_on_detect(link); 828 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX; 829 sink_caps.signal = SIGNAL_TYPE_EDP; 830 break; 831 } 832 833 case SIGNAL_TYPE_DISPLAY_PORT: { 834 835 /* wa HPD high coming too early*/ 836 if (link->link_enc->features.flags.bits.DP_IS_USB_C == 1) { 837 838 /* if alt mode times out, return false */ 839 if (wait_for_alt_mode(link) == false) { 840 return false; 841 } 842 } 843 844 if (!detect_dp( 845 link, 846 &sink_caps, 847 &converter_disable_audio, 848 aud_support, reason)) { 849 if (prev_sink != NULL) 850 dc_sink_release(prev_sink); 851 return false; 852 } 853 854 // Check if dpcp block is the same 855 if (prev_sink != NULL) { 856 if (memcmp(&link->dpcd_caps, &prev_dpcd_caps, sizeof(struct dpcd_caps))) 857 same_dpcd = false; 858 } 859 /* Active dongle downstream unplug*/ 860 if (link->type == dc_connection_active_dongle && 861 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) { 862 if (prev_sink != NULL) 863 /* Downstream unplug */ 864 dc_sink_release(prev_sink); 865 return true; 866 } 867 868 if (link->type == dc_connection_mst_branch) { 869 LINK_INFO("link=%d, mst branch is now Connected\n", 870 link->link_index); 871 /* Need to setup mst link_cap struct here 872 * otherwise dc_link_detect() will leave mst link_cap 873 * empty which leads to allocate_mst_payload() has "0" 874 * pbn_per_slot value leading to exception on dc_fixpt_div() 875 */ 876 dp_verify_mst_link_cap(link); 877 878 if (prev_sink != NULL) 879 dc_sink_release(prev_sink); 880 return false; 881 } 882 883 // For seamless boot, to skip verify link cap, we read UEFI settings and set them as verified. 884 if (reason == DETECT_REASON_BOOT && 885 dc_ctx->dc->config.power_down_display_on_boot == false && 886 link->link_status.link_active == true) 887 perform_dp_seamless_boot = true; 888 889 if (perform_dp_seamless_boot) { 890 read_current_link_settings_on_detect(link); 891 link->verified_link_cap = link->reported_link_cap; 892 } 893 894 break; 895 } 896 897 default: 898 DC_ERROR("Invalid connector type! signal:%d\n", 899 link->connector_signal); 900 if (prev_sink != NULL) 901 dc_sink_release(prev_sink); 902 return false; 903 } /* switch() */ 904 905 if (link->dpcd_caps.sink_count.bits.SINK_COUNT) 906 link->dpcd_sink_count = link->dpcd_caps.sink_count. 907 bits.SINK_COUNT; 908 else 909 link->dpcd_sink_count = 1; 910 911 dal_ddc_service_set_transaction_type( 912 link->ddc, 913 sink_caps.transaction_type); 914 915 link->aux_mode = dal_ddc_service_is_in_aux_transaction_mode( 916 link->ddc); 917 918 sink_init_data.link = link; 919 sink_init_data.sink_signal = sink_caps.signal; 920 921 sink = dc_sink_create(&sink_init_data); 922 if (!sink) { 923 DC_ERROR("Failed to create sink!\n"); 924 if (prev_sink != NULL) 925 dc_sink_release(prev_sink); 926 return false; 927 } 928 929 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; 930 sink->converter_disable_audio = converter_disable_audio; 931 932 /* dc_sink_create returns a new reference */ 933 link->local_sink = sink; 934 935 edid_status = dm_helpers_read_local_edid( 936 link->ctx, 937 link, 938 sink); 939 940 switch (edid_status) { 941 case EDID_BAD_CHECKSUM: 942 DC_LOG_ERROR("EDID checksum invalid.\n"); 943 break; 944 case EDID_NO_RESPONSE: 945 DC_LOG_ERROR("No EDID read.\n"); 946 947 /* 948 * Abort detection for non-DP connectors if we have 949 * no EDID 950 * 951 * DP needs to report as connected if HDP is high 952 * even if we have no EDID in order to go to 953 * fail-safe mode 954 */ 955 if (dc_is_hdmi_signal(link->connector_signal) || 956 dc_is_dvi_signal(link->connector_signal)) { 957 if (prev_sink != NULL) 958 dc_sink_release(prev_sink); 959 960 return false; 961 } 962 default: 963 break; 964 } 965 966 // Check if edid is the same 967 if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME) || (edid_status == EDID_OK))) 968 same_edid = is_same_edid(&prev_sink->dc_edid, &sink->dc_edid); 969 970 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT && 971 sink_caps.transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) { 972 /* 973 * TODO debug why Dell 2413 doesn't like 974 * two link trainings 975 */ 976 977 // verify link cap for SST non-seamless boot 978 if (!perform_dp_seamless_boot) 979 dp_verify_link_cap_with_retries(link, 980 &link->reported_link_cap, 981 LINK_TRAINING_MAX_VERIFY_RETRY); 982 } else { 983 // If edid is the same, then discard new sink and revert back to original sink 984 if (same_edid) { 985 link_disconnect_remap(prev_sink, link); 986 sink = prev_sink; 987 prev_sink = NULL; 988 989 } 990 } 991 992 /* HDMI-DVI Dongle */ 993 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && 994 !sink->edid_caps.edid_hdmi) 995 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 996 997 /* Connectivity log: detection */ 998 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) { 999 CONN_DATA_DETECT(link, 1000 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE], 1001 DC_EDID_BLOCK_SIZE, 1002 "%s: [Block %d] ", sink->edid_caps.display_name, i); 1003 } 1004 1005 DC_LOG_DETECTION_EDID_PARSER("%s: " 1006 "manufacturer_id = %X, " 1007 "product_id = %X, " 1008 "serial_number = %X, " 1009 "manufacture_week = %d, " 1010 "manufacture_year = %d, " 1011 "display_name = %s, " 1012 "speaker_flag = %d, " 1013 "audio_mode_count = %d\n", 1014 __func__, 1015 sink->edid_caps.manufacturer_id, 1016 sink->edid_caps.product_id, 1017 sink->edid_caps.serial_number, 1018 sink->edid_caps.manufacture_week, 1019 sink->edid_caps.manufacture_year, 1020 sink->edid_caps.display_name, 1021 sink->edid_caps.speaker_flags, 1022 sink->edid_caps.audio_mode_count); 1023 1024 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { 1025 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, " 1026 "format_code = %d, " 1027 "channel_count = %d, " 1028 "sample_rate = %d, " 1029 "sample_size = %d\n", 1030 __func__, 1031 i, 1032 sink->edid_caps.audio_modes[i].format_code, 1033 sink->edid_caps.audio_modes[i].channel_count, 1034 sink->edid_caps.audio_modes[i].sample_rate, 1035 sink->edid_caps.audio_modes[i].sample_size); 1036 } 1037 1038 } else { 1039 /* From Connected-to-Disconnected. */ 1040 if (link->type == dc_connection_mst_branch) { 1041 LINK_INFO("link=%d, mst branch is now Disconnected\n", 1042 link->link_index); 1043 1044 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link); 1045 1046 link->mst_stream_alloc_table.stream_count = 0; 1047 memset(link->mst_stream_alloc_table.stream_allocations, 0, sizeof(link->mst_stream_alloc_table.stream_allocations)); 1048 } 1049 1050 link->type = dc_connection_none; 1051 sink_caps.signal = SIGNAL_TYPE_NONE; 1052 /* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk 1053 * is not cleared. If we emulate a DP signal on this connection, it thinks 1054 * the dongle is still there and limits the number of modes we can emulate. 1055 * Clear dongle_max_pix_clk on disconnect to fix this 1056 */ 1057 link->dongle_max_pix_clk = 0; 1058 } 1059 1060 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n", 1061 link->link_index, sink, 1062 (sink_caps.signal == SIGNAL_TYPE_NONE ? 1063 "Disconnected":"Connected"), prev_sink, 1064 same_dpcd, same_edid); 1065 1066 if (prev_sink != NULL) 1067 dc_sink_release(prev_sink); 1068 1069 return true; 1070 1071} 1072 1073bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) 1074{ 1075 const struct dc *dc = link->dc; 1076 bool ret; 1077 1078 /* get out of low power state */ 1079 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 1080 1081 ret = dc_link_detect_helper(link, reason); 1082 1083 /* Go back to power optimized state */ 1084 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 1085 1086 return ret; 1087} 1088 1089bool dc_link_get_hpd_state(struct dc_link *dc_link) 1090{ 1091 uint32_t state; 1092 1093 dal_gpio_lock_pin(dc_link->hpd_gpio); 1094 dal_gpio_get_value(dc_link->hpd_gpio, &state); 1095 dal_gpio_unlock_pin(dc_link->hpd_gpio); 1096 1097 return state; 1098} 1099 1100static enum hpd_source_id get_hpd_line( 1101 struct dc_link *link) 1102{ 1103 struct gpio *hpd; 1104 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN; 1105 1106 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); 1107 1108 if (hpd) { 1109 switch (dal_irq_get_source(hpd)) { 1110 case DC_IRQ_SOURCE_HPD1: 1111 hpd_id = HPD_SOURCEID1; 1112 break; 1113 case DC_IRQ_SOURCE_HPD2: 1114 hpd_id = HPD_SOURCEID2; 1115 break; 1116 case DC_IRQ_SOURCE_HPD3: 1117 hpd_id = HPD_SOURCEID3; 1118 break; 1119 case DC_IRQ_SOURCE_HPD4: 1120 hpd_id = HPD_SOURCEID4; 1121 break; 1122 case DC_IRQ_SOURCE_HPD5: 1123 hpd_id = HPD_SOURCEID5; 1124 break; 1125 case DC_IRQ_SOURCE_HPD6: 1126 hpd_id = HPD_SOURCEID6; 1127 break; 1128 default: 1129 BREAK_TO_DEBUGGER(); 1130 break; 1131 } 1132 1133 dal_gpio_destroy_irq(&hpd); 1134 } 1135 1136 return hpd_id; 1137} 1138 1139static enum channel_id get_ddc_line(struct dc_link *link) 1140{ 1141 struct ddc *ddc; 1142 enum channel_id channel = CHANNEL_ID_UNKNOWN; 1143 1144 ddc = dal_ddc_service_get_ddc_pin(link->ddc); 1145 1146 if (ddc) { 1147 switch (dal_ddc_get_line(ddc)) { 1148 case GPIO_DDC_LINE_DDC1: 1149 channel = CHANNEL_ID_DDC1; 1150 break; 1151 case GPIO_DDC_LINE_DDC2: 1152 channel = CHANNEL_ID_DDC2; 1153 break; 1154 case GPIO_DDC_LINE_DDC3: 1155 channel = CHANNEL_ID_DDC3; 1156 break; 1157 case GPIO_DDC_LINE_DDC4: 1158 channel = CHANNEL_ID_DDC4; 1159 break; 1160 case GPIO_DDC_LINE_DDC5: 1161 channel = CHANNEL_ID_DDC5; 1162 break; 1163 case GPIO_DDC_LINE_DDC6: 1164 channel = CHANNEL_ID_DDC6; 1165 break; 1166 case GPIO_DDC_LINE_DDC_VGA: 1167 channel = CHANNEL_ID_DDC_VGA; 1168 break; 1169 case GPIO_DDC_LINE_I2C_PAD: 1170 channel = CHANNEL_ID_I2C_PAD; 1171 break; 1172 default: 1173 BREAK_TO_DEBUGGER(); 1174 break; 1175 } 1176 } 1177 1178 return channel; 1179} 1180 1181static enum transmitter translate_encoder_to_transmitter( 1182 struct graphics_object_id encoder) 1183{ 1184 switch (encoder.id) { 1185 case ENCODER_ID_INTERNAL_UNIPHY: 1186 switch (encoder.enum_id) { 1187 case ENUM_ID_1: 1188 return TRANSMITTER_UNIPHY_A; 1189 case ENUM_ID_2: 1190 return TRANSMITTER_UNIPHY_B; 1191 default: 1192 return TRANSMITTER_UNKNOWN; 1193 } 1194 break; 1195 case ENCODER_ID_INTERNAL_UNIPHY1: 1196 switch (encoder.enum_id) { 1197 case ENUM_ID_1: 1198 return TRANSMITTER_UNIPHY_C; 1199 case ENUM_ID_2: 1200 return TRANSMITTER_UNIPHY_D; 1201 default: 1202 return TRANSMITTER_UNKNOWN; 1203 } 1204 break; 1205 case ENCODER_ID_INTERNAL_UNIPHY2: 1206 switch (encoder.enum_id) { 1207 case ENUM_ID_1: 1208 return TRANSMITTER_UNIPHY_E; 1209 case ENUM_ID_2: 1210 return TRANSMITTER_UNIPHY_F; 1211 default: 1212 return TRANSMITTER_UNKNOWN; 1213 } 1214 break; 1215 case ENCODER_ID_INTERNAL_UNIPHY3: 1216 switch (encoder.enum_id) { 1217 case ENUM_ID_1: 1218 return TRANSMITTER_UNIPHY_G; 1219 default: 1220 return TRANSMITTER_UNKNOWN; 1221 } 1222 break; 1223 case ENCODER_ID_EXTERNAL_NUTMEG: 1224 switch (encoder.enum_id) { 1225 case ENUM_ID_1: 1226 return TRANSMITTER_NUTMEG_CRT; 1227 default: 1228 return TRANSMITTER_UNKNOWN; 1229 } 1230 break; 1231 case ENCODER_ID_EXTERNAL_TRAVIS: 1232 switch (encoder.enum_id) { 1233 case ENUM_ID_1: 1234 return TRANSMITTER_TRAVIS_CRT; 1235 case ENUM_ID_2: 1236 return TRANSMITTER_TRAVIS_LCD; 1237 default: 1238 return TRANSMITTER_UNKNOWN; 1239 } 1240 break; 1241 default: 1242 return TRANSMITTER_UNKNOWN; 1243 } 1244} 1245 1246static bool dc_link_construct( 1247 struct dc_link *link, 1248 const struct link_init_data *init_params) 1249{ 1250 uint8_t i; 1251 struct ddc_service_init_data ddc_service_init_data = { { 0 } }; 1252 struct dc_context *dc_ctx = init_params->ctx; 1253 struct encoder_init_data enc_init_data = { 0 }; 1254 struct integrated_info info = {{{ 0 }}}; 1255 struct dc_bios *bios = init_params->dc->ctx->dc_bios; 1256 const struct dc_vbios_funcs *bp_funcs = bios->funcs; 1257 DC_LOGGER_INIT(dc_ctx->logger); 1258 1259 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; 1260 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID; 1261 1262 link->link_status.dpcd_caps = &link->dpcd_caps; 1263 1264 link->dc = init_params->dc; 1265 link->ctx = dc_ctx; 1266 link->link_index = init_params->link_index; 1267 1268 memset(&link->preferred_training_settings, 0, sizeof(struct dc_link_training_overrides)); 1269 memset(&link->preferred_link_setting, 0, sizeof(struct dc_link_settings)); 1270 1271 link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index); 1272 1273 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) { 1274 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n", 1275 __func__, init_params->connector_index, 1276 link->link_id.type, OBJECT_TYPE_CONNECTOR); 1277 goto create_fail; 1278 } 1279 1280 if (link->dc->res_pool->funcs->link_init) 1281 link->dc->res_pool->funcs->link_init(link); 1282 1283 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); 1284 if (link->hpd_gpio != NULL) { 1285 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT); 1286 dal_gpio_unlock_pin(link->hpd_gpio); 1287 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio); 1288 } 1289 1290 switch (link->link_id.id) { 1291 case CONNECTOR_ID_HDMI_TYPE_A: 1292 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A; 1293 1294 break; 1295 case CONNECTOR_ID_SINGLE_LINK_DVID: 1296 case CONNECTOR_ID_SINGLE_LINK_DVII: 1297 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; 1298 break; 1299 case CONNECTOR_ID_DUAL_LINK_DVID: 1300 case CONNECTOR_ID_DUAL_LINK_DVII: 1301 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; 1302 break; 1303 case CONNECTOR_ID_DISPLAY_PORT: 1304 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; 1305 1306 if (link->hpd_gpio != NULL) 1307 link->irq_source_hpd_rx = 1308 dal_irq_get_rx_source(link->hpd_gpio); 1309 1310 break; 1311 case CONNECTOR_ID_EDP: 1312 link->connector_signal = SIGNAL_TYPE_EDP; 1313 1314 if (link->hpd_gpio != NULL) { 1315 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID; 1316 link->irq_source_hpd_rx = 1317 dal_irq_get_rx_source(link->hpd_gpio); 1318 } 1319 break; 1320 case CONNECTOR_ID_LVDS: 1321 link->connector_signal = SIGNAL_TYPE_LVDS; 1322 break; 1323 default: 1324 DC_LOG_WARNING("Unsupported Connector type:%d!\n", link->link_id.id); 1325 goto create_fail; 1326 } 1327 1328 /* TODO: #DAL3 Implement id to str function.*/ 1329 LINK_INFO("Connector[%d] description:" 1330 "signal %d\n", 1331 init_params->connector_index, 1332 link->connector_signal); 1333 1334 ddc_service_init_data.ctx = link->ctx; 1335 ddc_service_init_data.id = link->link_id; 1336 ddc_service_init_data.link = link; 1337 link->ddc = dal_ddc_service_create(&ddc_service_init_data); 1338 1339 if (link->ddc == NULL) { 1340 DC_ERROR("Failed to create ddc_service!\n"); 1341 goto ddc_create_fail; 1342 } 1343 1344 link->ddc_hw_inst = 1345 dal_ddc_get_line( 1346 dal_ddc_service_get_ddc_pin(link->ddc)); 1347 1348 enc_init_data.ctx = dc_ctx; 1349 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0, &enc_init_data.encoder); 1350 enc_init_data.connector = link->link_id; 1351 enc_init_data.channel = get_ddc_line(link); 1352 enc_init_data.hpd_source = get_hpd_line(link); 1353 1354 link->hpd_src = enc_init_data.hpd_source; 1355 1356 enc_init_data.transmitter = 1357 translate_encoder_to_transmitter(enc_init_data.encoder); 1358 link->link_enc = link->dc->res_pool->funcs->link_enc_create( 1359 &enc_init_data); 1360 1361 if (link->link_enc == NULL) { 1362 DC_ERROR("Failed to create link encoder!\n"); 1363 goto link_enc_create_fail; 1364 } 1365 1366 link->link_enc_hw_inst = link->link_enc->transmitter; 1367 1368 for (i = 0; i < 4; i++) { 1369 if (BP_RESULT_OK != 1370 bp_funcs->get_device_tag(dc_ctx->dc_bios, link->link_id, i, &link->device_tag)) { 1371 DC_ERROR("Failed to find device tag!\n"); 1372 goto device_tag_fail; 1373 } 1374 1375 /* Look for device tag that matches connector signal, 1376 * CRT for rgb, LCD for other supported signal tyes 1377 */ 1378 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios, link->device_tag.dev_id)) 1379 continue; 1380 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT 1381 && link->connector_signal != SIGNAL_TYPE_RGB) 1382 continue; 1383 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD 1384 && link->connector_signal == SIGNAL_TYPE_RGB) 1385 continue; 1386 break; 1387 } 1388 1389 if (bios->integrated_info) 1390 info = *bios->integrated_info; 1391 1392 /* Look for channel mapping corresponding to connector and device tag */ 1393 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) { 1394 struct external_display_path *path = 1395 &info.ext_disp_conn_info.path[i]; 1396 if (path->device_connector_id.enum_id == link->link_id.enum_id 1397 && path->device_connector_id.id == link->link_id.id 1398 && path->device_connector_id.type == link->link_id.type) { 1399 1400 if (link->device_tag.acpi_device != 0 1401 && path->device_acpi_enum == link->device_tag.acpi_device) { 1402 link->ddi_channel_mapping = path->channel_mapping; 1403 link->chip_caps = path->caps; 1404 } else if (path->device_tag == 1405 link->device_tag.dev_id.raw_device_tag) { 1406 link->ddi_channel_mapping = path->channel_mapping; 1407 link->chip_caps = path->caps; 1408 } 1409 break; 1410 } 1411 } 1412 1413 /* 1414 * TODO check if GPIO programmed correctly 1415 * 1416 * If GPIO isn't programmed correctly HPD might not rise or drain 1417 * fast enough, leading to bounces. 1418 */ 1419 program_hpd_filter(link); 1420 1421 return true; 1422device_tag_fail: 1423 link->link_enc->funcs->destroy(&link->link_enc); 1424link_enc_create_fail: 1425 dal_ddc_service_destroy(&link->ddc); 1426ddc_create_fail: 1427create_fail: 1428 1429 if (link->hpd_gpio != NULL) { 1430 dal_gpio_destroy_irq(&link->hpd_gpio); 1431 link->hpd_gpio = NULL; 1432 } 1433 1434 return false; 1435} 1436 1437/******************************************************************************* 1438 * Public functions 1439 ******************************************************************************/ 1440struct dc_link *link_create(const struct link_init_data *init_params) 1441{ 1442 struct dc_link *link = 1443 kzalloc(sizeof(*link), GFP_KERNEL); 1444 1445 if (NULL == link) 1446 goto alloc_fail; 1447 1448 if (false == dc_link_construct(link, init_params)) 1449 goto construct_fail; 1450 1451 return link; 1452 1453construct_fail: 1454 kfree(link); 1455 1456alloc_fail: 1457 return NULL; 1458} 1459 1460void link_destroy(struct dc_link **link) 1461{ 1462 dc_link_destruct(*link); 1463 kfree(*link); 1464 *link = NULL; 1465} 1466 1467static void enable_stream_features(struct pipe_ctx *pipe_ctx) 1468{ 1469 struct dc_stream_state *stream = pipe_ctx->stream; 1470 struct dc_link *link = stream->link; 1471 union down_spread_ctrl old_downspread; 1472 union down_spread_ctrl new_downspread; 1473 1474 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL, 1475 &old_downspread.raw, sizeof(old_downspread)); 1476 1477 new_downspread.raw = old_downspread.raw; 1478 1479 new_downspread.bits.IGNORE_MSA_TIMING_PARAM = 1480 (stream->ignore_msa_timing_param) ? 1 : 0; 1481 1482 if (new_downspread.raw != old_downspread.raw) { 1483 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, 1484 &new_downspread.raw, sizeof(new_downspread)); 1485 } 1486} 1487 1488static enum dc_status enable_link_dp( 1489 struct dc_state *state, 1490 struct pipe_ctx *pipe_ctx) 1491{ 1492 struct dc_stream_state *stream = pipe_ctx->stream; 1493 enum dc_status status; 1494 bool skip_video_pattern; 1495 struct dc_link *link = stream->link; 1496 struct dc_link_settings link_settings = {0}; 1497 bool fec_enable; 1498 int i; 1499 bool apply_seamless_boot_optimization = false; 1500 1501 // check for seamless boot 1502 for (i = 0; i < state->stream_count; i++) { 1503 if (state->streams[i]->apply_seamless_boot_optimization) { 1504 apply_seamless_boot_optimization = true; 1505 break; 1506 } 1507 } 1508 1509 /* get link settings for video mode timing */ 1510 decide_link_settings(stream, &link_settings); 1511 1512 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { 1513 /*in case it is not on*/ 1514 link->dc->hwss.edp_power_control(link, true); 1515 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 1516 } 1517 1518 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk = 1519 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ; 1520 if (state->clk_mgr && !apply_seamless_boot_optimization) 1521 state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, false); 1522 1523 skip_video_pattern = true; 1524 1525 if (link_settings.link_rate == LINK_RATE_LOW) 1526 skip_video_pattern = false; 1527 1528 if (perform_link_training_with_retries( 1529 &link_settings, 1530 skip_video_pattern, 1531 LINK_TRAINING_ATTEMPTS, 1532 pipe_ctx, 1533 pipe_ctx->stream->signal)) { 1534 link->cur_link_settings = link_settings; 1535 status = DC_OK; 1536 } 1537 else 1538 status = DC_FAIL_DP_LINK_TRAINING; 1539 1540 if (link->preferred_training_settings.fec_enable != NULL) 1541 fec_enable = *link->preferred_training_settings.fec_enable; 1542 else 1543 fec_enable = true; 1544 1545 dp_set_fec_enable(link, fec_enable); 1546 return status; 1547} 1548 1549static enum dc_status enable_link_edp( 1550 struct dc_state *state, 1551 struct pipe_ctx *pipe_ctx) 1552{ 1553 enum dc_status status; 1554 1555 status = enable_link_dp(state, pipe_ctx); 1556 1557 return status; 1558} 1559 1560static enum dc_status enable_link_dp_mst( 1561 struct dc_state *state, 1562 struct pipe_ctx *pipe_ctx) 1563{ 1564 struct dc_link *link = pipe_ctx->stream->link; 1565 1566 /* sink signal type after MST branch is MST. Multiple MST sinks 1567 * share one link. Link DP PHY is enable or training only once. 1568 */ 1569 if (link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) 1570 return DC_OK; 1571 1572 /* clear payload table */ 1573 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link); 1574 1575 /* to make sure the pending down rep can be processed 1576 * before enabling the link 1577 */ 1578 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link); 1579 1580 /* set the sink to MST mode before enabling the link */ 1581 dp_enable_mst_on_sink(link, true); 1582 1583 return enable_link_dp(state, pipe_ctx); 1584} 1585 1586static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx, 1587 enum engine_id eng_id, 1588 struct ext_hdmi_settings *settings) 1589{ 1590 bool result = false; 1591 int i = 0; 1592 struct integrated_info *integrated_info = 1593 pipe_ctx->stream->ctx->dc_bios->integrated_info; 1594 1595 if (integrated_info == NULL) 1596 return false; 1597 1598 /* 1599 * Get retimer settings from sbios for passing SI eye test for DCE11 1600 * The setting values are varied based on board revision and port id 1601 * Therefore the setting values of each ports is passed by sbios. 1602 */ 1603 1604 // Check if current bios contains ext Hdmi settings 1605 if (integrated_info->gpu_cap_info & 0x20) { 1606 switch (eng_id) { 1607 case ENGINE_ID_DIGA: 1608 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr; 1609 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num; 1610 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num; 1611 memmove(settings->reg_settings, 1612 integrated_info->dp0_ext_hdmi_reg_settings, 1613 sizeof(integrated_info->dp0_ext_hdmi_reg_settings)); 1614 memmove(settings->reg_settings_6g, 1615 integrated_info->dp0_ext_hdmi_6g_reg_settings, 1616 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings)); 1617 result = true; 1618 break; 1619 case ENGINE_ID_DIGB: 1620 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr; 1621 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num; 1622 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num; 1623 memmove(settings->reg_settings, 1624 integrated_info->dp1_ext_hdmi_reg_settings, 1625 sizeof(integrated_info->dp1_ext_hdmi_reg_settings)); 1626 memmove(settings->reg_settings_6g, 1627 integrated_info->dp1_ext_hdmi_6g_reg_settings, 1628 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings)); 1629 result = true; 1630 break; 1631 case ENGINE_ID_DIGC: 1632 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr; 1633 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num; 1634 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num; 1635 memmove(settings->reg_settings, 1636 integrated_info->dp2_ext_hdmi_reg_settings, 1637 sizeof(integrated_info->dp2_ext_hdmi_reg_settings)); 1638 memmove(settings->reg_settings_6g, 1639 integrated_info->dp2_ext_hdmi_6g_reg_settings, 1640 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings)); 1641 result = true; 1642 break; 1643 case ENGINE_ID_DIGD: 1644 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr; 1645 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num; 1646 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num; 1647 memmove(settings->reg_settings, 1648 integrated_info->dp3_ext_hdmi_reg_settings, 1649 sizeof(integrated_info->dp3_ext_hdmi_reg_settings)); 1650 memmove(settings->reg_settings_6g, 1651 integrated_info->dp3_ext_hdmi_6g_reg_settings, 1652 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings)); 1653 result = true; 1654 break; 1655 default: 1656 break; 1657 } 1658 1659 if (result == true) { 1660 // Validate settings from bios integrated info table 1661 if (settings->slv_addr == 0) 1662 return false; 1663 if (settings->reg_num > 9) 1664 return false; 1665 if (settings->reg_num_6g > 3) 1666 return false; 1667 1668 for (i = 0; i < settings->reg_num; i++) { 1669 if (settings->reg_settings[i].i2c_reg_index > 0x20) 1670 return false; 1671 } 1672 1673 for (i = 0; i < settings->reg_num_6g; i++) { 1674 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20) 1675 return false; 1676 } 1677 } 1678 } 1679 1680 return result; 1681} 1682 1683static bool i2c_write(struct pipe_ctx *pipe_ctx, 1684 uint8_t address, uint8_t *buffer, uint32_t length) 1685{ 1686 struct i2c_command cmd = {0}; 1687 struct i2c_payload payload = {0}; 1688 1689 memset(&payload, 0, sizeof(payload)); 1690 memset(&cmd, 0, sizeof(cmd)); 1691 1692 cmd.number_of_payloads = 1; 1693 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; 1694 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz; 1695 1696 payload.address = address; 1697 payload.data = buffer; 1698 payload.length = length; 1699 payload.write = true; 1700 cmd.payloads = &payload; 1701 1702 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx, 1703 pipe_ctx->stream->link, &cmd)) 1704 return true; 1705 1706 return false; 1707} 1708 1709static void write_i2c_retimer_setting( 1710 struct pipe_ctx *pipe_ctx, 1711 bool is_vga_mode, 1712 bool is_over_340mhz, 1713 struct ext_hdmi_settings *settings) 1714{ 1715 uint8_t slave_address = (settings->slv_addr >> 1); 1716 uint8_t buffer[2]; 1717 const uint8_t apply_rx_tx_change = 0x4; 1718 uint8_t offset = 0xA; 1719 uint8_t value = 0; 1720 int i = 0; 1721 bool i2c_success = false; 1722 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1723 1724 memset(&buffer, 0, sizeof(buffer)); 1725 1726 /* Start Ext-Hdmi programming*/ 1727 1728 for (i = 0; i < settings->reg_num; i++) { 1729 /* Apply 3G settings */ 1730 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 1731 1732 buffer[0] = settings->reg_settings[i].i2c_reg_index; 1733 buffer[1] = settings->reg_settings[i].i2c_reg_val; 1734 i2c_success = i2c_write(pipe_ctx, slave_address, 1735 buffer, sizeof(buffer)); 1736 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1737 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 1738 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1739 1740 if (!i2c_success) 1741 /* Write failure */ 1742 ASSERT(i2c_success); 1743 1744 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 1745 * needs to be set to 1 on every 0xA-0xC write. 1746 */ 1747 if (settings->reg_settings[i].i2c_reg_index == 0xA || 1748 settings->reg_settings[i].i2c_reg_index == 0xB || 1749 settings->reg_settings[i].i2c_reg_index == 0xC) { 1750 1751 /* Query current value from offset 0xA */ 1752 if (settings->reg_settings[i].i2c_reg_index == 0xA) 1753 value = settings->reg_settings[i].i2c_reg_val; 1754 else { 1755 i2c_success = 1756 dal_ddc_service_query_ddc_data( 1757 pipe_ctx->stream->link->ddc, 1758 slave_address, &offset, 1, &value, 1); 1759 if (!i2c_success) 1760 /* Write failure */ 1761 ASSERT(i2c_success); 1762 } 1763 1764 buffer[0] = offset; 1765 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 1766 buffer[1] = value | apply_rx_tx_change; 1767 i2c_success = i2c_write(pipe_ctx, slave_address, 1768 buffer, sizeof(buffer)); 1769 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1770 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1771 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1772 if (!i2c_success) 1773 /* Write failure */ 1774 ASSERT(i2c_success); 1775 } 1776 } 1777 } 1778 1779 /* Apply 3G settings */ 1780 if (is_over_340mhz) { 1781 for (i = 0; i < settings->reg_num_6g; i++) { 1782 /* Apply 3G settings */ 1783 if (settings->reg_settings[i].i2c_reg_index <= 0x20) { 1784 1785 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index; 1786 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val; 1787 i2c_success = i2c_write(pipe_ctx, slave_address, 1788 buffer, sizeof(buffer)); 1789 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\ 1790 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1791 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1792 1793 if (!i2c_success) 1794 /* Write failure */ 1795 ASSERT(i2c_success); 1796 1797 /* Based on DP159 specs, APPLY_RX_TX_CHANGE bit in 0x0A 1798 * needs to be set to 1 on every 0xA-0xC write. 1799 */ 1800 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA || 1801 settings->reg_settings_6g[i].i2c_reg_index == 0xB || 1802 settings->reg_settings_6g[i].i2c_reg_index == 0xC) { 1803 1804 /* Query current value from offset 0xA */ 1805 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA) 1806 value = settings->reg_settings_6g[i].i2c_reg_val; 1807 else { 1808 i2c_success = 1809 dal_ddc_service_query_ddc_data( 1810 pipe_ctx->stream->link->ddc, 1811 slave_address, &offset, 1, &value, 1); 1812 if (!i2c_success) 1813 /* Write failure */ 1814 ASSERT(i2c_success); 1815 } 1816 1817 buffer[0] = offset; 1818 /* Set APPLY_RX_TX_CHANGE bit to 1 */ 1819 buffer[1] = value | apply_rx_tx_change; 1820 i2c_success = i2c_write(pipe_ctx, slave_address, 1821 buffer, sizeof(buffer)); 1822 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1823 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1824 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1825 if (!i2c_success) 1826 /* Write failure */ 1827 ASSERT(i2c_success); 1828 } 1829 } 1830 } 1831 } 1832 1833 if (is_vga_mode) { 1834 /* Program additional settings if using 640x480 resolution */ 1835 1836 /* Write offset 0xFF to 0x01 */ 1837 buffer[0] = 0xff; 1838 buffer[1] = 0x01; 1839 i2c_success = i2c_write(pipe_ctx, slave_address, 1840 buffer, sizeof(buffer)); 1841 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1842 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1843 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1844 if (!i2c_success) 1845 /* Write failure */ 1846 ASSERT(i2c_success); 1847 1848 /* Write offset 0x00 to 0x23 */ 1849 buffer[0] = 0x00; 1850 buffer[1] = 0x23; 1851 i2c_success = i2c_write(pipe_ctx, slave_address, 1852 buffer, sizeof(buffer)); 1853 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1854 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1855 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1856 if (!i2c_success) 1857 /* Write failure */ 1858 ASSERT(i2c_success); 1859 1860 /* Write offset 0xff to 0x00 */ 1861 buffer[0] = 0xff; 1862 buffer[1] = 0x00; 1863 i2c_success = i2c_write(pipe_ctx, slave_address, 1864 buffer, sizeof(buffer)); 1865 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\ 1866 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1867 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1868 if (!i2c_success) 1869 /* Write failure */ 1870 ASSERT(i2c_success); 1871 1872 } 1873} 1874 1875static void write_i2c_default_retimer_setting( 1876 struct pipe_ctx *pipe_ctx, 1877 bool is_vga_mode, 1878 bool is_over_340mhz) 1879{ 1880 uint8_t slave_address = (0xBA >> 1); 1881 uint8_t buffer[2]; 1882 bool i2c_success = false; 1883 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 1884 1885 memset(&buffer, 0, sizeof(buffer)); 1886 1887 /* Program Slave Address for tuning single integrity */ 1888 /* Write offset 0x0A to 0x13 */ 1889 buffer[0] = 0x0A; 1890 buffer[1] = 0x13; 1891 i2c_success = i2c_write(pipe_ctx, slave_address, 1892 buffer, sizeof(buffer)); 1893 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\ 1894 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1895 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1896 if (!i2c_success) 1897 /* Write failure */ 1898 ASSERT(i2c_success); 1899 1900 /* Write offset 0x0A to 0x17 */ 1901 buffer[0] = 0x0A; 1902 buffer[1] = 0x17; 1903 i2c_success = i2c_write(pipe_ctx, slave_address, 1904 buffer, sizeof(buffer)); 1905 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1906 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1907 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1908 if (!i2c_success) 1909 /* Write failure */ 1910 ASSERT(i2c_success); 1911 1912 /* Write offset 0x0B to 0xDA or 0xD8 */ 1913 buffer[0] = 0x0B; 1914 buffer[1] = is_over_340mhz ? 0xDA : 0xD8; 1915 i2c_success = i2c_write(pipe_ctx, slave_address, 1916 buffer, sizeof(buffer)); 1917 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1918 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1919 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1920 if (!i2c_success) 1921 /* Write failure */ 1922 ASSERT(i2c_success); 1923 1924 /* Write offset 0x0A to 0x17 */ 1925 buffer[0] = 0x0A; 1926 buffer[1] = 0x17; 1927 i2c_success = i2c_write(pipe_ctx, slave_address, 1928 buffer, sizeof(buffer)); 1929 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1930 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 1931 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1932 if (!i2c_success) 1933 /* Write failure */ 1934 ASSERT(i2c_success); 1935 1936 /* Write offset 0x0C to 0x1D or 0x91 */ 1937 buffer[0] = 0x0C; 1938 buffer[1] = is_over_340mhz ? 0x1D : 0x91; 1939 i2c_success = i2c_write(pipe_ctx, slave_address, 1940 buffer, sizeof(buffer)); 1941 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1942 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1943 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1944 if (!i2c_success) 1945 /* Write failure */ 1946 ASSERT(i2c_success); 1947 1948 /* Write offset 0x0A to 0x17 */ 1949 buffer[0] = 0x0A; 1950 buffer[1] = 0x17; 1951 i2c_success = i2c_write(pipe_ctx, slave_address, 1952 buffer, sizeof(buffer)); 1953 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1954 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1955 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1956 if (!i2c_success) 1957 /* Write failure */ 1958 ASSERT(i2c_success); 1959 1960 1961 if (is_vga_mode) { 1962 /* Program additional settings if using 640x480 resolution */ 1963 1964 /* Write offset 0xFF to 0x01 */ 1965 buffer[0] = 0xff; 1966 buffer[1] = 0x01; 1967 i2c_success = i2c_write(pipe_ctx, slave_address, 1968 buffer, sizeof(buffer)); 1969 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1970 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n", 1971 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1972 if (!i2c_success) 1973 /* Write failure */ 1974 ASSERT(i2c_success); 1975 1976 /* Write offset 0x00 to 0x23 */ 1977 buffer[0] = 0x00; 1978 buffer[1] = 0x23; 1979 i2c_success = i2c_write(pipe_ctx, slave_address, 1980 buffer, sizeof(buffer)); 1981 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\ 1982 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n", 1983 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1984 if (!i2c_success) 1985 /* Write failure */ 1986 ASSERT(i2c_success); 1987 1988 /* Write offset 0xff to 0x00 */ 1989 buffer[0] = 0xff; 1990 buffer[1] = 0x00; 1991 i2c_success = i2c_write(pipe_ctx, slave_address, 1992 buffer, sizeof(buffer)); 1993 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\ 1994 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n", 1995 slave_address, buffer[0], buffer[1], i2c_success?1:0); 1996 if (!i2c_success) 1997 /* Write failure */ 1998 ASSERT(i2c_success); 1999 } 2000} 2001 2002static void write_i2c_redriver_setting( 2003 struct pipe_ctx *pipe_ctx, 2004 bool is_over_340mhz) 2005{ 2006 uint8_t slave_address = (0xF0 >> 1); 2007 uint8_t buffer[16]; 2008 bool i2c_success = false; 2009 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2010 2011 memset(&buffer, 0, sizeof(buffer)); 2012 2013 // Program Slave Address for tuning single integrity 2014 buffer[3] = 0x4E; 2015 buffer[4] = 0x4E; 2016 buffer[5] = 0x4E; 2017 buffer[6] = is_over_340mhz ? 0x4E : 0x4A; 2018 2019 i2c_success = i2c_write(pipe_ctx, slave_address, 2020 buffer, sizeof(buffer)); 2021 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\ 2022 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\ 2023 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\ 2024 i2c_success = %d\n", 2025 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0); 2026 2027 if (!i2c_success) 2028 /* Write failure */ 2029 ASSERT(i2c_success); 2030} 2031 2032static void disable_link(struct dc_link *link, enum signal_type signal) 2033{ 2034 /* 2035 * TODO: implement call for dp_set_hw_test_pattern 2036 * it is needed for compliance testing 2037 */ 2038 2039 /* Here we need to specify that encoder output settings 2040 * need to be calculated as for the set mode, 2041 * it will lead to querying dynamic link capabilities 2042 * which should be done before enable output 2043 */ 2044 2045 if (dc_is_dp_signal(signal)) { 2046 /* SST DP, eDP */ 2047 if (dc_is_dp_sst_signal(signal)) 2048 dp_disable_link_phy(link, signal); 2049 else 2050 dp_disable_link_phy_mst(link, signal); 2051 2052 if (dc_is_dp_sst_signal(signal) || 2053 link->mst_stream_alloc_table.stream_count == 0) { 2054 dp_set_fec_enable(link, false); 2055 dp_set_fec_ready(link, false); 2056 } 2057 } else { 2058 if (signal != SIGNAL_TYPE_VIRTUAL) 2059 link->link_enc->funcs->disable_output(link->link_enc, signal); 2060 } 2061 2062 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2063 /* MST disable link only when no stream use the link */ 2064 if (link->mst_stream_alloc_table.stream_count <= 0) 2065 link->link_status.link_active = false; 2066 } else { 2067 link->link_status.link_active = false; 2068 } 2069} 2070 2071static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) 2072{ 2073 struct dc_stream_state *stream = pipe_ctx->stream; 2074 struct dc_link *link = stream->link; 2075 enum dc_color_depth display_color_depth; 2076 enum engine_id eng_id; 2077 struct ext_hdmi_settings settings = {0}; 2078 bool is_over_340mhz = false; 2079 bool is_vga_mode = (stream->timing.h_addressable == 640) 2080 && (stream->timing.v_addressable == 480); 2081 2082 if (stream->phy_pix_clk == 0) 2083 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2084 if (stream->phy_pix_clk > 340000) 2085 is_over_340mhz = true; 2086 2087 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 2088 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps & 2089 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 2090 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 2091 /* DP159, Retimer settings */ 2092 eng_id = pipe_ctx->stream_res.stream_enc->id; 2093 2094 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) { 2095 write_i2c_retimer_setting(pipe_ctx, 2096 is_vga_mode, is_over_340mhz, &settings); 2097 } else { 2098 write_i2c_default_retimer_setting(pipe_ctx, 2099 is_vga_mode, is_over_340mhz); 2100 } 2101 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 2102 /* PI3EQX1204, Redriver settings */ 2103 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz); 2104 } 2105 } 2106 2107 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2108 dal_ddc_service_write_scdc_data( 2109 stream->link->ddc, 2110 stream->phy_pix_clk, 2111 stream->timing.flags.LTE_340MCSC_SCRAMBLE); 2112 2113 memset(&stream->link->cur_link_settings, 0, 2114 sizeof(struct dc_link_settings)); 2115 2116 display_color_depth = stream->timing.display_color_depth; 2117 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 2118 display_color_depth = COLOR_DEPTH_888; 2119 2120 link->link_enc->funcs->enable_tmds_output( 2121 link->link_enc, 2122 pipe_ctx->clock_source->id, 2123 display_color_depth, 2124 pipe_ctx->stream->signal, 2125 stream->phy_pix_clk); 2126 2127 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) 2128 dal_ddc_service_read_scdc_data(link->ddc); 2129} 2130 2131static void enable_link_lvds(struct pipe_ctx *pipe_ctx) 2132{ 2133 struct dc_stream_state *stream = pipe_ctx->stream; 2134 struct dc_link *link = stream->link; 2135 2136 if (stream->phy_pix_clk == 0) 2137 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10; 2138 2139 memset(&stream->link->cur_link_settings, 0, 2140 sizeof(struct dc_link_settings)); 2141 2142 link->link_enc->funcs->enable_lvds_output( 2143 link->link_enc, 2144 pipe_ctx->clock_source->id, 2145 stream->phy_pix_clk); 2146 2147} 2148 2149/****************************enable_link***********************************/ 2150static enum dc_status enable_link( 2151 struct dc_state *state, 2152 struct pipe_ctx *pipe_ctx) 2153{ 2154 enum dc_status status = DC_ERROR_UNEXPECTED; 2155 struct dc_stream_state *stream = pipe_ctx->stream; 2156 struct dc_link *link = stream->link; 2157 2158 /* There's some scenarios where driver is unloaded with display 2159 * still enabled. When driver is reloaded, it may cause a display 2160 * to not light up if there is a mismatch between old and new 2161 * link settings. Need to call disable first before enabling at 2162 * new link settings. 2163 */ 2164 if (link->link_status.link_active) { 2165 disable_link(link, pipe_ctx->stream->signal); 2166 } 2167 2168 switch (pipe_ctx->stream->signal) { 2169 case SIGNAL_TYPE_DISPLAY_PORT: 2170 status = enable_link_dp(state, pipe_ctx); 2171 break; 2172 case SIGNAL_TYPE_EDP: 2173 status = enable_link_edp(state, pipe_ctx); 2174 break; 2175 case SIGNAL_TYPE_DISPLAY_PORT_MST: 2176 status = enable_link_dp_mst(state, pipe_ctx); 2177 msleep(200); 2178 break; 2179 case SIGNAL_TYPE_DVI_SINGLE_LINK: 2180 case SIGNAL_TYPE_DVI_DUAL_LINK: 2181 case SIGNAL_TYPE_HDMI_TYPE_A: 2182 enable_link_hdmi(pipe_ctx); 2183 status = DC_OK; 2184 break; 2185 case SIGNAL_TYPE_LVDS: 2186 enable_link_lvds(pipe_ctx); 2187 status = DC_OK; 2188 break; 2189 case SIGNAL_TYPE_VIRTUAL: 2190 status = DC_OK; 2191 break; 2192 default: 2193 break; 2194 } 2195 2196 if (status == DC_OK) 2197 pipe_ctx->stream->link->link_status.link_active = true; 2198 2199 return status; 2200} 2201 2202static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing) 2203{ 2204 2205 uint32_t pxl_clk = timing->pix_clk_100hz; 2206 2207 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 2208 pxl_clk /= 2; 2209 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 2210 pxl_clk = pxl_clk * 2 / 3; 2211 2212 if (timing->display_color_depth == COLOR_DEPTH_101010) 2213 pxl_clk = pxl_clk * 10 / 8; 2214 else if (timing->display_color_depth == COLOR_DEPTH_121212) 2215 pxl_clk = pxl_clk * 12 / 8; 2216 2217 return pxl_clk; 2218} 2219 2220static bool dp_active_dongle_validate_timing( 2221 const struct dc_crtc_timing *timing, 2222 const struct dpcd_caps *dpcd_caps) 2223{ 2224 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; 2225 2226 switch (dpcd_caps->dongle_type) { 2227 case DISPLAY_DONGLE_DP_VGA_CONVERTER: 2228 case DISPLAY_DONGLE_DP_DVI_CONVERTER: 2229 case DISPLAY_DONGLE_DP_DVI_DONGLE: 2230 if (timing->pixel_encoding == PIXEL_ENCODING_RGB) 2231 return true; 2232 else 2233 return false; 2234 default: 2235 break; 2236 } 2237 2238 if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER || 2239 dongle_caps->extendedCapValid == false) 2240 return true; 2241 2242 /* Check Pixel Encoding */ 2243 switch (timing->pixel_encoding) { 2244 case PIXEL_ENCODING_RGB: 2245 case PIXEL_ENCODING_YCBCR444: 2246 break; 2247 case PIXEL_ENCODING_YCBCR422: 2248 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through) 2249 return false; 2250 break; 2251 case PIXEL_ENCODING_YCBCR420: 2252 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through) 2253 return false; 2254 break; 2255 default: 2256 /* Invalid Pixel Encoding*/ 2257 return false; 2258 } 2259 2260 switch (timing->display_color_depth) { 2261 case COLOR_DEPTH_666: 2262 case COLOR_DEPTH_888: 2263 /*888 and 666 should always be supported*/ 2264 break; 2265 case COLOR_DEPTH_101010: 2266 if (dongle_caps->dp_hdmi_max_bpc < 10) 2267 return false; 2268 break; 2269 case COLOR_DEPTH_121212: 2270 if (dongle_caps->dp_hdmi_max_bpc < 12) 2271 return false; 2272 break; 2273 case COLOR_DEPTH_141414: 2274 case COLOR_DEPTH_161616: 2275 default: 2276 /* These color depths are currently not supported */ 2277 return false; 2278 } 2279 2280 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10)) 2281 return false; 2282 2283 return true; 2284} 2285 2286enum dc_status dc_link_validate_mode_timing( 2287 const struct dc_stream_state *stream, 2288 struct dc_link *link, 2289 const struct dc_crtc_timing *timing) 2290{ 2291 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10; 2292 struct dpcd_caps *dpcd_caps = &link->dpcd_caps; 2293 2294 /* A hack to avoid failing any modes for EDID override feature on 2295 * topology change such as lower quality cable for DP or different dongle 2296 */ 2297 if (link->remote_sinks[0]) 2298 return DC_OK; 2299 2300 /* Passive Dongle */ 2301 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk) 2302 return DC_EXCEED_DONGLE_CAP; 2303 2304 /* Active Dongle*/ 2305 if (!dp_active_dongle_validate_timing(timing, dpcd_caps)) 2306 return DC_EXCEED_DONGLE_CAP; 2307 2308 switch (stream->signal) { 2309 case SIGNAL_TYPE_EDP: 2310 case SIGNAL_TYPE_DISPLAY_PORT: 2311 if (!dp_validate_mode_timing( 2312 link, 2313 timing)) 2314 return DC_NO_DP_LINK_BANDWIDTH; 2315 break; 2316 2317 default: 2318 break; 2319 } 2320 2321 return DC_OK; 2322} 2323 2324int dc_link_get_backlight_level(const struct dc_link *link) 2325{ 2326 struct abm *abm = link->ctx->dc->res_pool->abm; 2327 2328 if (abm == NULL || abm->funcs->get_current_backlight == NULL) 2329 return DC_ERROR_UNEXPECTED; 2330 2331 return (int) abm->funcs->get_current_backlight(abm); 2332} 2333 2334bool dc_link_set_backlight_level(const struct dc_link *link, 2335 uint32_t backlight_pwm_u16_16, 2336 uint32_t frame_ramp) 2337{ 2338 struct dc *dc = link->ctx->dc; 2339 struct abm *abm = dc->res_pool->abm; 2340 struct dmcu *dmcu = dc->res_pool->dmcu; 2341 unsigned int controller_id = 0; 2342 bool use_smooth_brightness = true; 2343 int i; 2344 DC_LOGGER_INIT(link->ctx->logger); 2345 2346 if ((dmcu == NULL) || 2347 (abm == NULL) || 2348 (abm->funcs->set_backlight_level_pwm == NULL)) 2349 return false; 2350 2351 use_smooth_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 2352 2353 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", 2354 backlight_pwm_u16_16, backlight_pwm_u16_16); 2355 2356 if (dc_is_embedded_signal(link->connector_signal)) { 2357 for (i = 0; i < MAX_PIPES; i++) { 2358 if (dc->current_state->res_ctx.pipe_ctx[i].stream) { 2359 if (dc->current_state->res_ctx. 2360 pipe_ctx[i].stream->link 2361 == link) { 2362 /* DMCU -1 for all controller id values, 2363 * therefore +1 here 2364 */ 2365 controller_id = 2366 dc->current_state-> 2367 res_ctx.pipe_ctx[i].stream_res.tg->inst + 2368 1; 2369 2370 /* Disable brightness ramping when the display is blanked 2371 * as it can hang the DMCU 2372 */ 2373 if (dc->current_state->res_ctx.pipe_ctx[i].plane_state == NULL) 2374 frame_ramp = 0; 2375 } 2376 } 2377 } 2378 abm->funcs->set_backlight_level_pwm( 2379 abm, 2380 backlight_pwm_u16_16, 2381 frame_ramp, 2382 controller_id, 2383 use_smooth_brightness); 2384 } 2385 2386 return true; 2387} 2388 2389bool dc_link_set_abm_disable(const struct dc_link *link) 2390{ 2391 struct dc *dc = link->ctx->dc; 2392 struct abm *abm = dc->res_pool->abm; 2393 2394 if ((abm == NULL) || (abm->funcs->set_backlight_level_pwm == NULL)) 2395 return false; 2396 2397 abm->funcs->set_abm_immediate_disable(abm); 2398 2399 return true; 2400} 2401 2402bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active, bool wait) 2403{ 2404 struct dc *dc = link->ctx->dc; 2405 struct dmcu *dmcu = dc->res_pool->dmcu; 2406 struct dmub_psr *psr = dc->res_pool->psr; 2407 2408 if ((psr != NULL) && link->psr_feature_enabled) 2409 psr->funcs->set_psr_enable(psr, allow_active); 2410 else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_feature_enabled) 2411 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait); 2412 2413 link->psr_allow_active = allow_active; 2414 2415 return true; 2416} 2417 2418bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) 2419{ 2420 struct dc *dc = link->ctx->dc; 2421 struct dmcu *dmcu = dc->res_pool->dmcu; 2422 struct dmub_psr *psr = dc->res_pool->psr; 2423 2424 if (psr != NULL && link->psr_feature_enabled) 2425 psr->funcs->get_psr_state(psr_state); 2426 else if (dmcu != NULL && link->psr_feature_enabled) 2427 dmcu->funcs->get_psr_state(dmcu, psr_state); 2428 2429 return true; 2430} 2431 2432static inline enum physical_phy_id 2433transmitter_to_phy_id(enum transmitter transmitter_value) 2434{ 2435 switch (transmitter_value) { 2436 case TRANSMITTER_UNIPHY_A: 2437 return PHYLD_0; 2438 case TRANSMITTER_UNIPHY_B: 2439 return PHYLD_1; 2440 case TRANSMITTER_UNIPHY_C: 2441 return PHYLD_2; 2442 case TRANSMITTER_UNIPHY_D: 2443 return PHYLD_3; 2444 case TRANSMITTER_UNIPHY_E: 2445 return PHYLD_4; 2446 case TRANSMITTER_UNIPHY_F: 2447 return PHYLD_5; 2448 case TRANSMITTER_NUTMEG_CRT: 2449 return PHYLD_6; 2450 case TRANSMITTER_TRAVIS_CRT: 2451 return PHYLD_7; 2452 case TRANSMITTER_TRAVIS_LCD: 2453 return PHYLD_8; 2454 case TRANSMITTER_UNIPHY_G: 2455 return PHYLD_9; 2456 case TRANSMITTER_COUNT: 2457 return PHYLD_COUNT; 2458 case TRANSMITTER_UNKNOWN: 2459 return PHYLD_UNKNOWN; 2460 default: 2461 WARN_ONCE(1, "Unknown transmitter value %d\n", 2462 transmitter_value); 2463 return PHYLD_UNKNOWN; 2464 } 2465} 2466 2467bool dc_link_setup_psr(struct dc_link *link, 2468 const struct dc_stream_state *stream, struct psr_config *psr_config, 2469 struct psr_context *psr_context) 2470{ 2471 struct dc *dc; 2472 struct dmcu *dmcu; 2473 struct dmub_psr *psr; 2474 int i; 2475 /* updateSinkPsrDpcdConfig*/ 2476 union dpcd_psr_configuration psr_configuration; 2477 2478 psr_context->controllerId = CONTROLLER_ID_UNDEFINED; 2479 2480 if (!link) 2481 return false; 2482 2483 dc = link->ctx->dc; 2484 dmcu = dc->res_pool->dmcu; 2485 psr = dc->res_pool->psr; 2486 2487 if (!dmcu && !psr) 2488 return false; 2489 2490 2491 memset(&psr_configuration, 0, sizeof(psr_configuration)); 2492 2493 psr_configuration.bits.ENABLE = 1; 2494 psr_configuration.bits.CRC_VERIFICATION = 1; 2495 psr_configuration.bits.FRAME_CAPTURE_INDICATION = 2496 psr_config->psr_frame_capture_indication_req; 2497 2498 /* Check for PSR v2*/ 2499 if (psr_config->psr_version == 0x2) { 2500 /* For PSR v2 selective update. 2501 * Indicates whether sink should start capturing 2502 * immediately following active scan line, 2503 * or starting with the 2nd active scan line. 2504 */ 2505 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0; 2506 /*For PSR v2, determines whether Sink should generate 2507 * IRQ_HPD when CRC mismatch is detected. 2508 */ 2509 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1; 2510 } 2511 2512 dm_helpers_dp_write_dpcd( 2513 link->ctx, 2514 link, 2515 368, 2516 &psr_configuration.raw, 2517 sizeof(psr_configuration.raw)); 2518 2519 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel; 2520 psr_context->transmitterId = link->link_enc->transmitter; 2521 psr_context->engineId = link->link_enc->preferred_engine; 2522 2523 for (i = 0; i < MAX_PIPES; i++) { 2524 if (dc->current_state->res_ctx.pipe_ctx[i].stream 2525 == stream) { 2526 /* dmcu -1 for all controller id values, 2527 * therefore +1 here 2528 */ 2529 psr_context->controllerId = 2530 dc->current_state->res_ctx. 2531 pipe_ctx[i].stream_res.tg->inst + 1; 2532 break; 2533 } 2534 } 2535 2536 /* Hardcoded for now. Can be Pcie or Uniphy (or Unknown)*/ 2537 psr_context->phyType = PHY_TYPE_UNIPHY; 2538 /*PhyId is associated with the transmitter id*/ 2539 psr_context->smuPhyId = 2540 transmitter_to_phy_id(link->link_enc->transmitter); 2541 2542 psr_context->crtcTimingVerticalTotal = stream->timing.v_total; 2543 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream-> 2544 timing.pix_clk_100hz * 100), 2545 stream->timing.v_total), 2546 stream->timing.h_total); 2547 2548 psr_context->psrSupportedDisplayConfig = true; 2549 psr_context->psrExitLinkTrainingRequired = 2550 psr_config->psr_exit_link_training_required; 2551 psr_context->sdpTransmitLineNumDeadline = 2552 psr_config->psr_sdp_transmit_line_num_deadline; 2553 psr_context->psrFrameCaptureIndicationReq = 2554 psr_config->psr_frame_capture_indication_req; 2555 2556 psr_context->skipPsrWaitForPllLock = 0; /* only = 1 in KV */ 2557 2558 psr_context->numberOfControllers = 2559 link->dc->res_pool->timing_generator_count; 2560 2561 psr_context->rfb_update_auto_en = true; 2562 2563 /* 2 frames before enter PSR. */ 2564 psr_context->timehyst_frames = 2; 2565 /* half a frame 2566 * (units in 100 lines, i.e. a value of 1 represents 100 lines) 2567 */ 2568 psr_context->hyst_lines = stream->timing.v_total / 2 / 100; 2569 psr_context->aux_repeats = 10; 2570 2571 psr_context->psr_level.u32all = 0; 2572 2573#if defined(CONFIG_DRM_AMD_DC_DCN) 2574 /*skip power down the single pipe since it blocks the cstate*/ 2575 if (ASICREV_IS_RAVEN(link->ctx->asic_id.hw_internal_rev)) 2576 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true; 2577#endif 2578 2579 /* SMU will perform additional powerdown sequence. 2580 * For unsupported ASICs, set psr_level flag to skip PSR 2581 * static screen notification to SMU. 2582 * (Always set for DAL2, did not check ASIC) 2583 */ 2584 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations; 2585 2586 /* Complete PSR entry before aborting to prevent intermittent 2587 * freezes on certain eDPs 2588 */ 2589 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1; 2590 2591 /* Controls additional delay after remote frame capture before 2592 * continuing power down, default = 0 2593 */ 2594 psr_context->frame_delay = 0; 2595 2596 if (psr) 2597 link->psr_feature_enabled = psr->funcs->setup_psr(psr, link, psr_context); 2598 else 2599 link->psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context); 2600 2601 /* psr_enabled == 0 indicates setup_psr did not succeed, but this 2602 * should not happen since firmware should be running at this point 2603 */ 2604 if (link->psr_feature_enabled == 0) 2605 ASSERT(0); 2606 2607 return true; 2608 2609} 2610 2611const struct dc_link_status *dc_link_get_status(const struct dc_link *link) 2612{ 2613 return &link->link_status; 2614} 2615 2616void core_link_resume(struct dc_link *link) 2617{ 2618 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL) 2619 program_hpd_filter(link); 2620} 2621 2622static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) 2623{ 2624 struct fixed31_32 mbytes_per_sec; 2625 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link, 2626 &stream->link->cur_link_settings); 2627 link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */ 2628 2629 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec); 2630 2631 return dc_fixpt_div_int(mbytes_per_sec, 54); 2632} 2633 2634static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx) 2635{ 2636 uint64_t kbps; 2637 struct fixed31_32 peak_kbps; 2638 uint32_t numerator; 2639 uint32_t denominator; 2640 2641 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing); 2642 2643 /* 2644 * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006 2645 * The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on 2646 * common multiplier to render an integer PBN for all link rate/lane 2647 * counts combinations 2648 * calculate 2649 * peak_kbps *= (1006/1000) 2650 * peak_kbps *= (64/54) 2651 * peak_kbps *= 8 convert to bytes 2652 */ 2653 2654 numerator = 64 * PEAK_FACTOR_X1000; 2655 denominator = 54 * 8 * 1000 * 1000; 2656 kbps *= numerator; 2657 peak_kbps = dc_fixpt_from_fraction(kbps, denominator); 2658 2659 return peak_kbps; 2660} 2661 2662static void update_mst_stream_alloc_table( 2663 struct dc_link *link, 2664 struct stream_encoder *stream_enc, 2665 const struct dp_mst_stream_allocation_table *proposed_table) 2666{ 2667 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = { 2668 { 0 } }; 2669 struct link_mst_stream_allocation *dc_alloc; 2670 2671 int i; 2672 int j; 2673 2674 /* if DRM proposed_table has more than one new payload */ 2675 ASSERT(proposed_table->stream_count - 2676 link->mst_stream_alloc_table.stream_count < 2); 2677 2678 /* copy proposed_table to link, add stream encoder */ 2679 for (i = 0; i < proposed_table->stream_count; i++) { 2680 2681 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) { 2682 dc_alloc = 2683 &link->mst_stream_alloc_table.stream_allocations[j]; 2684 2685 if (dc_alloc->vcp_id == 2686 proposed_table->stream_allocations[i].vcp_id) { 2687 2688 work_table[i] = *dc_alloc; 2689 break; /* exit j loop */ 2690 } 2691 } 2692 2693 /* new vcp_id */ 2694 if (j == link->mst_stream_alloc_table.stream_count) { 2695 work_table[i].vcp_id = 2696 proposed_table->stream_allocations[i].vcp_id; 2697 work_table[i].slot_count = 2698 proposed_table->stream_allocations[i].slot_count; 2699 work_table[i].stream_enc = stream_enc; 2700 } 2701 } 2702 2703 /* update link->mst_stream_alloc_table with work_table */ 2704 link->mst_stream_alloc_table.stream_count = 2705 proposed_table->stream_count; 2706 for (i = 0; i < MAX_CONTROLLER_NUM; i++) 2707 link->mst_stream_alloc_table.stream_allocations[i] = 2708 work_table[i]; 2709} 2710 2711/* convert link_mst_stream_alloc_table to dm dp_mst_stream_alloc_table 2712 * because stream_encoder is not exposed to dm 2713 */ 2714enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx) 2715{ 2716 struct dc_stream_state *stream = pipe_ctx->stream; 2717 struct dc_link *link = stream->link; 2718 struct link_encoder *link_encoder = link->link_enc; 2719 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; 2720 struct dp_mst_stream_allocation_table proposed_table = {0}; 2721 struct fixed31_32 avg_time_slots_per_mtp; 2722 struct fixed31_32 pbn; 2723 struct fixed31_32 pbn_per_slot; 2724 uint8_t i; 2725 enum act_return_status ret; 2726 DC_LOGGER_INIT(link->ctx->logger); 2727 2728 /* enable_link_dp_mst already check link->enabled_stream_count 2729 * and stream is in link->stream[]. This is called during set mode, 2730 * stream_enc is available. 2731 */ 2732 2733 /* get calculate VC payload for stream: stream_alloc */ 2734 if (dm_helpers_dp_mst_write_payload_allocation_table( 2735 stream->ctx, 2736 stream, 2737 &proposed_table, 2738 true)) { 2739 update_mst_stream_alloc_table( 2740 link, pipe_ctx->stream_res.stream_enc, &proposed_table); 2741 } 2742 else 2743 DC_LOG_WARNING("Failed to update" 2744 "MST allocation table for" 2745 "pipe idx:%d\n", 2746 pipe_ctx->pipe_idx); 2747 2748 DC_LOG_MST("%s " 2749 "stream_count: %d: \n ", 2750 __func__, 2751 link->mst_stream_alloc_table.stream_count); 2752 2753 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 2754 DC_LOG_MST("stream_enc[%d]: %p " 2755 "stream[%d].vcp_id: %d " 2756 "stream[%d].slot_count: %d\n", 2757 i, 2758 (const void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 2759 i, 2760 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 2761 i, 2762 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 2763 } 2764 2765 ASSERT(proposed_table.stream_count > 0); 2766 2767 /* program DP source TX for payload */ 2768 link_encoder->funcs->update_mst_stream_allocation_table( 2769 link_encoder, 2770 &link->mst_stream_alloc_table); 2771 2772 /* send down message */ 2773 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger( 2774 stream->ctx, 2775 stream); 2776 2777 if (ret != ACT_LINK_LOST) { 2778 dm_helpers_dp_mst_send_payload_allocation( 2779 stream->ctx, 2780 stream, 2781 true); 2782 } 2783 2784 /* slot X.Y for only current stream */ 2785 pbn_per_slot = get_pbn_per_slot(stream); 2786 pbn = get_pbn_from_timing(pipe_ctx); 2787 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot); 2788 2789 stream_encoder->funcs->set_mst_bandwidth( 2790 stream_encoder, 2791 avg_time_slots_per_mtp); 2792 2793 return DC_OK; 2794 2795} 2796 2797static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) 2798{ 2799 struct dc_stream_state *stream = pipe_ctx->stream; 2800 struct dc_link *link = stream->link; 2801 struct link_encoder *link_encoder = link->link_enc; 2802 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc; 2803 struct dp_mst_stream_allocation_table proposed_table = {0}; 2804 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); 2805 uint8_t i; 2806 bool mst_mode = (link->type == dc_connection_mst_branch); 2807 DC_LOGGER_INIT(link->ctx->logger); 2808 2809 /* deallocate_mst_payload is called before disable link. When mode or 2810 * disable/enable monitor, new stream is created which is not in link 2811 * stream[] yet. For this, payload is not allocated yet, so de-alloc 2812 * should not done. For new mode set, map_resources will get engine 2813 * for new stream, so stream_enc->id should be validated until here. 2814 */ 2815 2816 /* slot X.Y */ 2817 stream_encoder->funcs->set_mst_bandwidth( 2818 stream_encoder, 2819 avg_time_slots_per_mtp); 2820 2821 /* TODO: which component is responsible for remove payload table? */ 2822 if (mst_mode) { 2823 if (dm_helpers_dp_mst_write_payload_allocation_table( 2824 stream->ctx, 2825 stream, 2826 &proposed_table, 2827 false)) { 2828 2829 update_mst_stream_alloc_table( 2830 link, pipe_ctx->stream_res.stream_enc, &proposed_table); 2831 } 2832 else { 2833 DC_LOG_WARNING("Failed to update" 2834 "MST allocation table for" 2835 "pipe idx:%d\n", 2836 pipe_ctx->pipe_idx); 2837 } 2838 } 2839 2840 DC_LOG_MST("%s" 2841 "stream_count: %d: ", 2842 __func__, 2843 link->mst_stream_alloc_table.stream_count); 2844 2845 for (i = 0; i < MAX_CONTROLLER_NUM; i++) { 2846 DC_LOG_MST("stream_enc[%d]: %p " 2847 "stream[%d].vcp_id: %d " 2848 "stream[%d].slot_count: %d\n", 2849 i, 2850 (const void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, 2851 i, 2852 link->mst_stream_alloc_table.stream_allocations[i].vcp_id, 2853 i, 2854 link->mst_stream_alloc_table.stream_allocations[i].slot_count); 2855 } 2856 2857 link_encoder->funcs->update_mst_stream_allocation_table( 2858 link_encoder, 2859 &link->mst_stream_alloc_table); 2860 2861 if (mst_mode) { 2862 dm_helpers_dp_mst_poll_for_allocation_change_trigger( 2863 stream->ctx, 2864 stream); 2865 2866 dm_helpers_dp_mst_send_payload_allocation( 2867 stream->ctx, 2868 stream, 2869 false); 2870 } 2871 2872 return DC_OK; 2873} 2874 2875enum dc_status dc_link_reallocate_mst_payload(struct dc_link *link) 2876{ 2877 int i; 2878 struct pipe_ctx *pipe_ctx; 2879 2880 // Clear all of MST payload then reallocate 2881 for (i = 0; i < MAX_PIPES; i++) { 2882 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 2883 2884 /* driver enable split pipe for external monitors 2885 * we have to check pipe_ctx is split pipe or not 2886 * If it's split pipe, driver using top pipe to 2887 * reaallocate. 2888 */ 2889 if (!pipe_ctx || pipe_ctx->top_pipe) 2890 continue; 2891 2892 if (pipe_ctx->stream && pipe_ctx->stream->link == link && 2893 pipe_ctx->stream->dpms_off == false && 2894 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2895 deallocate_mst_payload(pipe_ctx); 2896 } 2897 } 2898 2899 for (i = 0; i < MAX_PIPES; i++) { 2900 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 2901 2902 if (!pipe_ctx || pipe_ctx->top_pipe) 2903 continue; 2904 2905 if (pipe_ctx->stream && pipe_ctx->stream->link == link && 2906 pipe_ctx->stream->dpms_off == false && 2907 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 2908 /* enable/disable PHY will clear connection between BE and FE 2909 * need to restore it. 2910 */ 2911 link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc, 2912 pipe_ctx->stream_res.stream_enc->id, true); 2913 dc_link_allocate_mst_payload(pipe_ctx); 2914 } 2915 } 2916 2917 return DC_OK; 2918} 2919 2920#if defined(CONFIG_DRM_AMD_DC_HDCP) 2921static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off) 2922{ 2923 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp; 2924 if (cp_psp && cp_psp->funcs.update_stream_config) { 2925 struct cp_psp_stream_config config; 2926 2927 memset(&config, 0, sizeof(config)); 2928 2929 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst; 2930 config.stream_enc_inst = (uint8_t) pipe_ctx->stream_res.stream_enc->id; 2931 config.link_enc_inst = pipe_ctx->stream->link->link_enc_hw_inst; 2932 config.dpms_off = dpms_off; 2933 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context; 2934 cp_psp->funcs.update_stream_config(cp_psp->handle, &config); 2935 } 2936} 2937#endif 2938 2939void core_link_enable_stream( 2940 struct dc_state *state, 2941 struct pipe_ctx *pipe_ctx) 2942{ 2943 struct dc *dc = pipe_ctx->stream->ctx->dc; 2944 struct dc_stream_state *stream = pipe_ctx->stream; 2945 enum dc_status status; 2946 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); 2947 2948 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && 2949 dc_is_virtual_signal(pipe_ctx->stream->signal)) 2950 return; 2951 2952 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) { 2953 stream->link->link_enc->funcs->setup( 2954 stream->link->link_enc, 2955 pipe_ctx->stream->signal); 2956 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync( 2957 pipe_ctx->stream_res.stream_enc, 2958 pipe_ctx->stream_res.tg->inst, 2959 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); 2960 } 2961 2962 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 2963 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute( 2964 pipe_ctx->stream_res.stream_enc, 2965 &stream->timing, 2966 stream->output_color_space, 2967 stream->use_vsc_sdp_for_colorimetry, 2968 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP); 2969 2970 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) 2971 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute( 2972 pipe_ctx->stream_res.stream_enc, 2973 &stream->timing, 2974 stream->phy_pix_clk, 2975 pipe_ctx->stream_res.audio != NULL); 2976 2977 pipe_ctx->stream->link->link_state_valid = true; 2978 2979 if (dc_is_dvi_signal(pipe_ctx->stream->signal)) 2980 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute( 2981 pipe_ctx->stream_res.stream_enc, 2982 &stream->timing, 2983 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? 2984 true : false); 2985 2986 if (dc_is_lvds_signal(pipe_ctx->stream->signal)) 2987 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute( 2988 pipe_ctx->stream_res.stream_enc, 2989 &stream->timing); 2990 2991 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 2992 bool apply_edp_fast_boot_optimization = 2993 pipe_ctx->stream->apply_edp_fast_boot_optimization; 2994 2995 pipe_ctx->stream->apply_edp_fast_boot_optimization = false; 2996 2997 resource_build_info_frame(pipe_ctx); 2998 dc->hwss.update_info_frame(pipe_ctx); 2999 3000 /* Do not touch link on seamless boot optimization. */ 3001 if (pipe_ctx->stream->apply_seamless_boot_optimization) { 3002 pipe_ctx->stream->dpms_off = false; 3003#if defined(CONFIG_DRM_AMD_DC_HDCP) 3004 update_psp_stream_config(pipe_ctx, false); 3005#endif 3006 return; 3007 } 3008 3009 /* eDP lit up by bios already, no need to enable again. */ 3010 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 3011 apply_edp_fast_boot_optimization) { 3012 pipe_ctx->stream->dpms_off = false; 3013#if defined(CONFIG_DRM_AMD_DC_HDCP) 3014 update_psp_stream_config(pipe_ctx, false); 3015#endif 3016 return; 3017 } 3018 3019 if (pipe_ctx->stream->dpms_off) 3020 return; 3021 3022 status = enable_link(state, pipe_ctx); 3023 3024 if (status != DC_OK) { 3025 DC_LOG_WARNING("enabling link %u failed: %d\n", 3026 pipe_ctx->stream->link->link_index, 3027 status); 3028 3029 /* Abort stream enable *unless* the failure was due to 3030 * DP link training - some DP monitors will recover and 3031 * show the stream anyway. But MST displays can't proceed 3032 * without link training. 3033 */ 3034 if (status != DC_FAIL_DP_LINK_TRAINING || 3035 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { 3036 BREAK_TO_DEBUGGER(); 3037 return; 3038 } 3039 } 3040 3041 dc->hwss.enable_audio_stream(pipe_ctx); 3042 3043 /* turn off otg test pattern if enable */ 3044 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) 3045 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, 3046 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE, 3047 COLOR_DEPTH_UNDEFINED); 3048 3049 if (pipe_ctx->stream->timing.flags.DSC) { 3050 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 3051 dc_is_virtual_signal(pipe_ctx->stream->signal)) 3052 dp_set_dsc_enable(pipe_ctx, true); 3053 } 3054 dc->hwss.enable_stream(pipe_ctx); 3055 3056 /* Set DPS PPS SDP (AKA "info frames") */ 3057 if (pipe_ctx->stream->timing.flags.DSC) { 3058 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 3059 dc_is_virtual_signal(pipe_ctx->stream->signal)) 3060 dp_set_dsc_pps_sdp(pipe_ctx, true); 3061 } 3062 3063 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 3064 dc_link_allocate_mst_payload(pipe_ctx); 3065 3066 dc->hwss.unblank_stream(pipe_ctx, 3067 &pipe_ctx->stream->link->cur_link_settings); 3068 3069 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 3070 enable_stream_features(pipe_ctx); 3071#if defined(CONFIG_DRM_AMD_DC_HDCP) 3072 update_psp_stream_config(pipe_ctx, false); 3073#endif 3074 } else { // if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) 3075 if (dc_is_dp_signal(pipe_ctx->stream->signal) || 3076 dc_is_virtual_signal(pipe_ctx->stream->signal)) 3077 dp_set_dsc_enable(pipe_ctx, true); 3078 3079 } 3080} 3081 3082void core_link_disable_stream(struct pipe_ctx *pipe_ctx) 3083{ 3084 struct dc *dc = pipe_ctx->stream->ctx->dc; 3085 struct dc_stream_state *stream = pipe_ctx->stream; 3086 struct dc_link *link = stream->sink->link; 3087 3088 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && 3089 dc_is_virtual_signal(pipe_ctx->stream->signal)) 3090 return; 3091 3092#if defined(CONFIG_DRM_AMD_DC_HDCP) 3093 update_psp_stream_config(pipe_ctx, true); 3094#endif 3095 3096 dc->hwss.blank_stream(pipe_ctx); 3097 3098 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) 3099 deallocate_mst_payload(pipe_ctx); 3100 3101 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) { 3102 struct ext_hdmi_settings settings = {0}; 3103 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id; 3104 3105 unsigned short masked_chip_caps = link->chip_caps & 3106 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK; 3107 //Need to inform that sink is going to use legacy HDMI mode. 3108 dal_ddc_service_write_scdc_data( 3109 link->ddc, 3110 165000,//vbios only handles 165Mhz. 3111 false); 3112 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) { 3113 /* DP159, Retimer settings */ 3114 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) 3115 write_i2c_retimer_setting(pipe_ctx, 3116 false, false, &settings); 3117 else 3118 write_i2c_default_retimer_setting(pipe_ctx, 3119 false, false); 3120 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) { 3121 /* PI3EQX1204, Redriver settings */ 3122 write_i2c_redriver_setting(pipe_ctx, false); 3123 } 3124 } 3125 dc->hwss.disable_stream(pipe_ctx); 3126 3127 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal); 3128 if (pipe_ctx->stream->timing.flags.DSC) { 3129 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 3130 dp_set_dsc_enable(pipe_ctx, false); 3131 } 3132} 3133 3134void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 3135{ 3136 struct dc *dc = pipe_ctx->stream->ctx->dc; 3137 3138 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) 3139 return; 3140 3141 dc->hwss.set_avmute(pipe_ctx, enable); 3142} 3143 3144/** 3145 ***************************************************************************** 3146 * Function: dc_link_enable_hpd_filter 3147 * 3148 * @brief 3149 * If enable is true, programs HPD filter on associated HPD line using 3150 * delay_on_disconnect/delay_on_connect values dependent on 3151 * link->connector_signal 3152 * 3153 * If enable is false, programs HPD filter on associated HPD line with no 3154 * delays on connect or disconnect 3155 * 3156 * @param [in] link: pointer to the dc link 3157 * @param [in] enable: boolean specifying whether to enable hbd 3158 ***************************************************************************** 3159 */ 3160void dc_link_enable_hpd_filter(struct dc_link *link, bool enable) 3161{ 3162 struct gpio *hpd; 3163 3164 if (enable) { 3165 link->is_hpd_filter_disabled = false; 3166 program_hpd_filter(link); 3167 } else { 3168 link->is_hpd_filter_disabled = true; 3169 /* Obtain HPD handle */ 3170 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service); 3171 3172 if (!hpd) 3173 return; 3174 3175 /* Setup HPD filtering */ 3176 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) { 3177 struct gpio_hpd_config config; 3178 3179 config.delay_on_connect = 0; 3180 config.delay_on_disconnect = 0; 3181 3182 dal_irq_setup_hpd_filter(hpd, &config); 3183 3184 dal_gpio_close(hpd); 3185 } else { 3186 ASSERT_CRITICAL(false); 3187 } 3188 /* Release HPD handle */ 3189 dal_gpio_destroy_irq(&hpd); 3190 } 3191} 3192 3193uint32_t dc_bandwidth_in_kbps_from_timing( 3194 const struct dc_crtc_timing *timing) 3195{ 3196 uint32_t bits_per_channel = 0; 3197 uint32_t kbps; 3198 3199 if (timing->flags.DSC) { 3200 kbps = (timing->pix_clk_100hz * timing->dsc_cfg.bits_per_pixel); 3201 kbps = kbps / 160 + ((kbps % 160) ? 1 : 0); 3202 return kbps; 3203 } 3204 3205 switch (timing->display_color_depth) { 3206 case COLOR_DEPTH_666: 3207 bits_per_channel = 6; 3208 break; 3209 case COLOR_DEPTH_888: 3210 bits_per_channel = 8; 3211 break; 3212 case COLOR_DEPTH_101010: 3213 bits_per_channel = 10; 3214 break; 3215 case COLOR_DEPTH_121212: 3216 bits_per_channel = 12; 3217 break; 3218 case COLOR_DEPTH_141414: 3219 bits_per_channel = 14; 3220 break; 3221 case COLOR_DEPTH_161616: 3222 bits_per_channel = 16; 3223 break; 3224 default: 3225 break; 3226 } 3227 3228 ASSERT(bits_per_channel != 0); 3229 3230 kbps = timing->pix_clk_100hz / 10; 3231 kbps *= bits_per_channel; 3232 3233 if (timing->flags.Y_ONLY != 1) { 3234 /*Only YOnly make reduce bandwidth by 1/3 compares to RGB*/ 3235 kbps *= 3; 3236 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3237 kbps /= 2; 3238 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 3239 kbps = kbps * 2 / 3; 3240 } 3241 3242 return kbps; 3243 3244} 3245 3246void dc_link_set_drive_settings(struct dc *dc, 3247 struct link_training_settings *lt_settings, 3248 const struct dc_link *link) 3249{ 3250 3251 int i; 3252 3253 for (i = 0; i < dc->link_count; i++) { 3254 if (dc->links[i] == link) 3255 break; 3256 } 3257 3258 if (i >= dc->link_count) 3259 ASSERT_CRITICAL(false); 3260 3261 dc_link_dp_set_drive_settings(dc->links[i], lt_settings); 3262} 3263 3264void dc_link_perform_link_training(struct dc *dc, 3265 struct dc_link_settings *link_setting, 3266 bool skip_video_pattern) 3267{ 3268 int i; 3269 3270 for (i = 0; i < dc->link_count; i++) 3271 dc_link_dp_perform_link_training( 3272 dc->links[i], 3273 link_setting, 3274 skip_video_pattern); 3275} 3276 3277void dc_link_set_preferred_link_settings(struct dc *dc, 3278 struct dc_link_settings *link_setting, 3279 struct dc_link *link) 3280{ 3281 int i; 3282 struct pipe_ctx *pipe; 3283 struct dc_stream_state *link_stream; 3284 struct dc_link_settings store_settings = *link_setting; 3285 3286 link->preferred_link_setting = store_settings; 3287 3288 /* Retrain with preferred link settings only relevant for 3289 * DP signal type 3290 * Check for non-DP signal or if passive dongle present 3291 */ 3292 if (!dc_is_dp_signal(link->connector_signal) || 3293 link->dongle_max_pix_clk > 0) 3294 return; 3295 3296 for (i = 0; i < MAX_PIPES; i++) { 3297 pipe = &dc->current_state->res_ctx.pipe_ctx[i]; 3298 if (pipe->stream && pipe->stream->link) { 3299 if (pipe->stream->link == link) { 3300 link_stream = pipe->stream; 3301 break; 3302 } 3303 } 3304 } 3305 3306 /* Stream not found */ 3307 if (i == MAX_PIPES) 3308 return; 3309 3310 /* Cannot retrain link if backend is off */ 3311 if (link_stream->dpms_off) 3312 return; 3313 3314 decide_link_settings(link_stream, &store_settings); 3315 3316 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) && 3317 (store_settings.link_rate != LINK_RATE_UNKNOWN)) 3318 dp_retrain_link_dp_test(link, &store_settings, false); 3319} 3320 3321void dc_link_set_preferred_training_settings(struct dc *dc, 3322 struct dc_link_settings *link_setting, 3323 struct dc_link_training_overrides *lt_overrides, 3324 struct dc_link *link, 3325 bool skip_immediate_retrain) 3326{ 3327 if (lt_overrides != NULL) 3328 link->preferred_training_settings = *lt_overrides; 3329 else 3330 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings)); 3331 3332 if (link_setting != NULL) { 3333 link->preferred_link_setting = *link_setting; 3334 } else { 3335 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN; 3336 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN; 3337 } 3338 3339 /* Retrain now, or wait until next stream update to apply */ 3340 if (skip_immediate_retrain == false) 3341 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link); 3342} 3343 3344void dc_link_enable_hpd(const struct dc_link *link) 3345{ 3346 dc_link_dp_enable_hpd(link); 3347} 3348 3349void dc_link_disable_hpd(const struct dc_link *link) 3350{ 3351 dc_link_dp_disable_hpd(link); 3352} 3353 3354void dc_link_set_test_pattern(struct dc_link *link, 3355 enum dp_test_pattern test_pattern, 3356 enum dp_test_pattern_color_space test_pattern_color_space, 3357 const struct link_training_settings *p_link_settings, 3358 const unsigned char *p_custom_pattern, 3359 unsigned int cust_pattern_size) 3360{ 3361 if (link != NULL) 3362 dc_link_dp_set_test_pattern( 3363 link, 3364 test_pattern, 3365 test_pattern_color_space, 3366 p_link_settings, 3367 p_custom_pattern, 3368 cust_pattern_size); 3369} 3370 3371uint32_t dc_link_bandwidth_kbps( 3372 const struct dc_link *link, 3373 const struct dc_link_settings *link_setting) 3374{ 3375 uint32_t link_bw_kbps = 3376 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; /* bytes per sec */ 3377 3378 link_bw_kbps *= 8; /* 8 bits per byte*/ 3379 link_bw_kbps *= link_setting->lane_count; 3380 3381 if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) { 3382 /* Account for FEC overhead. 3383 * We have to do it based on caps, 3384 * and not based on FEC being set ready, 3385 * because FEC is set ready too late in 3386 * the process to correctly be picked up 3387 * by mode enumeration. 3388 * 3389 * There's enough zeros at the end of 'kbps' 3390 * that make the below operation 100% precise 3391 * for our purposes. 3392 * 'long long' makes it work even for HDMI 2.1 3393 * max bandwidth (and much, much bigger bandwidths 3394 * than that, actually). 3395 * 3396 * NOTE: Reducing link BW by 3% may not be precise 3397 * because it may be a stream BT that increases by 3%, and so 3398 * 1/1.03 = 0.970873 factor should have been used instead, 3399 * but the difference is minimal and is in a safe direction, 3400 * which all works well around potential ambiguity of DP 1.4a spec. 3401 */ 3402 link_bw_kbps = mul_u64_u32_shr(BIT_ULL(32) * 970LL / 1000, 3403 link_bw_kbps, 32); 3404 } 3405 3406 return link_bw_kbps; 3407 3408} 3409 3410const struct dc_link_settings *dc_link_get_link_cap( 3411 const struct dc_link *link) 3412{ 3413 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN && 3414 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) 3415 return &link->preferred_link_setting; 3416 return &link->verified_link_cap; 3417} 3418 3419void dc_link_overwrite_extended_receiver_cap( 3420 struct dc_link *link) 3421{ 3422 dp_overwrite_extended_receiver_cap(link); 3423} 3424 3425